drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "nbio_v7_9.h"
  39 #include "atom.h"
  40 #include "amdgpu_reset.h"
  41
  42 #ifdef CONFIG_X86_MCE_AMD
  43 #include <asm/mce.h>
  44
  45 static bool notifier_registered;
  46 #endif
  47 static const char *RAS_FS_NAME = "ras";
  48
  49 const char *ras_error_string[] = {
  50         "none",
  51         "parity",
  52         "single_correctable",
  53         "multi_uncorrectable",
  54         "poison",
  55 };
  56
  57 const char *ras_block_string[] = {
  58         "umc",
  59         "sdma",
  60         "gfx",
  61         "mmhub",
  62         "athub",
  63         "pcie_bif",
  64         "hdp",
  65         "xgmi_wafl",
  66         "df",
  67         "smn",
  68         "sem",
  69         "mp0",
  70         "mp1",
  71         "fuse",
  72         "mca",
  73         "vcn",
  74         "jpeg",
  75 };
  76
  77 const char *ras_mca_block_string[] = {
  78         "mca_mp0",
  79         "mca_mp1",
  80         "mca_mpio",
  81         "mca_iohc",
  82 };
  83
  84 struct amdgpu_ras_block_list {
  85         /* ras block link */
  86         struct list_head node;
  87
  88         struct amdgpu_ras_block_object *ras_obj;
  89 };
  90
  91 const char *get_ras_block_str(struct ras_common_if *ras_block)
  92 {
  93         if (!ras_block)
  94                 return "NULL";
  95
  96         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  97                 return "OUT OF RANGE";
  98
  99         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 100                 return ras_mca_block_string[ras_block->sub_block_index];
 101
 102         return ras_block_string[ras_block->block];
 103 }
 104
 105 #define ras_block_str(_BLOCK_) \
 106         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 107
 108 #define ras_err_str(i) (ras_error_string[ffs(i)])
 109
 110 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 111
 112 /* inject address is 52 bits */
 113 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 114
 115 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 116 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 117
 118 enum amdgpu_ras_retire_page_reservation {
 119         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 120         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 121         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 122 };
 123
 124 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 125
 126 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 127                                 uint64_t addr);
 128 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 129                                 uint64_t addr);
 130 #ifdef CONFIG_X86_MCE_AMD
 131 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 132 struct mce_notifier_adev_list {
 133         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 134         int num_gpu;
 135 };
 136 static struct mce_notifier_adev_list mce_adev_list;
 137 #endif
 138
 139 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 140 {
 141         if (adev && amdgpu_ras_get_context(adev))
 142                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 143 }
 144
 145 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 146 {
 147         if (adev && amdgpu_ras_get_context(adev))
 148                 return amdgpu_ras_get_context(adev)->error_query_ready;
 149
 150         return false;
 151 }
 152
 153 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 154 {
 155         struct ras_err_data err_data;
 156         struct eeprom_table_record err_rec;
 157         int ret;
 158
 159         if ((address >= adev->gmc.mc_vram_size) ||
 160             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 161                 dev_warn(adev->dev,
 162                          "RAS WARN: input address 0x%llx is invalid.\n",
 163                          address);
 164                 return -EINVAL;
 165         }
 166
 167         if (amdgpu_ras_check_bad_page(adev, address)) {
 168                 dev_warn(adev->dev,
 169                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 170                          address);
 171                 return 0;
 172         }
 173
 174         ret = amdgpu_ras_error_data_init(&err_data);
 175         if (ret)
 176                 return ret;
 177
 178         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 179         err_data.err_addr = &err_rec;
 180         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 181
 182         if (amdgpu_bad_page_threshold != 0) {
 183                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 184                                          err_data.err_addr_cnt);
 185                 amdgpu_ras_save_bad_pages(adev, NULL);
 186         }
 187
 188         amdgpu_ras_error_data_fini(&err_data);
 189
 190         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 191         dev_warn(adev->dev, "Clear EEPROM:\n");
 192         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 193
 194         return 0;
 195 }
 196
 197 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 198                                         size_t size, loff_t *pos)
 199 {
 200         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 201         struct ras_query_if info = {
 202                 .head = obj->head,
 203         };
 204         ssize_t s;
 205         char val[128];
 206
 207         if (amdgpu_ras_query_error_status(obj->adev, &info))
 208                 return -EINVAL;
 209
 210         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 211         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 212             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 213                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 214                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 215         }
 216
 217         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 218                         "ue", info.ue_count,
 219                         "ce", info.ce_count);
 220         if (*pos >= s)
 221                 return 0;
 222
 223         s -= *pos;
 224         s = min_t(u64, s, size);
 225
 226
 227         if (copy_to_user(buf, &val[*pos], s))
 228                 return -EINVAL;
 229
 230         *pos += s;
 231
 232         return s;
 233 }
 234
 235 static const struct file_operations amdgpu_ras_debugfs_ops = {
 236         .owner = THIS_MODULE,
 237         .read = amdgpu_ras_debugfs_read,
 238         .write = NULL,
 239         .llseek = default_llseek
 240 };
 241
 242 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 243 {
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 247                 *block_id = i;
 248                 if (strcmp(name, ras_block_string[i]) == 0)
 249                         return 0;
 250         }
 251         return -EINVAL;
 252 }
 253
 254 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 255                 const char __user *buf, size_t size,
 256                 loff_t *pos, struct ras_debug_if *data)
 257 {
 258         ssize_t s = min_t(u64, 64, size);
 259         char str[65];
 260         char block_name[33];
 261         char err[9] = "ue";
 262         int op = -1;
 263         int block_id;
 264         uint32_t sub_block;
 265         u64 address, value;
 266         /* default value is 0 if the mask is not set by user */
 267         u32 instance_mask = 0;
 268
 269         if (*pos)
 270                 return -EINVAL;
 271         *pos = size;
 272
 273         memset(str, 0, sizeof(str));
 274         memset(data, 0, sizeof(*data));
 275
 276         if (copy_from_user(str, buf, s))
 277                 return -EINVAL;
 278
 279         if (sscanf(str, "disable %32s", block_name) == 1)
 280                 op = 0;
 281         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 282                 op = 1;
 283         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 284                 op = 2;
 285         else if (strstr(str, "retire_page") != NULL)
 286                 op = 3;
 287         else if (str[0] && str[1] && str[2] && str[3])
 288                 /* ascii string, but commands are not matched. */
 289                 return -EINVAL;
 290
 291         if (op != -1) {
 292                 if (op == 3) {
 293                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 294                             sscanf(str, "%*s %llu", &address) != 1)
 295                                 return -EINVAL;
 296
 297                         data->op = op;
 298                         data->inject.address = address;
 299
 300                         return 0;
 301                 }
 302
 303                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 304                         return -EINVAL;
 305
 306                 data->head.block = block_id;
 307                 /* only ue and ce errors are supported */
 308                 if (!memcmp("ue", err, 2))
 309                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 310                 else if (!memcmp("ce", err, 2))
 311                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 312                 else
 313                         return -EINVAL;
 314
 315                 data->op = op;
 316
 317                 if (op == 2) {
 318                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 319                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 320                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 321                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 322                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 323                                    &sub_block, &address, &value) != 3 &&
 324                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 325                                    &sub_block, &address, &value) != 3)
 326                                 return -EINVAL;
 327                         data->head.sub_block_index = sub_block;
 328                         data->inject.address = address;
 329                         data->inject.value = value;
 330                         data->inject.instance_mask = instance_mask;
 331                 }
 332         } else {
 333                 if (size < sizeof(*data))
 334                         return -EINVAL;
 335
 336                 if (copy_from_user(data, buf, sizeof(*data)))
 337                         return -EINVAL;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 344                                 struct ras_debug_if *data)
 345 {
 346         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 347         uint32_t mask, inst_mask = data->inject.instance_mask;
 348
 349         /* no need to set instance mask if there is only one instance */
 350         if (num_xcc <= 1 && inst_mask) {
 351                 data->inject.instance_mask = 0;
 352                 dev_dbg(adev->dev,
 353                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 354                         inst_mask);
 355
 356                 return;
 357         }
 358
 359         switch (data->head.block) {
 360         case AMDGPU_RAS_BLOCK__GFX:
 361                 mask = GENMASK(num_xcc - 1, 0);
 362                 break;
 363         case AMDGPU_RAS_BLOCK__SDMA:
 364                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 365                 break;
 366         case AMDGPU_RAS_BLOCK__VCN:
 367         case AMDGPU_RAS_BLOCK__JPEG:
 368                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 369                 break;
 370         default:
 371                 mask = inst_mask;
 372                 break;
 373         }
 374
 375         /* remove invalid bits in instance mask */
 376         data->inject.instance_mask &= mask;
 377         if (inst_mask != data->inject.instance_mask)
 378                 dev_dbg(adev->dev,
 379                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 380                         inst_mask, data->inject.instance_mask);
 381 }
 382
 383 /**
 384  * DOC: AMDGPU RAS debugfs control interface
 385  *
 386  * The control interface accepts struct ras_debug_if which has two members.
 387  *
 388  * First member: ras_debug_if::head or ras_debug_if::inject.
 389  *
 390  * head is used to indicate which IP block will be under control.
 391  *
 392  * head has four members, they are block, type, sub_block_index, name.
 393  * block: which IP will be under control.
 394  * type: what kind of error will be enabled/disabled/injected.
 395  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 396  * name: the name of IP.
 397  *
 398  * inject has three more members than head, they are address, value and mask.
 399  * As their names indicate, inject operation will write the
 400  * value to the address.
 401  *
 402  * The second member: struct ras_debug_if::op.
 403  * It has three kinds of operations.
 404  *
 405  * - 0: disable RAS on the block. Take ::head as its data.
 406  * - 1: enable RAS on the block. Take ::head as its data.
 407  * - 2: inject errors on the block. Take ::inject as its data.
 408  *
 409  * How to use the interface?
 410  *
 411  * In a program
 412  *
 413  * Copy the struct ras_debug_if in your code and initialize it.
 414  * Write the struct to the control interface.
 415  *
 416  * From shell
 417  *
 418  * .. code-block:: bash
 419  *
 420  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 421  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 422  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 423  *
 424  * Where N, is the card which you want to affect.
 425  *
 426  * "disable" requires only the block.
 427  * "enable" requires the block and error type.
 428  * "inject" requires the block, error type, address, and value.
 429  *
 430  * The block is one of: umc, sdma, gfx, etc.
 431  *      see ras_block_string[] for details
 432  *
 433  * The error type is one of: ue, ce, where,
 434  *      ue is multi-uncorrectable
 435  *      ce is single-correctable
 436  *
 437  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 438  * The address and value are hexadecimal numbers, leading 0x is optional.
 439  * The mask means instance mask, is optional, default value is 0x1.
 440  *
 441  * For instance,
 442  *
 443  * .. code-block:: bash
 444  *
 445  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 446  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 447  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 448  *
 449  * How to check the result of the operation?
 450  *
 451  * To check disable/enable, see "ras" features at,
 452  * /sys/class/drm/card[0/1/2...]/device/ras/features
 453  *
 454  * To check inject, see the corresponding error count at,
 455  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 456  *
 457  * .. note::
 458  *      Operations are only allowed on blocks which are supported.
 459  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 460  *      to see which blocks support RAS on a particular asic.
 461  *
 462  */
 463 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 464                                              const char __user *buf,
 465                                              size_t size, loff_t *pos)
 466 {
 467         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 468         struct ras_debug_if data;
 469         int ret = 0;
 470
 471         if (!amdgpu_ras_get_error_query_ready(adev)) {
 472                 dev_warn(adev->dev, "RAS WARN: error injection "
 473                                 "currently inaccessible\n");
 474                 return size;
 475         }
 476
 477         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 478         if (ret)
 479                 return ret;
 480
 481         if (data.op == 3) {
 482                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 483                 if (!ret)
 484                         return size;
 485                 else
 486                         return ret;
 487         }
 488
 489         if (!amdgpu_ras_is_supported(adev, data.head.block))
 490                 return -EINVAL;
 491
 492         switch (data.op) {
 493         case 0:
 494                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 495                 break;
 496         case 1:
 497                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 498                 break;
 499         case 2:
 500                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 501                     adev->gmc.mc_vram_size) ||
 502                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 503                         dev_warn(adev->dev, "RAS WARN: input address "
 504                                         "0x%llx is invalid.",
 505                                         data.inject.address);
 506                         ret = -EINVAL;
 507                         break;
 508                 }
 509
 510                 /* umc ce/ue error injection for a bad page is not allowed */
 511                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 512                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 513                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 514                                  "already been marked as bad!\n",
 515                                  data.inject.address);
 516                         break;
 517                 }
 518
 519                 amdgpu_ras_instance_mask_check(adev, &data);
 520
 521                 /* data.inject.address is offset instead of absolute gpu address */
 522                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 523                 break;
 524         default:
 525                 ret = -EINVAL;
 526                 break;
 527         }
 528
 529         if (ret)
 530                 return ret;
 531
 532         return size;
 533 }
 534
 535 /**
 536  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 537  *
 538  * Some boards contain an EEPROM which is used to persistently store a list of
 539  * bad pages which experiences ECC errors in vram.  This interface provides
 540  * a way to reset the EEPROM, e.g., after testing error injection.
 541  *
 542  * Usage:
 543  *
 544  * .. code-block:: bash
 545  *
 546  *      echo 1 > ../ras/ras_eeprom_reset
 547  *
 548  * will reset EEPROM table to 0 entries.
 549  *
 550  */
 551 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 552                                                const char __user *buf,
 553                                                size_t size, loff_t *pos)
 554 {
 555         struct amdgpu_device *adev =
 556                 (struct amdgpu_device *)file_inode(f)->i_private;
 557         int ret;
 558
 559         ret = amdgpu_ras_eeprom_reset_table(
 560                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 561
 562         if (!ret) {
 563                 /* Something was written to EEPROM.
 564                  */
 565                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 566                 return size;
 567         } else {
 568                 return ret;
 569         }
 570 }
 571
 572 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 573         .owner = THIS_MODULE,
 574         .read = NULL,
 575         .write = amdgpu_ras_debugfs_ctrl_write,
 576         .llseek = default_llseek
 577 };
 578
 579 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 580         .owner = THIS_MODULE,
 581         .read = NULL,
 582         .write = amdgpu_ras_debugfs_eeprom_write,
 583         .llseek = default_llseek
 584 };
 585
 586 /**
 587  * DOC: AMDGPU RAS sysfs Error Count Interface
 588  *
 589  * It allows the user to read the error count for each IP block on the gpu through
 590  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 591  *
 592  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 593  * (ce) error counts.
 594  *
 595  * The format of one line is below,
 596  *
 597  * [ce|ue]: count
 598  *
 599  * Example:
 600  *
 601  * .. code-block:: bash
 602  *
 603  *      ue: 0
 604  *      ce: 1
 605  *
 606  */
 607 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 608                 struct device_attribute *attr, char *buf)
 609 {
 610         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 611         struct ras_query_if info = {
 612                 .head = obj->head,
 613         };
 614
 615         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 616                 return sysfs_emit(buf, "Query currently inaccessible\n");
 617
 618         if (amdgpu_ras_query_error_status(obj->adev, &info))
 619                 return -EINVAL;
 620
 621         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 622             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 623                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 624                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 625         }
 626
 627         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 628                           "ce", info.ce_count);
 629 }
 630
 631 /* obj begin */
 632
 633 #define get_obj(obj) do { (obj)->use++; } while (0)
 634 #define alive_obj(obj) ((obj)->use)
 635
 636 static inline void put_obj(struct ras_manager *obj)
 637 {
 638         if (obj && (--obj->use == 0)) {
 639                 list_del(&obj->node);
 640                 amdgpu_ras_error_data_fini(&obj->err_data);
 641         }
 642
 643         if (obj && (obj->use < 0))
 644                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 645 }
 646
 647 /* make one obj and return it. */
 648 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 649                 struct ras_common_if *head)
 650 {
 651         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 652         struct ras_manager *obj;
 653
 654         if (!adev->ras_enabled || !con)
 655                 return NULL;
 656
 657         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 658                 return NULL;
 659
 660         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 661                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 662                         return NULL;
 663
 664                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 665         } else
 666                 obj = &con->objs[head->block];
 667
 668         /* already exist. return obj? */
 669         if (alive_obj(obj))
 670                 return NULL;
 671
 672         if (amdgpu_ras_error_data_init(&obj->err_data))
 673                 return NULL;
 674
 675         obj->head = *head;
 676         obj->adev = adev;
 677         list_add(&obj->node, &con->head);
 678         get_obj(obj);
 679
 680         return obj;
 681 }
 682
 683 /* return an obj equal to head, or the first when head is NULL */
 684 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 685                 struct ras_common_if *head)
 686 {
 687         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 688         struct ras_manager *obj;
 689         int i;
 690
 691         if (!adev->ras_enabled || !con)
 692                 return NULL;
 693
 694         if (head) {
 695                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 696                         return NULL;
 697
 698                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 699                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 700                                 return NULL;
 701
 702                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 703                 } else
 704                         obj = &con->objs[head->block];
 705
 706                 if (alive_obj(obj))
 707                         return obj;
 708         } else {
 709                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 710                         obj = &con->objs[i];
 711                         if (alive_obj(obj))
 712                                 return obj;
 713                 }
 714         }
 715
 716         return NULL;
 717 }
 718 /* obj end */
 719
 720 /* feature ctl begin */
 721 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 722                                          struct ras_common_if *head)
 723 {
 724         return adev->ras_hw_enabled & BIT(head->block);
 725 }
 726
 727 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 728                 struct ras_common_if *head)
 729 {
 730         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 731
 732         return con->features & BIT(head->block);
 733 }
 734
 735 /*
 736  * if obj is not created, then create one.
 737  * set feature enable flag.
 738  */
 739 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 740                 struct ras_common_if *head, int enable)
 741 {
 742         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 743         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 744
 745         /* If hardware does not support ras, then do not create obj.
 746          * But if hardware support ras, we can create the obj.
 747          * Ras framework checks con->hw_supported to see if it need do
 748          * corresponding initialization.
 749          * IP checks con->support to see if it need disable ras.
 750          */
 751         if (!amdgpu_ras_is_feature_allowed(adev, head))
 752                 return 0;
 753
 754         if (enable) {
 755                 if (!obj) {
 756                         obj = amdgpu_ras_create_obj(adev, head);
 757                         if (!obj)
 758                                 return -EINVAL;
 759                 } else {
 760                         /* In case we create obj somewhere else */
 761                         get_obj(obj);
 762                 }
 763                 con->features |= BIT(head->block);
 764         } else {
 765                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 766                         con->features &= ~BIT(head->block);
 767                         put_obj(obj);
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 /* wrapper of psp_ras_enable_features */
 775 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 776                 struct ras_common_if *head, bool enable)
 777 {
 778         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 779         union ta_ras_cmd_input *info;
 780         int ret;
 781
 782         if (!con)
 783                 return -EINVAL;
 784
 785         /* For non-gfx ip, do not enable ras feature if it is not allowed */
 786         /* For gfx ip, regardless of feature support status, */
 787         /* Force issue enable or disable ras feature commands */
 788         if (head->block != AMDGPU_RAS_BLOCK__GFX &&
 789             !amdgpu_ras_is_feature_allowed(adev, head))
 790                 return 0;
 791
 792         /* Only enable gfx ras feature from host side */
 793         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 794             !amdgpu_sriov_vf(adev) &&
 795             !amdgpu_ras_intr_triggered()) {
 796                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 797                 if (!info)
 798                         return -ENOMEM;
 799
 800                 if (!enable) {
 801                         info->disable_features = (struct ta_ras_disable_features_input) {
 802                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 803                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 804                         };
 805                 } else {
 806                         info->enable_features = (struct ta_ras_enable_features_input) {
 807                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 808                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 809                         };
 810                 }
 811
 812                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 813                 if (ret) {
 814                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 815                                 enable ? "enable":"disable",
 816                                 get_ras_block_str(head),
 817                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 818                         kfree(info);
 819                         return ret;
 820                 }
 821
 822                 kfree(info);
 823         }
 824
 825         /* setup the obj */
 826         __amdgpu_ras_feature_enable(adev, head, enable);
 827
 828         return 0;
 829 }
 830
 831 /* Only used in device probe stage and called only once. */
 832 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 833                 struct ras_common_if *head, bool enable)
 834 {
 835         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 836         int ret;
 837
 838         if (!con)
 839                 return -EINVAL;
 840
 841         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 842                 if (enable) {
 843                         /* There is no harm to issue a ras TA cmd regardless of
 844                          * the currecnt ras state.
 845                          * If current state == target state, it will do nothing
 846                          * But sometimes it requests driver to reset and repost
 847                          * with error code -EAGAIN.
 848                          */
 849                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 850                         /* With old ras TA, we might fail to enable ras.
 851                          * Log it and just setup the object.
 852                          * TODO need remove this WA in the future.
 853                          */
 854                         if (ret == -EINVAL) {
 855                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 856                                 if (!ret)
 857                                         dev_info(adev->dev,
 858                                                 "RAS INFO: %s setup object\n",
 859                                                 get_ras_block_str(head));
 860                         }
 861                 } else {
 862                         /* setup the object then issue a ras TA disable cmd.*/
 863                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 864                         if (ret)
 865                                 return ret;
 866
 867                         /* gfx block ras dsiable cmd must send to ras-ta */
 868                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 869                                 con->features |= BIT(head->block);
 870
 871                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 872
 873                         /* clean gfx block ras features flag */
 874                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 875                                 con->features &= ~BIT(head->block);
 876                 }
 877         } else
 878                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 879
 880         return ret;
 881 }
 882
 883 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 884                 bool bypass)
 885 {
 886         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 887         struct ras_manager *obj, *tmp;
 888
 889         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 890                 /* bypass psp.
 891                  * aka just release the obj and corresponding flags
 892                  */
 893                 if (bypass) {
 894                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 895                                 break;
 896                 } else {
 897                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 898                                 break;
 899                 }
 900         }
 901
 902         return con->features;
 903 }
 904
 905 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 906                 bool bypass)
 907 {
 908         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 909         int i;
 910         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 911
 912         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 913                 struct ras_common_if head = {
 914                         .block = i,
 915                         .type = default_ras_type,
 916                         .sub_block_index = 0,
 917                 };
 918
 919                 if (i == AMDGPU_RAS_BLOCK__MCA)
 920                         continue;
 921
 922                 if (bypass) {
 923                         /*
 924                          * bypass psp. vbios enable ras for us.
 925                          * so just create the obj
 926                          */
 927                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 928                                 break;
 929                 } else {
 930                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 931                                 break;
 932                 }
 933         }
 934
 935         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 936                 struct ras_common_if head = {
 937                         .block = AMDGPU_RAS_BLOCK__MCA,
 938                         .type = default_ras_type,
 939                         .sub_block_index = i,
 940                 };
 941
 942                 if (bypass) {
 943                         /*
 944                          * bypass psp. vbios enable ras for us.
 945                          * so just create the obj
 946                          */
 947                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 948                                 break;
 949                 } else {
 950                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 951                                 break;
 952                 }
 953         }
 954
 955         return con->features;
 956 }
 957 /* feature ctl end */
 958
 959 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 960                 enum amdgpu_ras_block block)
 961 {
 962         if (!block_obj)
 963                 return -EINVAL;
 964
 965         if (block_obj->ras_comm.block == block)
 966                 return 0;
 967
 968         return -EINVAL;
 969 }
 970
 971 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 972                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 973 {
 974         struct amdgpu_ras_block_list *node, *tmp;
 975         struct amdgpu_ras_block_object *obj;
 976
 977         if (block >= AMDGPU_RAS_BLOCK__LAST)
 978                 return NULL;
 979
 980         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 981                 if (!node->ras_obj) {
 982                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 983                         continue;
 984                 }
 985
 986                 obj = node->ras_obj;
 987                 if (obj->ras_block_match) {
 988                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 989                                 return obj;
 990                 } else {
 991                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 992                                 return obj;
 993                 }
 994         }
 995
 996         return NULL;
 997 }
 998
 999 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
1000 {
1001         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1002         int ret = 0;
1003
1004         /*
1005          * choosing right query method according to
1006          * whether smu support query error information
1007          */
1008         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1009         if (ret == -EOPNOTSUPP) {
1010                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1011                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1012                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1013
1014                 /* umc query_ras_error_address is also responsible for clearing
1015                  * error status
1016                  */
1017                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1018                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1019                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1020         } else if (!ret) {
1021                 if (adev->umc.ras &&
1022                         adev->umc.ras->ecc_info_query_ras_error_count)
1023                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1024
1025                 if (adev->umc.ras &&
1026                         adev->umc.ras->ecc_info_query_ras_error_address)
1027                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1028         }
1029 }
1030
1031 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1032                                               struct ras_manager *ras_mgr,
1033                                               struct ras_err_data *err_data,
1034                                               const char *blk_name,
1035                                               bool is_ue)
1036 {
1037         struct amdgpu_smuio_mcm_config_info *mcm_info;
1038         struct ras_err_node *err_node;
1039         struct ras_err_info *err_info;
1040
1041         if (is_ue) {
1042                 for_each_ras_error(err_node, err_data) {
1043                         err_info = &err_node->err_info;
1044                         mcm_info = &err_info->mcm_info;
1045                         if (err_info->ue_count) {
1046                                 dev_info(adev->dev, "socket: %d, die: %d, "
1047                                          "%lld new uncorrectable hardware errors detected in %s block\n",
1048                                          mcm_info->socket_id,
1049                                          mcm_info->die_id,
1050                                          err_info->ue_count,
1051                                          blk_name);
1052                         }
1053                 }
1054
1055                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1056                         err_info = &err_node->err_info;
1057                         mcm_info = &err_info->mcm_info;
1058                         dev_info(adev->dev, "socket: %d, die: %d, "
1059                                  "%lld uncorrectable hardware errors detected in total in %s block\n",
1060                                  mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name);
1061                 }
1062
1063         } else {
1064                 for_each_ras_error(err_node, err_data) {
1065                         err_info = &err_node->err_info;
1066                         mcm_info = &err_info->mcm_info;
1067                         if (err_info->ce_count) {
1068                                 dev_info(adev->dev, "socket: %d, die: %d, "
1069                                          "%lld new correctable hardware errors detected in %s block, "
1070                                          "no user action is needed\n",
1071                                          mcm_info->socket_id,
1072                                          mcm_info->die_id,
1073                                          err_info->ce_count,
1074                                          blk_name);
1075                         }
1076                 }
1077
1078                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1079                         err_info = &err_node->err_info;
1080                         mcm_info = &err_info->mcm_info;
1081                         dev_info(adev->dev, "socket: %d, die: %d, "
1082                                  "%lld correctable hardware errors detected in total in %s block, "
1083                                  "no user action is needed\n",
1084                                  mcm_info->socket_id, mcm_info->die_id, err_info->ce_count, blk_name);
1085                 }
1086         }
1087 }
1088
1089 static inline bool err_data_has_source_info(struct ras_err_data *data)
1090 {
1091         return !list_empty(&data->err_node_list);
1092 }
1093
1094 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1095                                              struct ras_query_if *query_if,
1096                                              struct ras_err_data *err_data)
1097 {
1098         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1099         const char *blk_name = get_ras_block_str(&query_if->head);
1100
1101         if (err_data->ce_count) {
1102                 if (err_data_has_source_info(err_data)) {
1103                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, false);
1104                 } else if (!adev->aid_mask &&
1105                            adev->smuio.funcs &&
1106                            adev->smuio.funcs->get_socket_id &&
1107                            adev->smuio.funcs->get_die_id) {
1108                         dev_info(adev->dev, "socket: %d, die: %d "
1109                                  "%ld correctable hardware errors "
1110                                  "detected in %s block, no user "
1111                                  "action is needed.\n",
1112                                  adev->smuio.funcs->get_socket_id(adev),
1113                                  adev->smuio.funcs->get_die_id(adev),
1114                                  ras_mgr->err_data.ce_count,
1115                                  blk_name);
1116                 } else {
1117                         dev_info(adev->dev, "%ld correctable hardware errors "
1118                                  "detected in %s block, no user "
1119                                  "action is needed.\n",
1120                                  ras_mgr->err_data.ce_count,
1121                                  blk_name);
1122                 }
1123         }
1124
1125         if (err_data->ue_count) {
1126                 if (err_data_has_source_info(err_data)) {
1127                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, true);
1128                 } else if (!adev->aid_mask &&
1129                            adev->smuio.funcs &&
1130                            adev->smuio.funcs->get_socket_id &&
1131                            adev->smuio.funcs->get_die_id) {
1132                         dev_info(adev->dev, "socket: %d, die: %d "
1133                                  "%ld uncorrectable hardware errors "
1134                                  "detected in %s block\n",
1135                                  adev->smuio.funcs->get_socket_id(adev),
1136                                  adev->smuio.funcs->get_die_id(adev),
1137                                  ras_mgr->err_data.ue_count,
1138                                  blk_name);
1139                 } else {
1140                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1141                                  "detected in %s block\n",
1142                                  ras_mgr->err_data.ue_count,
1143                                  blk_name);
1144                 }
1145         }
1146
1147 }
1148
1149 static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1150 {
1151         struct ras_err_node *err_node;
1152         struct ras_err_info *err_info;
1153
1154         if (err_data_has_source_info(err_data)) {
1155                 for_each_ras_error(err_node, err_data) {
1156                         err_info = &err_node->err_info;
1157
1158                         amdgpu_ras_error_statistic_ce_count(&obj->err_data, &err_info->mcm_info, err_info->ce_count);
1159                         amdgpu_ras_error_statistic_ue_count(&obj->err_data, &err_info->mcm_info, err_info->ue_count);
1160                 }
1161         } else {
1162                 /* for legacy asic path which doesn't has error source info */
1163                 obj->err_data.ue_count += err_data->ue_count;
1164                 obj->err_data.ce_count += err_data->ce_count;
1165         }
1166 }
1167
1168 /* query/inject/cure begin */
1169 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
1170                                   struct ras_query_if *info)
1171 {
1172         struct amdgpu_ras_block_object *block_obj = NULL;
1173         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1174         struct ras_err_data err_data;
1175         int ret;
1176
1177         if (!obj)
1178                 return -EINVAL;
1179
1180         ret = amdgpu_ras_error_data_init(&err_data);
1181         if (ret)
1182                 return ret;
1183
1184         if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1185                 amdgpu_ras_get_ecc_info(adev, &err_data);
1186         } else {
1187                 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1188                 if (!block_obj || !block_obj->hw_ops)   {
1189                         dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1190                                      get_ras_block_str(&info->head));
1191                         ret = -EINVAL;
1192                         goto out_fini_err_data;
1193                 }
1194
1195                 if (block_obj->hw_ops->query_ras_error_count)
1196                         block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1197
1198                 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1199                     (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1200                     (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1201                                 if (block_obj->hw_ops->query_ras_error_status)
1202                                         block_obj->hw_ops->query_ras_error_status(adev);
1203                         }
1204         }
1205
1206         amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
1207
1208         info->ue_count = obj->err_data.ue_count;
1209         info->ce_count = obj->err_data.ce_count;
1210
1211         amdgpu_ras_error_generate_report(adev, info, &err_data);
1212
1213 out_fini_err_data:
1214         amdgpu_ras_error_data_fini(&err_data);
1215
1216         return ret;
1217 }
1218
1219 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
1220                 enum amdgpu_ras_block block)
1221 {
1222         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1223         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1224         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
1225
1226         if (!block_obj || !block_obj->hw_ops) {
1227                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1228                                 ras_block_str(block));
1229                 return -EOPNOTSUPP;
1230         }
1231
1232         /* skip ras error reset in gpu reset */
1233         if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery)) &&
1234             mca_funcs && mca_funcs->mca_set_debug_mode)
1235                 return -EOPNOTSUPP;
1236
1237         if (!amdgpu_ras_is_supported(adev, block) ||
1238             !amdgpu_ras_get_mca_debug_mode(adev))
1239                 return -EOPNOTSUPP;
1240
1241         if (block_obj->hw_ops->reset_ras_error_count)
1242                 block_obj->hw_ops->reset_ras_error_count(adev);
1243
1244         return 0;
1245 }
1246
1247 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1248                 enum amdgpu_ras_block block)
1249 {
1250         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1251
1252         if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1253                 return 0;
1254
1255         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1256             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1257                 if (block_obj->hw_ops->reset_ras_error_status)
1258                         block_obj->hw_ops->reset_ras_error_status(adev);
1259         }
1260
1261         return 0;
1262 }
1263
1264 /* wrapper of psp_ras_trigger_error */
1265 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1266                 struct ras_inject_if *info)
1267 {
1268         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1269         struct ta_ras_trigger_error_input block_info = {
1270                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1271                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1272                 .sub_block_index = info->head.sub_block_index,
1273                 .address = info->address,
1274                 .value = info->value,
1275         };
1276         int ret = -EINVAL;
1277         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1278                                                         info->head.block,
1279                                                         info->head.sub_block_index);
1280
1281         /* inject on guest isn't allowed, return success directly */
1282         if (amdgpu_sriov_vf(adev))
1283                 return 0;
1284
1285         if (!obj)
1286                 return -EINVAL;
1287
1288         if (!block_obj || !block_obj->hw_ops)   {
1289                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1290                              get_ras_block_str(&info->head));
1291                 return -EINVAL;
1292         }
1293
1294         /* Calculate XGMI relative offset */
1295         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1296             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1297                 block_info.address =
1298                         amdgpu_xgmi_get_relative_phy_addr(adev,
1299                                                           block_info.address);
1300         }
1301
1302         if (block_obj->hw_ops->ras_error_inject) {
1303                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1304                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1305                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1306                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1307                                                 info->instance_mask);
1308         } else {
1309                 /* default path */
1310                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1311         }
1312
1313         if (ret)
1314                 dev_err(adev->dev, "ras inject %s failed %d\n",
1315                         get_ras_block_str(&info->head), ret);
1316
1317         return ret;
1318 }
1319
1320 /**
1321  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1322  * @adev: pointer to AMD GPU device
1323  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1324  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1325  * @query_info: pointer to ras_query_if
1326  *
1327  * Return 0 for query success or do nothing, otherwise return an error
1328  * on failures
1329  */
1330 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1331                                                unsigned long *ce_count,
1332                                                unsigned long *ue_count,
1333                                                struct ras_query_if *query_info)
1334 {
1335         int ret;
1336
1337         if (!query_info)
1338                 /* do nothing if query_info is not specified */
1339                 return 0;
1340
1341         ret = amdgpu_ras_query_error_status(adev, query_info);
1342         if (ret)
1343                 return ret;
1344
1345         *ce_count += query_info->ce_count;
1346         *ue_count += query_info->ue_count;
1347
1348         /* some hardware/IP supports read to clear
1349          * no need to explictly reset the err status after the query call */
1350         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1351             amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1352                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1353                         dev_warn(adev->dev,
1354                                  "Failed to reset error counter and error status\n");
1355         }
1356
1357         return 0;
1358 }
1359
1360 /**
1361  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1362  * @adev: pointer to AMD GPU device
1363  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1364  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1365  * errors.
1366  * @query_info: pointer to ras_query_if if the query request is only for
1367  * specific ip block; if info is NULL, then the qurey request is for
1368  * all the ip blocks that support query ras error counters/status
1369  *
1370  * If set, @ce_count or @ue_count, count and return the corresponding
1371  * error counts in those integer pointers. Return 0 if the device
1372  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1373  */
1374 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1375                                  unsigned long *ce_count,
1376                                  unsigned long *ue_count,
1377                                  struct ras_query_if *query_info)
1378 {
1379         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1380         struct ras_manager *obj;
1381         unsigned long ce, ue;
1382         int ret;
1383
1384         if (!adev->ras_enabled || !con)
1385                 return -EOPNOTSUPP;
1386
1387         /* Don't count since no reporting.
1388          */
1389         if (!ce_count && !ue_count)
1390                 return 0;
1391
1392         ce = 0;
1393         ue = 0;
1394         if (!query_info) {
1395                 /* query all the ip blocks that support ras query interface */
1396                 list_for_each_entry(obj, &con->head, node) {
1397                         struct ras_query_if info = {
1398                                 .head = obj->head,
1399                         };
1400
1401                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1402                 }
1403         } else {
1404                 /* query specific ip block */
1405                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1406         }
1407
1408         if (ret)
1409                 return ret;
1410
1411         if (ce_count)
1412                 *ce_count = ce;
1413
1414         if (ue_count)
1415                 *ue_count = ue;
1416
1417         return 0;
1418 }
1419 /* query/inject/cure end */
1420
1421
1422 /* sysfs begin */
1423
1424 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1425                 struct ras_badpage **bps, unsigned int *count);
1426
1427 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1428 {
1429         switch (flags) {
1430         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1431                 return "R";
1432         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1433                 return "P";
1434         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1435         default:
1436                 return "F";
1437         }
1438 }
1439
1440 /**
1441  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1442  *
1443  * It allows user to read the bad pages of vram on the gpu through
1444  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1445  *
1446  * It outputs multiple lines, and each line stands for one gpu page.
1447  *
1448  * The format of one line is below,
1449  * gpu pfn : gpu page size : flags
1450  *
1451  * gpu pfn and gpu page size are printed in hex format.
1452  * flags can be one of below character,
1453  *
1454  * R: reserved, this gpu page is reserved and not able to use.
1455  *
1456  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1457  * in next window of page_reserve.
1458  *
1459  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1460  *
1461  * Examples:
1462  *
1463  * .. code-block:: bash
1464  *
1465  *      0x00000001 : 0x00001000 : R
1466  *      0x00000002 : 0x00001000 : P
1467  *
1468  */
1469
1470 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1471                 struct kobject *kobj, struct bin_attribute *attr,
1472                 char *buf, loff_t ppos, size_t count)
1473 {
1474         struct amdgpu_ras *con =
1475                 container_of(attr, struct amdgpu_ras, badpages_attr);
1476         struct amdgpu_device *adev = con->adev;
1477         const unsigned int element_size =
1478                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1479         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1480         unsigned int end = div64_ul(ppos + count - 1, element_size);
1481         ssize_t s = 0;
1482         struct ras_badpage *bps = NULL;
1483         unsigned int bps_count = 0;
1484
1485         memset(buf, 0, count);
1486
1487         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1488                 return 0;
1489
1490         for (; start < end && start < bps_count; start++)
1491                 s += scnprintf(&buf[s], element_size + 1,
1492                                 "0x%08x : 0x%08x : %1s\n",
1493                                 bps[start].bp,
1494                                 bps[start].size,
1495                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1496
1497         kfree(bps);
1498
1499         return s;
1500 }
1501
1502 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1503                 struct device_attribute *attr, char *buf)
1504 {
1505         struct amdgpu_ras *con =
1506                 container_of(attr, struct amdgpu_ras, features_attr);
1507
1508         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1509 }
1510
1511 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1512                 struct device_attribute *attr, char *buf)
1513 {
1514         struct amdgpu_ras *con =
1515                 container_of(attr, struct amdgpu_ras, version_attr);
1516         return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1517 }
1518
1519 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1520                 struct device_attribute *attr, char *buf)
1521 {
1522         struct amdgpu_ras *con =
1523                 container_of(attr, struct amdgpu_ras, schema_attr);
1524         return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1525 }
1526
1527 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1528 {
1529         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1530
1531         sysfs_remove_file_from_group(&adev->dev->kobj,
1532                                 &con->badpages_attr.attr,
1533                                 RAS_FS_NAME);
1534 }
1535
1536 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1537 {
1538         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1539         struct attribute *attrs[] = {
1540                 &con->features_attr.attr,
1541                 &con->version_attr.attr,
1542                 &con->schema_attr.attr,
1543                 NULL
1544         };
1545         struct attribute_group group = {
1546                 .name = RAS_FS_NAME,
1547                 .attrs = attrs,
1548         };
1549
1550         sysfs_remove_group(&adev->dev->kobj, &group);
1551
1552         return 0;
1553 }
1554
1555 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1556                 struct ras_common_if *head)
1557 {
1558         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1559
1560         if (!obj || obj->attr_inuse)
1561                 return -EINVAL;
1562
1563         get_obj(obj);
1564
1565         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1566                 "%s_err_count", head->name);
1567
1568         obj->sysfs_attr = (struct device_attribute){
1569                 .attr = {
1570                         .name = obj->fs_data.sysfs_name,
1571                         .mode = S_IRUGO,
1572                 },
1573                         .show = amdgpu_ras_sysfs_read,
1574         };
1575         sysfs_attr_init(&obj->sysfs_attr.attr);
1576
1577         if (sysfs_add_file_to_group(&adev->dev->kobj,
1578                                 &obj->sysfs_attr.attr,
1579                                 RAS_FS_NAME)) {
1580                 put_obj(obj);
1581                 return -EINVAL;
1582         }
1583
1584         obj->attr_inuse = 1;
1585
1586         return 0;
1587 }
1588
1589 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1590                 struct ras_common_if *head)
1591 {
1592         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1593
1594         if (!obj || !obj->attr_inuse)
1595                 return -EINVAL;
1596
1597         sysfs_remove_file_from_group(&adev->dev->kobj,
1598                                 &obj->sysfs_attr.attr,
1599                                 RAS_FS_NAME);
1600         obj->attr_inuse = 0;
1601         put_obj(obj);
1602
1603         return 0;
1604 }
1605
1606 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1607 {
1608         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1609         struct ras_manager *obj, *tmp;
1610
1611         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1612                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1613         }
1614
1615         if (amdgpu_bad_page_threshold != 0)
1616                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1617
1618         amdgpu_ras_sysfs_remove_dev_attr_node(adev);
1619
1620         return 0;
1621 }
1622 /* sysfs end */
1623
1624 /**
1625  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1626  *
1627  * Normally when there is an uncorrectable error, the driver will reset
1628  * the GPU to recover.  However, in the event of an unrecoverable error,
1629  * the driver provides an interface to reboot the system automatically
1630  * in that event.
1631  *
1632  * The following file in debugfs provides that interface:
1633  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1634  *
1635  * Usage:
1636  *
1637  * .. code-block:: bash
1638  *
1639  *      echo true > .../ras/auto_reboot
1640  *
1641  */
1642 /* debugfs begin */
1643 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1644 {
1645         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1646         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1647         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1648         struct dentry     *dir;
1649
1650         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1651         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1652                             &amdgpu_ras_debugfs_ctrl_ops);
1653         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1654                             &amdgpu_ras_debugfs_eeprom_ops);
1655         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1656                            &con->bad_page_cnt_threshold);
1657         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1658         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1659         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1660         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1661                             &amdgpu_ras_debugfs_eeprom_size_ops);
1662         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1663                                                        S_IRUGO, dir, adev,
1664                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1665         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1666
1667         /*
1668          * After one uncorrectable error happens, usually GPU recovery will
1669          * be scheduled. But due to the known problem in GPU recovery failing
1670          * to bring GPU back, below interface provides one direct way to
1671          * user to reboot system automatically in such case within
1672          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1673          * will never be called.
1674          */
1675         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1676
1677         /*
1678          * User could set this not to clean up hardware's error count register
1679          * of RAS IPs during ras recovery.
1680          */
1681         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1682                             &con->disable_ras_err_cnt_harvest);
1683         return dir;
1684 }
1685
1686 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1687                                       struct ras_fs_if *head,
1688                                       struct dentry *dir)
1689 {
1690         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1691
1692         if (!obj || !dir)
1693                 return;
1694
1695         get_obj(obj);
1696
1697         memcpy(obj->fs_data.debugfs_name,
1698                         head->debugfs_name,
1699                         sizeof(obj->fs_data.debugfs_name));
1700
1701         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1702                             obj, &amdgpu_ras_debugfs_ops);
1703 }
1704
1705 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1706 {
1707         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1708         struct dentry *dir;
1709         struct ras_manager *obj;
1710         struct ras_fs_if fs_info;
1711
1712         /*
1713          * it won't be called in resume path, no need to check
1714          * suspend and gpu reset status
1715          */
1716         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1717                 return;
1718
1719         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1720
1721         list_for_each_entry(obj, &con->head, node) {
1722                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1723                         (obj->attr_inuse == 1)) {
1724                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1725                                         get_ras_block_str(&obj->head));
1726                         fs_info.head = obj->head;
1727                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1728                 }
1729         }
1730
1731         amdgpu_mca_smu_debugfs_init(adev, dir);
1732 }
1733
1734 /* debugfs end */
1735
1736 /* ras fs */
1737 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1738                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1739 static DEVICE_ATTR(features, S_IRUGO,
1740                 amdgpu_ras_sysfs_features_read, NULL);
1741 static DEVICE_ATTR(version, 0444,
1742                 amdgpu_ras_sysfs_version_show, NULL);
1743 static DEVICE_ATTR(schema, 0444,
1744                 amdgpu_ras_sysfs_schema_show, NULL);
1745 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1746 {
1747         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1748         struct attribute_group group = {
1749                 .name = RAS_FS_NAME,
1750         };
1751         struct attribute *attrs[] = {
1752                 &con->features_attr.attr,
1753                 &con->version_attr.attr,
1754                 &con->schema_attr.attr,
1755                 NULL
1756         };
1757         struct bin_attribute *bin_attrs[] = {
1758                 NULL,
1759                 NULL,
1760         };
1761         int r;
1762
1763         group.attrs = attrs;
1764
1765         /* add features entry */
1766         con->features_attr = dev_attr_features;
1767         sysfs_attr_init(attrs[0]);
1768
1769         /* add version entry */
1770         con->version_attr = dev_attr_version;
1771         sysfs_attr_init(attrs[1]);
1772
1773         /* add schema entry */
1774         con->schema_attr = dev_attr_schema;
1775         sysfs_attr_init(attrs[2]);
1776
1777         if (amdgpu_bad_page_threshold != 0) {
1778                 /* add bad_page_features entry */
1779                 bin_attr_gpu_vram_bad_pages.private = NULL;
1780                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1781                 bin_attrs[0] = &con->badpages_attr;
1782                 group.bin_attrs = bin_attrs;
1783                 sysfs_bin_attr_init(bin_attrs[0]);
1784         }
1785
1786         r = sysfs_create_group(&adev->dev->kobj, &group);
1787         if (r)
1788                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1789
1790         return 0;
1791 }
1792
1793 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1794 {
1795         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1796         struct ras_manager *con_obj, *ip_obj, *tmp;
1797
1798         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1799                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1800                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1801                         if (ip_obj)
1802                                 put_obj(ip_obj);
1803                 }
1804         }
1805
1806         amdgpu_ras_sysfs_remove_all(adev);
1807         return 0;
1808 }
1809 /* ras fs end */
1810
1811 /* ih begin */
1812
1813 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1814  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1815  * register to check whether the interrupt is triggered or not, and properly
1816  * ack the interrupt if it is there
1817  */
1818 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1819 {
1820         /* Fatal error events are handled on host side */
1821         if (amdgpu_sriov_vf(adev))
1822                 return;
1823
1824         if (adev->nbio.ras &&
1825             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1826                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1827
1828         if (adev->nbio.ras &&
1829             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1830                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1831 }
1832
1833 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1834                                 struct amdgpu_iv_entry *entry)
1835 {
1836         bool poison_stat = false;
1837         struct amdgpu_device *adev = obj->adev;
1838         struct amdgpu_ras_block_object *block_obj =
1839                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1840
1841         if (!block_obj)
1842                 return;
1843
1844         /* both query_poison_status and handle_poison_consumption are optional,
1845          * but at least one of them should be implemented if we need poison
1846          * consumption handler
1847          */
1848         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1849                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1850                 if (!poison_stat) {
1851                         /* Not poison consumption interrupt, no need to handle it */
1852                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1853                                         block_obj->ras_comm.name);
1854
1855                         return;
1856                 }
1857         }
1858
1859         amdgpu_umc_poison_handler(adev, false);
1860
1861         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1862                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1863
1864         /* gpu reset is fallback for failed and default cases */
1865         if (poison_stat) {
1866                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1867                                 block_obj->ras_comm.name);
1868                 amdgpu_ras_reset_gpu(adev);
1869         } else {
1870                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1871         }
1872 }
1873
1874 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1875                                 struct amdgpu_iv_entry *entry)
1876 {
1877         dev_info(obj->adev->dev,
1878                 "Poison is created, no user action is needed.\n");
1879 }
1880
1881 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1882                                 struct amdgpu_iv_entry *entry)
1883 {
1884         struct ras_ih_data *data = &obj->ih_data;
1885         struct ras_err_data err_data;
1886         int ret;
1887
1888         if (!data->cb)
1889                 return;
1890
1891         ret = amdgpu_ras_error_data_init(&err_data);
1892         if (ret)
1893                 return;
1894
1895         /* Let IP handle its data, maybe we need get the output
1896          * from the callback to update the error type/count, etc
1897          */
1898         ret = data->cb(obj->adev, &err_data, entry);
1899         /* ue will trigger an interrupt, and in that case
1900          * we need do a reset to recovery the whole system.
1901          * But leave IP do that recovery, here we just dispatch
1902          * the error.
1903          */
1904         if (ret == AMDGPU_RAS_SUCCESS) {
1905                 /* these counts could be left as 0 if
1906                  * some blocks do not count error number
1907                  */
1908                 obj->err_data.ue_count += err_data.ue_count;
1909                 obj->err_data.ce_count += err_data.ce_count;
1910         }
1911
1912         amdgpu_ras_error_data_fini(&err_data);
1913 }
1914
1915 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1916 {
1917         struct ras_ih_data *data = &obj->ih_data;
1918         struct amdgpu_iv_entry entry;
1919
1920         while (data->rptr != data->wptr) {
1921                 rmb();
1922                 memcpy(&entry, &data->ring[data->rptr],
1923                                 data->element_size);
1924
1925                 wmb();
1926                 data->rptr = (data->aligned_element_size +
1927                                 data->rptr) % data->ring_size;
1928
1929                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1930                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1931                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1932                         else
1933                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1934                 } else {
1935                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1936                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1937                         else
1938                                 dev_warn(obj->adev->dev,
1939                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1940                 }
1941         }
1942 }
1943
1944 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1945 {
1946         struct ras_ih_data *data =
1947                 container_of(work, struct ras_ih_data, ih_work);
1948         struct ras_manager *obj =
1949                 container_of(data, struct ras_manager, ih_data);
1950
1951         amdgpu_ras_interrupt_handler(obj);
1952 }
1953
1954 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1955                 struct ras_dispatch_if *info)
1956 {
1957         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1958         struct ras_ih_data *data = &obj->ih_data;
1959
1960         if (!obj)
1961                 return -EINVAL;
1962
1963         if (data->inuse == 0)
1964                 return 0;
1965
1966         /* Might be overflow... */
1967         memcpy(&data->ring[data->wptr], info->entry,
1968                         data->element_size);
1969
1970         wmb();
1971         data->wptr = (data->aligned_element_size +
1972                         data->wptr) % data->ring_size;
1973
1974         schedule_work(&data->ih_work);
1975
1976         return 0;
1977 }
1978
1979 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1980                 struct ras_common_if *head)
1981 {
1982         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1983         struct ras_ih_data *data;
1984
1985         if (!obj)
1986                 return -EINVAL;
1987
1988         data = &obj->ih_data;
1989         if (data->inuse == 0)
1990                 return 0;
1991
1992         cancel_work_sync(&data->ih_work);
1993
1994         kfree(data->ring);
1995         memset(data, 0, sizeof(*data));
1996         put_obj(obj);
1997
1998         return 0;
1999 }
2000
2001 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
2002                 struct ras_common_if *head)
2003 {
2004         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2005         struct ras_ih_data *data;
2006         struct amdgpu_ras_block_object *ras_obj;
2007
2008         if (!obj) {
2009                 /* in case we registe the IH before enable ras feature */
2010                 obj = amdgpu_ras_create_obj(adev, head);
2011                 if (!obj)
2012                         return -EINVAL;
2013         } else
2014                 get_obj(obj);
2015
2016         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
2017
2018         data = &obj->ih_data;
2019         /* add the callback.etc */
2020         *data = (struct ras_ih_data) {
2021                 .inuse = 0,
2022                 .cb = ras_obj->ras_cb,
2023                 .element_size = sizeof(struct amdgpu_iv_entry),
2024                 .rptr = 0,
2025                 .wptr = 0,
2026         };
2027
2028         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
2029
2030         data->aligned_element_size = ALIGN(data->element_size, 8);
2031         /* the ring can store 64 iv entries. */
2032         data->ring_size = 64 * data->aligned_element_size;
2033         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
2034         if (!data->ring) {
2035                 put_obj(obj);
2036                 return -ENOMEM;
2037         }
2038
2039         /* IH is ready */
2040         data->inuse = 1;
2041
2042         return 0;
2043 }
2044
2045 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
2046 {
2047         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2048         struct ras_manager *obj, *tmp;
2049
2050         list_for_each_entry_safe(obj, tmp, &con->head, node) {
2051                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
2052         }
2053
2054         return 0;
2055 }
2056 /* ih end */
2057
2058 /* traversal all IPs except NBIO to query error counter */
2059 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
2060 {
2061         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2062         struct ras_manager *obj;
2063
2064         if (!adev->ras_enabled || !con)
2065                 return;
2066
2067         list_for_each_entry(obj, &con->head, node) {
2068                 struct ras_query_if info = {
2069                         .head = obj->head,
2070                 };
2071
2072                 /*
2073                  * PCIE_BIF IP has one different isr by ras controller
2074                  * interrupt, the specific ras counter query will be
2075                  * done in that isr. So skip such block from common
2076                  * sync flood interrupt isr calling.
2077                  */
2078                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2079                         continue;
2080
2081                 /*
2082                  * this is a workaround for aldebaran, skip send msg to
2083                  * smu to get ecc_info table due to smu handle get ecc
2084                  * info table failed temporarily.
2085                  * should be removed until smu fix handle ecc_info table.
2086                  */
2087                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2088                     (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2089                      IP_VERSION(13, 0, 2)))
2090                         continue;
2091
2092                 amdgpu_ras_query_error_status(adev, &info);
2093
2094                 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2095                             IP_VERSION(11, 0, 2) &&
2096                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2097                             IP_VERSION(11, 0, 4) &&
2098                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2099                             IP_VERSION(13, 0, 0)) {
2100                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
2101                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
2102                 }
2103         }
2104 }
2105
2106 /* Parse RdRspStatus and WrRspStatus */
2107 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2108                                           struct ras_query_if *info)
2109 {
2110         struct amdgpu_ras_block_object *block_obj;
2111         /*
2112          * Only two block need to query read/write
2113          * RspStatus at current state
2114          */
2115         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2116                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2117                 return;
2118
2119         block_obj = amdgpu_ras_get_ras_block(adev,
2120                                         info->head.block,
2121                                         info->head.sub_block_index);
2122
2123         if (!block_obj || !block_obj->hw_ops) {
2124                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2125                              get_ras_block_str(&info->head));
2126                 return;
2127         }
2128
2129         if (block_obj->hw_ops->query_ras_error_status)
2130                 block_obj->hw_ops->query_ras_error_status(adev);
2131
2132 }
2133
2134 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2135 {
2136         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2137         struct ras_manager *obj;
2138
2139         if (!adev->ras_enabled || !con)
2140                 return;
2141
2142         list_for_each_entry(obj, &con->head, node) {
2143                 struct ras_query_if info = {
2144                         .head = obj->head,
2145                 };
2146
2147                 amdgpu_ras_error_status_query(adev, &info);
2148         }
2149 }
2150
2151 /* recovery begin */
2152
2153 /* return 0 on success.
2154  * caller need free bps.
2155  */
2156 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2157                 struct ras_badpage **bps, unsigned int *count)
2158 {
2159         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2160         struct ras_err_handler_data *data;
2161         int i = 0;
2162         int ret = 0, status;
2163
2164         if (!con || !con->eh_data || !bps || !count)
2165                 return -EINVAL;
2166
2167         mutex_lock(&con->recovery_lock);
2168         data = con->eh_data;
2169         if (!data || data->count == 0) {
2170                 *bps = NULL;
2171                 ret = -EINVAL;
2172                 goto out;
2173         }
2174
2175         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2176         if (!*bps) {
2177                 ret = -ENOMEM;
2178                 goto out;
2179         }
2180
2181         for (; i < data->count; i++) {
2182                 (*bps)[i] = (struct ras_badpage){
2183                         .bp = data->bps[i].retired_page,
2184                         .size = AMDGPU_GPU_PAGE_SIZE,
2185                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2186                 };
2187                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2188                                 data->bps[i].retired_page);
2189                 if (status == -EBUSY)
2190                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2191                 else if (status == -ENOENT)
2192                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2193         }
2194
2195         *count = data->count;
2196 out:
2197         mutex_unlock(&con->recovery_lock);
2198         return ret;
2199 }
2200
2201 static void amdgpu_ras_do_recovery(struct work_struct *work)
2202 {
2203         struct amdgpu_ras *ras =
2204                 container_of(work, struct amdgpu_ras, recovery_work);
2205         struct amdgpu_device *remote_adev = NULL;
2206         struct amdgpu_device *adev = ras->adev;
2207         struct list_head device_list, *device_list_handle =  NULL;
2208         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2209
2210         if (hive)
2211                 atomic_set(&hive->ras_recovery, 1);
2212         if (!ras->disable_ras_err_cnt_harvest) {
2213
2214                 /* Build list of devices to query RAS related errors */
2215                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2216                         device_list_handle = &hive->device_list;
2217                 } else {
2218                         INIT_LIST_HEAD(&device_list);
2219                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2220                         device_list_handle = &device_list;
2221                 }
2222
2223                 list_for_each_entry(remote_adev,
2224                                 device_list_handle, gmc.xgmi.head) {
2225                         amdgpu_ras_query_err_status(remote_adev);
2226                         amdgpu_ras_log_on_err_counter(remote_adev);
2227                 }
2228
2229         }
2230
2231         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2232                 struct amdgpu_reset_context reset_context;
2233                 memset(&reset_context, 0, sizeof(reset_context));
2234
2235                 reset_context.method = AMD_RESET_METHOD_NONE;
2236                 reset_context.reset_req_dev = adev;
2237
2238                 /* Perform full reset in fatal error mode */
2239                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2240                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2241                 else {
2242                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2243
2244                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2245                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2246                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2247                         }
2248
2249                         /* Fatal error occurs in poison mode, mode1 reset is used to
2250                          * recover gpu.
2251                          */
2252                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2253                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2254                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2255
2256                                 psp_fatal_error_recovery_quirk(&adev->psp);
2257                         }
2258                 }
2259
2260                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2261         }
2262         atomic_set(&ras->in_recovery, 0);
2263         if (hive) {
2264                 atomic_set(&hive->ras_recovery, 0);
2265                 amdgpu_put_xgmi_hive(hive);
2266         }
2267 }
2268
2269 /* alloc/realloc bps array */
2270 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2271                 struct ras_err_handler_data *data, int pages)
2272 {
2273         unsigned int old_space = data->count + data->space_left;
2274         unsigned int new_space = old_space + pages;
2275         unsigned int align_space = ALIGN(new_space, 512);
2276         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2277
2278         if (!bps) {
2279                 return -ENOMEM;
2280         }
2281
2282         if (data->bps) {
2283                 memcpy(bps, data->bps,
2284                                 data->count * sizeof(*data->bps));
2285                 kfree(data->bps);
2286         }
2287
2288         data->bps = bps;
2289         data->space_left += align_space - old_space;
2290         return 0;
2291 }
2292
2293 /* it deal with vram only. */
2294 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2295                 struct eeprom_table_record *bps, int pages)
2296 {
2297         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2298         struct ras_err_handler_data *data;
2299         int ret = 0;
2300         uint32_t i;
2301
2302         if (!con || !con->eh_data || !bps || pages <= 0)
2303                 return 0;
2304
2305         mutex_lock(&con->recovery_lock);
2306         data = con->eh_data;
2307         if (!data)
2308                 goto out;
2309
2310         for (i = 0; i < pages; i++) {
2311                 if (amdgpu_ras_check_bad_page_unlock(con,
2312                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2313                         continue;
2314
2315                 if (!data->space_left &&
2316                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2317                         ret = -ENOMEM;
2318                         goto out;
2319                 }
2320
2321                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2322                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2323                         AMDGPU_GPU_PAGE_SIZE);
2324
2325                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2326                 data->count++;
2327                 data->space_left--;
2328         }
2329 out:
2330         mutex_unlock(&con->recovery_lock);
2331
2332         return ret;
2333 }
2334
2335 /*
2336  * write error record array to eeprom, the function should be
2337  * protected by recovery_lock
2338  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2339  */
2340 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2341                 unsigned long *new_cnt)
2342 {
2343         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2344         struct ras_err_handler_data *data;
2345         struct amdgpu_ras_eeprom_control *control;
2346         int save_count;
2347
2348         if (!con || !con->eh_data) {
2349                 if (new_cnt)
2350                         *new_cnt = 0;
2351
2352                 return 0;
2353         }
2354
2355         mutex_lock(&con->recovery_lock);
2356         control = &con->eeprom_control;
2357         data = con->eh_data;
2358         save_count = data->count - control->ras_num_recs;
2359         mutex_unlock(&con->recovery_lock);
2360
2361         if (new_cnt)
2362                 *new_cnt = save_count / adev->umc.retire_unit;
2363
2364         /* only new entries are saved */
2365         if (save_count > 0) {
2366                 if (amdgpu_ras_eeprom_append(control,
2367                                              &data->bps[control->ras_num_recs],
2368                                              save_count)) {
2369                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2370                         return -EIO;
2371                 }
2372
2373                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2374         }
2375
2376         return 0;
2377 }
2378
2379 /*
2380  * read error record array in eeprom and reserve enough space for
2381  * storing new bad pages
2382  */
2383 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2384 {
2385         struct amdgpu_ras_eeprom_control *control =
2386                 &adev->psp.ras_context.ras->eeprom_control;
2387         struct eeprom_table_record *bps;
2388         int ret;
2389
2390         /* no bad page record, skip eeprom access */
2391         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2392                 return 0;
2393
2394         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2395         if (!bps)
2396                 return -ENOMEM;
2397
2398         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2399         if (ret)
2400                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2401         else
2402                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2403
2404         kfree(bps);
2405         return ret;
2406 }
2407
2408 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2409                                 uint64_t addr)
2410 {
2411         struct ras_err_handler_data *data = con->eh_data;
2412         int i;
2413
2414         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2415         for (i = 0; i < data->count; i++)
2416                 if (addr == data->bps[i].retired_page)
2417                         return true;
2418
2419         return false;
2420 }
2421
2422 /*
2423  * check if an address belongs to bad page
2424  *
2425  * Note: this check is only for umc block
2426  */
2427 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2428                                 uint64_t addr)
2429 {
2430         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2431         bool ret = false;
2432
2433         if (!con || !con->eh_data)
2434                 return ret;
2435
2436         mutex_lock(&con->recovery_lock);
2437         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2438         mutex_unlock(&con->recovery_lock);
2439         return ret;
2440 }
2441
2442 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2443                                           uint32_t max_count)
2444 {
2445         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2446
2447         /*
2448          * Justification of value bad_page_cnt_threshold in ras structure
2449          *
2450          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2451          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2452          * scenarios accordingly.
2453          *
2454          * Bad page retirement enablement:
2455          *    - If amdgpu_bad_page_threshold = -2,
2456          *      bad_page_cnt_threshold = typical value by formula.
2457          *
2458          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2459          *      max record length in eeprom, use it directly.
2460          *
2461          * Bad page retirement disablement:
2462          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2463          *      functionality is disabled, and bad_page_cnt_threshold will
2464          *      take no effect.
2465          */
2466
2467         if (amdgpu_bad_page_threshold < 0) {
2468                 u64 val = adev->gmc.mc_vram_size;
2469
2470                 do_div(val, RAS_BAD_PAGE_COVER);
2471                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2472                                                   max_count);
2473         } else {
2474                 con->bad_page_cnt_threshold = min_t(int, max_count,
2475                                                     amdgpu_bad_page_threshold);
2476         }
2477 }
2478
2479 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2480 {
2481         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2482         struct ras_err_handler_data **data;
2483         u32  max_eeprom_records_count = 0;
2484         bool exc_err_limit = false;
2485         int ret;
2486
2487         if (!con || amdgpu_sriov_vf(adev))
2488                 return 0;
2489
2490         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2491          * supports RAS and debugfs is enabled, but when
2492          * adev->ras_enabled is unset, i.e. when "ras_enable"
2493          * module parameter is set to 0.
2494          */
2495         con->adev = adev;
2496
2497         if (!adev->ras_enabled)
2498                 return 0;
2499
2500         data = &con->eh_data;
2501         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2502         if (!*data) {
2503                 ret = -ENOMEM;
2504                 goto out;
2505         }
2506
2507         mutex_init(&con->recovery_lock);
2508         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2509         atomic_set(&con->in_recovery, 0);
2510         con->eeprom_control.bad_channel_bitmap = 0;
2511
2512         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2513         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2514
2515         /* Todo: During test the SMU might fail to read the eeprom through I2C
2516          * when the GPU is pending on XGMI reset during probe time
2517          * (Mostly after second bus reset), skip it now
2518          */
2519         if (adev->gmc.xgmi.pending_reset)
2520                 return 0;
2521         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2522         /*
2523          * This calling fails when exc_err_limit is true or
2524          * ret != 0.
2525          */
2526         if (exc_err_limit || ret)
2527                 goto free;
2528
2529         if (con->eeprom_control.ras_num_recs) {
2530                 ret = amdgpu_ras_load_bad_pages(adev);
2531                 if (ret)
2532                         goto free;
2533
2534                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2535
2536                 if (con->update_channel_flag == true) {
2537                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2538                         con->update_channel_flag = false;
2539                 }
2540         }
2541
2542 #ifdef CONFIG_X86_MCE_AMD
2543         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2544             (adev->gmc.xgmi.connected_to_cpu))
2545                 amdgpu_register_bad_pages_mca_notifier(adev);
2546 #endif
2547         return 0;
2548
2549 free:
2550         kfree((*data)->bps);
2551         kfree(*data);
2552         con->eh_data = NULL;
2553 out:
2554         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2555
2556         /*
2557          * Except error threshold exceeding case, other failure cases in this
2558          * function would not fail amdgpu driver init.
2559          */
2560         if (!exc_err_limit)
2561                 ret = 0;
2562         else
2563                 ret = -EINVAL;
2564
2565         return ret;
2566 }
2567
2568 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2569 {
2570         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2571         struct ras_err_handler_data *data = con->eh_data;
2572
2573         /* recovery_init failed to init it, fini is useless */
2574         if (!data)
2575                 return 0;
2576
2577         cancel_work_sync(&con->recovery_work);
2578
2579         mutex_lock(&con->recovery_lock);
2580         con->eh_data = NULL;
2581         kfree(data->bps);
2582         kfree(data);
2583         mutex_unlock(&con->recovery_lock);
2584
2585         return 0;
2586 }
2587 /* recovery end */
2588
2589 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2590 {
2591         if (amdgpu_sriov_vf(adev)) {
2592                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2593                 case IP_VERSION(13, 0, 2):
2594                 case IP_VERSION(13, 0, 6):
2595                         return true;
2596                 default:
2597                         return false;
2598                 }
2599         }
2600
2601         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2602                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2603                 case IP_VERSION(13, 0, 0):
2604                 case IP_VERSION(13, 0, 6):
2605                 case IP_VERSION(13, 0, 10):
2606                         return true;
2607                 default:
2608                         return false;
2609                 }
2610         }
2611
2612         return adev->asic_type == CHIP_VEGA10 ||
2613                 adev->asic_type == CHIP_VEGA20 ||
2614                 adev->asic_type == CHIP_ARCTURUS ||
2615                 adev->asic_type == CHIP_ALDEBARAN ||
2616                 adev->asic_type == CHIP_SIENNA_CICHLID;
2617 }
2618
2619 /*
2620  * this is workaround for vega20 workstation sku,
2621  * force enable gfx ras, ignore vbios gfx ras flag
2622  * due to GC EDC can not write
2623  */
2624 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2625 {
2626         struct atom_context *ctx = adev->mode_info.atom_context;
2627
2628         if (!ctx)
2629                 return;
2630
2631         if (strnstr(ctx->vbios_pn, "D16406",
2632                     sizeof(ctx->vbios_pn)) ||
2633                 strnstr(ctx->vbios_pn, "D36002",
2634                         sizeof(ctx->vbios_pn)))
2635                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2636 }
2637
2638 /*
2639  * check hardware's ras ability which will be saved in hw_supported.
2640  * if hardware does not support ras, we can skip some ras initializtion and
2641  * forbid some ras operations from IP.
2642  * if software itself, say boot parameter, limit the ras ability. We still
2643  * need allow IP do some limited operations, like disable. In such case,
2644  * we have to initialize ras as normal. but need check if operation is
2645  * allowed or not in each function.
2646  */
2647 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2648 {
2649         adev->ras_hw_enabled = adev->ras_enabled = 0;
2650
2651         if (!amdgpu_ras_asic_supported(adev))
2652                 return;
2653
2654         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2655                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2656                         dev_info(adev->dev, "MEM ECC is active.\n");
2657                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2658                                                    1 << AMDGPU_RAS_BLOCK__DF);
2659                 } else {
2660                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2661                 }
2662
2663                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2664                         dev_info(adev->dev, "SRAM ECC is active.\n");
2665                         if (!amdgpu_sriov_vf(adev))
2666                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2667                                                             1 << AMDGPU_RAS_BLOCK__DF);
2668                         else
2669                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2670                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2671                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2672
2673                         /* VCN/JPEG RAS can be supported on both bare metal and
2674                          * SRIOV environment
2675                          */
2676                         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2677                                     IP_VERSION(2, 6, 0) ||
2678                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2679                                     IP_VERSION(4, 0, 0) ||
2680                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2681                                     IP_VERSION(4, 0, 3))
2682                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2683                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2684                         else
2685                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2686                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2687
2688                         /*
2689                          * XGMI RAS is not supported if xgmi num physical nodes
2690                          * is zero
2691                          */
2692                         if (!adev->gmc.xgmi.num_physical_nodes)
2693                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2694                 } else {
2695                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2696                 }
2697         } else {
2698                 /* driver only manages a few IP blocks RAS feature
2699                  * when GPU is connected cpu through XGMI */
2700                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2701                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2702                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2703         }
2704
2705         amdgpu_ras_get_quirks(adev);
2706
2707         /* hw_supported needs to be aligned with RAS block mask. */
2708         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2709
2710         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2711                 adev->ras_hw_enabled & amdgpu_ras_mask;
2712 }
2713
2714 static void amdgpu_ras_counte_dw(struct work_struct *work)
2715 {
2716         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2717                                               ras_counte_delay_work.work);
2718         struct amdgpu_device *adev = con->adev;
2719         struct drm_device *dev = adev_to_drm(adev);
2720         unsigned long ce_count, ue_count;
2721         int res;
2722
2723         res = pm_runtime_get_sync(dev->dev);
2724         if (res < 0)
2725                 goto Out;
2726
2727         /* Cache new values.
2728          */
2729         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2730                 atomic_set(&con->ras_ce_count, ce_count);
2731                 atomic_set(&con->ras_ue_count, ue_count);
2732         }
2733
2734         pm_runtime_mark_last_busy(dev->dev);
2735 Out:
2736         pm_runtime_put_autosuspend(dev->dev);
2737 }
2738
2739 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2740 {
2741         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2742         bool df_poison, umc_poison;
2743
2744         /* poison setting is useless on SRIOV guest */
2745         if (amdgpu_sriov_vf(adev) || !con)
2746                 return;
2747
2748         /* Init poison supported flag, the default value is false */
2749         if (adev->gmc.xgmi.connected_to_cpu ||
2750             adev->gmc.is_app_apu) {
2751                 /* enabled by default when GPU is connected to CPU */
2752                 con->poison_supported = true;
2753         } else if (adev->df.funcs &&
2754             adev->df.funcs->query_ras_poison_mode &&
2755             adev->umc.ras &&
2756             adev->umc.ras->query_ras_poison_mode) {
2757                 df_poison =
2758                         adev->df.funcs->query_ras_poison_mode(adev);
2759                 umc_poison =
2760                         adev->umc.ras->query_ras_poison_mode(adev);
2761
2762                 /* Only poison is set in both DF and UMC, we can support it */
2763                 if (df_poison && umc_poison)
2764                         con->poison_supported = true;
2765                 else if (df_poison != umc_poison)
2766                         dev_warn(adev->dev,
2767                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2768                                 df_poison, umc_poison);
2769         }
2770 }
2771
2772 static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
2773 {
2774         return  amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
2775                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
2776                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
2777                         AMDGPU_RAS_ERROR__PARITY;
2778 }
2779
2780 int amdgpu_ras_init(struct amdgpu_device *adev)
2781 {
2782         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2783         int r;
2784
2785         if (con)
2786                 return 0;
2787
2788         con = kmalloc(sizeof(struct amdgpu_ras) +
2789                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2790                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2791                         GFP_KERNEL|__GFP_ZERO);
2792         if (!con)
2793                 return -ENOMEM;
2794
2795         con->adev = adev;
2796         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2797         atomic_set(&con->ras_ce_count, 0);
2798         atomic_set(&con->ras_ue_count, 0);
2799
2800         con->objs = (struct ras_manager *)(con + 1);
2801
2802         amdgpu_ras_set_context(adev, con);
2803
2804         amdgpu_ras_check_supported(adev);
2805
2806         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2807                 /* set gfx block ras context feature for VEGA20 Gaming
2808                  * send ras disable cmd to ras ta during ras late init.
2809                  */
2810                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2811                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2812
2813                         return 0;
2814                 }
2815
2816                 r = 0;
2817                 goto release_con;
2818         }
2819
2820         con->update_channel_flag = false;
2821         con->features = 0;
2822         con->schema = 0;
2823         INIT_LIST_HEAD(&con->head);
2824         /* Might need get this flag from vbios. */
2825         con->flags = RAS_DEFAULT_FLAGS;
2826
2827         /* initialize nbio ras function ahead of any other
2828          * ras functions so hardware fatal error interrupt
2829          * can be enabled as early as possible */
2830         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2831         case IP_VERSION(7, 4, 0):
2832         case IP_VERSION(7, 4, 1):
2833         case IP_VERSION(7, 4, 4):
2834                 if (!adev->gmc.xgmi.connected_to_cpu)
2835                         adev->nbio.ras = &nbio_v7_4_ras;
2836                 break;
2837         case IP_VERSION(4, 3, 0):
2838                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2839                         /* unlike other generation of nbio ras,
2840                          * nbio v4_3 only support fatal error interrupt
2841                          * to inform software that DF is freezed due to
2842                          * system fatal error event. driver should not
2843                          * enable nbio ras in such case. Instead,
2844                          * check DF RAS */
2845                         adev->nbio.ras = &nbio_v4_3_ras;
2846                 break;
2847         case IP_VERSION(7, 9, 0):
2848                 if (!adev->gmc.is_app_apu)
2849                         adev->nbio.ras = &nbio_v7_9_ras;
2850                 break;
2851         default:
2852                 /* nbio ras is not available */
2853                 break;
2854         }
2855
2856         /* nbio ras block needs to be enabled ahead of other ras blocks
2857          * to handle fatal error */
2858         r = amdgpu_nbio_ras_sw_init(adev);
2859         if (r)
2860                 return r;
2861
2862         if (adev->nbio.ras &&
2863             adev->nbio.ras->init_ras_controller_interrupt) {
2864                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2865                 if (r)
2866                         goto release_con;
2867         }
2868
2869         if (adev->nbio.ras &&
2870             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2871                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2872                 if (r)
2873                         goto release_con;
2874         }
2875
2876         amdgpu_ras_query_poison_mode(adev);
2877
2878         /* Get RAS schema for particular SOC */
2879         con->schema = amdgpu_get_ras_schema(adev);
2880
2881         if (amdgpu_ras_fs_init(adev)) {
2882                 r = -EINVAL;
2883                 goto release_con;
2884         }
2885
2886         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2887                  "hardware ability[%x] ras_mask[%x]\n",
2888                  adev->ras_hw_enabled, adev->ras_enabled);
2889
2890         return 0;
2891 release_con:
2892         amdgpu_ras_set_context(adev, NULL);
2893         kfree(con);
2894
2895         return r;
2896 }
2897
2898 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2899 {
2900         if (adev->gmc.xgmi.connected_to_cpu ||
2901             adev->gmc.is_app_apu)
2902                 return 1;
2903         return 0;
2904 }
2905
2906 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2907                                         struct ras_common_if *ras_block)
2908 {
2909         struct ras_query_if info = {
2910                 .head = *ras_block,
2911         };
2912
2913         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2914                 return 0;
2915
2916         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2917                 DRM_WARN("RAS init harvest failure");
2918
2919         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2920                 DRM_WARN("RAS init harvest reset failure");
2921
2922         return 0;
2923 }
2924
2925 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2926 {
2927        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2928
2929        if (!con)
2930                return false;
2931
2932        return con->poison_supported;
2933 }
2934
2935 /* helper function to handle common stuff in ip late init phase */
2936 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2937                          struct ras_common_if *ras_block)
2938 {
2939         struct amdgpu_ras_block_object *ras_obj = NULL;
2940         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2941         struct ras_query_if *query_info;
2942         unsigned long ue_count, ce_count;
2943         int r;
2944
2945         /* disable RAS feature per IP block if it is not supported */
2946         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2947                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2948                 return 0;
2949         }
2950
2951         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2952         if (r) {
2953                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2954                         /* in resume phase, if fail to enable ras,
2955                          * clean up all ras fs nodes, and disable ras */
2956                         goto cleanup;
2957                 } else
2958                         return r;
2959         }
2960
2961         /* check for errors on warm reset edc persisant supported ASIC */
2962         amdgpu_persistent_edc_harvesting(adev, ras_block);
2963
2964         /* in resume phase, no need to create ras fs node */
2965         if (adev->in_suspend || amdgpu_in_reset(adev))
2966                 return 0;
2967
2968         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2969         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2970             (ras_obj->hw_ops->query_poison_status ||
2971             ras_obj->hw_ops->handle_poison_consumption))) {
2972                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2973                 if (r)
2974                         goto cleanup;
2975         }
2976
2977         if (ras_obj->hw_ops &&
2978             (ras_obj->hw_ops->query_ras_error_count ||
2979              ras_obj->hw_ops->query_ras_error_status)) {
2980                 r = amdgpu_ras_sysfs_create(adev, ras_block);
2981                 if (r)
2982                         goto interrupt;
2983
2984                 /* Those are the cached values at init.
2985                  */
2986                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
2987                 if (!query_info)
2988                         return -ENOMEM;
2989                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2990
2991                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2992                         atomic_set(&con->ras_ce_count, ce_count);
2993                         atomic_set(&con->ras_ue_count, ue_count);
2994                 }
2995
2996                 kfree(query_info);
2997         }
2998
2999         return 0;
3000
3001 interrupt:
3002         if (ras_obj->ras_cb)
3003                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3004 cleanup:
3005         amdgpu_ras_feature_enable(adev, ras_block, 0);
3006         return r;
3007 }
3008
3009 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
3010                          struct ras_common_if *ras_block)
3011 {
3012         return amdgpu_ras_block_late_init(adev, ras_block);
3013 }
3014
3015 /* helper function to remove ras fs node and interrupt handler */
3016 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
3017                           struct ras_common_if *ras_block)
3018 {
3019         struct amdgpu_ras_block_object *ras_obj;
3020         if (!ras_block)
3021                 return;
3022
3023         amdgpu_ras_sysfs_remove(adev, ras_block);
3024
3025         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3026         if (ras_obj->ras_cb)
3027                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3028 }
3029
3030 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
3031                           struct ras_common_if *ras_block)
3032 {
3033         return amdgpu_ras_block_late_fini(adev, ras_block);
3034 }
3035
3036 /* do some init work after IP late init as dependence.
3037  * and it runs in resume/gpu reset/booting up cases.
3038  */
3039 void amdgpu_ras_resume(struct amdgpu_device *adev)
3040 {
3041         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3042         struct ras_manager *obj, *tmp;
3043
3044         if (!adev->ras_enabled || !con) {
3045                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
3046                 amdgpu_release_ras_context(adev);
3047
3048                 return;
3049         }
3050
3051         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
3052                 /* Set up all other IPs which are not implemented. There is a
3053                  * tricky thing that IP's actual ras error type should be
3054                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3055                  * ERROR_NONE make sense anyway.
3056                  */
3057                 amdgpu_ras_enable_all_features(adev, 1);
3058
3059                 /* We enable ras on all hw_supported block, but as boot
3060                  * parameter might disable some of them and one or more IP has
3061                  * not implemented yet. So we disable them on behalf.
3062                  */
3063                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3064                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3065                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3066                                 /* there should be no any reference. */
3067                                 WARN_ON(alive_obj(obj));
3068                         }
3069                 }
3070         }
3071 }
3072
3073 void amdgpu_ras_suspend(struct amdgpu_device *adev)
3074 {
3075         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3076
3077         if (!adev->ras_enabled || !con)
3078                 return;
3079
3080         amdgpu_ras_disable_all_features(adev, 0);
3081         /* Make sure all ras objects are disabled. */
3082         if (con->features)
3083                 amdgpu_ras_disable_all_features(adev, 1);
3084 }
3085
3086 int amdgpu_ras_late_init(struct amdgpu_device *adev)
3087 {
3088         struct amdgpu_ras_block_list *node, *tmp;
3089         struct amdgpu_ras_block_object *obj;
3090         int r;
3091
3092         /* Guest side doesn't need init ras feature */
3093         if (amdgpu_sriov_vf(adev))
3094                 return 0;
3095
3096         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3097                 if (!node->ras_obj) {
3098                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3099                         continue;
3100                 }
3101
3102                 obj = node->ras_obj;
3103                 if (obj->ras_late_init) {
3104                         r = obj->ras_late_init(adev, &obj->ras_comm);
3105                         if (r) {
3106                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3107                                         obj->ras_comm.name, r);
3108                                 return r;
3109                         }
3110                 } else
3111                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3112         }
3113
3114         return 0;
3115 }
3116
3117 /* do some fini work before IP fini as dependence */
3118 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3119 {
3120         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3121
3122         if (!adev->ras_enabled || !con)
3123                 return 0;
3124
3125
3126         /* Need disable ras on all IPs here before ip [hw/sw]fini */
3127         if (con->features)
3128                 amdgpu_ras_disable_all_features(adev, 0);
3129         amdgpu_ras_recovery_fini(adev);
3130         return 0;
3131 }
3132
3133 int amdgpu_ras_fini(struct amdgpu_device *adev)
3134 {
3135         struct amdgpu_ras_block_list *ras_node, *tmp;
3136         struct amdgpu_ras_block_object *obj = NULL;
3137         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3138
3139         if (!adev->ras_enabled || !con)
3140                 return 0;
3141
3142         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3143                 if (ras_node->ras_obj) {
3144                         obj = ras_node->ras_obj;
3145                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3146                             obj->ras_fini)
3147                                 obj->ras_fini(adev, &obj->ras_comm);
3148                         else
3149                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3150                 }
3151
3152                 /* Clear ras blocks from ras_list and free ras block list node */
3153                 list_del(&ras_node->node);
3154                 kfree(ras_node);
3155         }
3156
3157         amdgpu_ras_fs_fini(adev);
3158         amdgpu_ras_interrupt_remove_all(adev);
3159
3160         WARN(con->features, "Feature mask is not cleared");
3161
3162         if (con->features)
3163                 amdgpu_ras_disable_all_features(adev, 1);
3164
3165         cancel_delayed_work_sync(&con->ras_counte_delay_work);
3166
3167         amdgpu_ras_set_context(adev, NULL);
3168         kfree(con);
3169
3170         return 0;
3171 }
3172
3173 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3174 {
3175         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
3176                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3177
3178                 dev_info(adev->dev, "uncorrectable hardware error"
3179                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
3180
3181                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
3182                 amdgpu_ras_reset_gpu(adev);
3183         }
3184 }
3185
3186 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3187 {
3188         if (adev->asic_type == CHIP_VEGA20 &&
3189             adev->pm.fw_version <= 0x283400) {
3190                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3191                                 amdgpu_ras_intr_triggered();
3192         }
3193
3194         return false;
3195 }
3196
3197 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3198 {
3199         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3200
3201         if (!con)
3202                 return;
3203
3204         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3205                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3206                 amdgpu_ras_set_context(adev, NULL);
3207                 kfree(con);
3208         }
3209 }
3210
3211 #ifdef CONFIG_X86_MCE_AMD
3212 static struct amdgpu_device *find_adev(uint32_t node_id)
3213 {
3214         int i;
3215         struct amdgpu_device *adev = NULL;
3216
3217         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3218                 adev = mce_adev_list.devs[i];
3219
3220                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3221                     adev->gmc.xgmi.physical_node_id == node_id)
3222                         break;
3223                 adev = NULL;
3224         }
3225
3226         return adev;
3227 }
3228
3229 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3230 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3231 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3232 #define GPU_ID_OFFSET           8
3233
3234 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3235                                     unsigned long val, void *data)
3236 {
3237         struct mce *m = (struct mce *)data;
3238         struct amdgpu_device *adev = NULL;
3239         uint32_t gpu_id = 0;
3240         uint32_t umc_inst = 0, ch_inst = 0;
3241
3242         /*
3243          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3244          * and error occurred in DramECC (Extended error code = 0) then only
3245          * process the error, else bail out.
3246          */
3247         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3248                     (XEC(m->status, 0x3f) == 0x0)))
3249                 return NOTIFY_DONE;
3250
3251         /*
3252          * If it is correctable error, return.
3253          */
3254         if (mce_is_correctable(m))
3255                 return NOTIFY_OK;
3256
3257         /*
3258          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3259          */
3260         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3261
3262         adev = find_adev(gpu_id);
3263         if (!adev) {
3264                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3265                                                                 gpu_id);
3266                 return NOTIFY_DONE;
3267         }
3268
3269         /*
3270          * If it is uncorrectable error, then find out UMC instance and
3271          * channel index.
3272          */
3273         umc_inst = GET_UMC_INST(m->ipid);
3274         ch_inst = GET_CHAN_INDEX(m->ipid);
3275
3276         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3277                              umc_inst, ch_inst);
3278
3279         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3280                 return NOTIFY_OK;
3281         else
3282                 return NOTIFY_DONE;
3283 }
3284
3285 static struct notifier_block amdgpu_bad_page_nb = {
3286         .notifier_call  = amdgpu_bad_page_notifier,
3287         .priority       = MCE_PRIO_UC,
3288 };
3289
3290 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3291 {
3292         /*
3293          * Add the adev to the mce_adev_list.
3294          * During mode2 reset, amdgpu device is temporarily
3295          * removed from the mgpu_info list which can cause
3296          * page retirement to fail.
3297          * Use this list instead of mgpu_info to find the amdgpu
3298          * device on which the UMC error was reported.
3299          */
3300         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3301
3302         /*
3303          * Register the x86 notifier only once
3304          * with MCE subsystem.
3305          */
3306         if (notifier_registered == false) {
3307                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3308                 notifier_registered = true;
3309         }
3310 }
3311 #endif
3312
3313 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3314 {
3315         if (!adev)
3316                 return NULL;
3317
3318         return adev->psp.ras_context.ras;
3319 }
3320
3321 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3322 {
3323         if (!adev)
3324                 return -EINVAL;
3325
3326         adev->psp.ras_context.ras = ras_con;
3327         return 0;
3328 }
3329
3330 /* check if ras is supported on block, say, sdma, gfx */
3331 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3332                 unsigned int block)
3333 {
3334         int ret = 0;
3335         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3336
3337         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3338                 return 0;
3339
3340         ret = ras && (adev->ras_enabled & (1 << block));
3341
3342         /* For the special asic with mem ecc enabled but sram ecc
3343          * not enabled, even if the ras block is not supported on
3344          * .ras_enabled, if the asic supports poison mode and the
3345          * ras block has ras configuration, it can be considered
3346          * that the ras block supports ras function.
3347          */
3348         if (!ret &&
3349             (block == AMDGPU_RAS_BLOCK__GFX ||
3350              block == AMDGPU_RAS_BLOCK__SDMA ||
3351              block == AMDGPU_RAS_BLOCK__VCN ||
3352              block == AMDGPU_RAS_BLOCK__JPEG) &&
3353             amdgpu_ras_is_poison_mode_supported(adev) &&
3354             amdgpu_ras_get_ras_block(adev, block, 0))
3355                 ret = 1;
3356
3357         return ret;
3358 }
3359
3360 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3361 {
3362         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3363
3364         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3365                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3366         return 0;
3367 }
3368
3369 void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
3370 {
3371         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3372
3373         if (con)
3374                 con->is_mca_debug_mode = enable;
3375 }
3376
3377 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev)
3378 {
3379         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3380         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3381
3382         if (!con)
3383                 return false;
3384
3385         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3386                 return con->is_mca_debug_mode;
3387         else
3388                 return true;
3389 }
3390
3391 /* Register each ip ras block into amdgpu ras */
3392 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3393                 struct amdgpu_ras_block_object *ras_block_obj)
3394 {
3395         struct amdgpu_ras_block_list *ras_node;
3396         if (!adev || !ras_block_obj)
3397                 return -EINVAL;
3398
3399         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3400         if (!ras_node)
3401                 return -ENOMEM;
3402
3403         INIT_LIST_HEAD(&ras_node->node);
3404         ras_node->ras_obj = ras_block_obj;
3405         list_add_tail(&ras_node->node, &adev->ras_list);
3406
3407         return 0;
3408 }
3409
3410 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3411 {
3412         if (!err_type_name)
3413                 return;
3414
3415         switch (err_type) {
3416         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3417                 sprintf(err_type_name, "correctable");
3418                 break;
3419         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3420                 sprintf(err_type_name, "uncorrectable");
3421                 break;
3422         default:
3423                 sprintf(err_type_name, "unknown");
3424                 break;
3425         }
3426 }
3427
3428 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3429                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3430                                          uint32_t instance,
3431                                          uint32_t *memory_id)
3432 {
3433         uint32_t err_status_lo_data, err_status_lo_offset;
3434
3435         if (!reg_entry)
3436                 return false;
3437
3438         err_status_lo_offset =
3439                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3440                                             reg_entry->seg_lo, reg_entry->reg_lo);
3441         err_status_lo_data = RREG32(err_status_lo_offset);
3442
3443         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3444             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3445                 return false;
3446
3447         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3448
3449         return true;
3450 }
3451
3452 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3453                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3454                                        uint32_t instance,
3455                                        unsigned long *err_cnt)
3456 {
3457         uint32_t err_status_hi_data, err_status_hi_offset;
3458
3459         if (!reg_entry)
3460                 return false;
3461
3462         err_status_hi_offset =
3463                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3464                                             reg_entry->seg_hi, reg_entry->reg_hi);
3465         err_status_hi_data = RREG32(err_status_hi_offset);
3466
3467         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3468             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3469                 /* keep the check here in case we need to refer to the result later */
3470                 dev_dbg(adev->dev, "Invalid err_info field\n");
3471
3472         /* read err count */
3473         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3474
3475         return true;
3476 }
3477
3478 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3479                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3480                                            uint32_t reg_list_size,
3481                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3482                                            uint32_t mem_list_size,
3483                                            uint32_t instance,
3484                                            uint32_t err_type,
3485                                            unsigned long *err_count)
3486 {
3487         uint32_t memory_id;
3488         unsigned long err_cnt;
3489         char err_type_name[16];
3490         uint32_t i, j;
3491
3492         for (i = 0; i < reg_list_size; i++) {
3493                 /* query memory_id from err_status_lo */
3494                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3495                                                          instance, &memory_id))
3496                         continue;
3497
3498                 /* query err_cnt from err_status_hi */
3499                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3500                                                        instance, &err_cnt) ||
3501                     !err_cnt)
3502                         continue;
3503
3504                 *err_count += err_cnt;
3505
3506                 /* log the errors */
3507                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3508                 if (!mem_list) {
3509                         /* memory_list is not supported */
3510                         dev_info(adev->dev,
3511                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3512                                  err_cnt, err_type_name,
3513                                  reg_list[i].block_name,
3514                                  instance, memory_id);
3515                 } else {
3516                         for (j = 0; j < mem_list_size; j++) {
3517                                 if (memory_id == mem_list[j].memory_id) {
3518                                         dev_info(adev->dev,
3519                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3520                                                  err_cnt, err_type_name,
3521                                                  reg_list[i].block_name,
3522                                                  instance, mem_list[j].name);
3523                                         break;
3524                                 }
3525                         }
3526                 }
3527         }
3528 }
3529
3530 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3531                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3532                                            uint32_t reg_list_size,
3533                                            uint32_t instance)
3534 {
3535         uint32_t err_status_lo_offset, err_status_hi_offset;
3536         uint32_t i;
3537
3538         for (i = 0; i < reg_list_size; i++) {
3539                 err_status_lo_offset =
3540                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3541                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3542                 err_status_hi_offset =
3543                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3544                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3545                 WREG32(err_status_lo_offset, 0);
3546                 WREG32(err_status_hi_offset, 0);
3547         }
3548 }
3549
3550 int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
3551 {
3552         memset(err_data, 0, sizeof(*err_data));
3553
3554         INIT_LIST_HEAD(&err_data->err_node_list);
3555
3556         return 0;
3557 }
3558
3559 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
3560 {
3561         if (!err_node)
3562                 return;
3563
3564         list_del(&err_node->node);
3565         kvfree(err_node);
3566 }
3567
3568 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
3569 {
3570         struct ras_err_node *err_node, *tmp;
3571
3572         list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
3573                 amdgpu_ras_error_node_release(err_node);
3574 }
3575
3576 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
3577                                                              struct amdgpu_smuio_mcm_config_info *mcm_info)
3578 {
3579         struct ras_err_node *err_node;
3580         struct amdgpu_smuio_mcm_config_info *ref_id;
3581
3582         if (!err_data || !mcm_info)
3583                 return NULL;
3584
3585         for_each_ras_error(err_node, err_data) {
3586                 ref_id = &err_node->err_info.mcm_info;
3587
3588                 if (mcm_info->socket_id == ref_id->socket_id &&
3589                     mcm_info->die_id == ref_id->die_id)
3590                         return err_node;
3591         }
3592
3593         return NULL;
3594 }
3595
3596 static struct ras_err_node *amdgpu_ras_error_node_new(void)
3597 {
3598         struct ras_err_node *err_node;
3599
3600         err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
3601         if (!err_node)
3602                 return NULL;
3603
3604         INIT_LIST_HEAD(&err_node->node);
3605
3606         return err_node;
3607 }
3608
3609 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
3610                                                       struct amdgpu_smuio_mcm_config_info *mcm_info)
3611 {
3612         struct ras_err_node *err_node;
3613
3614         err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
3615         if (err_node)
3616                 return &err_node->err_info;
3617
3618         err_node = amdgpu_ras_error_node_new();
3619         if (!err_node)
3620                 return NULL;
3621
3622         memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
3623
3624         err_data->err_list_count++;
3625         list_add_tail(&err_node->node, &err_data->err_node_list);
3626
3627         return &err_node->err_info;
3628 }
3629
3630 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
3631                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3632 {
3633         struct ras_err_info *err_info;
3634
3635         if (!err_data || !mcm_info)
3636                 return -EINVAL;
3637
3638         if (!count)
3639                 return 0;
3640
3641         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3642         if (!err_info)
3643                 return -EINVAL;
3644
3645         err_info->ue_count += count;
3646         err_data->ue_count += count;
3647
3648         return 0;
3649 }
3650
3651 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
3652                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3653 {
3654         struct ras_err_info *err_info;
3655
3656         if (!err_data || !mcm_info)
3657                 return -EINVAL;
3658
3659         if (!count)
3660                 return 0;
3661
3662         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3663         if (!err_info)
3664                 return -EINVAL;
3665
3666         err_info->ce_count += count;
3667         err_data->ce_count += count;
3668
3669         return 0;
3670 }