drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "nbio_v7_9.h"
  39 #include "atom.h"
  40 #include "amdgpu_reset.h"
  41
  42 #ifdef CONFIG_X86_MCE_AMD
  43 #include <asm/mce.h>
  44
  45 static bool notifier_registered;
  46 #endif
  47 static const char *RAS_FS_NAME = "ras";
  48
  49 const char *ras_error_string[] = {
  50         "none",
  51         "parity",
  52         "single_correctable",
  53         "multi_uncorrectable",
  54         "poison",
  55 };
  56
  57 const char *ras_block_string[] = {
  58         "umc",
  59         "sdma",
  60         "gfx",
  61         "mmhub",
  62         "athub",
  63         "pcie_bif",
  64         "hdp",
  65         "xgmi_wafl",
  66         "df",
  67         "smn",
  68         "sem",
  69         "mp0",
  70         "mp1",
  71         "fuse",
  72         "mca",
  73         "vcn",
  74         "jpeg",
  75 };
  76
  77 const char *ras_mca_block_string[] = {
  78         "mca_mp0",
  79         "mca_mp1",
  80         "mca_mpio",
  81         "mca_iohc",
  82 };
  83
  84 struct amdgpu_ras_block_list {
  85         /* ras block link */
  86         struct list_head node;
  87
  88         struct amdgpu_ras_block_object *ras_obj;
  89 };
  90
  91 const char *get_ras_block_str(struct ras_common_if *ras_block)
  92 {
  93         if (!ras_block)
  94                 return "NULL";
  95
  96         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  97                 return "OUT OF RANGE";
  98
  99         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 100                 return ras_mca_block_string[ras_block->sub_block_index];
 101
 102         return ras_block_string[ras_block->block];
 103 }
 104
 105 #define ras_block_str(_BLOCK_) \
 106         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 107
 108 #define ras_err_str(i) (ras_error_string[ffs(i)])
 109
 110 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 111
 112 /* inject address is 52 bits */
 113 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 114
 115 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 116 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 117
 118 enum amdgpu_ras_retire_page_reservation {
 119         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 120         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 121         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 122 };
 123
 124 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 125
 126 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 127                                 uint64_t addr);
 128 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 129                                 uint64_t addr);
 130 #ifdef CONFIG_X86_MCE_AMD
 131 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 132 struct mce_notifier_adev_list {
 133         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 134         int num_gpu;
 135 };
 136 static struct mce_notifier_adev_list mce_adev_list;
 137 #endif
 138
 139 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 140 {
 141         if (adev && amdgpu_ras_get_context(adev))
 142                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 143 }
 144
 145 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 146 {
 147         if (adev && amdgpu_ras_get_context(adev))
 148                 return amdgpu_ras_get_context(adev)->error_query_ready;
 149
 150         return false;
 151 }
 152
 153 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 154 {
 155         struct ras_err_data err_data;
 156         struct eeprom_table_record err_rec;
 157         int ret;
 158
 159         if ((address >= adev->gmc.mc_vram_size) ||
 160             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 161                 dev_warn(adev->dev,
 162                          "RAS WARN: input address 0x%llx is invalid.\n",
 163                          address);
 164                 return -EINVAL;
 165         }
 166
 167         if (amdgpu_ras_check_bad_page(adev, address)) {
 168                 dev_warn(adev->dev,
 169                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 170                          address);
 171                 return 0;
 172         }
 173
 174         ret = amdgpu_ras_error_data_init(&err_data);
 175         if (ret)
 176                 return ret;
 177
 178         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 179         err_data.err_addr = &err_rec;
 180         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 181
 182         if (amdgpu_bad_page_threshold != 0) {
 183                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 184                                          err_data.err_addr_cnt);
 185                 amdgpu_ras_save_bad_pages(adev, NULL);
 186         }
 187
 188         amdgpu_ras_error_data_fini(&err_data);
 189
 190         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 191         dev_warn(adev->dev, "Clear EEPROM:\n");
 192         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 193
 194         return 0;
 195 }
 196
 197 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 198                                         size_t size, loff_t *pos)
 199 {
 200         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 201         struct ras_query_if info = {
 202                 .head = obj->head,
 203         };
 204         ssize_t s;
 205         char val[128];
 206
 207         if (amdgpu_ras_query_error_status(obj->adev, &info))
 208                 return -EINVAL;
 209
 210         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 211         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 212             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 213                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 214                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 215         }
 216
 217         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 218                         "ue", info.ue_count,
 219                         "ce", info.ce_count);
 220         if (*pos >= s)
 221                 return 0;
 222
 223         s -= *pos;
 224         s = min_t(u64, s, size);
 225
 226
 227         if (copy_to_user(buf, &val[*pos], s))
 228                 return -EINVAL;
 229
 230         *pos += s;
 231
 232         return s;
 233 }
 234
 235 static const struct file_operations amdgpu_ras_debugfs_ops = {
 236         .owner = THIS_MODULE,
 237         .read = amdgpu_ras_debugfs_read,
 238         .write = NULL,
 239         .llseek = default_llseek
 240 };
 241
 242 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 243 {
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 247                 *block_id = i;
 248                 if (strcmp(name, ras_block_string[i]) == 0)
 249                         return 0;
 250         }
 251         return -EINVAL;
 252 }
 253
 254 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 255                 const char __user *buf, size_t size,
 256                 loff_t *pos, struct ras_debug_if *data)
 257 {
 258         ssize_t s = min_t(u64, 64, size);
 259         char str[65];
 260         char block_name[33];
 261         char err[9] = "ue";
 262         int op = -1;
 263         int block_id;
 264         uint32_t sub_block;
 265         u64 address, value;
 266         /* default value is 0 if the mask is not set by user */
 267         u32 instance_mask = 0;
 268
 269         if (*pos)
 270                 return -EINVAL;
 271         *pos = size;
 272
 273         memset(str, 0, sizeof(str));
 274         memset(data, 0, sizeof(*data));
 275
 276         if (copy_from_user(str, buf, s))
 277                 return -EINVAL;
 278
 279         if (sscanf(str, "disable %32s", block_name) == 1)
 280                 op = 0;
 281         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 282                 op = 1;
 283         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 284                 op = 2;
 285         else if (strstr(str, "retire_page") != NULL)
 286                 op = 3;
 287         else if (str[0] && str[1] && str[2] && str[3])
 288                 /* ascii string, but commands are not matched. */
 289                 return -EINVAL;
 290
 291         if (op != -1) {
 292                 if (op == 3) {
 293                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 294                             sscanf(str, "%*s %llu", &address) != 1)
 295                                 return -EINVAL;
 296
 297                         data->op = op;
 298                         data->inject.address = address;
 299
 300                         return 0;
 301                 }
 302
 303                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 304                         return -EINVAL;
 305
 306                 data->head.block = block_id;
 307                 /* only ue and ce errors are supported */
 308                 if (!memcmp("ue", err, 2))
 309                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 310                 else if (!memcmp("ce", err, 2))
 311                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 312                 else
 313                         return -EINVAL;
 314
 315                 data->op = op;
 316
 317                 if (op == 2) {
 318                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 319                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 320                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 321                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 322                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 323                                    &sub_block, &address, &value) != 3 &&
 324                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 325                                    &sub_block, &address, &value) != 3)
 326                                 return -EINVAL;
 327                         data->head.sub_block_index = sub_block;
 328                         data->inject.address = address;
 329                         data->inject.value = value;
 330                         data->inject.instance_mask = instance_mask;
 331                 }
 332         } else {
 333                 if (size < sizeof(*data))
 334                         return -EINVAL;
 335
 336                 if (copy_from_user(data, buf, sizeof(*data)))
 337                         return -EINVAL;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 344                                 struct ras_debug_if *data)
 345 {
 346         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 347         uint32_t mask, inst_mask = data->inject.instance_mask;
 348
 349         /* no need to set instance mask if there is only one instance */
 350         if (num_xcc <= 1 && inst_mask) {
 351                 data->inject.instance_mask = 0;
 352                 dev_dbg(adev->dev,
 353                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 354                         inst_mask);
 355
 356                 return;
 357         }
 358
 359         switch (data->head.block) {
 360         case AMDGPU_RAS_BLOCK__GFX:
 361                 mask = GENMASK(num_xcc - 1, 0);
 362                 break;
 363         case AMDGPU_RAS_BLOCK__SDMA:
 364                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 365                 break;
 366         case AMDGPU_RAS_BLOCK__VCN:
 367         case AMDGPU_RAS_BLOCK__JPEG:
 368                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 369                 break;
 370         default:
 371                 mask = inst_mask;
 372                 break;
 373         }
 374
 375         /* remove invalid bits in instance mask */
 376         data->inject.instance_mask &= mask;
 377         if (inst_mask != data->inject.instance_mask)
 378                 dev_dbg(adev->dev,
 379                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 380                         inst_mask, data->inject.instance_mask);
 381 }
 382
 383 /**
 384  * DOC: AMDGPU RAS debugfs control interface
 385  *
 386  * The control interface accepts struct ras_debug_if which has two members.
 387  *
 388  * First member: ras_debug_if::head or ras_debug_if::inject.
 389  *
 390  * head is used to indicate which IP block will be under control.
 391  *
 392  * head has four members, they are block, type, sub_block_index, name.
 393  * block: which IP will be under control.
 394  * type: what kind of error will be enabled/disabled/injected.
 395  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 396  * name: the name of IP.
 397  *
 398  * inject has three more members than head, they are address, value and mask.
 399  * As their names indicate, inject operation will write the
 400  * value to the address.
 401  *
 402  * The second member: struct ras_debug_if::op.
 403  * It has three kinds of operations.
 404  *
 405  * - 0: disable RAS on the block. Take ::head as its data.
 406  * - 1: enable RAS on the block. Take ::head as its data.
 407  * - 2: inject errors on the block. Take ::inject as its data.
 408  *
 409  * How to use the interface?
 410  *
 411  * In a program
 412  *
 413  * Copy the struct ras_debug_if in your code and initialize it.
 414  * Write the struct to the control interface.
 415  *
 416  * From shell
 417  *
 418  * .. code-block:: bash
 419  *
 420  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 421  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 422  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 423  *
 424  * Where N, is the card which you want to affect.
 425  *
 426  * "disable" requires only the block.
 427  * "enable" requires the block and error type.
 428  * "inject" requires the block, error type, address, and value.
 429  *
 430  * The block is one of: umc, sdma, gfx, etc.
 431  *      see ras_block_string[] for details
 432  *
 433  * The error type is one of: ue, ce, where,
 434  *      ue is multi-uncorrectable
 435  *      ce is single-correctable
 436  *
 437  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 438  * The address and value are hexadecimal numbers, leading 0x is optional.
 439  * The mask means instance mask, is optional, default value is 0x1.
 440  *
 441  * For instance,
 442  *
 443  * .. code-block:: bash
 444  *
 445  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 446  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 447  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 448  *
 449  * How to check the result of the operation?
 450  *
 451  * To check disable/enable, see "ras" features at,
 452  * /sys/class/drm/card[0/1/2...]/device/ras/features
 453  *
 454  * To check inject, see the corresponding error count at,
 455  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 456  *
 457  * .. note::
 458  *      Operations are only allowed on blocks which are supported.
 459  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 460  *      to see which blocks support RAS on a particular asic.
 461  *
 462  */
 463 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 464                                              const char __user *buf,
 465                                              size_t size, loff_t *pos)
 466 {
 467         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 468         struct ras_debug_if data;
 469         int ret = 0;
 470
 471         if (!amdgpu_ras_get_error_query_ready(adev)) {
 472                 dev_warn(adev->dev, "RAS WARN: error injection "
 473                                 "currently inaccessible\n");
 474                 return size;
 475         }
 476
 477         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 478         if (ret)
 479                 return ret;
 480
 481         if (data.op == 3) {
 482                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 483                 if (!ret)
 484                         return size;
 485                 else
 486                         return ret;
 487         }
 488
 489         if (!amdgpu_ras_is_supported(adev, data.head.block))
 490                 return -EINVAL;
 491
 492         switch (data.op) {
 493         case 0:
 494                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 495                 break;
 496         case 1:
 497                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 498                 break;
 499         case 2:
 500                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 501                     adev->gmc.mc_vram_size) ||
 502                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 503                         dev_warn(adev->dev, "RAS WARN: input address "
 504                                         "0x%llx is invalid.",
 505                                         data.inject.address);
 506                         ret = -EINVAL;
 507                         break;
 508                 }
 509
 510                 /* umc ce/ue error injection for a bad page is not allowed */
 511                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 512                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 513                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 514                                  "already been marked as bad!\n",
 515                                  data.inject.address);
 516                         break;
 517                 }
 518
 519                 amdgpu_ras_instance_mask_check(adev, &data);
 520
 521                 /* data.inject.address is offset instead of absolute gpu address */
 522                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 523                 break;
 524         default:
 525                 ret = -EINVAL;
 526                 break;
 527         }
 528
 529         if (ret)
 530                 return ret;
 531
 532         return size;
 533 }
 534
 535 /**
 536  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 537  *
 538  * Some boards contain an EEPROM which is used to persistently store a list of
 539  * bad pages which experiences ECC errors in vram.  This interface provides
 540  * a way to reset the EEPROM, e.g., after testing error injection.
 541  *
 542  * Usage:
 543  *
 544  * .. code-block:: bash
 545  *
 546  *      echo 1 > ../ras/ras_eeprom_reset
 547  *
 548  * will reset EEPROM table to 0 entries.
 549  *
 550  */
 551 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 552                                                const char __user *buf,
 553                                                size_t size, loff_t *pos)
 554 {
 555         struct amdgpu_device *adev =
 556                 (struct amdgpu_device *)file_inode(f)->i_private;
 557         int ret;
 558
 559         ret = amdgpu_ras_eeprom_reset_table(
 560                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 561
 562         if (!ret) {
 563                 /* Something was written to EEPROM.
 564                  */
 565                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 566                 return size;
 567         } else {
 568                 return ret;
 569         }
 570 }
 571
 572 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 573         .owner = THIS_MODULE,
 574         .read = NULL,
 575         .write = amdgpu_ras_debugfs_ctrl_write,
 576         .llseek = default_llseek
 577 };
 578
 579 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 580         .owner = THIS_MODULE,
 581         .read = NULL,
 582         .write = amdgpu_ras_debugfs_eeprom_write,
 583         .llseek = default_llseek
 584 };
 585
 586 /**
 587  * DOC: AMDGPU RAS sysfs Error Count Interface
 588  *
 589  * It allows the user to read the error count for each IP block on the gpu through
 590  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 591  *
 592  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 593  * (ce) error counts.
 594  *
 595  * The format of one line is below,
 596  *
 597  * [ce|ue]: count
 598  *
 599  * Example:
 600  *
 601  * .. code-block:: bash
 602  *
 603  *      ue: 0
 604  *      ce: 1
 605  *
 606  */
 607 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 608                 struct device_attribute *attr, char *buf)
 609 {
 610         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 611         struct ras_query_if info = {
 612                 .head = obj->head,
 613         };
 614
 615         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 616                 return sysfs_emit(buf, "Query currently inaccessible\n");
 617
 618         if (amdgpu_ras_query_error_status(obj->adev, &info))
 619                 return -EINVAL;
 620
 621         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 622             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 623                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 624                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 625         }
 626
 627         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 628                           "ce", info.ce_count);
 629 }
 630
 631 /* obj begin */
 632
 633 #define get_obj(obj) do { (obj)->use++; } while (0)
 634 #define alive_obj(obj) ((obj)->use)
 635
 636 static inline void put_obj(struct ras_manager *obj)
 637 {
 638         if (obj && (--obj->use == 0)) {
 639                 list_del(&obj->node);
 640                 amdgpu_ras_error_data_fini(&obj->err_data);
 641         }
 642
 643         if (obj && (obj->use < 0))
 644                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 645 }
 646
 647 /* make one obj and return it. */
 648 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 649                 struct ras_common_if *head)
 650 {
 651         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 652         struct ras_manager *obj;
 653
 654         if (!adev->ras_enabled || !con)
 655                 return NULL;
 656
 657         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 658                 return NULL;
 659
 660         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 661                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 662                         return NULL;
 663
 664                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 665         } else
 666                 obj = &con->objs[head->block];
 667
 668         /* already exist. return obj? */
 669         if (alive_obj(obj))
 670                 return NULL;
 671
 672         if (amdgpu_ras_error_data_init(&obj->err_data))
 673                 return NULL;
 674
 675         obj->head = *head;
 676         obj->adev = adev;
 677         list_add(&obj->node, &con->head);
 678         get_obj(obj);
 679
 680         return obj;
 681 }
 682
 683 /* return an obj equal to head, or the first when head is NULL */
 684 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 685                 struct ras_common_if *head)
 686 {
 687         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 688         struct ras_manager *obj;
 689         int i;
 690
 691         if (!adev->ras_enabled || !con)
 692                 return NULL;
 693
 694         if (head) {
 695                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 696                         return NULL;
 697
 698                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 699                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 700                                 return NULL;
 701
 702                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 703                 } else
 704                         obj = &con->objs[head->block];
 705
 706                 if (alive_obj(obj))
 707                         return obj;
 708         } else {
 709                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 710                         obj = &con->objs[i];
 711                         if (alive_obj(obj))
 712                                 return obj;
 713                 }
 714         }
 715
 716         return NULL;
 717 }
 718 /* obj end */
 719
 720 /* feature ctl begin */
 721 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 722                                          struct ras_common_if *head)
 723 {
 724         return adev->ras_hw_enabled & BIT(head->block);
 725 }
 726
 727 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 728                 struct ras_common_if *head)
 729 {
 730         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 731
 732         return con->features & BIT(head->block);
 733 }
 734
 735 /*
 736  * if obj is not created, then create one.
 737  * set feature enable flag.
 738  */
 739 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 740                 struct ras_common_if *head, int enable)
 741 {
 742         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 743         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 744
 745         /* If hardware does not support ras, then do not create obj.
 746          * But if hardware support ras, we can create the obj.
 747          * Ras framework checks con->hw_supported to see if it need do
 748          * corresponding initialization.
 749          * IP checks con->support to see if it need disable ras.
 750          */
 751         if (!amdgpu_ras_is_feature_allowed(adev, head))
 752                 return 0;
 753
 754         if (enable) {
 755                 if (!obj) {
 756                         obj = amdgpu_ras_create_obj(adev, head);
 757                         if (!obj)
 758                                 return -EINVAL;
 759                 } else {
 760                         /* In case we create obj somewhere else */
 761                         get_obj(obj);
 762                 }
 763                 con->features |= BIT(head->block);
 764         } else {
 765                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 766                         con->features &= ~BIT(head->block);
 767                         put_obj(obj);
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 /* wrapper of psp_ras_enable_features */
 775 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 776                 struct ras_common_if *head, bool enable)
 777 {
 778         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 779         union ta_ras_cmd_input *info;
 780         int ret;
 781
 782         if (!con)
 783                 return -EINVAL;
 784
 785         /* For non-gfx ip, do not enable ras feature if it is not allowed */
 786         /* For gfx ip, regardless of feature support status, */
 787         /* Force issue enable or disable ras feature commands */
 788         if (head->block != AMDGPU_RAS_BLOCK__GFX &&
 789             !amdgpu_ras_is_feature_allowed(adev, head))
 790                 return 0;
 791
 792         /* Only enable gfx ras feature from host side */
 793         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 794             !amdgpu_sriov_vf(adev) &&
 795             !amdgpu_ras_intr_triggered()) {
 796                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 797                 if (!info)
 798                         return -ENOMEM;
 799
 800                 if (!enable) {
 801                         info->disable_features = (struct ta_ras_disable_features_input) {
 802                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 803                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 804                         };
 805                 } else {
 806                         info->enable_features = (struct ta_ras_enable_features_input) {
 807                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 808                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 809                         };
 810                 }
 811
 812                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 813                 if (ret) {
 814                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 815                                 enable ? "enable":"disable",
 816                                 get_ras_block_str(head),
 817                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 818                         kfree(info);
 819                         return ret;
 820                 }
 821
 822                 kfree(info);
 823         }
 824
 825         /* setup the obj */
 826         __amdgpu_ras_feature_enable(adev, head, enable);
 827
 828         return 0;
 829 }
 830
 831 /* Only used in device probe stage and called only once. */
 832 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 833                 struct ras_common_if *head, bool enable)
 834 {
 835         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 836         int ret;
 837
 838         if (!con)
 839                 return -EINVAL;
 840
 841         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 842                 if (enable) {
 843                         /* There is no harm to issue a ras TA cmd regardless of
 844                          * the currecnt ras state.
 845                          * If current state == target state, it will do nothing
 846                          * But sometimes it requests driver to reset and repost
 847                          * with error code -EAGAIN.
 848                          */
 849                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 850                         /* With old ras TA, we might fail to enable ras.
 851                          * Log it and just setup the object.
 852                          * TODO need remove this WA in the future.
 853                          */
 854                         if (ret == -EINVAL) {
 855                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 856                                 if (!ret)
 857                                         dev_info(adev->dev,
 858                                                 "RAS INFO: %s setup object\n",
 859                                                 get_ras_block_str(head));
 860                         }
 861                 } else {
 862                         /* setup the object then issue a ras TA disable cmd.*/
 863                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 864                         if (ret)
 865                                 return ret;
 866
 867                         /* gfx block ras dsiable cmd must send to ras-ta */
 868                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 869                                 con->features |= BIT(head->block);
 870
 871                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 872
 873                         /* clean gfx block ras features flag */
 874                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 875                                 con->features &= ~BIT(head->block);
 876                 }
 877         } else
 878                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 879
 880         return ret;
 881 }
 882
 883 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 884                 bool bypass)
 885 {
 886         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 887         struct ras_manager *obj, *tmp;
 888
 889         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 890                 /* bypass psp.
 891                  * aka just release the obj and corresponding flags
 892                  */
 893                 if (bypass) {
 894                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 895                                 break;
 896                 } else {
 897                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 898                                 break;
 899                 }
 900         }
 901
 902         return con->features;
 903 }
 904
 905 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 906                 bool bypass)
 907 {
 908         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 909         int i;
 910         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 911
 912         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 913                 struct ras_common_if head = {
 914                         .block = i,
 915                         .type = default_ras_type,
 916                         .sub_block_index = 0,
 917                 };
 918
 919                 if (i == AMDGPU_RAS_BLOCK__MCA)
 920                         continue;
 921
 922                 if (bypass) {
 923                         /*
 924                          * bypass psp. vbios enable ras for us.
 925                          * so just create the obj
 926                          */
 927                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 928                                 break;
 929                 } else {
 930                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 931                                 break;
 932                 }
 933         }
 934
 935         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 936                 struct ras_common_if head = {
 937                         .block = AMDGPU_RAS_BLOCK__MCA,
 938                         .type = default_ras_type,
 939                         .sub_block_index = i,
 940                 };
 941
 942                 if (bypass) {
 943                         /*
 944                          * bypass psp. vbios enable ras for us.
 945                          * so just create the obj
 946                          */
 947                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 948                                 break;
 949                 } else {
 950                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 951                                 break;
 952                 }
 953         }
 954
 955         return con->features;
 956 }
 957 /* feature ctl end */
 958
 959 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 960                 enum amdgpu_ras_block block)
 961 {
 962         if (!block_obj)
 963                 return -EINVAL;
 964
 965         if (block_obj->ras_comm.block == block)
 966                 return 0;
 967
 968         return -EINVAL;
 969 }
 970
 971 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 972                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 973 {
 974         struct amdgpu_ras_block_list *node, *tmp;
 975         struct amdgpu_ras_block_object *obj;
 976
 977         if (block >= AMDGPU_RAS_BLOCK__LAST)
 978                 return NULL;
 979
 980         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 981                 if (!node->ras_obj) {
 982                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 983                         continue;
 984                 }
 985
 986                 obj = node->ras_obj;
 987                 if (obj->ras_block_match) {
 988                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 989                                 return obj;
 990                 } else {
 991                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 992                                 return obj;
 993                 }
 994         }
 995
 996         return NULL;
 997 }
 998
 999 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
1000 {
1001         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1002         int ret = 0;
1003
1004         /*
1005          * choosing right query method according to
1006          * whether smu support query error information
1007          */
1008         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1009         if (ret == -EOPNOTSUPP) {
1010                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1011                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1012                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1013
1014                 /* umc query_ras_error_address is also responsible for clearing
1015                  * error status
1016                  */
1017                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1018                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1019                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1020         } else if (!ret) {
1021                 if (adev->umc.ras &&
1022                         adev->umc.ras->ecc_info_query_ras_error_count)
1023                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1024
1025                 if (adev->umc.ras &&
1026                         adev->umc.ras->ecc_info_query_ras_error_address)
1027                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1028         }
1029 }
1030
1031 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1032                                               struct ras_manager *ras_mgr,
1033                                               struct ras_err_data *err_data,
1034                                               const char *blk_name,
1035                                               bool is_ue)
1036 {
1037         struct amdgpu_smuio_mcm_config_info *mcm_info;
1038         struct ras_err_node *err_node;
1039         struct ras_err_info *err_info;
1040
1041         if (is_ue) {
1042                 for_each_ras_error(err_node, err_data) {
1043                         err_info = &err_node->err_info;
1044                         mcm_info = &err_info->mcm_info;
1045                         if (err_info->ue_count) {
1046                                 dev_info(adev->dev, "socket: %d, die: %d, "
1047                                          "%lld new uncorrectable hardware errors detected in %s block\n",
1048                                          mcm_info->socket_id,
1049                                          mcm_info->die_id,
1050                                          err_info->ue_count,
1051                                          blk_name);
1052                         }
1053                 }
1054
1055                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1056                         err_info = &err_node->err_info;
1057                         mcm_info = &err_info->mcm_info;
1058                         dev_info(adev->dev, "socket: %d, die: %d, "
1059                                  "%lld uncorrectable hardware errors detected in total in %s block\n",
1060                                  mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name);
1061                 }
1062
1063         } else {
1064                 for_each_ras_error(err_node, err_data) {
1065                         err_info = &err_node->err_info;
1066                         mcm_info = &err_info->mcm_info;
1067                         if (err_info->ce_count) {
1068                                 dev_info(adev->dev, "socket: %d, die: %d, "
1069                                          "%lld new correctable hardware errors detected in %s block, "
1070                                          "no user action is needed\n",
1071                                          mcm_info->socket_id,
1072                                          mcm_info->die_id,
1073                                          err_info->ce_count,
1074                                          blk_name);
1075                         }
1076                 }
1077
1078                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1079                         err_info = &err_node->err_info;
1080                         mcm_info = &err_info->mcm_info;
1081                         dev_info(adev->dev, "socket: %d, die: %d, "
1082                                  "%lld correctable hardware errors detected in total in %s block, "
1083                                  "no user action is needed\n",
1084                                  mcm_info->socket_id, mcm_info->die_id, err_info->ce_count, blk_name);
1085                 }
1086         }
1087 }
1088
1089 static inline bool err_data_has_source_info(struct ras_err_data *data)
1090 {
1091         return !list_empty(&data->err_node_list);
1092 }
1093
1094 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1095                                              struct ras_query_if *query_if,
1096                                              struct ras_err_data *err_data)
1097 {
1098         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1099         const char *blk_name = get_ras_block_str(&query_if->head);
1100
1101         if (err_data->ce_count) {
1102                 if (err_data_has_source_info(err_data)) {
1103                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, false);
1104                 } else if (!adev->aid_mask &&
1105                            adev->smuio.funcs &&
1106                            adev->smuio.funcs->get_socket_id &&
1107                            adev->smuio.funcs->get_die_id) {
1108                         dev_info(adev->dev, "socket: %d, die: %d "
1109                                  "%ld correctable hardware errors "
1110                                  "detected in %s block, no user "
1111                                  "action is needed.\n",
1112                                  adev->smuio.funcs->get_socket_id(adev),
1113                                  adev->smuio.funcs->get_die_id(adev),
1114                                  ras_mgr->err_data.ce_count,
1115                                  blk_name);
1116                 } else {
1117                         dev_info(adev->dev, "%ld correctable hardware errors "
1118                                  "detected in %s block, no user "
1119                                  "action is needed.\n",
1120                                  ras_mgr->err_data.ce_count,
1121                                  blk_name);
1122                 }
1123         }
1124
1125         if (err_data->ue_count) {
1126                 if (err_data_has_source_info(err_data)) {
1127                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, true);
1128                 } else if (!adev->aid_mask &&
1129                            adev->smuio.funcs &&
1130                            adev->smuio.funcs->get_socket_id &&
1131                            adev->smuio.funcs->get_die_id) {
1132                         dev_info(adev->dev, "socket: %d, die: %d "
1133                                  "%ld uncorrectable hardware errors "
1134                                  "detected in %s block\n",
1135                                  adev->smuio.funcs->get_socket_id(adev),
1136                                  adev->smuio.funcs->get_die_id(adev),
1137                                  ras_mgr->err_data.ue_count,
1138                                  blk_name);
1139                 } else {
1140                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1141                                  "detected in %s block\n",
1142                                  ras_mgr->err_data.ue_count,
1143                                  blk_name);
1144                 }
1145         }
1146
1147 }
1148
1149 static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1150 {
1151         struct ras_err_node *err_node;
1152         struct ras_err_info *err_info;
1153
1154         if (err_data_has_source_info(err_data)) {
1155                 for_each_ras_error(err_node, err_data) {
1156                         err_info = &err_node->err_info;
1157
1158                         amdgpu_ras_error_statistic_ce_count(&obj->err_data, &err_info->mcm_info, err_info->ce_count);
1159                         amdgpu_ras_error_statistic_ue_count(&obj->err_data, &err_info->mcm_info, err_info->ue_count);
1160                 }
1161         } else {
1162                 /* for legacy asic path which doesn't has error source info */
1163                 obj->err_data.ue_count += err_data->ue_count;
1164                 obj->err_data.ce_count += err_data->ce_count;
1165         }
1166 }
1167
1168 static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
1169                                                 struct ras_query_if *info,
1170                                                 struct ras_err_data *err_data,
1171                                                 unsigned int error_query_mode)
1172 {
1173         enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT;
1174         struct amdgpu_ras_block_object *block_obj = NULL;
1175
1176         if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
1177                 return -EINVAL;
1178
1179         if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
1180                 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1181                         amdgpu_ras_get_ecc_info(adev, err_data);
1182                 } else {
1183                         block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1184                         if (!block_obj || !block_obj->hw_ops) {
1185                                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1186                                              get_ras_block_str(&info->head));
1187                                 return -EINVAL;
1188                         }
1189
1190                         if (block_obj->hw_ops->query_ras_error_count)
1191                                 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1192
1193                         if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1194                             (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1195                             (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1196                                 if (block_obj->hw_ops->query_ras_error_status)
1197                                         block_obj->hw_ops->query_ras_error_status(adev);
1198                         }
1199                 }
1200         } else {
1201                 /* FIXME: add code to check return value later */
1202                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data);
1203                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data);
1204         }
1205
1206         return 0;
1207 }
1208
1209 /* query/inject/cure begin */
1210 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
1211 {
1212         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1213         struct ras_err_data err_data;
1214         unsigned int error_query_mode;
1215         int ret;
1216
1217         if (!obj)
1218                 return -EINVAL;
1219
1220         ret = amdgpu_ras_error_data_init(&err_data);
1221         if (ret)
1222                 return ret;
1223
1224         if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode))
1225                 return -EINVAL;
1226
1227         ret = amdgpu_ras_query_error_status_helper(adev, info,
1228                                                    &err_data,
1229                                                    error_query_mode);
1230         if (ret)
1231                 goto out_fini_err_data;
1232
1233         amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
1234
1235         info->ue_count = obj->err_data.ue_count;
1236         info->ce_count = obj->err_data.ce_count;
1237
1238         amdgpu_ras_error_generate_report(adev, info, &err_data);
1239
1240 out_fini_err_data:
1241         amdgpu_ras_error_data_fini(&err_data);
1242
1243         return ret;
1244 }
1245
1246 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
1247                 enum amdgpu_ras_block block)
1248 {
1249         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1250         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1251         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
1252         struct amdgpu_hive_info *hive;
1253         int hive_ras_recovery = 0;
1254
1255         if (!block_obj || !block_obj->hw_ops) {
1256                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1257                                 ras_block_str(block));
1258                 return -EOPNOTSUPP;
1259         }
1260
1261         if (!amdgpu_ras_is_supported(adev, block) ||
1262             !amdgpu_ras_get_mca_debug_mode(adev))
1263                 return -EOPNOTSUPP;
1264
1265         hive = amdgpu_get_xgmi_hive(adev);
1266         if (hive) {
1267                 hive_ras_recovery = atomic_read(&hive->ras_recovery);
1268                 amdgpu_put_xgmi_hive(hive);
1269         }
1270
1271         /* skip ras error reset in gpu reset */
1272         if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) ||
1273             hive_ras_recovery) &&
1274             mca_funcs && mca_funcs->mca_set_debug_mode)
1275                 return -EOPNOTSUPP;
1276
1277         if (block_obj->hw_ops->reset_ras_error_count)
1278                 block_obj->hw_ops->reset_ras_error_count(adev);
1279
1280         return 0;
1281 }
1282
1283 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1284                 enum amdgpu_ras_block block)
1285 {
1286         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1287
1288         if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1289                 return 0;
1290
1291         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1292             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1293                 if (block_obj->hw_ops->reset_ras_error_status)
1294                         block_obj->hw_ops->reset_ras_error_status(adev);
1295         }
1296
1297         return 0;
1298 }
1299
1300 /* wrapper of psp_ras_trigger_error */
1301 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1302                 struct ras_inject_if *info)
1303 {
1304         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1305         struct ta_ras_trigger_error_input block_info = {
1306                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1307                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1308                 .sub_block_index = info->head.sub_block_index,
1309                 .address = info->address,
1310                 .value = info->value,
1311         };
1312         int ret = -EINVAL;
1313         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1314                                                         info->head.block,
1315                                                         info->head.sub_block_index);
1316
1317         /* inject on guest isn't allowed, return success directly */
1318         if (amdgpu_sriov_vf(adev))
1319                 return 0;
1320
1321         if (!obj)
1322                 return -EINVAL;
1323
1324         if (!block_obj || !block_obj->hw_ops)   {
1325                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1326                              get_ras_block_str(&info->head));
1327                 return -EINVAL;
1328         }
1329
1330         /* Calculate XGMI relative offset */
1331         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1332             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1333                 block_info.address =
1334                         amdgpu_xgmi_get_relative_phy_addr(adev,
1335                                                           block_info.address);
1336         }
1337
1338         if (block_obj->hw_ops->ras_error_inject) {
1339                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1340                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1341                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1342                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1343                                                 info->instance_mask);
1344         } else {
1345                 /* default path */
1346                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1347         }
1348
1349         if (ret)
1350                 dev_err(adev->dev, "ras inject %s failed %d\n",
1351                         get_ras_block_str(&info->head), ret);
1352
1353         return ret;
1354 }
1355
1356 /**
1357  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1358  * @adev: pointer to AMD GPU device
1359  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1360  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1361  * @query_info: pointer to ras_query_if
1362  *
1363  * Return 0 for query success or do nothing, otherwise return an error
1364  * on failures
1365  */
1366 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1367                                                unsigned long *ce_count,
1368                                                unsigned long *ue_count,
1369                                                struct ras_query_if *query_info)
1370 {
1371         int ret;
1372
1373         if (!query_info)
1374                 /* do nothing if query_info is not specified */
1375                 return 0;
1376
1377         ret = amdgpu_ras_query_error_status(adev, query_info);
1378         if (ret)
1379                 return ret;
1380
1381         *ce_count += query_info->ce_count;
1382         *ue_count += query_info->ue_count;
1383
1384         /* some hardware/IP supports read to clear
1385          * no need to explictly reset the err status after the query call */
1386         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1387             amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1388                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1389                         dev_warn(adev->dev,
1390                                  "Failed to reset error counter and error status\n");
1391         }
1392
1393         return 0;
1394 }
1395
1396 /**
1397  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1398  * @adev: pointer to AMD GPU device
1399  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1400  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1401  * errors.
1402  * @query_info: pointer to ras_query_if if the query request is only for
1403  * specific ip block; if info is NULL, then the qurey request is for
1404  * all the ip blocks that support query ras error counters/status
1405  *
1406  * If set, @ce_count or @ue_count, count and return the corresponding
1407  * error counts in those integer pointers. Return 0 if the device
1408  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1409  */
1410 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1411                                  unsigned long *ce_count,
1412                                  unsigned long *ue_count,
1413                                  struct ras_query_if *query_info)
1414 {
1415         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1416         struct ras_manager *obj;
1417         unsigned long ce, ue;
1418         int ret;
1419
1420         if (!adev->ras_enabled || !con)
1421                 return -EOPNOTSUPP;
1422
1423         /* Don't count since no reporting.
1424          */
1425         if (!ce_count && !ue_count)
1426                 return 0;
1427
1428         ce = 0;
1429         ue = 0;
1430         if (!query_info) {
1431                 /* query all the ip blocks that support ras query interface */
1432                 list_for_each_entry(obj, &con->head, node) {
1433                         struct ras_query_if info = {
1434                                 .head = obj->head,
1435                         };
1436
1437                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1438                 }
1439         } else {
1440                 /* query specific ip block */
1441                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1442         }
1443
1444         if (ret)
1445                 return ret;
1446
1447         if (ce_count)
1448                 *ce_count = ce;
1449
1450         if (ue_count)
1451                 *ue_count = ue;
1452
1453         return 0;
1454 }
1455 /* query/inject/cure end */
1456
1457
1458 /* sysfs begin */
1459
1460 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1461                 struct ras_badpage **bps, unsigned int *count);
1462
1463 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1464 {
1465         switch (flags) {
1466         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1467                 return "R";
1468         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1469                 return "P";
1470         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1471         default:
1472                 return "F";
1473         }
1474 }
1475
1476 /**
1477  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1478  *
1479  * It allows user to read the bad pages of vram on the gpu through
1480  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1481  *
1482  * It outputs multiple lines, and each line stands for one gpu page.
1483  *
1484  * The format of one line is below,
1485  * gpu pfn : gpu page size : flags
1486  *
1487  * gpu pfn and gpu page size are printed in hex format.
1488  * flags can be one of below character,
1489  *
1490  * R: reserved, this gpu page is reserved and not able to use.
1491  *
1492  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1493  * in next window of page_reserve.
1494  *
1495  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1496  *
1497  * Examples:
1498  *
1499  * .. code-block:: bash
1500  *
1501  *      0x00000001 : 0x00001000 : R
1502  *      0x00000002 : 0x00001000 : P
1503  *
1504  */
1505
1506 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1507                 struct kobject *kobj, struct bin_attribute *attr,
1508                 char *buf, loff_t ppos, size_t count)
1509 {
1510         struct amdgpu_ras *con =
1511                 container_of(attr, struct amdgpu_ras, badpages_attr);
1512         struct amdgpu_device *adev = con->adev;
1513         const unsigned int element_size =
1514                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1515         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1516         unsigned int end = div64_ul(ppos + count - 1, element_size);
1517         ssize_t s = 0;
1518         struct ras_badpage *bps = NULL;
1519         unsigned int bps_count = 0;
1520
1521         memset(buf, 0, count);
1522
1523         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1524                 return 0;
1525
1526         for (; start < end && start < bps_count; start++)
1527                 s += scnprintf(&buf[s], element_size + 1,
1528                                 "0x%08x : 0x%08x : %1s\n",
1529                                 bps[start].bp,
1530                                 bps[start].size,
1531                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1532
1533         kfree(bps);
1534
1535         return s;
1536 }
1537
1538 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1539                 struct device_attribute *attr, char *buf)
1540 {
1541         struct amdgpu_ras *con =
1542                 container_of(attr, struct amdgpu_ras, features_attr);
1543
1544         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1545 }
1546
1547 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1548                 struct device_attribute *attr, char *buf)
1549 {
1550         struct amdgpu_ras *con =
1551                 container_of(attr, struct amdgpu_ras, version_attr);
1552         return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1553 }
1554
1555 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1556                 struct device_attribute *attr, char *buf)
1557 {
1558         struct amdgpu_ras *con =
1559                 container_of(attr, struct amdgpu_ras, schema_attr);
1560         return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1561 }
1562
1563 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1564 {
1565         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1566
1567         if (adev->dev->kobj.sd)
1568                 sysfs_remove_file_from_group(&adev->dev->kobj,
1569                                 &con->badpages_attr.attr,
1570                                 RAS_FS_NAME);
1571 }
1572
1573 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1574 {
1575         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1576         struct attribute *attrs[] = {
1577                 &con->features_attr.attr,
1578                 &con->version_attr.attr,
1579                 &con->schema_attr.attr,
1580                 NULL
1581         };
1582         struct attribute_group group = {
1583                 .name = RAS_FS_NAME,
1584                 .attrs = attrs,
1585         };
1586
1587         if (adev->dev->kobj.sd)
1588                 sysfs_remove_group(&adev->dev->kobj, &group);
1589
1590         return 0;
1591 }
1592
1593 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1594                 struct ras_common_if *head)
1595 {
1596         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1597
1598         if (!obj || obj->attr_inuse)
1599                 return -EINVAL;
1600
1601         get_obj(obj);
1602
1603         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1604                 "%s_err_count", head->name);
1605
1606         obj->sysfs_attr = (struct device_attribute){
1607                 .attr = {
1608                         .name = obj->fs_data.sysfs_name,
1609                         .mode = S_IRUGO,
1610                 },
1611                         .show = amdgpu_ras_sysfs_read,
1612         };
1613         sysfs_attr_init(&obj->sysfs_attr.attr);
1614
1615         if (sysfs_add_file_to_group(&adev->dev->kobj,
1616                                 &obj->sysfs_attr.attr,
1617                                 RAS_FS_NAME)) {
1618                 put_obj(obj);
1619                 return -EINVAL;
1620         }
1621
1622         obj->attr_inuse = 1;
1623
1624         return 0;
1625 }
1626
1627 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1628                 struct ras_common_if *head)
1629 {
1630         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1631
1632         if (!obj || !obj->attr_inuse)
1633                 return -EINVAL;
1634
1635         if (adev->dev->kobj.sd)
1636                 sysfs_remove_file_from_group(&adev->dev->kobj,
1637                                 &obj->sysfs_attr.attr,
1638                                 RAS_FS_NAME);
1639         obj->attr_inuse = 0;
1640         put_obj(obj);
1641
1642         return 0;
1643 }
1644
1645 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1646 {
1647         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1648         struct ras_manager *obj, *tmp;
1649
1650         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1651                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1652         }
1653
1654         if (amdgpu_bad_page_threshold != 0)
1655                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1656
1657         amdgpu_ras_sysfs_remove_dev_attr_node(adev);
1658
1659         return 0;
1660 }
1661 /* sysfs end */
1662
1663 /**
1664  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1665  *
1666  * Normally when there is an uncorrectable error, the driver will reset
1667  * the GPU to recover.  However, in the event of an unrecoverable error,
1668  * the driver provides an interface to reboot the system automatically
1669  * in that event.
1670  *
1671  * The following file in debugfs provides that interface:
1672  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1673  *
1674  * Usage:
1675  *
1676  * .. code-block:: bash
1677  *
1678  *      echo true > .../ras/auto_reboot
1679  *
1680  */
1681 /* debugfs begin */
1682 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1683 {
1684         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1685         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1686         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1687         struct dentry     *dir;
1688
1689         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1690         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1691                             &amdgpu_ras_debugfs_ctrl_ops);
1692         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1693                             &amdgpu_ras_debugfs_eeprom_ops);
1694         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1695                            &con->bad_page_cnt_threshold);
1696         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1697         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1698         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1699         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1700                             &amdgpu_ras_debugfs_eeprom_size_ops);
1701         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1702                                                        S_IRUGO, dir, adev,
1703                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1704         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1705
1706         /*
1707          * After one uncorrectable error happens, usually GPU recovery will
1708          * be scheduled. But due to the known problem in GPU recovery failing
1709          * to bring GPU back, below interface provides one direct way to
1710          * user to reboot system automatically in such case within
1711          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1712          * will never be called.
1713          */
1714         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1715
1716         /*
1717          * User could set this not to clean up hardware's error count register
1718          * of RAS IPs during ras recovery.
1719          */
1720         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1721                             &con->disable_ras_err_cnt_harvest);
1722         return dir;
1723 }
1724
1725 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1726                                       struct ras_fs_if *head,
1727                                       struct dentry *dir)
1728 {
1729         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1730
1731         if (!obj || !dir)
1732                 return;
1733
1734         get_obj(obj);
1735
1736         memcpy(obj->fs_data.debugfs_name,
1737                         head->debugfs_name,
1738                         sizeof(obj->fs_data.debugfs_name));
1739
1740         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1741                             obj, &amdgpu_ras_debugfs_ops);
1742 }
1743
1744 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1745 {
1746         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1747         struct dentry *dir;
1748         struct ras_manager *obj;
1749         struct ras_fs_if fs_info;
1750
1751         /*
1752          * it won't be called in resume path, no need to check
1753          * suspend and gpu reset status
1754          */
1755         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1756                 return;
1757
1758         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1759
1760         list_for_each_entry(obj, &con->head, node) {
1761                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1762                         (obj->attr_inuse == 1)) {
1763                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1764                                         get_ras_block_str(&obj->head));
1765                         fs_info.head = obj->head;
1766                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1767                 }
1768         }
1769
1770         amdgpu_mca_smu_debugfs_init(adev, dir);
1771 }
1772
1773 /* debugfs end */
1774
1775 /* ras fs */
1776 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1777                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1778 static DEVICE_ATTR(features, S_IRUGO,
1779                 amdgpu_ras_sysfs_features_read, NULL);
1780 static DEVICE_ATTR(version, 0444,
1781                 amdgpu_ras_sysfs_version_show, NULL);
1782 static DEVICE_ATTR(schema, 0444,
1783                 amdgpu_ras_sysfs_schema_show, NULL);
1784 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1785 {
1786         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1787         struct attribute_group group = {
1788                 .name = RAS_FS_NAME,
1789         };
1790         struct attribute *attrs[] = {
1791                 &con->features_attr.attr,
1792                 &con->version_attr.attr,
1793                 &con->schema_attr.attr,
1794                 NULL
1795         };
1796         struct bin_attribute *bin_attrs[] = {
1797                 NULL,
1798                 NULL,
1799         };
1800         int r;
1801
1802         group.attrs = attrs;
1803
1804         /* add features entry */
1805         con->features_attr = dev_attr_features;
1806         sysfs_attr_init(attrs[0]);
1807
1808         /* add version entry */
1809         con->version_attr = dev_attr_version;
1810         sysfs_attr_init(attrs[1]);
1811
1812         /* add schema entry */
1813         con->schema_attr = dev_attr_schema;
1814         sysfs_attr_init(attrs[2]);
1815
1816         if (amdgpu_bad_page_threshold != 0) {
1817                 /* add bad_page_features entry */
1818                 bin_attr_gpu_vram_bad_pages.private = NULL;
1819                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1820                 bin_attrs[0] = &con->badpages_attr;
1821                 group.bin_attrs = bin_attrs;
1822                 sysfs_bin_attr_init(bin_attrs[0]);
1823         }
1824
1825         r = sysfs_create_group(&adev->dev->kobj, &group);
1826         if (r)
1827                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1828
1829         return 0;
1830 }
1831
1832 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1833 {
1834         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1835         struct ras_manager *con_obj, *ip_obj, *tmp;
1836
1837         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1838                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1839                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1840                         if (ip_obj)
1841                                 put_obj(ip_obj);
1842                 }
1843         }
1844
1845         amdgpu_ras_sysfs_remove_all(adev);
1846         return 0;
1847 }
1848 /* ras fs end */
1849
1850 /* ih begin */
1851
1852 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1853  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1854  * register to check whether the interrupt is triggered or not, and properly
1855  * ack the interrupt if it is there
1856  */
1857 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1858 {
1859         /* Fatal error events are handled on host side */
1860         if (amdgpu_sriov_vf(adev))
1861                 return;
1862
1863         if (adev->nbio.ras &&
1864             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1865                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1866
1867         if (adev->nbio.ras &&
1868             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1869                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1870 }
1871
1872 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1873                                 struct amdgpu_iv_entry *entry)
1874 {
1875         bool poison_stat = false;
1876         struct amdgpu_device *adev = obj->adev;
1877         struct amdgpu_ras_block_object *block_obj =
1878                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1879
1880         if (!block_obj)
1881                 return;
1882
1883         /* both query_poison_status and handle_poison_consumption are optional,
1884          * but at least one of them should be implemented if we need poison
1885          * consumption handler
1886          */
1887         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1888                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1889                 if (!poison_stat) {
1890                         /* Not poison consumption interrupt, no need to handle it */
1891                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1892                                         block_obj->ras_comm.name);
1893
1894                         return;
1895                 }
1896         }
1897
1898         amdgpu_umc_poison_handler(adev, false);
1899
1900         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1901                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1902
1903         /* gpu reset is fallback for failed and default cases */
1904         if (poison_stat) {
1905                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1906                                 block_obj->ras_comm.name);
1907                 amdgpu_ras_reset_gpu(adev);
1908         } else {
1909                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1910         }
1911 }
1912
1913 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1914                                 struct amdgpu_iv_entry *entry)
1915 {
1916         dev_info(obj->adev->dev,
1917                 "Poison is created, no user action is needed.\n");
1918 }
1919
1920 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1921                                 struct amdgpu_iv_entry *entry)
1922 {
1923         struct ras_ih_data *data = &obj->ih_data;
1924         struct ras_err_data err_data;
1925         int ret;
1926
1927         if (!data->cb)
1928                 return;
1929
1930         ret = amdgpu_ras_error_data_init(&err_data);
1931         if (ret)
1932                 return;
1933
1934         /* Let IP handle its data, maybe we need get the output
1935          * from the callback to update the error type/count, etc
1936          */
1937         ret = data->cb(obj->adev, &err_data, entry);
1938         /* ue will trigger an interrupt, and in that case
1939          * we need do a reset to recovery the whole system.
1940          * But leave IP do that recovery, here we just dispatch
1941          * the error.
1942          */
1943         if (ret == AMDGPU_RAS_SUCCESS) {
1944                 /* these counts could be left as 0 if
1945                  * some blocks do not count error number
1946                  */
1947                 obj->err_data.ue_count += err_data.ue_count;
1948                 obj->err_data.ce_count += err_data.ce_count;
1949         }
1950
1951         amdgpu_ras_error_data_fini(&err_data);
1952 }
1953
1954 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1955 {
1956         struct ras_ih_data *data = &obj->ih_data;
1957         struct amdgpu_iv_entry entry;
1958
1959         while (data->rptr != data->wptr) {
1960                 rmb();
1961                 memcpy(&entry, &data->ring[data->rptr],
1962                                 data->element_size);
1963
1964                 wmb();
1965                 data->rptr = (data->aligned_element_size +
1966                                 data->rptr) % data->ring_size;
1967
1968                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1969                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1970                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1971                         else
1972                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1973                 } else {
1974                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1975                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1976                         else
1977                                 dev_warn(obj->adev->dev,
1978                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1979                 }
1980         }
1981 }
1982
1983 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1984 {
1985         struct ras_ih_data *data =
1986                 container_of(work, struct ras_ih_data, ih_work);
1987         struct ras_manager *obj =
1988                 container_of(data, struct ras_manager, ih_data);
1989
1990         amdgpu_ras_interrupt_handler(obj);
1991 }
1992
1993 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1994                 struct ras_dispatch_if *info)
1995 {
1996         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1997         struct ras_ih_data *data = &obj->ih_data;
1998
1999         if (!obj)
2000                 return -EINVAL;
2001
2002         if (data->inuse == 0)
2003                 return 0;
2004
2005         /* Might be overflow... */
2006         memcpy(&data->ring[data->wptr], info->entry,
2007                         data->element_size);
2008
2009         wmb();
2010         data->wptr = (data->aligned_element_size +
2011                         data->wptr) % data->ring_size;
2012
2013         schedule_work(&data->ih_work);
2014
2015         return 0;
2016 }
2017
2018 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
2019                 struct ras_common_if *head)
2020 {
2021         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2022         struct ras_ih_data *data;
2023
2024         if (!obj)
2025                 return -EINVAL;
2026
2027         data = &obj->ih_data;
2028         if (data->inuse == 0)
2029                 return 0;
2030
2031         cancel_work_sync(&data->ih_work);
2032
2033         kfree(data->ring);
2034         memset(data, 0, sizeof(*data));
2035         put_obj(obj);
2036
2037         return 0;
2038 }
2039
2040 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
2041                 struct ras_common_if *head)
2042 {
2043         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2044         struct ras_ih_data *data;
2045         struct amdgpu_ras_block_object *ras_obj;
2046
2047         if (!obj) {
2048                 /* in case we registe the IH before enable ras feature */
2049                 obj = amdgpu_ras_create_obj(adev, head);
2050                 if (!obj)
2051                         return -EINVAL;
2052         } else
2053                 get_obj(obj);
2054
2055         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
2056
2057         data = &obj->ih_data;
2058         /* add the callback.etc */
2059         *data = (struct ras_ih_data) {
2060                 .inuse = 0,
2061                 .cb = ras_obj->ras_cb,
2062                 .element_size = sizeof(struct amdgpu_iv_entry),
2063                 .rptr = 0,
2064                 .wptr = 0,
2065         };
2066
2067         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
2068
2069         data->aligned_element_size = ALIGN(data->element_size, 8);
2070         /* the ring can store 64 iv entries. */
2071         data->ring_size = 64 * data->aligned_element_size;
2072         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
2073         if (!data->ring) {
2074                 put_obj(obj);
2075                 return -ENOMEM;
2076         }
2077
2078         /* IH is ready */
2079         data->inuse = 1;
2080
2081         return 0;
2082 }
2083
2084 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
2085 {
2086         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2087         struct ras_manager *obj, *tmp;
2088
2089         list_for_each_entry_safe(obj, tmp, &con->head, node) {
2090                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
2091         }
2092
2093         return 0;
2094 }
2095 /* ih end */
2096
2097 /* traversal all IPs except NBIO to query error counter */
2098 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
2099 {
2100         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2101         struct ras_manager *obj;
2102
2103         if (!adev->ras_enabled || !con)
2104                 return;
2105
2106         list_for_each_entry(obj, &con->head, node) {
2107                 struct ras_query_if info = {
2108                         .head = obj->head,
2109                 };
2110
2111                 /*
2112                  * PCIE_BIF IP has one different isr by ras controller
2113                  * interrupt, the specific ras counter query will be
2114                  * done in that isr. So skip such block from common
2115                  * sync flood interrupt isr calling.
2116                  */
2117                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2118                         continue;
2119
2120                 /*
2121                  * this is a workaround for aldebaran, skip send msg to
2122                  * smu to get ecc_info table due to smu handle get ecc
2123                  * info table failed temporarily.
2124                  * should be removed until smu fix handle ecc_info table.
2125                  */
2126                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2127                     (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2128                      IP_VERSION(13, 0, 2)))
2129                         continue;
2130
2131                 amdgpu_ras_query_error_status(adev, &info);
2132
2133                 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2134                             IP_VERSION(11, 0, 2) &&
2135                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2136                             IP_VERSION(11, 0, 4) &&
2137                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2138                             IP_VERSION(13, 0, 0)) {
2139                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
2140                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
2141                 }
2142         }
2143 }
2144
2145 /* Parse RdRspStatus and WrRspStatus */
2146 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2147                                           struct ras_query_if *info)
2148 {
2149         struct amdgpu_ras_block_object *block_obj;
2150         /*
2151          * Only two block need to query read/write
2152          * RspStatus at current state
2153          */
2154         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2155                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2156                 return;
2157
2158         block_obj = amdgpu_ras_get_ras_block(adev,
2159                                         info->head.block,
2160                                         info->head.sub_block_index);
2161
2162         if (!block_obj || !block_obj->hw_ops) {
2163                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2164                              get_ras_block_str(&info->head));
2165                 return;
2166         }
2167
2168         if (block_obj->hw_ops->query_ras_error_status)
2169                 block_obj->hw_ops->query_ras_error_status(adev);
2170
2171 }
2172
2173 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2174 {
2175         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2176         struct ras_manager *obj;
2177
2178         if (!adev->ras_enabled || !con)
2179                 return;
2180
2181         list_for_each_entry(obj, &con->head, node) {
2182                 struct ras_query_if info = {
2183                         .head = obj->head,
2184                 };
2185
2186                 amdgpu_ras_error_status_query(adev, &info);
2187         }
2188 }
2189
2190 /* recovery begin */
2191
2192 /* return 0 on success.
2193  * caller need free bps.
2194  */
2195 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2196                 struct ras_badpage **bps, unsigned int *count)
2197 {
2198         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2199         struct ras_err_handler_data *data;
2200         int i = 0;
2201         int ret = 0, status;
2202
2203         if (!con || !con->eh_data || !bps || !count)
2204                 return -EINVAL;
2205
2206         mutex_lock(&con->recovery_lock);
2207         data = con->eh_data;
2208         if (!data || data->count == 0) {
2209                 *bps = NULL;
2210                 ret = -EINVAL;
2211                 goto out;
2212         }
2213
2214         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2215         if (!*bps) {
2216                 ret = -ENOMEM;
2217                 goto out;
2218         }
2219
2220         for (; i < data->count; i++) {
2221                 (*bps)[i] = (struct ras_badpage){
2222                         .bp = data->bps[i].retired_page,
2223                         .size = AMDGPU_GPU_PAGE_SIZE,
2224                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2225                 };
2226                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2227                                 data->bps[i].retired_page);
2228                 if (status == -EBUSY)
2229                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2230                 else if (status == -ENOENT)
2231                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2232         }
2233
2234         *count = data->count;
2235 out:
2236         mutex_unlock(&con->recovery_lock);
2237         return ret;
2238 }
2239
2240 static void amdgpu_ras_do_recovery(struct work_struct *work)
2241 {
2242         struct amdgpu_ras *ras =
2243                 container_of(work, struct amdgpu_ras, recovery_work);
2244         struct amdgpu_device *remote_adev = NULL;
2245         struct amdgpu_device *adev = ras->adev;
2246         struct list_head device_list, *device_list_handle =  NULL;
2247         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2248
2249         if (hive)
2250                 atomic_set(&hive->ras_recovery, 1);
2251         if (!ras->disable_ras_err_cnt_harvest) {
2252
2253                 /* Build list of devices to query RAS related errors */
2254                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2255                         device_list_handle = &hive->device_list;
2256                 } else {
2257                         INIT_LIST_HEAD(&device_list);
2258                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2259                         device_list_handle = &device_list;
2260                 }
2261
2262                 list_for_each_entry(remote_adev,
2263                                 device_list_handle, gmc.xgmi.head) {
2264                         amdgpu_ras_query_err_status(remote_adev);
2265                         amdgpu_ras_log_on_err_counter(remote_adev);
2266                 }
2267
2268         }
2269
2270         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2271                 struct amdgpu_reset_context reset_context;
2272                 memset(&reset_context, 0, sizeof(reset_context));
2273
2274                 reset_context.method = AMD_RESET_METHOD_NONE;
2275                 reset_context.reset_req_dev = adev;
2276
2277                 /* Perform full reset in fatal error mode */
2278                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2279                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2280                 else {
2281                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2282
2283                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2284                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2285                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2286                         }
2287
2288                         /* Fatal error occurs in poison mode, mode1 reset is used to
2289                          * recover gpu.
2290                          */
2291                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2292                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2293                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2294
2295                                 psp_fatal_error_recovery_quirk(&adev->psp);
2296                         }
2297                 }
2298
2299                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2300         }
2301         atomic_set(&ras->in_recovery, 0);
2302         if (hive) {
2303                 atomic_set(&hive->ras_recovery, 0);
2304                 amdgpu_put_xgmi_hive(hive);
2305         }
2306 }
2307
2308 /* alloc/realloc bps array */
2309 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2310                 struct ras_err_handler_data *data, int pages)
2311 {
2312         unsigned int old_space = data->count + data->space_left;
2313         unsigned int new_space = old_space + pages;
2314         unsigned int align_space = ALIGN(new_space, 512);
2315         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2316
2317         if (!bps) {
2318                 return -ENOMEM;
2319         }
2320
2321         if (data->bps) {
2322                 memcpy(bps, data->bps,
2323                                 data->count * sizeof(*data->bps));
2324                 kfree(data->bps);
2325         }
2326
2327         data->bps = bps;
2328         data->space_left += align_space - old_space;
2329         return 0;
2330 }
2331
2332 /* it deal with vram only. */
2333 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2334                 struct eeprom_table_record *bps, int pages)
2335 {
2336         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2337         struct ras_err_handler_data *data;
2338         int ret = 0;
2339         uint32_t i;
2340
2341         if (!con || !con->eh_data || !bps || pages <= 0)
2342                 return 0;
2343
2344         mutex_lock(&con->recovery_lock);
2345         data = con->eh_data;
2346         if (!data)
2347                 goto out;
2348
2349         for (i = 0; i < pages; i++) {
2350                 if (amdgpu_ras_check_bad_page_unlock(con,
2351                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2352                         continue;
2353
2354                 if (!data->space_left &&
2355                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2356                         ret = -ENOMEM;
2357                         goto out;
2358                 }
2359
2360                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2361                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2362                         AMDGPU_GPU_PAGE_SIZE);
2363
2364                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2365                 data->count++;
2366                 data->space_left--;
2367         }
2368 out:
2369         mutex_unlock(&con->recovery_lock);
2370
2371         return ret;
2372 }
2373
2374 /*
2375  * write error record array to eeprom, the function should be
2376  * protected by recovery_lock
2377  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2378  */
2379 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2380                 unsigned long *new_cnt)
2381 {
2382         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2383         struct ras_err_handler_data *data;
2384         struct amdgpu_ras_eeprom_control *control;
2385         int save_count;
2386
2387         if (!con || !con->eh_data) {
2388                 if (new_cnt)
2389                         *new_cnt = 0;
2390
2391                 return 0;
2392         }
2393
2394         mutex_lock(&con->recovery_lock);
2395         control = &con->eeprom_control;
2396         data = con->eh_data;
2397         save_count = data->count - control->ras_num_recs;
2398         mutex_unlock(&con->recovery_lock);
2399
2400         if (new_cnt)
2401                 *new_cnt = save_count / adev->umc.retire_unit;
2402
2403         /* only new entries are saved */
2404         if (save_count > 0) {
2405                 if (amdgpu_ras_eeprom_append(control,
2406                                              &data->bps[control->ras_num_recs],
2407                                              save_count)) {
2408                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2409                         return -EIO;
2410                 }
2411
2412                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2413         }
2414
2415         return 0;
2416 }
2417
2418 /*
2419  * read error record array in eeprom and reserve enough space for
2420  * storing new bad pages
2421  */
2422 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2423 {
2424         struct amdgpu_ras_eeprom_control *control =
2425                 &adev->psp.ras_context.ras->eeprom_control;
2426         struct eeprom_table_record *bps;
2427         int ret;
2428
2429         /* no bad page record, skip eeprom access */
2430         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2431                 return 0;
2432
2433         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2434         if (!bps)
2435                 return -ENOMEM;
2436
2437         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2438         if (ret)
2439                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2440         else
2441                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2442
2443         kfree(bps);
2444         return ret;
2445 }
2446
2447 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2448                                 uint64_t addr)
2449 {
2450         struct ras_err_handler_data *data = con->eh_data;
2451         int i;
2452
2453         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2454         for (i = 0; i < data->count; i++)
2455                 if (addr == data->bps[i].retired_page)
2456                         return true;
2457
2458         return false;
2459 }
2460
2461 /*
2462  * check if an address belongs to bad page
2463  *
2464  * Note: this check is only for umc block
2465  */
2466 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2467                                 uint64_t addr)
2468 {
2469         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2470         bool ret = false;
2471
2472         if (!con || !con->eh_data)
2473                 return ret;
2474
2475         mutex_lock(&con->recovery_lock);
2476         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2477         mutex_unlock(&con->recovery_lock);
2478         return ret;
2479 }
2480
2481 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2482                                           uint32_t max_count)
2483 {
2484         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2485
2486         /*
2487          * Justification of value bad_page_cnt_threshold in ras structure
2488          *
2489          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2490          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2491          * scenarios accordingly.
2492          *
2493          * Bad page retirement enablement:
2494          *    - If amdgpu_bad_page_threshold = -2,
2495          *      bad_page_cnt_threshold = typical value by formula.
2496          *
2497          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2498          *      max record length in eeprom, use it directly.
2499          *
2500          * Bad page retirement disablement:
2501          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2502          *      functionality is disabled, and bad_page_cnt_threshold will
2503          *      take no effect.
2504          */
2505
2506         if (amdgpu_bad_page_threshold < 0) {
2507                 u64 val = adev->gmc.mc_vram_size;
2508
2509                 do_div(val, RAS_BAD_PAGE_COVER);
2510                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2511                                                   max_count);
2512         } else {
2513                 con->bad_page_cnt_threshold = min_t(int, max_count,
2514                                                     amdgpu_bad_page_threshold);
2515         }
2516 }
2517
2518 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2519 {
2520         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2521         struct ras_err_handler_data **data;
2522         u32  max_eeprom_records_count = 0;
2523         bool exc_err_limit = false;
2524         int ret;
2525
2526         if (!con || amdgpu_sriov_vf(adev))
2527                 return 0;
2528
2529         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2530          * supports RAS and debugfs is enabled, but when
2531          * adev->ras_enabled is unset, i.e. when "ras_enable"
2532          * module parameter is set to 0.
2533          */
2534         con->adev = adev;
2535
2536         if (!adev->ras_enabled)
2537                 return 0;
2538
2539         data = &con->eh_data;
2540         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2541         if (!*data) {
2542                 ret = -ENOMEM;
2543                 goto out;
2544         }
2545
2546         mutex_init(&con->recovery_lock);
2547         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2548         atomic_set(&con->in_recovery, 0);
2549         con->eeprom_control.bad_channel_bitmap = 0;
2550
2551         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2552         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2553
2554         /* Todo: During test the SMU might fail to read the eeprom through I2C
2555          * when the GPU is pending on XGMI reset during probe time
2556          * (Mostly after second bus reset), skip it now
2557          */
2558         if (adev->gmc.xgmi.pending_reset)
2559                 return 0;
2560         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2561         /*
2562          * This calling fails when exc_err_limit is true or
2563          * ret != 0.
2564          */
2565         if (exc_err_limit || ret)
2566                 goto free;
2567
2568         if (con->eeprom_control.ras_num_recs) {
2569                 ret = amdgpu_ras_load_bad_pages(adev);
2570                 if (ret)
2571                         goto free;
2572
2573                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2574
2575                 if (con->update_channel_flag == true) {
2576                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2577                         con->update_channel_flag = false;
2578                 }
2579         }
2580
2581 #ifdef CONFIG_X86_MCE_AMD
2582         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2583             (adev->gmc.xgmi.connected_to_cpu))
2584                 amdgpu_register_bad_pages_mca_notifier(adev);
2585 #endif
2586         return 0;
2587
2588 free:
2589         kfree((*data)->bps);
2590         kfree(*data);
2591         con->eh_data = NULL;
2592 out:
2593         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2594
2595         /*
2596          * Except error threshold exceeding case, other failure cases in this
2597          * function would not fail amdgpu driver init.
2598          */
2599         if (!exc_err_limit)
2600                 ret = 0;
2601         else
2602                 ret = -EINVAL;
2603
2604         return ret;
2605 }
2606
2607 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2608 {
2609         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2610         struct ras_err_handler_data *data = con->eh_data;
2611
2612         /* recovery_init failed to init it, fini is useless */
2613         if (!data)
2614                 return 0;
2615
2616         cancel_work_sync(&con->recovery_work);
2617
2618         mutex_lock(&con->recovery_lock);
2619         con->eh_data = NULL;
2620         kfree(data->bps);
2621         kfree(data);
2622         mutex_unlock(&con->recovery_lock);
2623
2624         return 0;
2625 }
2626 /* recovery end */
2627
2628 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2629 {
2630         if (amdgpu_sriov_vf(adev)) {
2631                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2632                 case IP_VERSION(13, 0, 2):
2633                 case IP_VERSION(13, 0, 6):
2634                         return true;
2635                 default:
2636                         return false;
2637                 }
2638         }
2639
2640         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2641                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2642                 case IP_VERSION(13, 0, 0):
2643                 case IP_VERSION(13, 0, 6):
2644                 case IP_VERSION(13, 0, 10):
2645                         return true;
2646                 default:
2647                         return false;
2648                 }
2649         }
2650
2651         return adev->asic_type == CHIP_VEGA10 ||
2652                 adev->asic_type == CHIP_VEGA20 ||
2653                 adev->asic_type == CHIP_ARCTURUS ||
2654                 adev->asic_type == CHIP_ALDEBARAN ||
2655                 adev->asic_type == CHIP_SIENNA_CICHLID;
2656 }
2657
2658 /*
2659  * this is workaround for vega20 workstation sku,
2660  * force enable gfx ras, ignore vbios gfx ras flag
2661  * due to GC EDC can not write
2662  */
2663 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2664 {
2665         struct atom_context *ctx = adev->mode_info.atom_context;
2666
2667         if (!ctx)
2668                 return;
2669
2670         if (strnstr(ctx->vbios_pn, "D16406",
2671                     sizeof(ctx->vbios_pn)) ||
2672                 strnstr(ctx->vbios_pn, "D36002",
2673                         sizeof(ctx->vbios_pn)))
2674                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2675 }
2676
2677 /*
2678  * check hardware's ras ability which will be saved in hw_supported.
2679  * if hardware does not support ras, we can skip some ras initializtion and
2680  * forbid some ras operations from IP.
2681  * if software itself, say boot parameter, limit the ras ability. We still
2682  * need allow IP do some limited operations, like disable. In such case,
2683  * we have to initialize ras as normal. but need check if operation is
2684  * allowed or not in each function.
2685  */
2686 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2687 {
2688         adev->ras_hw_enabled = adev->ras_enabled = 0;
2689
2690         if (!amdgpu_ras_asic_supported(adev))
2691                 return;
2692
2693         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2694                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2695                         dev_info(adev->dev, "MEM ECC is active.\n");
2696                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2697                                                    1 << AMDGPU_RAS_BLOCK__DF);
2698                 } else {
2699                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2700                 }
2701
2702                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2703                         dev_info(adev->dev, "SRAM ECC is active.\n");
2704                         if (!amdgpu_sriov_vf(adev))
2705                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2706                                                             1 << AMDGPU_RAS_BLOCK__DF);
2707                         else
2708                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2709                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2710                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2711
2712                         /* VCN/JPEG RAS can be supported on both bare metal and
2713                          * SRIOV environment
2714                          */
2715                         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2716                                     IP_VERSION(2, 6, 0) ||
2717                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2718                                     IP_VERSION(4, 0, 0) ||
2719                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2720                                     IP_VERSION(4, 0, 3))
2721                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2722                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2723                         else
2724                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2725                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2726
2727                         /*
2728                          * XGMI RAS is not supported if xgmi num physical nodes
2729                          * is zero
2730                          */
2731                         if (!adev->gmc.xgmi.num_physical_nodes)
2732                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2733                 } else {
2734                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2735                 }
2736         } else {
2737                 /* driver only manages a few IP blocks RAS feature
2738                  * when GPU is connected cpu through XGMI */
2739                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2740                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2741                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2742         }
2743
2744         amdgpu_ras_get_quirks(adev);
2745
2746         /* hw_supported needs to be aligned with RAS block mask. */
2747         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2748
2749         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2750                 adev->ras_hw_enabled & amdgpu_ras_mask;
2751 }
2752
2753 static void amdgpu_ras_counte_dw(struct work_struct *work)
2754 {
2755         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2756                                               ras_counte_delay_work.work);
2757         struct amdgpu_device *adev = con->adev;
2758         struct drm_device *dev = adev_to_drm(adev);
2759         unsigned long ce_count, ue_count;
2760         int res;
2761
2762         res = pm_runtime_get_sync(dev->dev);
2763         if (res < 0)
2764                 goto Out;
2765
2766         /* Cache new values.
2767          */
2768         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2769                 atomic_set(&con->ras_ce_count, ce_count);
2770                 atomic_set(&con->ras_ue_count, ue_count);
2771         }
2772
2773         pm_runtime_mark_last_busy(dev->dev);
2774 Out:
2775         pm_runtime_put_autosuspend(dev->dev);
2776 }
2777
2778 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2779 {
2780         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2781         bool df_poison, umc_poison;
2782
2783         /* poison setting is useless on SRIOV guest */
2784         if (amdgpu_sriov_vf(adev) || !con)
2785                 return;
2786
2787         /* Init poison supported flag, the default value is false */
2788         if (adev->gmc.xgmi.connected_to_cpu ||
2789             adev->gmc.is_app_apu) {
2790                 /* enabled by default when GPU is connected to CPU */
2791                 con->poison_supported = true;
2792         } else if (adev->df.funcs &&
2793             adev->df.funcs->query_ras_poison_mode &&
2794             adev->umc.ras &&
2795             adev->umc.ras->query_ras_poison_mode) {
2796                 df_poison =
2797                         adev->df.funcs->query_ras_poison_mode(adev);
2798                 umc_poison =
2799                         adev->umc.ras->query_ras_poison_mode(adev);
2800
2801                 /* Only poison is set in both DF and UMC, we can support it */
2802                 if (df_poison && umc_poison)
2803                         con->poison_supported = true;
2804                 else if (df_poison != umc_poison)
2805                         dev_warn(adev->dev,
2806                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2807                                 df_poison, umc_poison);
2808         }
2809 }
2810
2811 static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
2812 {
2813         return  amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
2814                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
2815                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
2816                         AMDGPU_RAS_ERROR__PARITY;
2817 }
2818
2819 int amdgpu_ras_init(struct amdgpu_device *adev)
2820 {
2821         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2822         int r;
2823
2824         if (con)
2825                 return 0;
2826
2827         con = kmalloc(sizeof(struct amdgpu_ras) +
2828                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2829                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2830                         GFP_KERNEL|__GFP_ZERO);
2831         if (!con)
2832                 return -ENOMEM;
2833
2834         con->adev = adev;
2835         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2836         atomic_set(&con->ras_ce_count, 0);
2837         atomic_set(&con->ras_ue_count, 0);
2838
2839         con->objs = (struct ras_manager *)(con + 1);
2840
2841         amdgpu_ras_set_context(adev, con);
2842
2843         amdgpu_ras_check_supported(adev);
2844
2845         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2846                 /* set gfx block ras context feature for VEGA20 Gaming
2847                  * send ras disable cmd to ras ta during ras late init.
2848                  */
2849                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2850                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2851
2852                         return 0;
2853                 }
2854
2855                 r = 0;
2856                 goto release_con;
2857         }
2858
2859         con->update_channel_flag = false;
2860         con->features = 0;
2861         con->schema = 0;
2862         INIT_LIST_HEAD(&con->head);
2863         /* Might need get this flag from vbios. */
2864         con->flags = RAS_DEFAULT_FLAGS;
2865
2866         /* initialize nbio ras function ahead of any other
2867          * ras functions so hardware fatal error interrupt
2868          * can be enabled as early as possible */
2869         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2870         case IP_VERSION(7, 4, 0):
2871         case IP_VERSION(7, 4, 1):
2872         case IP_VERSION(7, 4, 4):
2873                 if (!adev->gmc.xgmi.connected_to_cpu)
2874                         adev->nbio.ras = &nbio_v7_4_ras;
2875                 break;
2876         case IP_VERSION(4, 3, 0):
2877                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2878                         /* unlike other generation of nbio ras,
2879                          * nbio v4_3 only support fatal error interrupt
2880                          * to inform software that DF is freezed due to
2881                          * system fatal error event. driver should not
2882                          * enable nbio ras in such case. Instead,
2883                          * check DF RAS */
2884                         adev->nbio.ras = &nbio_v4_3_ras;
2885                 break;
2886         case IP_VERSION(7, 9, 0):
2887                 if (!adev->gmc.is_app_apu)
2888                         adev->nbio.ras = &nbio_v7_9_ras;
2889                 break;
2890         default:
2891                 /* nbio ras is not available */
2892                 break;
2893         }
2894
2895         /* nbio ras block needs to be enabled ahead of other ras blocks
2896          * to handle fatal error */
2897         r = amdgpu_nbio_ras_sw_init(adev);
2898         if (r)
2899                 return r;
2900
2901         if (adev->nbio.ras &&
2902             adev->nbio.ras->init_ras_controller_interrupt) {
2903                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2904                 if (r)
2905                         goto release_con;
2906         }
2907
2908         if (adev->nbio.ras &&
2909             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2910                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2911                 if (r)
2912                         goto release_con;
2913         }
2914
2915         amdgpu_ras_query_poison_mode(adev);
2916
2917         /* Get RAS schema for particular SOC */
2918         con->schema = amdgpu_get_ras_schema(adev);
2919
2920         if (amdgpu_ras_fs_init(adev)) {
2921                 r = -EINVAL;
2922                 goto release_con;
2923         }
2924
2925         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2926                  "hardware ability[%x] ras_mask[%x]\n",
2927                  adev->ras_hw_enabled, adev->ras_enabled);
2928
2929         return 0;
2930 release_con:
2931         amdgpu_ras_set_context(adev, NULL);
2932         kfree(con);
2933
2934         return r;
2935 }
2936
2937 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2938 {
2939         if (adev->gmc.xgmi.connected_to_cpu ||
2940             adev->gmc.is_app_apu)
2941                 return 1;
2942         return 0;
2943 }
2944
2945 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2946                                         struct ras_common_if *ras_block)
2947 {
2948         struct ras_query_if info = {
2949                 .head = *ras_block,
2950         };
2951
2952         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2953                 return 0;
2954
2955         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2956                 DRM_WARN("RAS init harvest failure");
2957
2958         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2959                 DRM_WARN("RAS init harvest reset failure");
2960
2961         return 0;
2962 }
2963
2964 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2965 {
2966        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2967
2968        if (!con)
2969                return false;
2970
2971        return con->poison_supported;
2972 }
2973
2974 /* helper function to handle common stuff in ip late init phase */
2975 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2976                          struct ras_common_if *ras_block)
2977 {
2978         struct amdgpu_ras_block_object *ras_obj = NULL;
2979         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2980         struct ras_query_if *query_info;
2981         unsigned long ue_count, ce_count;
2982         int r;
2983
2984         /* disable RAS feature per IP block if it is not supported */
2985         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2986                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2987                 return 0;
2988         }
2989
2990         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2991         if (r) {
2992                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2993                         /* in resume phase, if fail to enable ras,
2994                          * clean up all ras fs nodes, and disable ras */
2995                         goto cleanup;
2996                 } else
2997                         return r;
2998         }
2999
3000         /* check for errors on warm reset edc persisant supported ASIC */
3001         amdgpu_persistent_edc_harvesting(adev, ras_block);
3002
3003         /* in resume phase, no need to create ras fs node */
3004         if (adev->in_suspend || amdgpu_in_reset(adev))
3005                 return 0;
3006
3007         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3008         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
3009             (ras_obj->hw_ops->query_poison_status ||
3010             ras_obj->hw_ops->handle_poison_consumption))) {
3011                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
3012                 if (r)
3013                         goto cleanup;
3014         }
3015
3016         if (ras_obj->hw_ops &&
3017             (ras_obj->hw_ops->query_ras_error_count ||
3018              ras_obj->hw_ops->query_ras_error_status)) {
3019                 r = amdgpu_ras_sysfs_create(adev, ras_block);
3020                 if (r)
3021                         goto interrupt;
3022
3023                 /* Those are the cached values at init.
3024                  */
3025                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
3026                 if (!query_info)
3027                         return -ENOMEM;
3028                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
3029
3030                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
3031                         atomic_set(&con->ras_ce_count, ce_count);
3032                         atomic_set(&con->ras_ue_count, ue_count);
3033                 }
3034
3035                 kfree(query_info);
3036         }
3037
3038         return 0;
3039
3040 interrupt:
3041         if (ras_obj->ras_cb)
3042                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3043 cleanup:
3044         amdgpu_ras_feature_enable(adev, ras_block, 0);
3045         return r;
3046 }
3047
3048 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
3049                          struct ras_common_if *ras_block)
3050 {
3051         return amdgpu_ras_block_late_init(adev, ras_block);
3052 }
3053
3054 /* helper function to remove ras fs node and interrupt handler */
3055 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
3056                           struct ras_common_if *ras_block)
3057 {
3058         struct amdgpu_ras_block_object *ras_obj;
3059         if (!ras_block)
3060                 return;
3061
3062         amdgpu_ras_sysfs_remove(adev, ras_block);
3063
3064         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3065         if (ras_obj->ras_cb)
3066                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3067 }
3068
3069 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
3070                           struct ras_common_if *ras_block)
3071 {
3072         return amdgpu_ras_block_late_fini(adev, ras_block);
3073 }
3074
3075 /* do some init work after IP late init as dependence.
3076  * and it runs in resume/gpu reset/booting up cases.
3077  */
3078 void amdgpu_ras_resume(struct amdgpu_device *adev)
3079 {
3080         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3081         struct ras_manager *obj, *tmp;
3082
3083         if (!adev->ras_enabled || !con) {
3084                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
3085                 amdgpu_release_ras_context(adev);
3086
3087                 return;
3088         }
3089
3090         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
3091                 /* Set up all other IPs which are not implemented. There is a
3092                  * tricky thing that IP's actual ras error type should be
3093                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3094                  * ERROR_NONE make sense anyway.
3095                  */
3096                 amdgpu_ras_enable_all_features(adev, 1);
3097
3098                 /* We enable ras on all hw_supported block, but as boot
3099                  * parameter might disable some of them and one or more IP has
3100                  * not implemented yet. So we disable them on behalf.
3101                  */
3102                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3103                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3104                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3105                                 /* there should be no any reference. */
3106                                 WARN_ON(alive_obj(obj));
3107                         }
3108                 }
3109         }
3110 }
3111
3112 void amdgpu_ras_suspend(struct amdgpu_device *adev)
3113 {
3114         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3115
3116         if (!adev->ras_enabled || !con)
3117                 return;
3118
3119         amdgpu_ras_disable_all_features(adev, 0);
3120         /* Make sure all ras objects are disabled. */
3121         if (con->features)
3122                 amdgpu_ras_disable_all_features(adev, 1);
3123 }
3124
3125 int amdgpu_ras_late_init(struct amdgpu_device *adev)
3126 {
3127         struct amdgpu_ras_block_list *node, *tmp;
3128         struct amdgpu_ras_block_object *obj;
3129         int r;
3130
3131         /* Guest side doesn't need init ras feature */
3132         if (amdgpu_sriov_vf(adev))
3133                 return 0;
3134
3135         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3136                 if (!node->ras_obj) {
3137                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3138                         continue;
3139                 }
3140
3141                 obj = node->ras_obj;
3142                 if (obj->ras_late_init) {
3143                         r = obj->ras_late_init(adev, &obj->ras_comm);
3144                         if (r) {
3145                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3146                                         obj->ras_comm.name, r);
3147                                 return r;
3148                         }
3149                 } else
3150                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3151         }
3152
3153         return 0;
3154 }
3155
3156 /* do some fini work before IP fini as dependence */
3157 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3158 {
3159         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3160
3161         if (!adev->ras_enabled || !con)
3162                 return 0;
3163
3164
3165         /* Need disable ras on all IPs here before ip [hw/sw]fini */
3166         if (con->features)
3167                 amdgpu_ras_disable_all_features(adev, 0);
3168         amdgpu_ras_recovery_fini(adev);
3169         return 0;
3170 }
3171
3172 int amdgpu_ras_fini(struct amdgpu_device *adev)
3173 {
3174         struct amdgpu_ras_block_list *ras_node, *tmp;
3175         struct amdgpu_ras_block_object *obj = NULL;
3176         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3177
3178         if (!adev->ras_enabled || !con)
3179                 return 0;
3180
3181         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3182                 if (ras_node->ras_obj) {
3183                         obj = ras_node->ras_obj;
3184                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3185                             obj->ras_fini)
3186                                 obj->ras_fini(adev, &obj->ras_comm);
3187                         else
3188                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3189                 }
3190
3191                 /* Clear ras blocks from ras_list and free ras block list node */
3192                 list_del(&ras_node->node);
3193                 kfree(ras_node);
3194         }
3195
3196         amdgpu_ras_fs_fini(adev);
3197         amdgpu_ras_interrupt_remove_all(adev);
3198
3199         WARN(con->features, "Feature mask is not cleared");
3200
3201         if (con->features)
3202                 amdgpu_ras_disable_all_features(adev, 1);
3203
3204         cancel_delayed_work_sync(&con->ras_counte_delay_work);
3205
3206         amdgpu_ras_set_context(adev, NULL);
3207         kfree(con);
3208
3209         return 0;
3210 }
3211
3212 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3213 {
3214         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
3215                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3216
3217                 dev_info(adev->dev, "uncorrectable hardware error"
3218                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
3219
3220                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
3221                 amdgpu_ras_reset_gpu(adev);
3222         }
3223 }
3224
3225 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3226 {
3227         if (adev->asic_type == CHIP_VEGA20 &&
3228             adev->pm.fw_version <= 0x283400) {
3229                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3230                                 amdgpu_ras_intr_triggered();
3231         }
3232
3233         return false;
3234 }
3235
3236 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3237 {
3238         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3239
3240         if (!con)
3241                 return;
3242
3243         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3244                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3245                 amdgpu_ras_set_context(adev, NULL);
3246                 kfree(con);
3247         }
3248 }
3249
3250 #ifdef CONFIG_X86_MCE_AMD
3251 static struct amdgpu_device *find_adev(uint32_t node_id)
3252 {
3253         int i;
3254         struct amdgpu_device *adev = NULL;
3255
3256         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3257                 adev = mce_adev_list.devs[i];
3258
3259                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3260                     adev->gmc.xgmi.physical_node_id == node_id)
3261                         break;
3262                 adev = NULL;
3263         }
3264
3265         return adev;
3266 }
3267
3268 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3269 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3270 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3271 #define GPU_ID_OFFSET           8
3272
3273 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3274                                     unsigned long val, void *data)
3275 {
3276         struct mce *m = (struct mce *)data;
3277         struct amdgpu_device *adev = NULL;
3278         uint32_t gpu_id = 0;
3279         uint32_t umc_inst = 0, ch_inst = 0;
3280
3281         /*
3282          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3283          * and error occurred in DramECC (Extended error code = 0) then only
3284          * process the error, else bail out.
3285          */
3286         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3287                     (XEC(m->status, 0x3f) == 0x0)))
3288                 return NOTIFY_DONE;
3289
3290         /*
3291          * If it is correctable error, return.
3292          */
3293         if (mce_is_correctable(m))
3294                 return NOTIFY_OK;
3295
3296         /*
3297          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3298          */
3299         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3300
3301         adev = find_adev(gpu_id);
3302         if (!adev) {
3303                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3304                                                                 gpu_id);
3305                 return NOTIFY_DONE;
3306         }
3307
3308         /*
3309          * If it is uncorrectable error, then find out UMC instance and
3310          * channel index.
3311          */
3312         umc_inst = GET_UMC_INST(m->ipid);
3313         ch_inst = GET_CHAN_INDEX(m->ipid);
3314
3315         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3316                              umc_inst, ch_inst);
3317
3318         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3319                 return NOTIFY_OK;
3320         else
3321                 return NOTIFY_DONE;
3322 }
3323
3324 static struct notifier_block amdgpu_bad_page_nb = {
3325         .notifier_call  = amdgpu_bad_page_notifier,
3326         .priority       = MCE_PRIO_UC,
3327 };
3328
3329 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3330 {
3331         /*
3332          * Add the adev to the mce_adev_list.
3333          * During mode2 reset, amdgpu device is temporarily
3334          * removed from the mgpu_info list which can cause
3335          * page retirement to fail.
3336          * Use this list instead of mgpu_info to find the amdgpu
3337          * device on which the UMC error was reported.
3338          */
3339         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3340
3341         /*
3342          * Register the x86 notifier only once
3343          * with MCE subsystem.
3344          */
3345         if (notifier_registered == false) {
3346                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3347                 notifier_registered = true;
3348         }
3349 }
3350 #endif
3351
3352 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3353 {
3354         if (!adev)
3355                 return NULL;
3356
3357         return adev->psp.ras_context.ras;
3358 }
3359
3360 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3361 {
3362         if (!adev)
3363                 return -EINVAL;
3364
3365         adev->psp.ras_context.ras = ras_con;
3366         return 0;
3367 }
3368
3369 /* check if ras is supported on block, say, sdma, gfx */
3370 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3371                 unsigned int block)
3372 {
3373         int ret = 0;
3374         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3375
3376         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3377                 return 0;
3378
3379         ret = ras && (adev->ras_enabled & (1 << block));
3380
3381         /* For the special asic with mem ecc enabled but sram ecc
3382          * not enabled, even if the ras block is not supported on
3383          * .ras_enabled, if the asic supports poison mode and the
3384          * ras block has ras configuration, it can be considered
3385          * that the ras block supports ras function.
3386          */
3387         if (!ret &&
3388             (block == AMDGPU_RAS_BLOCK__GFX ||
3389              block == AMDGPU_RAS_BLOCK__SDMA ||
3390              block == AMDGPU_RAS_BLOCK__VCN ||
3391              block == AMDGPU_RAS_BLOCK__JPEG) &&
3392             amdgpu_ras_is_poison_mode_supported(adev) &&
3393             amdgpu_ras_get_ras_block(adev, block, 0))
3394                 ret = 1;
3395
3396         return ret;
3397 }
3398
3399 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3400 {
3401         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3402
3403         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3404                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3405         return 0;
3406 }
3407
3408 void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
3409 {
3410         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3411
3412         if (con)
3413                 con->is_mca_debug_mode = enable;
3414 }
3415
3416 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev)
3417 {
3418         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3419         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3420
3421         if (!con)
3422                 return false;
3423
3424         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3425                 return con->is_mca_debug_mode;
3426         else
3427                 return true;
3428 }
3429
3430 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
3431                                      unsigned int *error_query_mode)
3432 {
3433         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3434         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3435
3436         if (!con) {
3437                 *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY;
3438                 return false;
3439         }
3440
3441         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3442                 *error_query_mode =
3443                         (con->is_mca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY;
3444         else
3445                 *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY;
3446
3447         return true;
3448 }
3449
3450 /* Register each ip ras block into amdgpu ras */
3451 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3452                 struct amdgpu_ras_block_object *ras_block_obj)
3453 {
3454         struct amdgpu_ras_block_list *ras_node;
3455         if (!adev || !ras_block_obj)
3456                 return -EINVAL;
3457
3458         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3459         if (!ras_node)
3460                 return -ENOMEM;
3461
3462         INIT_LIST_HEAD(&ras_node->node);
3463         ras_node->ras_obj = ras_block_obj;
3464         list_add_tail(&ras_node->node, &adev->ras_list);
3465
3466         return 0;
3467 }
3468
3469 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3470 {
3471         if (!err_type_name)
3472                 return;
3473
3474         switch (err_type) {
3475         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3476                 sprintf(err_type_name, "correctable");
3477                 break;
3478         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3479                 sprintf(err_type_name, "uncorrectable");
3480                 break;
3481         default:
3482                 sprintf(err_type_name, "unknown");
3483                 break;
3484         }
3485 }
3486
3487 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3488                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3489                                          uint32_t instance,
3490                                          uint32_t *memory_id)
3491 {
3492         uint32_t err_status_lo_data, err_status_lo_offset;
3493
3494         if (!reg_entry)
3495                 return false;
3496
3497         err_status_lo_offset =
3498                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3499                                             reg_entry->seg_lo, reg_entry->reg_lo);
3500         err_status_lo_data = RREG32(err_status_lo_offset);
3501
3502         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3503             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3504                 return false;
3505
3506         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3507
3508         return true;
3509 }
3510
3511 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3512                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3513                                        uint32_t instance,
3514                                        unsigned long *err_cnt)
3515 {
3516         uint32_t err_status_hi_data, err_status_hi_offset;
3517
3518         if (!reg_entry)
3519                 return false;
3520
3521         err_status_hi_offset =
3522                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3523                                             reg_entry->seg_hi, reg_entry->reg_hi);
3524         err_status_hi_data = RREG32(err_status_hi_offset);
3525
3526         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3527             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3528                 /* keep the check here in case we need to refer to the result later */
3529                 dev_dbg(adev->dev, "Invalid err_info field\n");
3530
3531         /* read err count */
3532         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3533
3534         return true;
3535 }
3536
3537 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3538                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3539                                            uint32_t reg_list_size,
3540                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3541                                            uint32_t mem_list_size,
3542                                            uint32_t instance,
3543                                            uint32_t err_type,
3544                                            unsigned long *err_count)
3545 {
3546         uint32_t memory_id;
3547         unsigned long err_cnt;
3548         char err_type_name[16];
3549         uint32_t i, j;
3550
3551         for (i = 0; i < reg_list_size; i++) {
3552                 /* query memory_id from err_status_lo */
3553                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3554                                                          instance, &memory_id))
3555                         continue;
3556
3557                 /* query err_cnt from err_status_hi */
3558                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3559                                                        instance, &err_cnt) ||
3560                     !err_cnt)
3561                         continue;
3562
3563                 *err_count += err_cnt;
3564
3565                 /* log the errors */
3566                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3567                 if (!mem_list) {
3568                         /* memory_list is not supported */
3569                         dev_info(adev->dev,
3570                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3571                                  err_cnt, err_type_name,
3572                                  reg_list[i].block_name,
3573                                  instance, memory_id);
3574                 } else {
3575                         for (j = 0; j < mem_list_size; j++) {
3576                                 if (memory_id == mem_list[j].memory_id) {
3577                                         dev_info(adev->dev,
3578                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3579                                                  err_cnt, err_type_name,
3580                                                  reg_list[i].block_name,
3581                                                  instance, mem_list[j].name);
3582                                         break;
3583                                 }
3584                         }
3585                 }
3586         }
3587 }
3588
3589 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3590                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3591                                            uint32_t reg_list_size,
3592                                            uint32_t instance)
3593 {
3594         uint32_t err_status_lo_offset, err_status_hi_offset;
3595         uint32_t i;
3596
3597         for (i = 0; i < reg_list_size; i++) {
3598                 err_status_lo_offset =
3599                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3600                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3601                 err_status_hi_offset =
3602                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3603                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3604                 WREG32(err_status_lo_offset, 0);
3605                 WREG32(err_status_hi_offset, 0);
3606         }
3607 }
3608
3609 int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
3610 {
3611         memset(err_data, 0, sizeof(*err_data));
3612
3613         INIT_LIST_HEAD(&err_data->err_node_list);
3614
3615         return 0;
3616 }
3617
3618 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
3619 {
3620         if (!err_node)
3621                 return;
3622
3623         list_del(&err_node->node);
3624         kvfree(err_node);
3625 }
3626
3627 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
3628 {
3629         struct ras_err_node *err_node, *tmp;
3630
3631         list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
3632                 amdgpu_ras_error_node_release(err_node);
3633 }
3634
3635 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
3636                                                              struct amdgpu_smuio_mcm_config_info *mcm_info)
3637 {
3638         struct ras_err_node *err_node;
3639         struct amdgpu_smuio_mcm_config_info *ref_id;
3640
3641         if (!err_data || !mcm_info)
3642                 return NULL;
3643
3644         for_each_ras_error(err_node, err_data) {
3645                 ref_id = &err_node->err_info.mcm_info;
3646
3647                 if (mcm_info->socket_id == ref_id->socket_id &&
3648                     mcm_info->die_id == ref_id->die_id)
3649                         return err_node;
3650         }
3651
3652         return NULL;
3653 }
3654
3655 static struct ras_err_node *amdgpu_ras_error_node_new(void)
3656 {
3657         struct ras_err_node *err_node;
3658
3659         err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
3660         if (!err_node)
3661                 return NULL;
3662
3663         INIT_LIST_HEAD(&err_node->node);
3664
3665         return err_node;
3666 }
3667
3668 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
3669                                                       struct amdgpu_smuio_mcm_config_info *mcm_info)
3670 {
3671         struct ras_err_node *err_node;
3672
3673         err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
3674         if (err_node)
3675                 return &err_node->err_info;
3676
3677         err_node = amdgpu_ras_error_node_new();
3678         if (!err_node)
3679                 return NULL;
3680
3681         memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
3682
3683         err_data->err_list_count++;
3684         list_add_tail(&err_node->node, &err_data->err_node_list);
3685
3686         return &err_node->err_info;
3687 }
3688
3689 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
3690                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3691 {
3692         struct ras_err_info *err_info;
3693
3694         if (!err_data || !mcm_info)
3695                 return -EINVAL;
3696
3697         if (!count)
3698                 return 0;
3699
3700         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3701         if (!err_info)
3702                 return -EINVAL;
3703
3704         err_info->ue_count += count;
3705         err_data->ue_count += count;
3706
3707         return 0;
3708 }
3709
3710 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
3711                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3712 {
3713         struct ras_err_info *err_info;
3714
3715         if (!err_data || !mcm_info)
3716                 return -EINVAL;
3717
3718         if (!count)
3719                 return 0;
3720
3721         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3722         if (!err_info)
3723                 return -EINVAL;
3724
3725         err_info->ce_count += count;
3726         err_data->ce_count += count;
3727
3728         return 0;
3729 }