drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "nbio_v7_9.h"
  39 #include "atom.h"
  40 #include "amdgpu_reset.h"
  41
  42 #ifdef CONFIG_X86_MCE_AMD
  43 #include <asm/mce.h>
  44
  45 static bool notifier_registered;
  46 #endif
  47 static const char *RAS_FS_NAME = "ras";
  48
  49 const char *ras_error_string[] = {
  50         "none",
  51         "parity",
  52         "single_correctable",
  53         "multi_uncorrectable",
  54         "poison",
  55 };
  56
  57 const char *ras_block_string[] = {
  58         "umc",
  59         "sdma",
  60         "gfx",
  61         "mmhub",
  62         "athub",
  63         "pcie_bif",
  64         "hdp",
  65         "xgmi_wafl",
  66         "df",
  67         "smn",
  68         "sem",
  69         "mp0",
  70         "mp1",
  71         "fuse",
  72         "mca",
  73         "vcn",
  74         "jpeg",
  75 };
  76
  77 const char *ras_mca_block_string[] = {
  78         "mca_mp0",
  79         "mca_mp1",
  80         "mca_mpio",
  81         "mca_iohc",
  82 };
  83
  84 struct amdgpu_ras_block_list {
  85         /* ras block link */
  86         struct list_head node;
  87
  88         struct amdgpu_ras_block_object *ras_obj;
  89 };
  90
  91 const char *get_ras_block_str(struct ras_common_if *ras_block)
  92 {
  93         if (!ras_block)
  94                 return "NULL";
  95
  96         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  97                 return "OUT OF RANGE";
  98
  99         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 100                 return ras_mca_block_string[ras_block->sub_block_index];
 101
 102         return ras_block_string[ras_block->block];
 103 }
 104
 105 #define ras_block_str(_BLOCK_) \
 106         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 107
 108 #define ras_err_str(i) (ras_error_string[ffs(i)])
 109
 110 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 111
 112 /* inject address is 52 bits */
 113 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 114
 115 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 116 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 117
 118 enum amdgpu_ras_retire_page_reservation {
 119         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 120         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 121         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 122 };
 123
 124 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 125
 126 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 127                                 uint64_t addr);
 128 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 129                                 uint64_t addr);
 130 #ifdef CONFIG_X86_MCE_AMD
 131 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 132 struct mce_notifier_adev_list {
 133         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 134         int num_gpu;
 135 };
 136 static struct mce_notifier_adev_list mce_adev_list;
 137 #endif
 138
 139 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 140 {
 141         if (adev && amdgpu_ras_get_context(adev))
 142                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 143 }
 144
 145 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 146 {
 147         if (adev && amdgpu_ras_get_context(adev))
 148                 return amdgpu_ras_get_context(adev)->error_query_ready;
 149
 150         return false;
 151 }
 152
 153 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 154 {
 155         struct ras_err_data err_data;
 156         struct eeprom_table_record err_rec;
 157         int ret;
 158
 159         if ((address >= adev->gmc.mc_vram_size) ||
 160             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 161                 dev_warn(adev->dev,
 162                          "RAS WARN: input address 0x%llx is invalid.\n",
 163                          address);
 164                 return -EINVAL;
 165         }
 166
 167         if (amdgpu_ras_check_bad_page(adev, address)) {
 168                 dev_warn(adev->dev,
 169                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 170                          address);
 171                 return 0;
 172         }
 173
 174         ret = amdgpu_ras_error_data_init(&err_data);
 175         if (ret)
 176                 return ret;
 177
 178         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 179         err_data.err_addr = &err_rec;
 180         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 181
 182         if (amdgpu_bad_page_threshold != 0) {
 183                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 184                                          err_data.err_addr_cnt);
 185                 amdgpu_ras_save_bad_pages(adev, NULL);
 186         }
 187
 188         amdgpu_ras_error_data_fini(&err_data);
 189
 190         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 191         dev_warn(adev->dev, "Clear EEPROM:\n");
 192         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 193
 194         return 0;
 195 }
 196
 197 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 198                                         size_t size, loff_t *pos)
 199 {
 200         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 201         struct ras_query_if info = {
 202                 .head = obj->head,
 203         };
 204         ssize_t s;
 205         char val[128];
 206
 207         if (amdgpu_ras_query_error_status(obj->adev, &info))
 208                 return -EINVAL;
 209
 210         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 211         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 212             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 213                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 214                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 215         }
 216
 217         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 218                         "ue", info.ue_count,
 219                         "ce", info.ce_count);
 220         if (*pos >= s)
 221                 return 0;
 222
 223         s -= *pos;
 224         s = min_t(u64, s, size);
 225
 226
 227         if (copy_to_user(buf, &val[*pos], s))
 228                 return -EINVAL;
 229
 230         *pos += s;
 231
 232         return s;
 233 }
 234
 235 static const struct file_operations amdgpu_ras_debugfs_ops = {
 236         .owner = THIS_MODULE,
 237         .read = amdgpu_ras_debugfs_read,
 238         .write = NULL,
 239         .llseek = default_llseek
 240 };
 241
 242 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 243 {
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 247                 *block_id = i;
 248                 if (strcmp(name, ras_block_string[i]) == 0)
 249                         return 0;
 250         }
 251         return -EINVAL;
 252 }
 253
 254 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 255                 const char __user *buf, size_t size,
 256                 loff_t *pos, struct ras_debug_if *data)
 257 {
 258         ssize_t s = min_t(u64, 64, size);
 259         char str[65];
 260         char block_name[33];
 261         char err[9] = "ue";
 262         int op = -1;
 263         int block_id;
 264         uint32_t sub_block;
 265         u64 address, value;
 266         /* default value is 0 if the mask is not set by user */
 267         u32 instance_mask = 0;
 268
 269         if (*pos)
 270                 return -EINVAL;
 271         *pos = size;
 272
 273         memset(str, 0, sizeof(str));
 274         memset(data, 0, sizeof(*data));
 275
 276         if (copy_from_user(str, buf, s))
 277                 return -EINVAL;
 278
 279         if (sscanf(str, "disable %32s", block_name) == 1)
 280                 op = 0;
 281         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 282                 op = 1;
 283         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 284                 op = 2;
 285         else if (strstr(str, "retire_page") != NULL)
 286                 op = 3;
 287         else if (str[0] && str[1] && str[2] && str[3])
 288                 /* ascii string, but commands are not matched. */
 289                 return -EINVAL;
 290
 291         if (op != -1) {
 292                 if (op == 3) {
 293                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 294                             sscanf(str, "%*s %llu", &address) != 1)
 295                                 return -EINVAL;
 296
 297                         data->op = op;
 298                         data->inject.address = address;
 299
 300                         return 0;
 301                 }
 302
 303                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 304                         return -EINVAL;
 305
 306                 data->head.block = block_id;
 307                 /* only ue and ce errors are supported */
 308                 if (!memcmp("ue", err, 2))
 309                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 310                 else if (!memcmp("ce", err, 2))
 311                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 312                 else
 313                         return -EINVAL;
 314
 315                 data->op = op;
 316
 317                 if (op == 2) {
 318                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 319                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 320                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 321                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 322                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 323                                    &sub_block, &address, &value) != 3 &&
 324                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 325                                    &sub_block, &address, &value) != 3)
 326                                 return -EINVAL;
 327                         data->head.sub_block_index = sub_block;
 328                         data->inject.address = address;
 329                         data->inject.value = value;
 330                         data->inject.instance_mask = instance_mask;
 331                 }
 332         } else {
 333                 if (size < sizeof(*data))
 334                         return -EINVAL;
 335
 336                 if (copy_from_user(data, buf, sizeof(*data)))
 337                         return -EINVAL;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 344                                 struct ras_debug_if *data)
 345 {
 346         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 347         uint32_t mask, inst_mask = data->inject.instance_mask;
 348
 349         /* no need to set instance mask if there is only one instance */
 350         if (num_xcc <= 1 && inst_mask) {
 351                 data->inject.instance_mask = 0;
 352                 dev_dbg(adev->dev,
 353                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 354                         inst_mask);
 355
 356                 return;
 357         }
 358
 359         switch (data->head.block) {
 360         case AMDGPU_RAS_BLOCK__GFX:
 361                 mask = GENMASK(num_xcc - 1, 0);
 362                 break;
 363         case AMDGPU_RAS_BLOCK__SDMA:
 364                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 365                 break;
 366         case AMDGPU_RAS_BLOCK__VCN:
 367         case AMDGPU_RAS_BLOCK__JPEG:
 368                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 369                 break;
 370         default:
 371                 mask = inst_mask;
 372                 break;
 373         }
 374
 375         /* remove invalid bits in instance mask */
 376         data->inject.instance_mask &= mask;
 377         if (inst_mask != data->inject.instance_mask)
 378                 dev_dbg(adev->dev,
 379                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 380                         inst_mask, data->inject.instance_mask);
 381 }
 382
 383 /**
 384  * DOC: AMDGPU RAS debugfs control interface
 385  *
 386  * The control interface accepts struct ras_debug_if which has two members.
 387  *
 388  * First member: ras_debug_if::head or ras_debug_if::inject.
 389  *
 390  * head is used to indicate which IP block will be under control.
 391  *
 392  * head has four members, they are block, type, sub_block_index, name.
 393  * block: which IP will be under control.
 394  * type: what kind of error will be enabled/disabled/injected.
 395  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 396  * name: the name of IP.
 397  *
 398  * inject has three more members than head, they are address, value and mask.
 399  * As their names indicate, inject operation will write the
 400  * value to the address.
 401  *
 402  * The second member: struct ras_debug_if::op.
 403  * It has three kinds of operations.
 404  *
 405  * - 0: disable RAS on the block. Take ::head as its data.
 406  * - 1: enable RAS on the block. Take ::head as its data.
 407  * - 2: inject errors on the block. Take ::inject as its data.
 408  *
 409  * How to use the interface?
 410  *
 411  * In a program
 412  *
 413  * Copy the struct ras_debug_if in your code and initialize it.
 414  * Write the struct to the control interface.
 415  *
 416  * From shell
 417  *
 418  * .. code-block:: bash
 419  *
 420  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 421  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 422  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 423  *
 424  * Where N, is the card which you want to affect.
 425  *
 426  * "disable" requires only the block.
 427  * "enable" requires the block and error type.
 428  * "inject" requires the block, error type, address, and value.
 429  *
 430  * The block is one of: umc, sdma, gfx, etc.
 431  *      see ras_block_string[] for details
 432  *
 433  * The error type is one of: ue, ce, where,
 434  *      ue is multi-uncorrectable
 435  *      ce is single-correctable
 436  *
 437  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 438  * The address and value are hexadecimal numbers, leading 0x is optional.
 439  * The mask means instance mask, is optional, default value is 0x1.
 440  *
 441  * For instance,
 442  *
 443  * .. code-block:: bash
 444  *
 445  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 446  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 447  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 448  *
 449  * How to check the result of the operation?
 450  *
 451  * To check disable/enable, see "ras" features at,
 452  * /sys/class/drm/card[0/1/2...]/device/ras/features
 453  *
 454  * To check inject, see the corresponding error count at,
 455  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 456  *
 457  * .. note::
 458  *      Operations are only allowed on blocks which are supported.
 459  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 460  *      to see which blocks support RAS on a particular asic.
 461  *
 462  */
 463 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 464                                              const char __user *buf,
 465                                              size_t size, loff_t *pos)
 466 {
 467         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 468         struct ras_debug_if data;
 469         int ret = 0;
 470
 471         if (!amdgpu_ras_get_error_query_ready(adev)) {
 472                 dev_warn(adev->dev, "RAS WARN: error injection "
 473                                 "currently inaccessible\n");
 474                 return size;
 475         }
 476
 477         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 478         if (ret)
 479                 return ret;
 480
 481         if (data.op == 3) {
 482                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 483                 if (!ret)
 484                         return size;
 485                 else
 486                         return ret;
 487         }
 488
 489         if (!amdgpu_ras_is_supported(adev, data.head.block))
 490                 return -EINVAL;
 491
 492         switch (data.op) {
 493         case 0:
 494                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 495                 break;
 496         case 1:
 497                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 498                 break;
 499         case 2:
 500                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 501                     adev->gmc.mc_vram_size) ||
 502                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 503                         dev_warn(adev->dev, "RAS WARN: input address "
 504                                         "0x%llx is invalid.",
 505                                         data.inject.address);
 506                         ret = -EINVAL;
 507                         break;
 508                 }
 509
 510                 /* umc ce/ue error injection for a bad page is not allowed */
 511                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 512                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 513                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 514                                  "already been marked as bad!\n",
 515                                  data.inject.address);
 516                         break;
 517                 }
 518
 519                 amdgpu_ras_instance_mask_check(adev, &data);
 520
 521                 /* data.inject.address is offset instead of absolute gpu address */
 522                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 523                 break;
 524         default:
 525                 ret = -EINVAL;
 526                 break;
 527         }
 528
 529         if (ret)
 530                 return ret;
 531
 532         return size;
 533 }
 534
 535 /**
 536  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 537  *
 538  * Some boards contain an EEPROM which is used to persistently store a list of
 539  * bad pages which experiences ECC errors in vram.  This interface provides
 540  * a way to reset the EEPROM, e.g., after testing error injection.
 541  *
 542  * Usage:
 543  *
 544  * .. code-block:: bash
 545  *
 546  *      echo 1 > ../ras/ras_eeprom_reset
 547  *
 548  * will reset EEPROM table to 0 entries.
 549  *
 550  */
 551 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 552                                                const char __user *buf,
 553                                                size_t size, loff_t *pos)
 554 {
 555         struct amdgpu_device *adev =
 556                 (struct amdgpu_device *)file_inode(f)->i_private;
 557         int ret;
 558
 559         ret = amdgpu_ras_eeprom_reset_table(
 560                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 561
 562         if (!ret) {
 563                 /* Something was written to EEPROM.
 564                  */
 565                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 566                 return size;
 567         } else {
 568                 return ret;
 569         }
 570 }
 571
 572 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 573         .owner = THIS_MODULE,
 574         .read = NULL,
 575         .write = amdgpu_ras_debugfs_ctrl_write,
 576         .llseek = default_llseek
 577 };
 578
 579 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 580         .owner = THIS_MODULE,
 581         .read = NULL,
 582         .write = amdgpu_ras_debugfs_eeprom_write,
 583         .llseek = default_llseek
 584 };
 585
 586 /**
 587  * DOC: AMDGPU RAS sysfs Error Count Interface
 588  *
 589  * It allows the user to read the error count for each IP block on the gpu through
 590  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 591  *
 592  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 593  * (ce) error counts.
 594  *
 595  * The format of one line is below,
 596  *
 597  * [ce|ue]: count
 598  *
 599  * Example:
 600  *
 601  * .. code-block:: bash
 602  *
 603  *      ue: 0
 604  *      ce: 1
 605  *
 606  */
 607 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 608                 struct device_attribute *attr, char *buf)
 609 {
 610         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 611         struct ras_query_if info = {
 612                 .head = obj->head,
 613         };
 614
 615         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 616                 return sysfs_emit(buf, "Query currently inaccessible\n");
 617
 618         if (amdgpu_ras_query_error_status(obj->adev, &info))
 619                 return -EINVAL;
 620
 621         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 622             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 623                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 624                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 625         }
 626
 627         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 628                           "ce", info.ce_count);
 629 }
 630
 631 /* obj begin */
 632
 633 #define get_obj(obj) do { (obj)->use++; } while (0)
 634 #define alive_obj(obj) ((obj)->use)
 635
 636 static inline void put_obj(struct ras_manager *obj)
 637 {
 638         if (obj && (--obj->use == 0)) {
 639                 list_del(&obj->node);
 640                 amdgpu_ras_error_data_fini(&obj->err_data);
 641         }
 642
 643         if (obj && (obj->use < 0))
 644                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 645 }
 646
 647 /* make one obj and return it. */
 648 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 649                 struct ras_common_if *head)
 650 {
 651         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 652         struct ras_manager *obj;
 653
 654         if (!adev->ras_enabled || !con)
 655                 return NULL;
 656
 657         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 658                 return NULL;
 659
 660         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 661                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 662                         return NULL;
 663
 664                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 665         } else
 666                 obj = &con->objs[head->block];
 667
 668         /* already exist. return obj? */
 669         if (alive_obj(obj))
 670                 return NULL;
 671
 672         if (amdgpu_ras_error_data_init(&obj->err_data))
 673                 return NULL;
 674
 675         obj->head = *head;
 676         obj->adev = adev;
 677         list_add(&obj->node, &con->head);
 678         get_obj(obj);
 679
 680         return obj;
 681 }
 682
 683 /* return an obj equal to head, or the first when head is NULL */
 684 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 685                 struct ras_common_if *head)
 686 {
 687         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 688         struct ras_manager *obj;
 689         int i;
 690
 691         if (!adev->ras_enabled || !con)
 692                 return NULL;
 693
 694         if (head) {
 695                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 696                         return NULL;
 697
 698                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 699                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 700                                 return NULL;
 701
 702                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 703                 } else
 704                         obj = &con->objs[head->block];
 705
 706                 if (alive_obj(obj))
 707                         return obj;
 708         } else {
 709                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 710                         obj = &con->objs[i];
 711                         if (alive_obj(obj))
 712                                 return obj;
 713                 }
 714         }
 715
 716         return NULL;
 717 }
 718 /* obj end */
 719
 720 /* feature ctl begin */
 721 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 722                                          struct ras_common_if *head)
 723 {
 724         return adev->ras_hw_enabled & BIT(head->block);
 725 }
 726
 727 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 728                 struct ras_common_if *head)
 729 {
 730         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 731
 732         return con->features & BIT(head->block);
 733 }
 734
 735 /*
 736  * if obj is not created, then create one.
 737  * set feature enable flag.
 738  */
 739 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 740                 struct ras_common_if *head, int enable)
 741 {
 742         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 743         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 744
 745         /* If hardware does not support ras, then do not create obj.
 746          * But if hardware support ras, we can create the obj.
 747          * Ras framework checks con->hw_supported to see if it need do
 748          * corresponding initialization.
 749          * IP checks con->support to see if it need disable ras.
 750          */
 751         if (!amdgpu_ras_is_feature_allowed(adev, head))
 752                 return 0;
 753
 754         if (enable) {
 755                 if (!obj) {
 756                         obj = amdgpu_ras_create_obj(adev, head);
 757                         if (!obj)
 758                                 return -EINVAL;
 759                 } else {
 760                         /* In case we create obj somewhere else */
 761                         get_obj(obj);
 762                 }
 763                 con->features |= BIT(head->block);
 764         } else {
 765                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 766                         con->features &= ~BIT(head->block);
 767                         put_obj(obj);
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 /* wrapper of psp_ras_enable_features */
 775 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 776                 struct ras_common_if *head, bool enable)
 777 {
 778         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 779         union ta_ras_cmd_input *info;
 780         int ret;
 781
 782         if (!con)
 783                 return -EINVAL;
 784
 785         /* For non-gfx ip, do not enable ras feature if it is not allowed */
 786         /* For gfx ip, regardless of feature support status, */
 787         /* Force issue enable or disable ras feature commands */
 788         if (head->block != AMDGPU_RAS_BLOCK__GFX &&
 789             !amdgpu_ras_is_feature_allowed(adev, head))
 790                 return 0;
 791
 792         /* Only enable gfx ras feature from host side */
 793         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 794             !amdgpu_sriov_vf(adev) &&
 795             !amdgpu_ras_intr_triggered()) {
 796                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 797                 if (!info)
 798                         return -ENOMEM;
 799
 800                 if (!enable) {
 801                         info->disable_features = (struct ta_ras_disable_features_input) {
 802                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 803                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 804                         };
 805                 } else {
 806                         info->enable_features = (struct ta_ras_enable_features_input) {
 807                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 808                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 809                         };
 810                 }
 811
 812                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 813                 if (ret) {
 814                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 815                                 enable ? "enable":"disable",
 816                                 get_ras_block_str(head),
 817                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 818                         kfree(info);
 819                         return ret;
 820                 }
 821
 822                 kfree(info);
 823         }
 824
 825         /* setup the obj */
 826         __amdgpu_ras_feature_enable(adev, head, enable);
 827
 828         return 0;
 829 }
 830
 831 /* Only used in device probe stage and called only once. */
 832 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 833                 struct ras_common_if *head, bool enable)
 834 {
 835         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 836         int ret;
 837
 838         if (!con)
 839                 return -EINVAL;
 840
 841         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 842                 if (enable) {
 843                         /* There is no harm to issue a ras TA cmd regardless of
 844                          * the currecnt ras state.
 845                          * If current state == target state, it will do nothing
 846                          * But sometimes it requests driver to reset and repost
 847                          * with error code -EAGAIN.
 848                          */
 849                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 850                         /* With old ras TA, we might fail to enable ras.
 851                          * Log it and just setup the object.
 852                          * TODO need remove this WA in the future.
 853                          */
 854                         if (ret == -EINVAL) {
 855                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 856                                 if (!ret)
 857                                         dev_info(adev->dev,
 858                                                 "RAS INFO: %s setup object\n",
 859                                                 get_ras_block_str(head));
 860                         }
 861                 } else {
 862                         /* setup the object then issue a ras TA disable cmd.*/
 863                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 864                         if (ret)
 865                                 return ret;
 866
 867                         /* gfx block ras dsiable cmd must send to ras-ta */
 868                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 869                                 con->features |= BIT(head->block);
 870
 871                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 872
 873                         /* clean gfx block ras features flag */
 874                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 875                                 con->features &= ~BIT(head->block);
 876                 }
 877         } else
 878                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 879
 880         return ret;
 881 }
 882
 883 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 884                 bool bypass)
 885 {
 886         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 887         struct ras_manager *obj, *tmp;
 888
 889         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 890                 /* bypass psp.
 891                  * aka just release the obj and corresponding flags
 892                  */
 893                 if (bypass) {
 894                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 895                                 break;
 896                 } else {
 897                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 898                                 break;
 899                 }
 900         }
 901
 902         return con->features;
 903 }
 904
 905 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 906                 bool bypass)
 907 {
 908         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 909         int i;
 910         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 911
 912         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 913                 struct ras_common_if head = {
 914                         .block = i,
 915                         .type = default_ras_type,
 916                         .sub_block_index = 0,
 917                 };
 918
 919                 if (i == AMDGPU_RAS_BLOCK__MCA)
 920                         continue;
 921
 922                 if (bypass) {
 923                         /*
 924                          * bypass psp. vbios enable ras for us.
 925                          * so just create the obj
 926                          */
 927                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 928                                 break;
 929                 } else {
 930                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 931                                 break;
 932                 }
 933         }
 934
 935         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 936                 struct ras_common_if head = {
 937                         .block = AMDGPU_RAS_BLOCK__MCA,
 938                         .type = default_ras_type,
 939                         .sub_block_index = i,
 940                 };
 941
 942                 if (bypass) {
 943                         /*
 944                          * bypass psp. vbios enable ras for us.
 945                          * so just create the obj
 946                          */
 947                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 948                                 break;
 949                 } else {
 950                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 951                                 break;
 952                 }
 953         }
 954
 955         return con->features;
 956 }
 957 /* feature ctl end */
 958
 959 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 960                 enum amdgpu_ras_block block)
 961 {
 962         if (!block_obj)
 963                 return -EINVAL;
 964
 965         if (block_obj->ras_comm.block == block)
 966                 return 0;
 967
 968         return -EINVAL;
 969 }
 970
 971 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 972                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 973 {
 974         struct amdgpu_ras_block_list *node, *tmp;
 975         struct amdgpu_ras_block_object *obj;
 976
 977         if (block >= AMDGPU_RAS_BLOCK__LAST)
 978                 return NULL;
 979
 980         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 981                 if (!node->ras_obj) {
 982                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 983                         continue;
 984                 }
 985
 986                 obj = node->ras_obj;
 987                 if (obj->ras_block_match) {
 988                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 989                                 return obj;
 990                 } else {
 991                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 992                                 return obj;
 993                 }
 994         }
 995
 996         return NULL;
 997 }
 998
 999 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
1000 {
1001         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1002         int ret = 0;
1003
1004         /*
1005          * choosing right query method according to
1006          * whether smu support query error information
1007          */
1008         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1009         if (ret == -EOPNOTSUPP) {
1010                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1011                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1012                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1013
1014                 /* umc query_ras_error_address is also responsible for clearing
1015                  * error status
1016                  */
1017                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1018                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1019                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1020         } else if (!ret) {
1021                 if (adev->umc.ras &&
1022                         adev->umc.ras->ecc_info_query_ras_error_count)
1023                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1024
1025                 if (adev->umc.ras &&
1026                         adev->umc.ras->ecc_info_query_ras_error_address)
1027                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1028         }
1029 }
1030
1031 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1032                                               struct ras_manager *ras_mgr,
1033                                               struct ras_err_data *err_data,
1034                                               const char *blk_name,
1035                                               bool is_ue)
1036 {
1037         struct amdgpu_smuio_mcm_config_info *mcm_info;
1038         struct ras_err_node *err_node;
1039         struct ras_err_info *err_info;
1040
1041         if (is_ue) {
1042                 for_each_ras_error(err_node, err_data) {
1043                         err_info = &err_node->err_info;
1044                         mcm_info = &err_info->mcm_info;
1045                         if (err_info->ue_count) {
1046                                 dev_info(adev->dev, "socket: %d, die: %d, "
1047                                          "%lld new uncorrectable hardware errors detected in %s block\n",
1048                                          mcm_info->socket_id,
1049                                          mcm_info->die_id,
1050                                          err_info->ue_count,
1051                                          blk_name);
1052                         }
1053                 }
1054
1055                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1056                         err_info = &err_node->err_info;
1057                         mcm_info = &err_info->mcm_info;
1058                         dev_info(adev->dev, "socket: %d, die: %d, "
1059                                  "%lld uncorrectable hardware errors detected in total in %s block\n",
1060                                  mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name);
1061                 }
1062
1063         } else {
1064                 for_each_ras_error(err_node, err_data) {
1065                         err_info = &err_node->err_info;
1066                         mcm_info = &err_info->mcm_info;
1067                         if (err_info->ce_count) {
1068                                 dev_info(adev->dev, "socket: %d, die: %d, "
1069                                          "%lld new correctable hardware errors detected in %s block, "
1070                                          "no user action is needed\n",
1071                                          mcm_info->socket_id,
1072                                          mcm_info->die_id,
1073                                          err_info->ce_count,
1074                                          blk_name);
1075                         }
1076                 }
1077
1078                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1079                         err_info = &err_node->err_info;
1080                         mcm_info = &err_info->mcm_info;
1081                         dev_info(adev->dev, "socket: %d, die: %d, "
1082                                  "%lld correctable hardware errors detected in total in %s block, "
1083                                  "no user action is needed\n",
1084                                  mcm_info->socket_id, mcm_info->die_id, err_info->ce_count, blk_name);
1085                 }
1086         }
1087 }
1088
1089 static inline bool err_data_has_source_info(struct ras_err_data *data)
1090 {
1091         return !list_empty(&data->err_node_list);
1092 }
1093
1094 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1095                                              struct ras_query_if *query_if,
1096                                              struct ras_err_data *err_data)
1097 {
1098         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1099         const char *blk_name = get_ras_block_str(&query_if->head);
1100
1101         if (err_data->ce_count) {
1102                 if (err_data_has_source_info(err_data)) {
1103                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, false);
1104                 } else if (!adev->aid_mask &&
1105                            adev->smuio.funcs &&
1106                            adev->smuio.funcs->get_socket_id &&
1107                            adev->smuio.funcs->get_die_id) {
1108                         dev_info(adev->dev, "socket: %d, die: %d "
1109                                  "%ld correctable hardware errors "
1110                                  "detected in %s block, no user "
1111                                  "action is needed.\n",
1112                                  adev->smuio.funcs->get_socket_id(adev),
1113                                  adev->smuio.funcs->get_die_id(adev),
1114                                  ras_mgr->err_data.ce_count,
1115                                  blk_name);
1116                 } else {
1117                         dev_info(adev->dev, "%ld correctable hardware errors "
1118                                  "detected in %s block, no user "
1119                                  "action is needed.\n",
1120                                  ras_mgr->err_data.ce_count,
1121                                  blk_name);
1122                 }
1123         }
1124
1125         if (err_data->ue_count) {
1126                 if (err_data_has_source_info(err_data)) {
1127                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, true);
1128                 } else if (!adev->aid_mask &&
1129                            adev->smuio.funcs &&
1130                            adev->smuio.funcs->get_socket_id &&
1131                            adev->smuio.funcs->get_die_id) {
1132                         dev_info(adev->dev, "socket: %d, die: %d "
1133                                  "%ld uncorrectable hardware errors "
1134                                  "detected in %s block\n",
1135                                  adev->smuio.funcs->get_socket_id(adev),
1136                                  adev->smuio.funcs->get_die_id(adev),
1137                                  ras_mgr->err_data.ue_count,
1138                                  blk_name);
1139                 } else {
1140                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1141                                  "detected in %s block\n",
1142                                  ras_mgr->err_data.ue_count,
1143                                  blk_name);
1144                 }
1145         }
1146
1147 }
1148
1149 static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1150 {
1151         struct ras_err_node *err_node;
1152         struct ras_err_info *err_info;
1153
1154         if (err_data_has_source_info(err_data)) {
1155                 for_each_ras_error(err_node, err_data) {
1156                         err_info = &err_node->err_info;
1157
1158                         amdgpu_ras_error_statistic_ce_count(&obj->err_data, &err_info->mcm_info, err_info->ce_count);
1159                         amdgpu_ras_error_statistic_ue_count(&obj->err_data, &err_info->mcm_info, err_info->ue_count);
1160                 }
1161         } else {
1162                 /* for legacy asic path which doesn't has error source info */
1163                 obj->err_data.ue_count += err_data->ue_count;
1164                 obj->err_data.ce_count += err_data->ce_count;
1165         }
1166 }
1167
1168 static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
1169                                                 struct ras_query_if *info,
1170                                                 struct ras_err_data *err_data,
1171                                                 unsigned int error_query_mode)
1172 {
1173         enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT;
1174         struct amdgpu_ras_block_object *block_obj = NULL;
1175
1176         if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
1177                 return -EINVAL;
1178
1179         if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
1180                 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1181                         amdgpu_ras_get_ecc_info(adev, err_data);
1182                 } else {
1183                         block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1184                         if (!block_obj || !block_obj->hw_ops) {
1185                                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1186                                              get_ras_block_str(&info->head));
1187                                 return -EINVAL;
1188                         }
1189
1190                         if (block_obj->hw_ops->query_ras_error_count)
1191                                 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1192
1193                         if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1194                             (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1195                             (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1196                                 if (block_obj->hw_ops->query_ras_error_status)
1197                                         block_obj->hw_ops->query_ras_error_status(adev);
1198                         }
1199                 }
1200         } else {
1201                 /* FIXME: add code to check return value later */
1202                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data);
1203                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data);
1204         }
1205
1206         return 0;
1207 }
1208
1209 /* query/inject/cure begin */
1210 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
1211 {
1212         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1213         struct ras_err_data err_data;
1214         unsigned int error_query_mode;
1215         int ret;
1216
1217         if (!obj)
1218                 return -EINVAL;
1219
1220         ret = amdgpu_ras_error_data_init(&err_data);
1221         if (ret)
1222                 return ret;
1223
1224         if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode))
1225                 return -EINVAL;
1226
1227         ret = amdgpu_ras_query_error_status_helper(adev, info,
1228                                                    &err_data,
1229                                                    error_query_mode);
1230         if (ret)
1231                 goto out_fini_err_data;
1232
1233         amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
1234
1235         info->ue_count = obj->err_data.ue_count;
1236         info->ce_count = obj->err_data.ce_count;
1237
1238         amdgpu_ras_error_generate_report(adev, info, &err_data);
1239
1240 out_fini_err_data:
1241         amdgpu_ras_error_data_fini(&err_data);
1242
1243         return ret;
1244 }
1245
1246 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
1247                 enum amdgpu_ras_block block)
1248 {
1249         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1250         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1251         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
1252         struct amdgpu_hive_info *hive;
1253         int hive_ras_recovery = 0;
1254
1255         if (!block_obj || !block_obj->hw_ops) {
1256                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1257                                 ras_block_str(block));
1258                 return -EOPNOTSUPP;
1259         }
1260
1261         if (!amdgpu_ras_is_supported(adev, block) ||
1262             !amdgpu_ras_get_mca_debug_mode(adev))
1263                 return -EOPNOTSUPP;
1264
1265         hive = amdgpu_get_xgmi_hive(adev);
1266         if (hive) {
1267                 hive_ras_recovery = atomic_read(&hive->ras_recovery);
1268                 amdgpu_put_xgmi_hive(hive);
1269         }
1270
1271         /* skip ras error reset in gpu reset */
1272         if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) ||
1273             hive_ras_recovery) &&
1274             mca_funcs && mca_funcs->mca_set_debug_mode)
1275                 return -EOPNOTSUPP;
1276
1277         if (block_obj->hw_ops->reset_ras_error_count)
1278                 block_obj->hw_ops->reset_ras_error_count(adev);
1279
1280         return 0;
1281 }
1282
1283 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1284                 enum amdgpu_ras_block block)
1285 {
1286         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1287
1288         if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1289                 return 0;
1290
1291         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1292             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1293                 if (block_obj->hw_ops->reset_ras_error_status)
1294                         block_obj->hw_ops->reset_ras_error_status(adev);
1295         }
1296
1297         return 0;
1298 }
1299
1300 /* wrapper of psp_ras_trigger_error */
1301 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1302                 struct ras_inject_if *info)
1303 {
1304         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1305         struct ta_ras_trigger_error_input block_info = {
1306                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1307                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1308                 .sub_block_index = info->head.sub_block_index,
1309                 .address = info->address,
1310                 .value = info->value,
1311         };
1312         int ret = -EINVAL;
1313         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1314                                                         info->head.block,
1315                                                         info->head.sub_block_index);
1316
1317         /* inject on guest isn't allowed, return success directly */
1318         if (amdgpu_sriov_vf(adev))
1319                 return 0;
1320
1321         if (!obj)
1322                 return -EINVAL;
1323
1324         if (!block_obj || !block_obj->hw_ops)   {
1325                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1326                              get_ras_block_str(&info->head));
1327                 return -EINVAL;
1328         }
1329
1330         /* Calculate XGMI relative offset */
1331         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1332             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1333                 block_info.address =
1334                         amdgpu_xgmi_get_relative_phy_addr(adev,
1335                                                           block_info.address);
1336         }
1337
1338         if (block_obj->hw_ops->ras_error_inject) {
1339                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1340                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1341                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1342                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1343                                                 info->instance_mask);
1344         } else {
1345                 /* default path */
1346                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1347         }
1348
1349         if (ret)
1350                 dev_err(adev->dev, "ras inject %s failed %d\n",
1351                         get_ras_block_str(&info->head), ret);
1352
1353         return ret;
1354 }
1355
1356 /**
1357  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1358  * @adev: pointer to AMD GPU device
1359  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1360  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1361  * @query_info: pointer to ras_query_if
1362  *
1363  * Return 0 for query success or do nothing, otherwise return an error
1364  * on failures
1365  */
1366 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1367                                                unsigned long *ce_count,
1368                                                unsigned long *ue_count,
1369                                                struct ras_query_if *query_info)
1370 {
1371         int ret;
1372
1373         if (!query_info)
1374                 /* do nothing if query_info is not specified */
1375                 return 0;
1376
1377         ret = amdgpu_ras_query_error_status(adev, query_info);
1378         if (ret)
1379                 return ret;
1380
1381         *ce_count += query_info->ce_count;
1382         *ue_count += query_info->ue_count;
1383
1384         /* some hardware/IP supports read to clear
1385          * no need to explictly reset the err status after the query call */
1386         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1387             amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1388                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1389                         dev_warn(adev->dev,
1390                                  "Failed to reset error counter and error status\n");
1391         }
1392
1393         return 0;
1394 }
1395
1396 /**
1397  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1398  * @adev: pointer to AMD GPU device
1399  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1400  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1401  * errors.
1402  * @query_info: pointer to ras_query_if if the query request is only for
1403  * specific ip block; if info is NULL, then the qurey request is for
1404  * all the ip blocks that support query ras error counters/status
1405  *
1406  * If set, @ce_count or @ue_count, count and return the corresponding
1407  * error counts in those integer pointers. Return 0 if the device
1408  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1409  */
1410 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1411                                  unsigned long *ce_count,
1412                                  unsigned long *ue_count,
1413                                  struct ras_query_if *query_info)
1414 {
1415         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1416         struct ras_manager *obj;
1417         unsigned long ce, ue;
1418         int ret;
1419
1420         if (!adev->ras_enabled || !con)
1421                 return -EOPNOTSUPP;
1422
1423         /* Don't count since no reporting.
1424          */
1425         if (!ce_count && !ue_count)
1426                 return 0;
1427
1428         ce = 0;
1429         ue = 0;
1430         if (!query_info) {
1431                 /* query all the ip blocks that support ras query interface */
1432                 list_for_each_entry(obj, &con->head, node) {
1433                         struct ras_query_if info = {
1434                                 .head = obj->head,
1435                         };
1436
1437                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1438                 }
1439         } else {
1440                 /* query specific ip block */
1441                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1442         }
1443
1444         if (ret)
1445                 return ret;
1446
1447         if (ce_count)
1448                 *ce_count = ce;
1449
1450         if (ue_count)
1451                 *ue_count = ue;
1452
1453         return 0;
1454 }
1455 /* query/inject/cure end */
1456
1457
1458 /* sysfs begin */
1459
1460 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1461                 struct ras_badpage **bps, unsigned int *count);
1462
1463 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1464 {
1465         switch (flags) {
1466         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1467                 return "R";
1468         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1469                 return "P";
1470         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1471         default:
1472                 return "F";
1473         }
1474 }
1475
1476 /**
1477  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1478  *
1479  * It allows user to read the bad pages of vram on the gpu through
1480  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1481  *
1482  * It outputs multiple lines, and each line stands for one gpu page.
1483  *
1484  * The format of one line is below,
1485  * gpu pfn : gpu page size : flags
1486  *
1487  * gpu pfn and gpu page size are printed in hex format.
1488  * flags can be one of below character,
1489  *
1490  * R: reserved, this gpu page is reserved and not able to use.
1491  *
1492  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1493  * in next window of page_reserve.
1494  *
1495  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1496  *
1497  * Examples:
1498  *
1499  * .. code-block:: bash
1500  *
1501  *      0x00000001 : 0x00001000 : R
1502  *      0x00000002 : 0x00001000 : P
1503  *
1504  */
1505
1506 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1507                 struct kobject *kobj, struct bin_attribute *attr,
1508                 char *buf, loff_t ppos, size_t count)
1509 {
1510         struct amdgpu_ras *con =
1511                 container_of(attr, struct amdgpu_ras, badpages_attr);
1512         struct amdgpu_device *adev = con->adev;
1513         const unsigned int element_size =
1514                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1515         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1516         unsigned int end = div64_ul(ppos + count - 1, element_size);
1517         ssize_t s = 0;
1518         struct ras_badpage *bps = NULL;
1519         unsigned int bps_count = 0;
1520
1521         memset(buf, 0, count);
1522
1523         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1524                 return 0;
1525
1526         for (; start < end && start < bps_count; start++)
1527                 s += scnprintf(&buf[s], element_size + 1,
1528                                 "0x%08x : 0x%08x : %1s\n",
1529                                 bps[start].bp,
1530                                 bps[start].size,
1531                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1532
1533         kfree(bps);
1534
1535         return s;
1536 }
1537
1538 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1539                 struct device_attribute *attr, char *buf)
1540 {
1541         struct amdgpu_ras *con =
1542                 container_of(attr, struct amdgpu_ras, features_attr);
1543
1544         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1545 }
1546
1547 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1548                 struct device_attribute *attr, char *buf)
1549 {
1550         struct amdgpu_ras *con =
1551                 container_of(attr, struct amdgpu_ras, version_attr);
1552         return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1553 }
1554
1555 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1556                 struct device_attribute *attr, char *buf)
1557 {
1558         struct amdgpu_ras *con =
1559                 container_of(attr, struct amdgpu_ras, schema_attr);
1560         return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1561 }
1562
1563 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1564 {
1565         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1566
1567         sysfs_remove_file_from_group(&adev->dev->kobj,
1568                                 &con->badpages_attr.attr,
1569                                 RAS_FS_NAME);
1570 }
1571
1572 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1573 {
1574         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1575         struct attribute *attrs[] = {
1576                 &con->features_attr.attr,
1577                 &con->version_attr.attr,
1578                 &con->schema_attr.attr,
1579                 NULL
1580         };
1581         struct attribute_group group = {
1582                 .name = RAS_FS_NAME,
1583                 .attrs = attrs,
1584         };
1585
1586         sysfs_remove_group(&adev->dev->kobj, &group);
1587
1588         return 0;
1589 }
1590
1591 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1592                 struct ras_common_if *head)
1593 {
1594         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1595
1596         if (!obj || obj->attr_inuse)
1597                 return -EINVAL;
1598
1599         get_obj(obj);
1600
1601         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1602                 "%s_err_count", head->name);
1603
1604         obj->sysfs_attr = (struct device_attribute){
1605                 .attr = {
1606                         .name = obj->fs_data.sysfs_name,
1607                         .mode = S_IRUGO,
1608                 },
1609                         .show = amdgpu_ras_sysfs_read,
1610         };
1611         sysfs_attr_init(&obj->sysfs_attr.attr);
1612
1613         if (sysfs_add_file_to_group(&adev->dev->kobj,
1614                                 &obj->sysfs_attr.attr,
1615                                 RAS_FS_NAME)) {
1616                 put_obj(obj);
1617                 return -EINVAL;
1618         }
1619
1620         obj->attr_inuse = 1;
1621
1622         return 0;
1623 }
1624
1625 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1626                 struct ras_common_if *head)
1627 {
1628         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1629
1630         if (!obj || !obj->attr_inuse)
1631                 return -EINVAL;
1632
1633         sysfs_remove_file_from_group(&adev->dev->kobj,
1634                                 &obj->sysfs_attr.attr,
1635                                 RAS_FS_NAME);
1636         obj->attr_inuse = 0;
1637         put_obj(obj);
1638
1639         return 0;
1640 }
1641
1642 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1643 {
1644         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1645         struct ras_manager *obj, *tmp;
1646
1647         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1648                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1649         }
1650
1651         if (amdgpu_bad_page_threshold != 0)
1652                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1653
1654         amdgpu_ras_sysfs_remove_dev_attr_node(adev);
1655
1656         return 0;
1657 }
1658 /* sysfs end */
1659
1660 /**
1661  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1662  *
1663  * Normally when there is an uncorrectable error, the driver will reset
1664  * the GPU to recover.  However, in the event of an unrecoverable error,
1665  * the driver provides an interface to reboot the system automatically
1666  * in that event.
1667  *
1668  * The following file in debugfs provides that interface:
1669  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1670  *
1671  * Usage:
1672  *
1673  * .. code-block:: bash
1674  *
1675  *      echo true > .../ras/auto_reboot
1676  *
1677  */
1678 /* debugfs begin */
1679 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1680 {
1681         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1682         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1683         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1684         struct dentry     *dir;
1685
1686         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1687         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1688                             &amdgpu_ras_debugfs_ctrl_ops);
1689         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1690                             &amdgpu_ras_debugfs_eeprom_ops);
1691         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1692                            &con->bad_page_cnt_threshold);
1693         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1694         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1695         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1696         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1697                             &amdgpu_ras_debugfs_eeprom_size_ops);
1698         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1699                                                        S_IRUGO, dir, adev,
1700                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1701         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1702
1703         /*
1704          * After one uncorrectable error happens, usually GPU recovery will
1705          * be scheduled. But due to the known problem in GPU recovery failing
1706          * to bring GPU back, below interface provides one direct way to
1707          * user to reboot system automatically in such case within
1708          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1709          * will never be called.
1710          */
1711         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1712
1713         /*
1714          * User could set this not to clean up hardware's error count register
1715          * of RAS IPs during ras recovery.
1716          */
1717         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1718                             &con->disable_ras_err_cnt_harvest);
1719         return dir;
1720 }
1721
1722 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1723                                       struct ras_fs_if *head,
1724                                       struct dentry *dir)
1725 {
1726         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1727
1728         if (!obj || !dir)
1729                 return;
1730
1731         get_obj(obj);
1732
1733         memcpy(obj->fs_data.debugfs_name,
1734                         head->debugfs_name,
1735                         sizeof(obj->fs_data.debugfs_name));
1736
1737         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1738                             obj, &amdgpu_ras_debugfs_ops);
1739 }
1740
1741 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1742 {
1743         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1744         struct dentry *dir;
1745         struct ras_manager *obj;
1746         struct ras_fs_if fs_info;
1747
1748         /*
1749          * it won't be called in resume path, no need to check
1750          * suspend and gpu reset status
1751          */
1752         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1753                 return;
1754
1755         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1756
1757         list_for_each_entry(obj, &con->head, node) {
1758                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1759                         (obj->attr_inuse == 1)) {
1760                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1761                                         get_ras_block_str(&obj->head));
1762                         fs_info.head = obj->head;
1763                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1764                 }
1765         }
1766
1767         amdgpu_mca_smu_debugfs_init(adev, dir);
1768 }
1769
1770 /* debugfs end */
1771
1772 /* ras fs */
1773 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1774                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1775 static DEVICE_ATTR(features, S_IRUGO,
1776                 amdgpu_ras_sysfs_features_read, NULL);
1777 static DEVICE_ATTR(version, 0444,
1778                 amdgpu_ras_sysfs_version_show, NULL);
1779 static DEVICE_ATTR(schema, 0444,
1780                 amdgpu_ras_sysfs_schema_show, NULL);
1781 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1782 {
1783         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1784         struct attribute_group group = {
1785                 .name = RAS_FS_NAME,
1786         };
1787         struct attribute *attrs[] = {
1788                 &con->features_attr.attr,
1789                 &con->version_attr.attr,
1790                 &con->schema_attr.attr,
1791                 NULL
1792         };
1793         struct bin_attribute *bin_attrs[] = {
1794                 NULL,
1795                 NULL,
1796         };
1797         int r;
1798
1799         group.attrs = attrs;
1800
1801         /* add features entry */
1802         con->features_attr = dev_attr_features;
1803         sysfs_attr_init(attrs[0]);
1804
1805         /* add version entry */
1806         con->version_attr = dev_attr_version;
1807         sysfs_attr_init(attrs[1]);
1808
1809         /* add schema entry */
1810         con->schema_attr = dev_attr_schema;
1811         sysfs_attr_init(attrs[2]);
1812
1813         if (amdgpu_bad_page_threshold != 0) {
1814                 /* add bad_page_features entry */
1815                 bin_attr_gpu_vram_bad_pages.private = NULL;
1816                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1817                 bin_attrs[0] = &con->badpages_attr;
1818                 group.bin_attrs = bin_attrs;
1819                 sysfs_bin_attr_init(bin_attrs[0]);
1820         }
1821
1822         r = sysfs_create_group(&adev->dev->kobj, &group);
1823         if (r)
1824                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1825
1826         return 0;
1827 }
1828
1829 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1830 {
1831         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1832         struct ras_manager *con_obj, *ip_obj, *tmp;
1833
1834         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1835                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1836                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1837                         if (ip_obj)
1838                                 put_obj(ip_obj);
1839                 }
1840         }
1841
1842         amdgpu_ras_sysfs_remove_all(adev);
1843         return 0;
1844 }
1845 /* ras fs end */
1846
1847 /* ih begin */
1848
1849 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1850  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1851  * register to check whether the interrupt is triggered or not, and properly
1852  * ack the interrupt if it is there
1853  */
1854 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1855 {
1856         /* Fatal error events are handled on host side */
1857         if (amdgpu_sriov_vf(adev))
1858                 return;
1859
1860         if (adev->nbio.ras &&
1861             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1862                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1863
1864         if (adev->nbio.ras &&
1865             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1866                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1867 }
1868
1869 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1870                                 struct amdgpu_iv_entry *entry)
1871 {
1872         bool poison_stat = false;
1873         struct amdgpu_device *adev = obj->adev;
1874         struct amdgpu_ras_block_object *block_obj =
1875                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1876
1877         if (!block_obj)
1878                 return;
1879
1880         /* both query_poison_status and handle_poison_consumption are optional,
1881          * but at least one of them should be implemented if we need poison
1882          * consumption handler
1883          */
1884         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1885                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1886                 if (!poison_stat) {
1887                         /* Not poison consumption interrupt, no need to handle it */
1888                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1889                                         block_obj->ras_comm.name);
1890
1891                         return;
1892                 }
1893         }
1894
1895         amdgpu_umc_poison_handler(adev, false);
1896
1897         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1898                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1899
1900         /* gpu reset is fallback for failed and default cases */
1901         if (poison_stat) {
1902                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1903                                 block_obj->ras_comm.name);
1904                 amdgpu_ras_reset_gpu(adev);
1905         } else {
1906                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1907         }
1908 }
1909
1910 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1911                                 struct amdgpu_iv_entry *entry)
1912 {
1913         dev_info(obj->adev->dev,
1914                 "Poison is created, no user action is needed.\n");
1915 }
1916
1917 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1918                                 struct amdgpu_iv_entry *entry)
1919 {
1920         struct ras_ih_data *data = &obj->ih_data;
1921         struct ras_err_data err_data;
1922         int ret;
1923
1924         if (!data->cb)
1925                 return;
1926
1927         ret = amdgpu_ras_error_data_init(&err_data);
1928         if (ret)
1929                 return;
1930
1931         /* Let IP handle its data, maybe we need get the output
1932          * from the callback to update the error type/count, etc
1933          */
1934         ret = data->cb(obj->adev, &err_data, entry);
1935         /* ue will trigger an interrupt, and in that case
1936          * we need do a reset to recovery the whole system.
1937          * But leave IP do that recovery, here we just dispatch
1938          * the error.
1939          */
1940         if (ret == AMDGPU_RAS_SUCCESS) {
1941                 /* these counts could be left as 0 if
1942                  * some blocks do not count error number
1943                  */
1944                 obj->err_data.ue_count += err_data.ue_count;
1945                 obj->err_data.ce_count += err_data.ce_count;
1946         }
1947
1948         amdgpu_ras_error_data_fini(&err_data);
1949 }
1950
1951 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1952 {
1953         struct ras_ih_data *data = &obj->ih_data;
1954         struct amdgpu_iv_entry entry;
1955
1956         while (data->rptr != data->wptr) {
1957                 rmb();
1958                 memcpy(&entry, &data->ring[data->rptr],
1959                                 data->element_size);
1960
1961                 wmb();
1962                 data->rptr = (data->aligned_element_size +
1963                                 data->rptr) % data->ring_size;
1964
1965                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1966                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1967                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1968                         else
1969                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1970                 } else {
1971                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1972                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1973                         else
1974                                 dev_warn(obj->adev->dev,
1975                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1976                 }
1977         }
1978 }
1979
1980 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1981 {
1982         struct ras_ih_data *data =
1983                 container_of(work, struct ras_ih_data, ih_work);
1984         struct ras_manager *obj =
1985                 container_of(data, struct ras_manager, ih_data);
1986
1987         amdgpu_ras_interrupt_handler(obj);
1988 }
1989
1990 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1991                 struct ras_dispatch_if *info)
1992 {
1993         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1994         struct ras_ih_data *data = &obj->ih_data;
1995
1996         if (!obj)
1997                 return -EINVAL;
1998
1999         if (data->inuse == 0)
2000                 return 0;
2001
2002         /* Might be overflow... */
2003         memcpy(&data->ring[data->wptr], info->entry,
2004                         data->element_size);
2005
2006         wmb();
2007         data->wptr = (data->aligned_element_size +
2008                         data->wptr) % data->ring_size;
2009
2010         schedule_work(&data->ih_work);
2011
2012         return 0;
2013 }
2014
2015 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
2016                 struct ras_common_if *head)
2017 {
2018         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2019         struct ras_ih_data *data;
2020
2021         if (!obj)
2022                 return -EINVAL;
2023
2024         data = &obj->ih_data;
2025         if (data->inuse == 0)
2026                 return 0;
2027
2028         cancel_work_sync(&data->ih_work);
2029
2030         kfree(data->ring);
2031         memset(data, 0, sizeof(*data));
2032         put_obj(obj);
2033
2034         return 0;
2035 }
2036
2037 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
2038                 struct ras_common_if *head)
2039 {
2040         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2041         struct ras_ih_data *data;
2042         struct amdgpu_ras_block_object *ras_obj;
2043
2044         if (!obj) {
2045                 /* in case we registe the IH before enable ras feature */
2046                 obj = amdgpu_ras_create_obj(adev, head);
2047                 if (!obj)
2048                         return -EINVAL;
2049         } else
2050                 get_obj(obj);
2051
2052         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
2053
2054         data = &obj->ih_data;
2055         /* add the callback.etc */
2056         *data = (struct ras_ih_data) {
2057                 .inuse = 0,
2058                 .cb = ras_obj->ras_cb,
2059                 .element_size = sizeof(struct amdgpu_iv_entry),
2060                 .rptr = 0,
2061                 .wptr = 0,
2062         };
2063
2064         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
2065
2066         data->aligned_element_size = ALIGN(data->element_size, 8);
2067         /* the ring can store 64 iv entries. */
2068         data->ring_size = 64 * data->aligned_element_size;
2069         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
2070         if (!data->ring) {
2071                 put_obj(obj);
2072                 return -ENOMEM;
2073         }
2074
2075         /* IH is ready */
2076         data->inuse = 1;
2077
2078         return 0;
2079 }
2080
2081 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
2082 {
2083         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2084         struct ras_manager *obj, *tmp;
2085
2086         list_for_each_entry_safe(obj, tmp, &con->head, node) {
2087                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
2088         }
2089
2090         return 0;
2091 }
2092 /* ih end */
2093
2094 /* traversal all IPs except NBIO to query error counter */
2095 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
2096 {
2097         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2098         struct ras_manager *obj;
2099
2100         if (!adev->ras_enabled || !con)
2101                 return;
2102
2103         list_for_each_entry(obj, &con->head, node) {
2104                 struct ras_query_if info = {
2105                         .head = obj->head,
2106                 };
2107
2108                 /*
2109                  * PCIE_BIF IP has one different isr by ras controller
2110                  * interrupt, the specific ras counter query will be
2111                  * done in that isr. So skip such block from common
2112                  * sync flood interrupt isr calling.
2113                  */
2114                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2115                         continue;
2116
2117                 /*
2118                  * this is a workaround for aldebaran, skip send msg to
2119                  * smu to get ecc_info table due to smu handle get ecc
2120                  * info table failed temporarily.
2121                  * should be removed until smu fix handle ecc_info table.
2122                  */
2123                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2124                     (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2125                      IP_VERSION(13, 0, 2)))
2126                         continue;
2127
2128                 amdgpu_ras_query_error_status(adev, &info);
2129
2130                 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2131                             IP_VERSION(11, 0, 2) &&
2132                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2133                             IP_VERSION(11, 0, 4) &&
2134                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2135                             IP_VERSION(13, 0, 0)) {
2136                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
2137                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
2138                 }
2139         }
2140 }
2141
2142 /* Parse RdRspStatus and WrRspStatus */
2143 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2144                                           struct ras_query_if *info)
2145 {
2146         struct amdgpu_ras_block_object *block_obj;
2147         /*
2148          * Only two block need to query read/write
2149          * RspStatus at current state
2150          */
2151         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2152                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2153                 return;
2154
2155         block_obj = amdgpu_ras_get_ras_block(adev,
2156                                         info->head.block,
2157                                         info->head.sub_block_index);
2158
2159         if (!block_obj || !block_obj->hw_ops) {
2160                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2161                              get_ras_block_str(&info->head));
2162                 return;
2163         }
2164
2165         if (block_obj->hw_ops->query_ras_error_status)
2166                 block_obj->hw_ops->query_ras_error_status(adev);
2167
2168 }
2169
2170 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2171 {
2172         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2173         struct ras_manager *obj;
2174
2175         if (!adev->ras_enabled || !con)
2176                 return;
2177
2178         list_for_each_entry(obj, &con->head, node) {
2179                 struct ras_query_if info = {
2180                         .head = obj->head,
2181                 };
2182
2183                 amdgpu_ras_error_status_query(adev, &info);
2184         }
2185 }
2186
2187 /* recovery begin */
2188
2189 /* return 0 on success.
2190  * caller need free bps.
2191  */
2192 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2193                 struct ras_badpage **bps, unsigned int *count)
2194 {
2195         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2196         struct ras_err_handler_data *data;
2197         int i = 0;
2198         int ret = 0, status;
2199
2200         if (!con || !con->eh_data || !bps || !count)
2201                 return -EINVAL;
2202
2203         mutex_lock(&con->recovery_lock);
2204         data = con->eh_data;
2205         if (!data || data->count == 0) {
2206                 *bps = NULL;
2207                 ret = -EINVAL;
2208                 goto out;
2209         }
2210
2211         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2212         if (!*bps) {
2213                 ret = -ENOMEM;
2214                 goto out;
2215         }
2216
2217         for (; i < data->count; i++) {
2218                 (*bps)[i] = (struct ras_badpage){
2219                         .bp = data->bps[i].retired_page,
2220                         .size = AMDGPU_GPU_PAGE_SIZE,
2221                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2222                 };
2223                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2224                                 data->bps[i].retired_page);
2225                 if (status == -EBUSY)
2226                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2227                 else if (status == -ENOENT)
2228                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2229         }
2230
2231         *count = data->count;
2232 out:
2233         mutex_unlock(&con->recovery_lock);
2234         return ret;
2235 }
2236
2237 static void amdgpu_ras_do_recovery(struct work_struct *work)
2238 {
2239         struct amdgpu_ras *ras =
2240                 container_of(work, struct amdgpu_ras, recovery_work);
2241         struct amdgpu_device *remote_adev = NULL;
2242         struct amdgpu_device *adev = ras->adev;
2243         struct list_head device_list, *device_list_handle =  NULL;
2244         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2245
2246         if (hive)
2247                 atomic_set(&hive->ras_recovery, 1);
2248         if (!ras->disable_ras_err_cnt_harvest) {
2249
2250                 /* Build list of devices to query RAS related errors */
2251                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2252                         device_list_handle = &hive->device_list;
2253                 } else {
2254                         INIT_LIST_HEAD(&device_list);
2255                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2256                         device_list_handle = &device_list;
2257                 }
2258
2259                 list_for_each_entry(remote_adev,
2260                                 device_list_handle, gmc.xgmi.head) {
2261                         amdgpu_ras_query_err_status(remote_adev);
2262                         amdgpu_ras_log_on_err_counter(remote_adev);
2263                 }
2264
2265         }
2266
2267         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2268                 struct amdgpu_reset_context reset_context;
2269                 memset(&reset_context, 0, sizeof(reset_context));
2270
2271                 reset_context.method = AMD_RESET_METHOD_NONE;
2272                 reset_context.reset_req_dev = adev;
2273
2274                 /* Perform full reset in fatal error mode */
2275                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2276                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2277                 else {
2278                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2279
2280                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2281                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2282                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2283                         }
2284
2285                         /* Fatal error occurs in poison mode, mode1 reset is used to
2286                          * recover gpu.
2287                          */
2288                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2289                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2290                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2291
2292                                 psp_fatal_error_recovery_quirk(&adev->psp);
2293                         }
2294                 }
2295
2296                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2297         }
2298         atomic_set(&ras->in_recovery, 0);
2299         if (hive) {
2300                 atomic_set(&hive->ras_recovery, 0);
2301                 amdgpu_put_xgmi_hive(hive);
2302         }
2303 }
2304
2305 /* alloc/realloc bps array */
2306 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2307                 struct ras_err_handler_data *data, int pages)
2308 {
2309         unsigned int old_space = data->count + data->space_left;
2310         unsigned int new_space = old_space + pages;
2311         unsigned int align_space = ALIGN(new_space, 512);
2312         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2313
2314         if (!bps) {
2315                 return -ENOMEM;
2316         }
2317
2318         if (data->bps) {
2319                 memcpy(bps, data->bps,
2320                                 data->count * sizeof(*data->bps));
2321                 kfree(data->bps);
2322         }
2323
2324         data->bps = bps;
2325         data->space_left += align_space - old_space;
2326         return 0;
2327 }
2328
2329 /* it deal with vram only. */
2330 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2331                 struct eeprom_table_record *bps, int pages)
2332 {
2333         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2334         struct ras_err_handler_data *data;
2335         int ret = 0;
2336         uint32_t i;
2337
2338         if (!con || !con->eh_data || !bps || pages <= 0)
2339                 return 0;
2340
2341         mutex_lock(&con->recovery_lock);
2342         data = con->eh_data;
2343         if (!data)
2344                 goto out;
2345
2346         for (i = 0; i < pages; i++) {
2347                 if (amdgpu_ras_check_bad_page_unlock(con,
2348                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2349                         continue;
2350
2351                 if (!data->space_left &&
2352                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2353                         ret = -ENOMEM;
2354                         goto out;
2355                 }
2356
2357                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2358                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2359                         AMDGPU_GPU_PAGE_SIZE);
2360
2361                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2362                 data->count++;
2363                 data->space_left--;
2364         }
2365 out:
2366         mutex_unlock(&con->recovery_lock);
2367
2368         return ret;
2369 }
2370
2371 /*
2372  * write error record array to eeprom, the function should be
2373  * protected by recovery_lock
2374  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2375  */
2376 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2377                 unsigned long *new_cnt)
2378 {
2379         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2380         struct ras_err_handler_data *data;
2381         struct amdgpu_ras_eeprom_control *control;
2382         int save_count;
2383
2384         if (!con || !con->eh_data) {
2385                 if (new_cnt)
2386                         *new_cnt = 0;
2387
2388                 return 0;
2389         }
2390
2391         mutex_lock(&con->recovery_lock);
2392         control = &con->eeprom_control;
2393         data = con->eh_data;
2394         save_count = data->count - control->ras_num_recs;
2395         mutex_unlock(&con->recovery_lock);
2396
2397         if (new_cnt)
2398                 *new_cnt = save_count / adev->umc.retire_unit;
2399
2400         /* only new entries are saved */
2401         if (save_count > 0) {
2402                 if (amdgpu_ras_eeprom_append(control,
2403                                              &data->bps[control->ras_num_recs],
2404                                              save_count)) {
2405                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2406                         return -EIO;
2407                 }
2408
2409                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2410         }
2411
2412         return 0;
2413 }
2414
2415 /*
2416  * read error record array in eeprom and reserve enough space for
2417  * storing new bad pages
2418  */
2419 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2420 {
2421         struct amdgpu_ras_eeprom_control *control =
2422                 &adev->psp.ras_context.ras->eeprom_control;
2423         struct eeprom_table_record *bps;
2424         int ret;
2425
2426         /* no bad page record, skip eeprom access */
2427         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2428                 return 0;
2429
2430         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2431         if (!bps)
2432                 return -ENOMEM;
2433
2434         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2435         if (ret)
2436                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2437         else
2438                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2439
2440         kfree(bps);
2441         return ret;
2442 }
2443
2444 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2445                                 uint64_t addr)
2446 {
2447         struct ras_err_handler_data *data = con->eh_data;
2448         int i;
2449
2450         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2451         for (i = 0; i < data->count; i++)
2452                 if (addr == data->bps[i].retired_page)
2453                         return true;
2454
2455         return false;
2456 }
2457
2458 /*
2459  * check if an address belongs to bad page
2460  *
2461  * Note: this check is only for umc block
2462  */
2463 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2464                                 uint64_t addr)
2465 {
2466         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2467         bool ret = false;
2468
2469         if (!con || !con->eh_data)
2470                 return ret;
2471
2472         mutex_lock(&con->recovery_lock);
2473         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2474         mutex_unlock(&con->recovery_lock);
2475         return ret;
2476 }
2477
2478 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2479                                           uint32_t max_count)
2480 {
2481         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2482
2483         /*
2484          * Justification of value bad_page_cnt_threshold in ras structure
2485          *
2486          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2487          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2488          * scenarios accordingly.
2489          *
2490          * Bad page retirement enablement:
2491          *    - If amdgpu_bad_page_threshold = -2,
2492          *      bad_page_cnt_threshold = typical value by formula.
2493          *
2494          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2495          *      max record length in eeprom, use it directly.
2496          *
2497          * Bad page retirement disablement:
2498          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2499          *      functionality is disabled, and bad_page_cnt_threshold will
2500          *      take no effect.
2501          */
2502
2503         if (amdgpu_bad_page_threshold < 0) {
2504                 u64 val = adev->gmc.mc_vram_size;
2505
2506                 do_div(val, RAS_BAD_PAGE_COVER);
2507                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2508                                                   max_count);
2509         } else {
2510                 con->bad_page_cnt_threshold = min_t(int, max_count,
2511                                                     amdgpu_bad_page_threshold);
2512         }
2513 }
2514
2515 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2516 {
2517         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2518         struct ras_err_handler_data **data;
2519         u32  max_eeprom_records_count = 0;
2520         bool exc_err_limit = false;
2521         int ret;
2522
2523         if (!con || amdgpu_sriov_vf(adev))
2524                 return 0;
2525
2526         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2527          * supports RAS and debugfs is enabled, but when
2528          * adev->ras_enabled is unset, i.e. when "ras_enable"
2529          * module parameter is set to 0.
2530          */
2531         con->adev = adev;
2532
2533         if (!adev->ras_enabled)
2534                 return 0;
2535
2536         data = &con->eh_data;
2537         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2538         if (!*data) {
2539                 ret = -ENOMEM;
2540                 goto out;
2541         }
2542
2543         mutex_init(&con->recovery_lock);
2544         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2545         atomic_set(&con->in_recovery, 0);
2546         con->eeprom_control.bad_channel_bitmap = 0;
2547
2548         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2549         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2550
2551         /* Todo: During test the SMU might fail to read the eeprom through I2C
2552          * when the GPU is pending on XGMI reset during probe time
2553          * (Mostly after second bus reset), skip it now
2554          */
2555         if (adev->gmc.xgmi.pending_reset)
2556                 return 0;
2557         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2558         /*
2559          * This calling fails when exc_err_limit is true or
2560          * ret != 0.
2561          */
2562         if (exc_err_limit || ret)
2563                 goto free;
2564
2565         if (con->eeprom_control.ras_num_recs) {
2566                 ret = amdgpu_ras_load_bad_pages(adev);
2567                 if (ret)
2568                         goto free;
2569
2570                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2571
2572                 if (con->update_channel_flag == true) {
2573                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2574                         con->update_channel_flag = false;
2575                 }
2576         }
2577
2578 #ifdef CONFIG_X86_MCE_AMD
2579         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2580             (adev->gmc.xgmi.connected_to_cpu))
2581                 amdgpu_register_bad_pages_mca_notifier(adev);
2582 #endif
2583         return 0;
2584
2585 free:
2586         kfree((*data)->bps);
2587         kfree(*data);
2588         con->eh_data = NULL;
2589 out:
2590         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2591
2592         /*
2593          * Except error threshold exceeding case, other failure cases in this
2594          * function would not fail amdgpu driver init.
2595          */
2596         if (!exc_err_limit)
2597                 ret = 0;
2598         else
2599                 ret = -EINVAL;
2600
2601         return ret;
2602 }
2603
2604 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2605 {
2606         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2607         struct ras_err_handler_data *data = con->eh_data;
2608
2609         /* recovery_init failed to init it, fini is useless */
2610         if (!data)
2611                 return 0;
2612
2613         cancel_work_sync(&con->recovery_work);
2614
2615         mutex_lock(&con->recovery_lock);
2616         con->eh_data = NULL;
2617         kfree(data->bps);
2618         kfree(data);
2619         mutex_unlock(&con->recovery_lock);
2620
2621         return 0;
2622 }
2623 /* recovery end */
2624
2625 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2626 {
2627         if (amdgpu_sriov_vf(adev)) {
2628                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2629                 case IP_VERSION(13, 0, 2):
2630                 case IP_VERSION(13, 0, 6):
2631                         return true;
2632                 default:
2633                         return false;
2634                 }
2635         }
2636
2637         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2638                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2639                 case IP_VERSION(13, 0, 0):
2640                 case IP_VERSION(13, 0, 6):
2641                 case IP_VERSION(13, 0, 10):
2642                         return true;
2643                 default:
2644                         return false;
2645                 }
2646         }
2647
2648         return adev->asic_type == CHIP_VEGA10 ||
2649                 adev->asic_type == CHIP_VEGA20 ||
2650                 adev->asic_type == CHIP_ARCTURUS ||
2651                 adev->asic_type == CHIP_ALDEBARAN ||
2652                 adev->asic_type == CHIP_SIENNA_CICHLID;
2653 }
2654
2655 /*
2656  * this is workaround for vega20 workstation sku,
2657  * force enable gfx ras, ignore vbios gfx ras flag
2658  * due to GC EDC can not write
2659  */
2660 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2661 {
2662         struct atom_context *ctx = adev->mode_info.atom_context;
2663
2664         if (!ctx)
2665                 return;
2666
2667         if (strnstr(ctx->vbios_pn, "D16406",
2668                     sizeof(ctx->vbios_pn)) ||
2669                 strnstr(ctx->vbios_pn, "D36002",
2670                         sizeof(ctx->vbios_pn)))
2671                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2672 }
2673
2674 /*
2675  * check hardware's ras ability which will be saved in hw_supported.
2676  * if hardware does not support ras, we can skip some ras initializtion and
2677  * forbid some ras operations from IP.
2678  * if software itself, say boot parameter, limit the ras ability. We still
2679  * need allow IP do some limited operations, like disable. In such case,
2680  * we have to initialize ras as normal. but need check if operation is
2681  * allowed or not in each function.
2682  */
2683 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2684 {
2685         adev->ras_hw_enabled = adev->ras_enabled = 0;
2686
2687         if (!amdgpu_ras_asic_supported(adev))
2688                 return;
2689
2690         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2691                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2692                         dev_info(adev->dev, "MEM ECC is active.\n");
2693                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2694                                                    1 << AMDGPU_RAS_BLOCK__DF);
2695                 } else {
2696                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2697                 }
2698
2699                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2700                         dev_info(adev->dev, "SRAM ECC is active.\n");
2701                         if (!amdgpu_sriov_vf(adev))
2702                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2703                                                             1 << AMDGPU_RAS_BLOCK__DF);
2704                         else
2705                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2706                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2707                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2708
2709                         /* VCN/JPEG RAS can be supported on both bare metal and
2710                          * SRIOV environment
2711                          */
2712                         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2713                                     IP_VERSION(2, 6, 0) ||
2714                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2715                                     IP_VERSION(4, 0, 0) ||
2716                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2717                                     IP_VERSION(4, 0, 3))
2718                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2719                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2720                         else
2721                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2722                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2723
2724                         /*
2725                          * XGMI RAS is not supported if xgmi num physical nodes
2726                          * is zero
2727                          */
2728                         if (!adev->gmc.xgmi.num_physical_nodes)
2729                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2730                 } else {
2731                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2732                 }
2733         } else {
2734                 /* driver only manages a few IP blocks RAS feature
2735                  * when GPU is connected cpu through XGMI */
2736                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2737                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2738                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2739         }
2740
2741         amdgpu_ras_get_quirks(adev);
2742
2743         /* hw_supported needs to be aligned with RAS block mask. */
2744         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2745
2746         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2747                 adev->ras_hw_enabled & amdgpu_ras_mask;
2748 }
2749
2750 static void amdgpu_ras_counte_dw(struct work_struct *work)
2751 {
2752         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2753                                               ras_counte_delay_work.work);
2754         struct amdgpu_device *adev = con->adev;
2755         struct drm_device *dev = adev_to_drm(adev);
2756         unsigned long ce_count, ue_count;
2757         int res;
2758
2759         res = pm_runtime_get_sync(dev->dev);
2760         if (res < 0)
2761                 goto Out;
2762
2763         /* Cache new values.
2764          */
2765         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2766                 atomic_set(&con->ras_ce_count, ce_count);
2767                 atomic_set(&con->ras_ue_count, ue_count);
2768         }
2769
2770         pm_runtime_mark_last_busy(dev->dev);
2771 Out:
2772         pm_runtime_put_autosuspend(dev->dev);
2773 }
2774
2775 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2776 {
2777         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2778         bool df_poison, umc_poison;
2779
2780         /* poison setting is useless on SRIOV guest */
2781         if (amdgpu_sriov_vf(adev) || !con)
2782                 return;
2783
2784         /* Init poison supported flag, the default value is false */
2785         if (adev->gmc.xgmi.connected_to_cpu ||
2786             adev->gmc.is_app_apu) {
2787                 /* enabled by default when GPU is connected to CPU */
2788                 con->poison_supported = true;
2789         } else if (adev->df.funcs &&
2790             adev->df.funcs->query_ras_poison_mode &&
2791             adev->umc.ras &&
2792             adev->umc.ras->query_ras_poison_mode) {
2793                 df_poison =
2794                         adev->df.funcs->query_ras_poison_mode(adev);
2795                 umc_poison =
2796                         adev->umc.ras->query_ras_poison_mode(adev);
2797
2798                 /* Only poison is set in both DF and UMC, we can support it */
2799                 if (df_poison && umc_poison)
2800                         con->poison_supported = true;
2801                 else if (df_poison != umc_poison)
2802                         dev_warn(adev->dev,
2803                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2804                                 df_poison, umc_poison);
2805         }
2806 }
2807
2808 static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
2809 {
2810         return  amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
2811                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
2812                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
2813                         AMDGPU_RAS_ERROR__PARITY;
2814 }
2815
2816 int amdgpu_ras_init(struct amdgpu_device *adev)
2817 {
2818         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2819         int r;
2820
2821         if (con)
2822                 return 0;
2823
2824         con = kmalloc(sizeof(struct amdgpu_ras) +
2825                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2826                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2827                         GFP_KERNEL|__GFP_ZERO);
2828         if (!con)
2829                 return -ENOMEM;
2830
2831         con->adev = adev;
2832         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2833         atomic_set(&con->ras_ce_count, 0);
2834         atomic_set(&con->ras_ue_count, 0);
2835
2836         con->objs = (struct ras_manager *)(con + 1);
2837
2838         amdgpu_ras_set_context(adev, con);
2839
2840         amdgpu_ras_check_supported(adev);
2841
2842         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2843                 /* set gfx block ras context feature for VEGA20 Gaming
2844                  * send ras disable cmd to ras ta during ras late init.
2845                  */
2846                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2847                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2848
2849                         return 0;
2850                 }
2851
2852                 r = 0;
2853                 goto release_con;
2854         }
2855
2856         con->update_channel_flag = false;
2857         con->features = 0;
2858         con->schema = 0;
2859         INIT_LIST_HEAD(&con->head);
2860         /* Might need get this flag from vbios. */
2861         con->flags = RAS_DEFAULT_FLAGS;
2862
2863         /* initialize nbio ras function ahead of any other
2864          * ras functions so hardware fatal error interrupt
2865          * can be enabled as early as possible */
2866         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2867         case IP_VERSION(7, 4, 0):
2868         case IP_VERSION(7, 4, 1):
2869         case IP_VERSION(7, 4, 4):
2870                 if (!adev->gmc.xgmi.connected_to_cpu)
2871                         adev->nbio.ras = &nbio_v7_4_ras;
2872                 break;
2873         case IP_VERSION(4, 3, 0):
2874                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2875                         /* unlike other generation of nbio ras,
2876                          * nbio v4_3 only support fatal error interrupt
2877                          * to inform software that DF is freezed due to
2878                          * system fatal error event. driver should not
2879                          * enable nbio ras in such case. Instead,
2880                          * check DF RAS */
2881                         adev->nbio.ras = &nbio_v4_3_ras;
2882                 break;
2883         case IP_VERSION(7, 9, 0):
2884                 if (!adev->gmc.is_app_apu)
2885                         adev->nbio.ras = &nbio_v7_9_ras;
2886                 break;
2887         default:
2888                 /* nbio ras is not available */
2889                 break;
2890         }
2891
2892         /* nbio ras block needs to be enabled ahead of other ras blocks
2893          * to handle fatal error */
2894         r = amdgpu_nbio_ras_sw_init(adev);
2895         if (r)
2896                 return r;
2897
2898         if (adev->nbio.ras &&
2899             adev->nbio.ras->init_ras_controller_interrupt) {
2900                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2901                 if (r)
2902                         goto release_con;
2903         }
2904
2905         if (adev->nbio.ras &&
2906             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2907                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2908                 if (r)
2909                         goto release_con;
2910         }
2911
2912         amdgpu_ras_query_poison_mode(adev);
2913
2914         /* Get RAS schema for particular SOC */
2915         con->schema = amdgpu_get_ras_schema(adev);
2916
2917         if (amdgpu_ras_fs_init(adev)) {
2918                 r = -EINVAL;
2919                 goto release_con;
2920         }
2921
2922         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2923                  "hardware ability[%x] ras_mask[%x]\n",
2924                  adev->ras_hw_enabled, adev->ras_enabled);
2925
2926         return 0;
2927 release_con:
2928         amdgpu_ras_set_context(adev, NULL);
2929         kfree(con);
2930
2931         return r;
2932 }
2933
2934 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2935 {
2936         if (adev->gmc.xgmi.connected_to_cpu ||
2937             adev->gmc.is_app_apu)
2938                 return 1;
2939         return 0;
2940 }
2941
2942 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2943                                         struct ras_common_if *ras_block)
2944 {
2945         struct ras_query_if info = {
2946                 .head = *ras_block,
2947         };
2948
2949         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2950                 return 0;
2951
2952         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2953                 DRM_WARN("RAS init harvest failure");
2954
2955         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2956                 DRM_WARN("RAS init harvest reset failure");
2957
2958         return 0;
2959 }
2960
2961 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2962 {
2963        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2964
2965        if (!con)
2966                return false;
2967
2968        return con->poison_supported;
2969 }
2970
2971 /* helper function to handle common stuff in ip late init phase */
2972 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2973                          struct ras_common_if *ras_block)
2974 {
2975         struct amdgpu_ras_block_object *ras_obj = NULL;
2976         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2977         struct ras_query_if *query_info;
2978         unsigned long ue_count, ce_count;
2979         int r;
2980
2981         /* disable RAS feature per IP block if it is not supported */
2982         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2983                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2984                 return 0;
2985         }
2986
2987         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2988         if (r) {
2989                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2990                         /* in resume phase, if fail to enable ras,
2991                          * clean up all ras fs nodes, and disable ras */
2992                         goto cleanup;
2993                 } else
2994                         return r;
2995         }
2996
2997         /* check for errors on warm reset edc persisant supported ASIC */
2998         amdgpu_persistent_edc_harvesting(adev, ras_block);
2999
3000         /* in resume phase, no need to create ras fs node */
3001         if (adev->in_suspend || amdgpu_in_reset(adev))
3002                 return 0;
3003
3004         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3005         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
3006             (ras_obj->hw_ops->query_poison_status ||
3007             ras_obj->hw_ops->handle_poison_consumption))) {
3008                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
3009                 if (r)
3010                         goto cleanup;
3011         }
3012
3013         if (ras_obj->hw_ops &&
3014             (ras_obj->hw_ops->query_ras_error_count ||
3015              ras_obj->hw_ops->query_ras_error_status)) {
3016                 r = amdgpu_ras_sysfs_create(adev, ras_block);
3017                 if (r)
3018                         goto interrupt;
3019
3020                 /* Those are the cached values at init.
3021                  */
3022                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
3023                 if (!query_info)
3024                         return -ENOMEM;
3025                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
3026
3027                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
3028                         atomic_set(&con->ras_ce_count, ce_count);
3029                         atomic_set(&con->ras_ue_count, ue_count);
3030                 }
3031
3032                 kfree(query_info);
3033         }
3034
3035         return 0;
3036
3037 interrupt:
3038         if (ras_obj->ras_cb)
3039                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3040 cleanup:
3041         amdgpu_ras_feature_enable(adev, ras_block, 0);
3042         return r;
3043 }
3044
3045 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
3046                          struct ras_common_if *ras_block)
3047 {
3048         return amdgpu_ras_block_late_init(adev, ras_block);
3049 }
3050
3051 /* helper function to remove ras fs node and interrupt handler */
3052 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
3053                           struct ras_common_if *ras_block)
3054 {
3055         struct amdgpu_ras_block_object *ras_obj;
3056         if (!ras_block)
3057                 return;
3058
3059         amdgpu_ras_sysfs_remove(adev, ras_block);
3060
3061         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3062         if (ras_obj->ras_cb)
3063                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3064 }
3065
3066 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
3067                           struct ras_common_if *ras_block)
3068 {
3069         return amdgpu_ras_block_late_fini(adev, ras_block);
3070 }
3071
3072 /* do some init work after IP late init as dependence.
3073  * and it runs in resume/gpu reset/booting up cases.
3074  */
3075 void amdgpu_ras_resume(struct amdgpu_device *adev)
3076 {
3077         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3078         struct ras_manager *obj, *tmp;
3079
3080         if (!adev->ras_enabled || !con) {
3081                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
3082                 amdgpu_release_ras_context(adev);
3083
3084                 return;
3085         }
3086
3087         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
3088                 /* Set up all other IPs which are not implemented. There is a
3089                  * tricky thing that IP's actual ras error type should be
3090                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3091                  * ERROR_NONE make sense anyway.
3092                  */
3093                 amdgpu_ras_enable_all_features(adev, 1);
3094
3095                 /* We enable ras on all hw_supported block, but as boot
3096                  * parameter might disable some of them and one or more IP has
3097                  * not implemented yet. So we disable them on behalf.
3098                  */
3099                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3100                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3101                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3102                                 /* there should be no any reference. */
3103                                 WARN_ON(alive_obj(obj));
3104                         }
3105                 }
3106         }
3107 }
3108
3109 void amdgpu_ras_suspend(struct amdgpu_device *adev)
3110 {
3111         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3112
3113         if (!adev->ras_enabled || !con)
3114                 return;
3115
3116         amdgpu_ras_disable_all_features(adev, 0);
3117         /* Make sure all ras objects are disabled. */
3118         if (con->features)
3119                 amdgpu_ras_disable_all_features(adev, 1);
3120 }
3121
3122 int amdgpu_ras_late_init(struct amdgpu_device *adev)
3123 {
3124         struct amdgpu_ras_block_list *node, *tmp;
3125         struct amdgpu_ras_block_object *obj;
3126         int r;
3127
3128         /* Guest side doesn't need init ras feature */
3129         if (amdgpu_sriov_vf(adev))
3130                 return 0;
3131
3132         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3133                 if (!node->ras_obj) {
3134                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3135                         continue;
3136                 }
3137
3138                 obj = node->ras_obj;
3139                 if (obj->ras_late_init) {
3140                         r = obj->ras_late_init(adev, &obj->ras_comm);
3141                         if (r) {
3142                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3143                                         obj->ras_comm.name, r);
3144                                 return r;
3145                         }
3146                 } else
3147                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3148         }
3149
3150         return 0;
3151 }
3152
3153 /* do some fini work before IP fini as dependence */
3154 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3155 {
3156         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3157
3158         if (!adev->ras_enabled || !con)
3159                 return 0;
3160
3161
3162         /* Need disable ras on all IPs here before ip [hw/sw]fini */
3163         if (con->features)
3164                 amdgpu_ras_disable_all_features(adev, 0);
3165         amdgpu_ras_recovery_fini(adev);
3166         return 0;
3167 }
3168
3169 int amdgpu_ras_fini(struct amdgpu_device *adev)
3170 {
3171         struct amdgpu_ras_block_list *ras_node, *tmp;
3172         struct amdgpu_ras_block_object *obj = NULL;
3173         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3174
3175         if (!adev->ras_enabled || !con)
3176                 return 0;
3177
3178         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3179                 if (ras_node->ras_obj) {
3180                         obj = ras_node->ras_obj;
3181                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3182                             obj->ras_fini)
3183                                 obj->ras_fini(adev, &obj->ras_comm);
3184                         else
3185                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3186                 }
3187
3188                 /* Clear ras blocks from ras_list and free ras block list node */
3189                 list_del(&ras_node->node);
3190                 kfree(ras_node);
3191         }
3192
3193         amdgpu_ras_fs_fini(adev);
3194         amdgpu_ras_interrupt_remove_all(adev);
3195
3196         WARN(con->features, "Feature mask is not cleared");
3197
3198         if (con->features)
3199                 amdgpu_ras_disable_all_features(adev, 1);
3200
3201         cancel_delayed_work_sync(&con->ras_counte_delay_work);
3202
3203         amdgpu_ras_set_context(adev, NULL);
3204         kfree(con);
3205
3206         return 0;
3207 }
3208
3209 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3210 {
3211         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
3212                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3213
3214                 dev_info(adev->dev, "uncorrectable hardware error"
3215                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
3216
3217                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
3218                 amdgpu_ras_reset_gpu(adev);
3219         }
3220 }
3221
3222 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3223 {
3224         if (adev->asic_type == CHIP_VEGA20 &&
3225             adev->pm.fw_version <= 0x283400) {
3226                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3227                                 amdgpu_ras_intr_triggered();
3228         }
3229
3230         return false;
3231 }
3232
3233 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3234 {
3235         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3236
3237         if (!con)
3238                 return;
3239
3240         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3241                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3242                 amdgpu_ras_set_context(adev, NULL);
3243                 kfree(con);
3244         }
3245 }
3246
3247 #ifdef CONFIG_X86_MCE_AMD
3248 static struct amdgpu_device *find_adev(uint32_t node_id)
3249 {
3250         int i;
3251         struct amdgpu_device *adev = NULL;
3252
3253         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3254                 adev = mce_adev_list.devs[i];
3255
3256                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3257                     adev->gmc.xgmi.physical_node_id == node_id)
3258                         break;
3259                 adev = NULL;
3260         }
3261
3262         return adev;
3263 }
3264
3265 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3266 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3267 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3268 #define GPU_ID_OFFSET           8
3269
3270 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3271                                     unsigned long val, void *data)
3272 {
3273         struct mce *m = (struct mce *)data;
3274         struct amdgpu_device *adev = NULL;
3275         uint32_t gpu_id = 0;
3276         uint32_t umc_inst = 0, ch_inst = 0;
3277
3278         /*
3279          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3280          * and error occurred in DramECC (Extended error code = 0) then only
3281          * process the error, else bail out.
3282          */
3283         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3284                     (XEC(m->status, 0x3f) == 0x0)))
3285                 return NOTIFY_DONE;
3286
3287         /*
3288          * If it is correctable error, return.
3289          */
3290         if (mce_is_correctable(m))
3291                 return NOTIFY_OK;
3292
3293         /*
3294          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3295          */
3296         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3297
3298         adev = find_adev(gpu_id);
3299         if (!adev) {
3300                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3301                                                                 gpu_id);
3302                 return NOTIFY_DONE;
3303         }
3304
3305         /*
3306          * If it is uncorrectable error, then find out UMC instance and
3307          * channel index.
3308          */
3309         umc_inst = GET_UMC_INST(m->ipid);
3310         ch_inst = GET_CHAN_INDEX(m->ipid);
3311
3312         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3313                              umc_inst, ch_inst);
3314
3315         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3316                 return NOTIFY_OK;
3317         else
3318                 return NOTIFY_DONE;
3319 }
3320
3321 static struct notifier_block amdgpu_bad_page_nb = {
3322         .notifier_call  = amdgpu_bad_page_notifier,
3323         .priority       = MCE_PRIO_UC,
3324 };
3325
3326 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3327 {
3328         /*
3329          * Add the adev to the mce_adev_list.
3330          * During mode2 reset, amdgpu device is temporarily
3331          * removed from the mgpu_info list which can cause
3332          * page retirement to fail.
3333          * Use this list instead of mgpu_info to find the amdgpu
3334          * device on which the UMC error was reported.
3335          */
3336         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3337
3338         /*
3339          * Register the x86 notifier only once
3340          * with MCE subsystem.
3341          */
3342         if (notifier_registered == false) {
3343                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3344                 notifier_registered = true;
3345         }
3346 }
3347 #endif
3348
3349 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3350 {
3351         if (!adev)
3352                 return NULL;
3353
3354         return adev->psp.ras_context.ras;
3355 }
3356
3357 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3358 {
3359         if (!adev)
3360                 return -EINVAL;
3361
3362         adev->psp.ras_context.ras = ras_con;
3363         return 0;
3364 }
3365
3366 /* check if ras is supported on block, say, sdma, gfx */
3367 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3368                 unsigned int block)
3369 {
3370         int ret = 0;
3371         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3372
3373         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3374                 return 0;
3375
3376         ret = ras && (adev->ras_enabled & (1 << block));
3377
3378         /* For the special asic with mem ecc enabled but sram ecc
3379          * not enabled, even if the ras block is not supported on
3380          * .ras_enabled, if the asic supports poison mode and the
3381          * ras block has ras configuration, it can be considered
3382          * that the ras block supports ras function.
3383          */
3384         if (!ret &&
3385             (block == AMDGPU_RAS_BLOCK__GFX ||
3386              block == AMDGPU_RAS_BLOCK__SDMA ||
3387              block == AMDGPU_RAS_BLOCK__VCN ||
3388              block == AMDGPU_RAS_BLOCK__JPEG) &&
3389             amdgpu_ras_is_poison_mode_supported(adev) &&
3390             amdgpu_ras_get_ras_block(adev, block, 0))
3391                 ret = 1;
3392
3393         return ret;
3394 }
3395
3396 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3397 {
3398         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3399
3400         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3401                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3402         return 0;
3403 }
3404
3405 void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
3406 {
3407         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3408
3409         if (con)
3410                 con->is_mca_debug_mode = enable;
3411 }
3412
3413 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev)
3414 {
3415         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3416         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3417
3418         if (!con)
3419                 return false;
3420
3421         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3422                 return con->is_mca_debug_mode;
3423         else
3424                 return true;
3425 }
3426
3427 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
3428                                      unsigned int *error_query_mode)
3429 {
3430         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3431         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3432
3433         if (!con) {
3434                 *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY;
3435                 return false;
3436         }
3437
3438         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3439                 *error_query_mode =
3440                         (con->is_mca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY;
3441         else
3442                 *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY;
3443
3444         return true;
3445 }
3446
3447 /* Register each ip ras block into amdgpu ras */
3448 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3449                 struct amdgpu_ras_block_object *ras_block_obj)
3450 {
3451         struct amdgpu_ras_block_list *ras_node;
3452         if (!adev || !ras_block_obj)
3453                 return -EINVAL;
3454
3455         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3456         if (!ras_node)
3457                 return -ENOMEM;
3458
3459         INIT_LIST_HEAD(&ras_node->node);
3460         ras_node->ras_obj = ras_block_obj;
3461         list_add_tail(&ras_node->node, &adev->ras_list);
3462
3463         return 0;
3464 }
3465
3466 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3467 {
3468         if (!err_type_name)
3469                 return;
3470
3471         switch (err_type) {
3472         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3473                 sprintf(err_type_name, "correctable");
3474                 break;
3475         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3476                 sprintf(err_type_name, "uncorrectable");
3477                 break;
3478         default:
3479                 sprintf(err_type_name, "unknown");
3480                 break;
3481         }
3482 }
3483
3484 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3485                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3486                                          uint32_t instance,
3487                                          uint32_t *memory_id)
3488 {
3489         uint32_t err_status_lo_data, err_status_lo_offset;
3490
3491         if (!reg_entry)
3492                 return false;
3493
3494         err_status_lo_offset =
3495                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3496                                             reg_entry->seg_lo, reg_entry->reg_lo);
3497         err_status_lo_data = RREG32(err_status_lo_offset);
3498
3499         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3500             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3501                 return false;
3502
3503         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3504
3505         return true;
3506 }
3507
3508 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3509                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3510                                        uint32_t instance,
3511                                        unsigned long *err_cnt)
3512 {
3513         uint32_t err_status_hi_data, err_status_hi_offset;
3514
3515         if (!reg_entry)
3516                 return false;
3517
3518         err_status_hi_offset =
3519                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3520                                             reg_entry->seg_hi, reg_entry->reg_hi);
3521         err_status_hi_data = RREG32(err_status_hi_offset);
3522
3523         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3524             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3525                 /* keep the check here in case we need to refer to the result later */
3526                 dev_dbg(adev->dev, "Invalid err_info field\n");
3527
3528         /* read err count */
3529         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3530
3531         return true;
3532 }
3533
3534 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3535                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3536                                            uint32_t reg_list_size,
3537                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3538                                            uint32_t mem_list_size,
3539                                            uint32_t instance,
3540                                            uint32_t err_type,
3541                                            unsigned long *err_count)
3542 {
3543         uint32_t memory_id;
3544         unsigned long err_cnt;
3545         char err_type_name[16];
3546         uint32_t i, j;
3547
3548         for (i = 0; i < reg_list_size; i++) {
3549                 /* query memory_id from err_status_lo */
3550                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3551                                                          instance, &memory_id))
3552                         continue;
3553
3554                 /* query err_cnt from err_status_hi */
3555                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3556                                                        instance, &err_cnt) ||
3557                     !err_cnt)
3558                         continue;
3559
3560                 *err_count += err_cnt;
3561
3562                 /* log the errors */
3563                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3564                 if (!mem_list) {
3565                         /* memory_list is not supported */
3566                         dev_info(adev->dev,
3567                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3568                                  err_cnt, err_type_name,
3569                                  reg_list[i].block_name,
3570                                  instance, memory_id);
3571                 } else {
3572                         for (j = 0; j < mem_list_size; j++) {
3573                                 if (memory_id == mem_list[j].memory_id) {
3574                                         dev_info(adev->dev,
3575                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3576                                                  err_cnt, err_type_name,
3577                                                  reg_list[i].block_name,
3578                                                  instance, mem_list[j].name);
3579                                         break;
3580                                 }
3581                         }
3582                 }
3583         }
3584 }
3585
3586 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3587                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3588                                            uint32_t reg_list_size,
3589                                            uint32_t instance)
3590 {
3591         uint32_t err_status_lo_offset, err_status_hi_offset;
3592         uint32_t i;
3593
3594         for (i = 0; i < reg_list_size; i++) {
3595                 err_status_lo_offset =
3596                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3597                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3598                 err_status_hi_offset =
3599                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3600                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3601                 WREG32(err_status_lo_offset, 0);
3602                 WREG32(err_status_hi_offset, 0);
3603         }
3604 }
3605
3606 int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
3607 {
3608         memset(err_data, 0, sizeof(*err_data));
3609
3610         INIT_LIST_HEAD(&err_data->err_node_list);
3611
3612         return 0;
3613 }
3614
3615 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
3616 {
3617         if (!err_node)
3618                 return;
3619
3620         list_del(&err_node->node);
3621         kvfree(err_node);
3622 }
3623
3624 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
3625 {
3626         struct ras_err_node *err_node, *tmp;
3627
3628         list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
3629                 amdgpu_ras_error_node_release(err_node);
3630 }
3631
3632 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
3633                                                              struct amdgpu_smuio_mcm_config_info *mcm_info)
3634 {
3635         struct ras_err_node *err_node;
3636         struct amdgpu_smuio_mcm_config_info *ref_id;
3637
3638         if (!err_data || !mcm_info)
3639                 return NULL;
3640
3641         for_each_ras_error(err_node, err_data) {
3642                 ref_id = &err_node->err_info.mcm_info;
3643
3644                 if (mcm_info->socket_id == ref_id->socket_id &&
3645                     mcm_info->die_id == ref_id->die_id)
3646                         return err_node;
3647         }
3648
3649         return NULL;
3650 }
3651
3652 static struct ras_err_node *amdgpu_ras_error_node_new(void)
3653 {
3654         struct ras_err_node *err_node;
3655
3656         err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
3657         if (!err_node)
3658                 return NULL;
3659
3660         INIT_LIST_HEAD(&err_node->node);
3661
3662         return err_node;
3663 }
3664
3665 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
3666                                                       struct amdgpu_smuio_mcm_config_info *mcm_info)
3667 {
3668         struct ras_err_node *err_node;
3669
3670         err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
3671         if (err_node)
3672                 return &err_node->err_info;
3673
3674         err_node = amdgpu_ras_error_node_new();
3675         if (!err_node)
3676                 return NULL;
3677
3678         memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
3679
3680         err_data->err_list_count++;
3681         list_add_tail(&err_node->node, &err_data->err_node_list);
3682
3683         return &err_node->err_info;
3684 }
3685
3686 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
3687                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3688 {
3689         struct ras_err_info *err_info;
3690
3691         if (!err_data || !mcm_info)
3692                 return -EINVAL;
3693
3694         if (!count)
3695                 return 0;
3696
3697         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3698         if (!err_info)
3699                 return -EINVAL;
3700
3701         err_info->ue_count += count;
3702         err_data->ue_count += count;
3703
3704         return 0;
3705 }
3706
3707 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
3708                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3709 {
3710         struct ras_err_info *err_info;
3711
3712         if (!err_data || !mcm_info)
3713                 return -EINVAL;
3714
3715         if (!count)
3716                 return 0;
3717
3718         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3719         if (!err_info)
3720                 return -EINVAL;
3721
3722         err_info->ce_count += count;
3723         err_data->ce_count += count;
3724
3725         return 0;
3726 }