drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36 #include "atom.h"
  37
  38 static const char *RAS_FS_NAME = "ras";
  39
  40 const char *ras_error_string[] = {
  41         "none",
  42         "parity",
  43         "single_correctable",
  44         "multi_uncorrectable",
  45         "poison",
  46 };
  47
  48 const char *ras_block_string[] = {
  49         "umc",
  50         "sdma",
  51         "gfx",
  52         "mmhub",
  53         "athub",
  54         "pcie_bif",
  55         "hdp",
  56         "xgmi_wafl",
  57         "df",
  58         "smn",
  59         "sem",
  60         "mp0",
  61         "mp1",
  62         "fuse",
  63 };
  64
  65 #define ras_err_str(i) (ras_error_string[ffs(i)])
  66 #define ras_block_str(i) (ras_block_string[i])
  67
  68 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  69
  70 /* inject address is 52 bits */
  71 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  72
  73 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  74 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  75
  76 enum amdgpu_ras_retire_page_reservation {
  77         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  78         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  79         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  80 };
  81
  82 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  83
  84 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  85                                 uint64_t addr);
  86 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  87                                 uint64_t addr);
  88
  89 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  90 {
  91         if (adev && amdgpu_ras_get_context(adev))
  92                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  93 }
  94
  95 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  96 {
  97         if (adev && amdgpu_ras_get_context(adev))
  98                 return amdgpu_ras_get_context(adev)->error_query_ready;
  99
 100         return false;
 101 }
 102
 103 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 104 {
 105         struct ras_err_data err_data = {0, 0, 0, NULL};
 106         struct eeprom_table_record err_rec;
 107
 108         if ((address >= adev->gmc.mc_vram_size) ||
 109             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 110                 dev_warn(adev->dev,
 111                          "RAS WARN: input address 0x%llx is invalid.\n",
 112                          address);
 113                 return -EINVAL;
 114         }
 115
 116         if (amdgpu_ras_check_bad_page(adev, address)) {
 117                 dev_warn(adev->dev,
 118                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 119                          address);
 120                 return 0;
 121         }
 122
 123         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 124
 125         err_rec.address = address;
 126         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 127         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 128         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 129
 130         err_data.err_addr = &err_rec;
 131         err_data.err_addr_cnt = 1;
 132
 133         if (amdgpu_bad_page_threshold != 0) {
 134                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 135                                          err_data.err_addr_cnt);
 136                 amdgpu_ras_save_bad_pages(adev);
 137         }
 138
 139         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 140         dev_warn(adev->dev, "Clear EEPROM:\n");
 141         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 142
 143         return 0;
 144 }
 145
 146 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 147                                         size_t size, loff_t *pos)
 148 {
 149         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 150         struct ras_query_if info = {
 151                 .head = obj->head,
 152         };
 153         ssize_t s;
 154         char val[128];
 155
 156         if (amdgpu_ras_query_error_status(obj->adev, &info))
 157                 return -EINVAL;
 158
 159         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 160                         "ue", info.ue_count,
 161                         "ce", info.ce_count);
 162         if (*pos >= s)
 163                 return 0;
 164
 165         s -= *pos;
 166         s = min_t(u64, s, size);
 167
 168
 169         if (copy_to_user(buf, &val[*pos], s))
 170                 return -EINVAL;
 171
 172         *pos += s;
 173
 174         return s;
 175 }
 176
 177 static const struct file_operations amdgpu_ras_debugfs_ops = {
 178         .owner = THIS_MODULE,
 179         .read = amdgpu_ras_debugfs_read,
 180         .write = NULL,
 181         .llseek = default_llseek
 182 };
 183
 184 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 185 {
 186         int i;
 187
 188         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 189                 *block_id = i;
 190                 if (strcmp(name, ras_block_str(i)) == 0)
 191                         return 0;
 192         }
 193         return -EINVAL;
 194 }
 195
 196 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 197                 const char __user *buf, size_t size,
 198                 loff_t *pos, struct ras_debug_if *data)
 199 {
 200         ssize_t s = min_t(u64, 64, size);
 201         char str[65];
 202         char block_name[33];
 203         char err[9] = "ue";
 204         int op = -1;
 205         int block_id;
 206         uint32_t sub_block;
 207         u64 address, value;
 208
 209         if (*pos)
 210                 return -EINVAL;
 211         *pos = size;
 212
 213         memset(str, 0, sizeof(str));
 214         memset(data, 0, sizeof(*data));
 215
 216         if (copy_from_user(str, buf, s))
 217                 return -EINVAL;
 218
 219         if (sscanf(str, "disable %32s", block_name) == 1)
 220                 op = 0;
 221         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 222                 op = 1;
 223         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 224                 op = 2;
 225         else if (strstr(str, "retire_page") != NULL)
 226                 op = 3;
 227         else if (str[0] && str[1] && str[2] && str[3])
 228                 /* ascii string, but commands are not matched. */
 229                 return -EINVAL;
 230
 231         if (op != -1) {
 232                 if (op == 3) {
 233                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 234                             sscanf(str, "%*s %llu", &address) != 1)
 235                                 return -EINVAL;
 236
 237                         data->op = op;
 238                         data->inject.address = address;
 239
 240                         return 0;
 241                 }
 242
 243                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 244                         return -EINVAL;
 245
 246                 data->head.block = block_id;
 247                 /* only ue and ce errors are supported */
 248                 if (!memcmp("ue", err, 2))
 249                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 250                 else if (!memcmp("ce", err, 2))
 251                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 252                 else
 253                         return -EINVAL;
 254
 255                 data->op = op;
 256
 257                 if (op == 2) {
 258                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 259                                    &sub_block, &address, &value) != 3 &&
 260                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 261                                    &sub_block, &address, &value) != 3)
 262                                 return -EINVAL;
 263                         data->head.sub_block_index = sub_block;
 264                         data->inject.address = address;
 265                         data->inject.value = value;
 266                 }
 267         } else {
 268                 if (size < sizeof(*data))
 269                         return -EINVAL;
 270
 271                 if (copy_from_user(data, buf, sizeof(*data)))
 272                         return -EINVAL;
 273         }
 274
 275         return 0;
 276 }
 277
 278 /**
 279  * DOC: AMDGPU RAS debugfs control interface
 280  *
 281  * The control interface accepts struct ras_debug_if which has two members.
 282  *
 283  * First member: ras_debug_if::head or ras_debug_if::inject.
 284  *
 285  * head is used to indicate which IP block will be under control.
 286  *
 287  * head has four members, they are block, type, sub_block_index, name.
 288  * block: which IP will be under control.
 289  * type: what kind of error will be enabled/disabled/injected.
 290  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 291  * name: the name of IP.
 292  *
 293  * inject has two more members than head, they are address, value.
 294  * As their names indicate, inject operation will write the
 295  * value to the address.
 296  *
 297  * The second member: struct ras_debug_if::op.
 298  * It has three kinds of operations.
 299  *
 300  * - 0: disable RAS on the block. Take ::head as its data.
 301  * - 1: enable RAS on the block. Take ::head as its data.
 302  * - 2: inject errors on the block. Take ::inject as its data.
 303  *
 304  * How to use the interface?
 305  *
 306  * In a program
 307  *
 308  * Copy the struct ras_debug_if in your code and initialize it.
 309  * Write the struct to the control interface.
 310  *
 311  * From shell
 312  *
 313  * .. code-block:: bash
 314  *
 315  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 316  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 317  *      echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 318  *
 319  * Where N, is the card which you want to affect.
 320  *
 321  * "disable" requires only the block.
 322  * "enable" requires the block and error type.
 323  * "inject" requires the block, error type, address, and value.
 324  * The block is one of: umc, sdma, gfx, etc.
 325  *      see ras_block_string[] for details
 326  * The error type is one of: ue, ce, where,
 327  *      ue is multi-uncorrectable
 328  *      ce is single-correctable
 329  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 330  * The address and value are hexadecimal numbers, leading 0x is optional.
 331  *
 332  * For instance,
 333  *
 334  * .. code-block:: bash
 335  *
 336  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 337  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 338  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 339  *
 340  * How to check the result of the operation?
 341  *
 342  * To check disable/enable, see "ras" features at,
 343  * /sys/class/drm/card[0/1/2...]/device/ras/features
 344  *
 345  * To check inject, see the corresponding error count at,
 346  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 347  *
 348  * .. note::
 349  *      Operations are only allowed on blocks which are supported.
 350  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 351  *      to see which blocks support RAS on a particular asic.
 352  *
 353  */
 354 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 355                 size_t size, loff_t *pos)
 356 {
 357         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 358         struct ras_debug_if data;
 359         int ret = 0;
 360
 361         if (!amdgpu_ras_get_error_query_ready(adev)) {
 362                 dev_warn(adev->dev, "RAS WARN: error injection "
 363                                 "currently inaccessible\n");
 364                 return size;
 365         }
 366
 367         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 368         if (ret)
 369                 return -EINVAL;
 370
 371         if (data.op == 3) {
 372                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 373                 if (!ret)
 374                         return size;
 375                 else
 376                         return ret;
 377         }
 378
 379         if (!amdgpu_ras_is_supported(adev, data.head.block))
 380                 return -EINVAL;
 381
 382         switch (data.op) {
 383         case 0:
 384                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 385                 break;
 386         case 1:
 387                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 388                 break;
 389         case 2:
 390                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 391                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 392                         dev_warn(adev->dev, "RAS WARN: input address "
 393                                         "0x%llx is invalid.",
 394                                         data.inject.address);
 395                         ret = -EINVAL;
 396                         break;
 397                 }
 398
 399                 /* umc ce/ue error injection for a bad page is not allowed */
 400                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 401                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 402                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 403                                         "as bad before error injection!\n",
 404                                         data.inject.address);
 405                         break;
 406                 }
 407
 408                 /* data.inject.address is offset instead of absolute gpu address */
 409                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 410                 break;
 411         default:
 412                 ret = -EINVAL;
 413                 break;
 414         }
 415
 416         if (ret)
 417                 return -EINVAL;
 418
 419         return size;
 420 }
 421
 422 /**
 423  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 424  *
 425  * Some boards contain an EEPROM which is used to persistently store a list of
 426  * bad pages which experiences ECC errors in vram.  This interface provides
 427  * a way to reset the EEPROM, e.g., after testing error injection.
 428  *
 429  * Usage:
 430  *
 431  * .. code-block:: bash
 432  *
 433  *      echo 1 > ../ras/ras_eeprom_reset
 434  *
 435  * will reset EEPROM table to 0 entries.
 436  *
 437  */
 438 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 439                 size_t size, loff_t *pos)
 440 {
 441         struct amdgpu_device *adev =
 442                 (struct amdgpu_device *)file_inode(f)->i_private;
 443         int ret;
 444
 445         ret = amdgpu_ras_eeprom_reset_table(
 446                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 447
 448         if (ret == 1) {
 449                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 450                 return size;
 451         } else {
 452                 return -EIO;
 453         }
 454 }
 455
 456 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 457         .owner = THIS_MODULE,
 458         .read = NULL,
 459         .write = amdgpu_ras_debugfs_ctrl_write,
 460         .llseek = default_llseek
 461 };
 462
 463 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 464         .owner = THIS_MODULE,
 465         .read = NULL,
 466         .write = amdgpu_ras_debugfs_eeprom_write,
 467         .llseek = default_llseek
 468 };
 469
 470 /**
 471  * DOC: AMDGPU RAS sysfs Error Count Interface
 472  *
 473  * It allows the user to read the error count for each IP block on the gpu through
 474  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 475  *
 476  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 477  * (ce) error counts.
 478  *
 479  * The format of one line is below,
 480  *
 481  * [ce|ue]: count
 482  *
 483  * Example:
 484  *
 485  * .. code-block:: bash
 486  *
 487  *      ue: 0
 488  *      ce: 1
 489  *
 490  */
 491 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 492                 struct device_attribute *attr, char *buf)
 493 {
 494         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 495         struct ras_query_if info = {
 496                 .head = obj->head,
 497         };
 498
 499         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 500                 return sysfs_emit(buf, "Query currently inaccessible\n");
 501
 502         if (amdgpu_ras_query_error_status(obj->adev, &info))
 503                 return -EINVAL;
 504
 505
 506         if (obj->adev->asic_type == CHIP_ALDEBARAN) {
 507                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 508                         DRM_WARN("Failed to reset error counter and error status");
 509         }
 510
 511         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 512                           "ce", info.ce_count);
 513 }
 514
 515 /* obj begin */
 516
 517 #define get_obj(obj) do { (obj)->use++; } while (0)
 518 #define alive_obj(obj) ((obj)->use)
 519
 520 static inline void put_obj(struct ras_manager *obj)
 521 {
 522         if (obj && (--obj->use == 0))
 523                 list_del(&obj->node);
 524         if (obj && (obj->use < 0))
 525                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 526 }
 527
 528 /* make one obj and return it. */
 529 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 530                 struct ras_common_if *head)
 531 {
 532         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 533         struct ras_manager *obj;
 534
 535         if (!adev->ras_enabled || !con)
 536                 return NULL;
 537
 538         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 539                 return NULL;
 540
 541         obj = &con->objs[head->block];
 542         /* already exist. return obj? */
 543         if (alive_obj(obj))
 544                 return NULL;
 545
 546         obj->head = *head;
 547         obj->adev = adev;
 548         list_add(&obj->node, &con->head);
 549         get_obj(obj);
 550
 551         return obj;
 552 }
 553
 554 /* return an obj equal to head, or the first when head is NULL */
 555 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 556                 struct ras_common_if *head)
 557 {
 558         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 559         struct ras_manager *obj;
 560         int i;
 561
 562         if (!adev->ras_enabled || !con)
 563                 return NULL;
 564
 565         if (head) {
 566                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 567                         return NULL;
 568
 569                 obj = &con->objs[head->block];
 570
 571                 if (alive_obj(obj)) {
 572                         WARN_ON(head->block != obj->head.block);
 573                         return obj;
 574                 }
 575         } else {
 576                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 577                         obj = &con->objs[i];
 578                         if (alive_obj(obj)) {
 579                                 WARN_ON(i != obj->head.block);
 580                                 return obj;
 581                         }
 582                 }
 583         }
 584
 585         return NULL;
 586 }
 587 /* obj end */
 588
 589 /* feature ctl begin */
 590 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 591                                          struct ras_common_if *head)
 592 {
 593         return adev->ras_hw_enabled & BIT(head->block);
 594 }
 595
 596 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 597                 struct ras_common_if *head)
 598 {
 599         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 600
 601         return con->features & BIT(head->block);
 602 }
 603
 604 /*
 605  * if obj is not created, then create one.
 606  * set feature enable flag.
 607  */
 608 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 609                 struct ras_common_if *head, int enable)
 610 {
 611         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 612         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 613
 614         /* If hardware does not support ras, then do not create obj.
 615          * But if hardware support ras, we can create the obj.
 616          * Ras framework checks con->hw_supported to see if it need do
 617          * corresponding initialization.
 618          * IP checks con->support to see if it need disable ras.
 619          */
 620         if (!amdgpu_ras_is_feature_allowed(adev, head))
 621                 return 0;
 622         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 623                 return 0;
 624
 625         if (enable) {
 626                 if (!obj) {
 627                         obj = amdgpu_ras_create_obj(adev, head);
 628                         if (!obj)
 629                                 return -EINVAL;
 630                 } else {
 631                         /* In case we create obj somewhere else */
 632                         get_obj(obj);
 633                 }
 634                 con->features |= BIT(head->block);
 635         } else {
 636                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 637                         con->features &= ~BIT(head->block);
 638                         put_obj(obj);
 639                 }
 640         }
 641
 642         return 0;
 643 }
 644
 645 /* wrapper of psp_ras_enable_features */
 646 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 647                 struct ras_common_if *head, bool enable)
 648 {
 649         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 650         union ta_ras_cmd_input *info;
 651         int ret;
 652
 653         if (!con)
 654                 return -EINVAL;
 655
 656         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 657         if (!info)
 658                 return -ENOMEM;
 659
 660         if (!enable) {
 661                 info->disable_features = (struct ta_ras_disable_features_input) {
 662                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 663                         .error_type = amdgpu_ras_error_to_ta(head->type),
 664                 };
 665         } else {
 666                 info->enable_features = (struct ta_ras_enable_features_input) {
 667                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 668                         .error_type = amdgpu_ras_error_to_ta(head->type),
 669                 };
 670         }
 671
 672         /* Do not enable if it is not allowed. */
 673         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 674         /* Are we alerady in that state we are going to set? */
 675         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 676                 ret = 0;
 677                 goto out;
 678         }
 679
 680         if (!amdgpu_ras_intr_triggered()) {
 681                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 682                 if (ret) {
 683                         dev_err(adev->dev, "ras %s %s failed %d\n",
 684                                 enable ? "enable":"disable",
 685                                 ras_block_str(head->block),
 686                                 ret);
 687                         goto out;
 688                 }
 689         }
 690
 691         /* setup the obj */
 692         __amdgpu_ras_feature_enable(adev, head, enable);
 693         ret = 0;
 694 out:
 695         kfree(info);
 696         return ret;
 697 }
 698
 699 /* Only used in device probe stage and called only once. */
 700 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 701                 struct ras_common_if *head, bool enable)
 702 {
 703         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 704         int ret;
 705
 706         if (!con)
 707                 return -EINVAL;
 708
 709         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 710                 if (enable) {
 711                         /* There is no harm to issue a ras TA cmd regardless of
 712                          * the currecnt ras state.
 713                          * If current state == target state, it will do nothing
 714                          * But sometimes it requests driver to reset and repost
 715                          * with error code -EAGAIN.
 716                          */
 717                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 718                         /* With old ras TA, we might fail to enable ras.
 719                          * Log it and just setup the object.
 720                          * TODO need remove this WA in the future.
 721                          */
 722                         if (ret == -EINVAL) {
 723                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 724                                 if (!ret)
 725                                         dev_info(adev->dev,
 726                                                 "RAS INFO: %s setup object\n",
 727                                                 ras_block_str(head->block));
 728                         }
 729                 } else {
 730                         /* setup the object then issue a ras TA disable cmd.*/
 731                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 732                         if (ret)
 733                                 return ret;
 734
 735                         /* gfx block ras dsiable cmd must send to ras-ta */
 736                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 737                                 con->features |= BIT(head->block);
 738
 739                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 740
 741                         /* clean gfx block ras features flag */
 742                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 743                                 con->features &= ~BIT(head->block);
 744                 }
 745         } else
 746                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 747
 748         return ret;
 749 }
 750
 751 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 752                 bool bypass)
 753 {
 754         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 755         struct ras_manager *obj, *tmp;
 756
 757         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 758                 /* bypass psp.
 759                  * aka just release the obj and corresponding flags
 760                  */
 761                 if (bypass) {
 762                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 763                                 break;
 764                 } else {
 765                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 766                                 break;
 767                 }
 768         }
 769
 770         return con->features;
 771 }
 772
 773 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 774                 bool bypass)
 775 {
 776         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 777         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 778         int i;
 779         const enum amdgpu_ras_error_type default_ras_type =
 780                 AMDGPU_RAS_ERROR__NONE;
 781
 782         for (i = 0; i < ras_block_count; i++) {
 783                 struct ras_common_if head = {
 784                         .block = i,
 785                         .type = default_ras_type,
 786                         .sub_block_index = 0,
 787                 };
 788                 strcpy(head.name, ras_block_str(i));
 789                 if (bypass) {
 790                         /*
 791                          * bypass psp. vbios enable ras for us.
 792                          * so just create the obj
 793                          */
 794                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 795                                 break;
 796                 } else {
 797                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 798                                 break;
 799                 }
 800         }
 801
 802         return con->features;
 803 }
 804 /* feature ctl end */
 805
 806 /* query/inject/cure begin */
 807 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 808         struct ras_query_if *info)
 809 {
 810         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 811         struct ras_err_data err_data = {0, 0, 0, NULL};
 812         int i;
 813
 814         if (!obj)
 815                 return -EINVAL;
 816
 817         switch (info->head.block) {
 818         case AMDGPU_RAS_BLOCK__UMC:
 819                 if (adev->umc.ras_funcs &&
 820                     adev->umc.ras_funcs->query_ras_error_count)
 821                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 822                 /* umc query_ras_error_address is also responsible for clearing
 823                  * error status
 824                  */
 825                 if (adev->umc.ras_funcs &&
 826                     adev->umc.ras_funcs->query_ras_error_address)
 827                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 828                 break;
 829         case AMDGPU_RAS_BLOCK__SDMA:
 830                 if (adev->sdma.funcs->query_ras_error_count) {
 831                         for (i = 0; i < adev->sdma.num_instances; i++)
 832                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 833                                                                         &err_data);
 834                 }
 835                 break;
 836         case AMDGPU_RAS_BLOCK__GFX:
 837                 if (adev->gfx.ras_funcs &&
 838                     adev->gfx.ras_funcs->query_ras_error_count)
 839                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 840
 841                 if (adev->gfx.ras_funcs &&
 842                     adev->gfx.ras_funcs->query_ras_error_status)
 843                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 844                 break;
 845         case AMDGPU_RAS_BLOCK__MMHUB:
 846                 if (adev->mmhub.ras_funcs &&
 847                     adev->mmhub.ras_funcs->query_ras_error_count)
 848                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 849
 850                 if (adev->mmhub.ras_funcs &&
 851                     adev->mmhub.ras_funcs->query_ras_error_status)
 852                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 853                 break;
 854         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 855                 if (adev->nbio.ras_funcs &&
 856                     adev->nbio.ras_funcs->query_ras_error_count)
 857                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 858                 break;
 859         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 860                 if (adev->gmc.xgmi.ras_funcs &&
 861                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 862                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 863                 break;
 864         case AMDGPU_RAS_BLOCK__HDP:
 865                 if (adev->hdp.ras_funcs &&
 866                     adev->hdp.ras_funcs->query_ras_error_count)
 867                         adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
 868                 break;
 869         default:
 870                 break;
 871         }
 872
 873         obj->err_data.ue_count += err_data.ue_count;
 874         obj->err_data.ce_count += err_data.ce_count;
 875
 876         info->ue_count = obj->err_data.ue_count;
 877         info->ce_count = obj->err_data.ce_count;
 878
 879         if (err_data.ce_count) {
 880                 if (adev->smuio.funcs &&
 881                     adev->smuio.funcs->get_socket_id &&
 882                     adev->smuio.funcs->get_die_id) {
 883                         dev_info(adev->dev, "socket: %d, die: %d "
 884                                         "%ld correctable hardware errors "
 885                                         "detected in %s block, no user "
 886                                         "action is needed.\n",
 887                                         adev->smuio.funcs->get_socket_id(adev),
 888                                         adev->smuio.funcs->get_die_id(adev),
 889                                         obj->err_data.ce_count,
 890                                         ras_block_str(info->head.block));
 891                 } else {
 892                         dev_info(adev->dev, "%ld correctable hardware errors "
 893                                         "detected in %s block, no user "
 894                                         "action is needed.\n",
 895                                         obj->err_data.ce_count,
 896                                         ras_block_str(info->head.block));
 897                 }
 898         }
 899         if (err_data.ue_count) {
 900                 if (adev->smuio.funcs &&
 901                     adev->smuio.funcs->get_socket_id &&
 902                     adev->smuio.funcs->get_die_id) {
 903                         dev_info(adev->dev, "socket: %d, die: %d "
 904                                         "%ld uncorrectable hardware errors "
 905                                         "detected in %s block\n",
 906                                         adev->smuio.funcs->get_socket_id(adev),
 907                                         adev->smuio.funcs->get_die_id(adev),
 908                                         obj->err_data.ue_count,
 909                                         ras_block_str(info->head.block));
 910                 } else {
 911                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
 912                                         "detected in %s block\n",
 913                                         obj->err_data.ue_count,
 914                                         ras_block_str(info->head.block));
 915                 }
 916         }
 917
 918         return 0;
 919 }
 920
 921 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 922                 enum amdgpu_ras_block block)
 923 {
 924         if (!amdgpu_ras_is_supported(adev, block))
 925                 return -EINVAL;
 926
 927         switch (block) {
 928         case AMDGPU_RAS_BLOCK__GFX:
 929                 if (adev->gfx.ras_funcs &&
 930                     adev->gfx.ras_funcs->reset_ras_error_count)
 931                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
 932
 933                 if (adev->gfx.ras_funcs &&
 934                     adev->gfx.ras_funcs->reset_ras_error_status)
 935                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
 936                 break;
 937         case AMDGPU_RAS_BLOCK__MMHUB:
 938                 if (adev->mmhub.ras_funcs &&
 939                     adev->mmhub.ras_funcs->reset_ras_error_count)
 940                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
 941
 942                 if (adev->mmhub.ras_funcs &&
 943                     adev->mmhub.ras_funcs->reset_ras_error_status)
 944                         adev->mmhub.ras_funcs->reset_ras_error_status(adev);
 945                 break;
 946         case AMDGPU_RAS_BLOCK__SDMA:
 947                 if (adev->sdma.funcs->reset_ras_error_count)
 948                         adev->sdma.funcs->reset_ras_error_count(adev);
 949                 break;
 950         case AMDGPU_RAS_BLOCK__HDP:
 951                 if (adev->hdp.ras_funcs &&
 952                     adev->hdp.ras_funcs->reset_ras_error_count)
 953                         adev->hdp.ras_funcs->reset_ras_error_count(adev);
 954                 break;
 955         default:
 956                 break;
 957         }
 958
 959         return 0;
 960 }
 961
 962 /* Trigger XGMI/WAFL error */
 963 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 964                                  struct ta_ras_trigger_error_input *block_info)
 965 {
 966         int ret;
 967
 968         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 969                 dev_warn(adev->dev, "Failed to disallow df cstate");
 970
 971         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 972                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 973
 974         ret = psp_ras_trigger_error(&adev->psp, block_info);
 975
 976         if (amdgpu_ras_intr_triggered())
 977                 return ret;
 978
 979         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 980                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 981
 982         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 983                 dev_warn(adev->dev, "Failed to allow df cstate");
 984
 985         return ret;
 986 }
 987
 988 /* wrapper of psp_ras_trigger_error */
 989 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 990                 struct ras_inject_if *info)
 991 {
 992         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 993         struct ta_ras_trigger_error_input block_info = {
 994                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 995                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 996                 .sub_block_index = info->head.sub_block_index,
 997                 .address = info->address,
 998                 .value = info->value,
 999         };
1000         int ret = 0;
1001
1002         if (!obj)
1003                 return -EINVAL;
1004
1005         /* Calculate XGMI relative offset */
1006         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1007                 block_info.address =
1008                         amdgpu_xgmi_get_relative_phy_addr(adev,
1009                                                           block_info.address);
1010         }
1011
1012         switch (info->head.block) {
1013         case AMDGPU_RAS_BLOCK__GFX:
1014                 if (adev->gfx.ras_funcs &&
1015                     adev->gfx.ras_funcs->ras_error_inject)
1016                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1017                 else
1018                         ret = -EINVAL;
1019                 break;
1020         case AMDGPU_RAS_BLOCK__UMC:
1021         case AMDGPU_RAS_BLOCK__SDMA:
1022         case AMDGPU_RAS_BLOCK__MMHUB:
1023         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1024                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1025                 break;
1026         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1027                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1028                 break;
1029         default:
1030                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1031                          ras_block_str(info->head.block));
1032                 ret = -EINVAL;
1033         }
1034
1035         if (ret)
1036                 dev_err(adev->dev, "ras inject %s failed %d\n",
1037                         ras_block_str(info->head.block), ret);
1038
1039         return ret;
1040 }
1041
1042 /* get the total error counts on all IPs */
1043 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1044                 bool is_ce)
1045 {
1046         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1047         struct ras_manager *obj;
1048         struct ras_err_data data = {0, 0};
1049
1050         if (!adev->ras_enabled || !con)
1051                 return 0;
1052
1053         list_for_each_entry(obj, &con->head, node) {
1054                 struct ras_query_if info = {
1055                         .head = obj->head,
1056                 };
1057
1058                 if (amdgpu_ras_query_error_status(adev, &info))
1059                         return 0;
1060
1061                 data.ce_count += info.ce_count;
1062                 data.ue_count += info.ue_count;
1063         }
1064
1065         return is_ce ? data.ce_count : data.ue_count;
1066 }
1067 /* query/inject/cure end */
1068
1069
1070 /* sysfs begin */
1071
1072 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1073                 struct ras_badpage **bps, unsigned int *count);
1074
1075 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1076 {
1077         switch (flags) {
1078         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1079                 return "R";
1080         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1081                 return "P";
1082         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1083         default:
1084                 return "F";
1085         }
1086 }
1087
1088 /**
1089  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1090  *
1091  * It allows user to read the bad pages of vram on the gpu through
1092  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1093  *
1094  * It outputs multiple lines, and each line stands for one gpu page.
1095  *
1096  * The format of one line is below,
1097  * gpu pfn : gpu page size : flags
1098  *
1099  * gpu pfn and gpu page size are printed in hex format.
1100  * flags can be one of below character,
1101  *
1102  * R: reserved, this gpu page is reserved and not able to use.
1103  *
1104  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1105  * in next window of page_reserve.
1106  *
1107  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1108  *
1109  * Examples:
1110  *
1111  * .. code-block:: bash
1112  *
1113  *      0x00000001 : 0x00001000 : R
1114  *      0x00000002 : 0x00001000 : P
1115  *
1116  */
1117
1118 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1119                 struct kobject *kobj, struct bin_attribute *attr,
1120                 char *buf, loff_t ppos, size_t count)
1121 {
1122         struct amdgpu_ras *con =
1123                 container_of(attr, struct amdgpu_ras, badpages_attr);
1124         struct amdgpu_device *adev = con->adev;
1125         const unsigned int element_size =
1126                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1127         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1128         unsigned int end = div64_ul(ppos + count - 1, element_size);
1129         ssize_t s = 0;
1130         struct ras_badpage *bps = NULL;
1131         unsigned int bps_count = 0;
1132
1133         memset(buf, 0, count);
1134
1135         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1136                 return 0;
1137
1138         for (; start < end && start < bps_count; start++)
1139                 s += scnprintf(&buf[s], element_size + 1,
1140                                 "0x%08x : 0x%08x : %1s\n",
1141                                 bps[start].bp,
1142                                 bps[start].size,
1143                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1144
1145         kfree(bps);
1146
1147         return s;
1148 }
1149
1150 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1151                 struct device_attribute *attr, char *buf)
1152 {
1153         struct amdgpu_ras *con =
1154                 container_of(attr, struct amdgpu_ras, features_attr);
1155
1156         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1157 }
1158
1159 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1160 {
1161         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1162
1163         sysfs_remove_file_from_group(&adev->dev->kobj,
1164                                 &con->badpages_attr.attr,
1165                                 RAS_FS_NAME);
1166 }
1167
1168 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1169 {
1170         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1171         struct attribute *attrs[] = {
1172                 &con->features_attr.attr,
1173                 NULL
1174         };
1175         struct attribute_group group = {
1176                 .name = RAS_FS_NAME,
1177                 .attrs = attrs,
1178         };
1179
1180         sysfs_remove_group(&adev->dev->kobj, &group);
1181
1182         return 0;
1183 }
1184
1185 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1186                 struct ras_fs_if *head)
1187 {
1188         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1189
1190         if (!obj || obj->attr_inuse)
1191                 return -EINVAL;
1192
1193         get_obj(obj);
1194
1195         memcpy(obj->fs_data.sysfs_name,
1196                         head->sysfs_name,
1197                         sizeof(obj->fs_data.sysfs_name));
1198
1199         obj->sysfs_attr = (struct device_attribute){
1200                 .attr = {
1201                         .name = obj->fs_data.sysfs_name,
1202                         .mode = S_IRUGO,
1203                 },
1204                         .show = amdgpu_ras_sysfs_read,
1205         };
1206         sysfs_attr_init(&obj->sysfs_attr.attr);
1207
1208         if (sysfs_add_file_to_group(&adev->dev->kobj,
1209                                 &obj->sysfs_attr.attr,
1210                                 RAS_FS_NAME)) {
1211                 put_obj(obj);
1212                 return -EINVAL;
1213         }
1214
1215         obj->attr_inuse = 1;
1216
1217         return 0;
1218 }
1219
1220 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1221                 struct ras_common_if *head)
1222 {
1223         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1224
1225         if (!obj || !obj->attr_inuse)
1226                 return -EINVAL;
1227
1228         sysfs_remove_file_from_group(&adev->dev->kobj,
1229                                 &obj->sysfs_attr.attr,
1230                                 RAS_FS_NAME);
1231         obj->attr_inuse = 0;
1232         put_obj(obj);
1233
1234         return 0;
1235 }
1236
1237 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1238 {
1239         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1240         struct ras_manager *obj, *tmp;
1241
1242         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1243                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1244         }
1245
1246         if (amdgpu_bad_page_threshold != 0)
1247                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1248
1249         amdgpu_ras_sysfs_remove_feature_node(adev);
1250
1251         return 0;
1252 }
1253 /* sysfs end */
1254
1255 /**
1256  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1257  *
1258  * Normally when there is an uncorrectable error, the driver will reset
1259  * the GPU to recover.  However, in the event of an unrecoverable error,
1260  * the driver provides an interface to reboot the system automatically
1261  * in that event.
1262  *
1263  * The following file in debugfs provides that interface:
1264  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1265  *
1266  * Usage:
1267  *
1268  * .. code-block:: bash
1269  *
1270  *      echo true > .../ras/auto_reboot
1271  *
1272  */
1273 /* debugfs begin */
1274 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1275 {
1276         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1277         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1278         struct dentry     *dir;
1279
1280         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1281         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1282                             &amdgpu_ras_debugfs_ctrl_ops);
1283         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1284                             &amdgpu_ras_debugfs_eeprom_ops);
1285         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1286                            &con->bad_page_cnt_threshold);
1287         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1288         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1289
1290         /*
1291          * After one uncorrectable error happens, usually GPU recovery will
1292          * be scheduled. But due to the known problem in GPU recovery failing
1293          * to bring GPU back, below interface provides one direct way to
1294          * user to reboot system automatically in such case within
1295          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1296          * will never be called.
1297          */
1298         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1299
1300         /*
1301          * User could set this not to clean up hardware's error count register
1302          * of RAS IPs during ras recovery.
1303          */
1304         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1305                             &con->disable_ras_err_cnt_harvest);
1306         return dir;
1307 }
1308
1309 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1310                                       struct ras_fs_if *head,
1311                                       struct dentry *dir)
1312 {
1313         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1314
1315         if (!obj || !dir)
1316                 return;
1317
1318         get_obj(obj);
1319
1320         memcpy(obj->fs_data.debugfs_name,
1321                         head->debugfs_name,
1322                         sizeof(obj->fs_data.debugfs_name));
1323
1324         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1325                             obj, &amdgpu_ras_debugfs_ops);
1326 }
1327
1328 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1329 {
1330         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1331         struct dentry *dir;
1332         struct ras_manager *obj;
1333         struct ras_fs_if fs_info;
1334
1335         /*
1336          * it won't be called in resume path, no need to check
1337          * suspend and gpu reset status
1338          */
1339         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1340                 return;
1341
1342         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1343
1344         list_for_each_entry(obj, &con->head, node) {
1345                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1346                         (obj->attr_inuse == 1)) {
1347                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1348                                         ras_block_str(obj->head.block));
1349                         fs_info.head = obj->head;
1350                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1351                 }
1352         }
1353 }
1354
1355 /* debugfs end */
1356
1357 /* ras fs */
1358 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1359                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1360 static DEVICE_ATTR(features, S_IRUGO,
1361                 amdgpu_ras_sysfs_features_read, NULL);
1362 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1363 {
1364         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1365         struct attribute_group group = {
1366                 .name = RAS_FS_NAME,
1367         };
1368         struct attribute *attrs[] = {
1369                 &con->features_attr.attr,
1370                 NULL
1371         };
1372         struct bin_attribute *bin_attrs[] = {
1373                 NULL,
1374                 NULL,
1375         };
1376         int r;
1377
1378         /* add features entry */
1379         con->features_attr = dev_attr_features;
1380         group.attrs = attrs;
1381         sysfs_attr_init(attrs[0]);
1382
1383         if (amdgpu_bad_page_threshold != 0) {
1384                 /* add bad_page_features entry */
1385                 bin_attr_gpu_vram_bad_pages.private = NULL;
1386                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1387                 bin_attrs[0] = &con->badpages_attr;
1388                 group.bin_attrs = bin_attrs;
1389                 sysfs_bin_attr_init(bin_attrs[0]);
1390         }
1391
1392         r = sysfs_create_group(&adev->dev->kobj, &group);
1393         if (r)
1394                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1395
1396         return 0;
1397 }
1398
1399 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1400 {
1401         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1402         struct ras_manager *con_obj, *ip_obj, *tmp;
1403
1404         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1405                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1406                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1407                         if (ip_obj)
1408                                 put_obj(ip_obj);
1409                 }
1410         }
1411
1412         amdgpu_ras_sysfs_remove_all(adev);
1413         return 0;
1414 }
1415 /* ras fs end */
1416
1417 /* ih begin */
1418 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1419 {
1420         struct ras_ih_data *data = &obj->ih_data;
1421         struct amdgpu_iv_entry entry;
1422         int ret;
1423         struct ras_err_data err_data = {0, 0, 0, NULL};
1424
1425         while (data->rptr != data->wptr) {
1426                 rmb();
1427                 memcpy(&entry, &data->ring[data->rptr],
1428                                 data->element_size);
1429
1430                 wmb();
1431                 data->rptr = (data->aligned_element_size +
1432                                 data->rptr) % data->ring_size;
1433
1434                 /* Let IP handle its data, maybe we need get the output
1435                  * from the callback to udpate the error type/count, etc
1436                  */
1437                 if (data->cb) {
1438                         ret = data->cb(obj->adev, &err_data, &entry);
1439                         /* ue will trigger an interrupt, and in that case
1440                          * we need do a reset to recovery the whole system.
1441                          * But leave IP do that recovery, here we just dispatch
1442                          * the error.
1443                          */
1444                         if (ret == AMDGPU_RAS_SUCCESS) {
1445                                 /* these counts could be left as 0 if
1446                                  * some blocks do not count error number
1447                                  */
1448                                 obj->err_data.ue_count += err_data.ue_count;
1449                                 obj->err_data.ce_count += err_data.ce_count;
1450                         }
1451                 }
1452         }
1453 }
1454
1455 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1456 {
1457         struct ras_ih_data *data =
1458                 container_of(work, struct ras_ih_data, ih_work);
1459         struct ras_manager *obj =
1460                 container_of(data, struct ras_manager, ih_data);
1461
1462         amdgpu_ras_interrupt_handler(obj);
1463 }
1464
1465 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1466                 struct ras_dispatch_if *info)
1467 {
1468         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1469         struct ras_ih_data *data = &obj->ih_data;
1470
1471         if (!obj)
1472                 return -EINVAL;
1473
1474         if (data->inuse == 0)
1475                 return 0;
1476
1477         /* Might be overflow... */
1478         memcpy(&data->ring[data->wptr], info->entry,
1479                         data->element_size);
1480
1481         wmb();
1482         data->wptr = (data->aligned_element_size +
1483                         data->wptr) % data->ring_size;
1484
1485         schedule_work(&data->ih_work);
1486
1487         return 0;
1488 }
1489
1490 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1491                 struct ras_ih_if *info)
1492 {
1493         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1494         struct ras_ih_data *data;
1495
1496         if (!obj)
1497                 return -EINVAL;
1498
1499         data = &obj->ih_data;
1500         if (data->inuse == 0)
1501                 return 0;
1502
1503         cancel_work_sync(&data->ih_work);
1504
1505         kfree(data->ring);
1506         memset(data, 0, sizeof(*data));
1507         put_obj(obj);
1508
1509         return 0;
1510 }
1511
1512 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1513                 struct ras_ih_if *info)
1514 {
1515         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1516         struct ras_ih_data *data;
1517
1518         if (!obj) {
1519                 /* in case we registe the IH before enable ras feature */
1520                 obj = amdgpu_ras_create_obj(adev, &info->head);
1521                 if (!obj)
1522                         return -EINVAL;
1523         } else
1524                 get_obj(obj);
1525
1526         data = &obj->ih_data;
1527         /* add the callback.etc */
1528         *data = (struct ras_ih_data) {
1529                 .inuse = 0,
1530                 .cb = info->cb,
1531                 .element_size = sizeof(struct amdgpu_iv_entry),
1532                 .rptr = 0,
1533                 .wptr = 0,
1534         };
1535
1536         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1537
1538         data->aligned_element_size = ALIGN(data->element_size, 8);
1539         /* the ring can store 64 iv entries. */
1540         data->ring_size = 64 * data->aligned_element_size;
1541         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1542         if (!data->ring) {
1543                 put_obj(obj);
1544                 return -ENOMEM;
1545         }
1546
1547         /* IH is ready */
1548         data->inuse = 1;
1549
1550         return 0;
1551 }
1552
1553 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1554 {
1555         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1556         struct ras_manager *obj, *tmp;
1557
1558         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1559                 struct ras_ih_if info = {
1560                         .head = obj->head,
1561                 };
1562                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1563         }
1564
1565         return 0;
1566 }
1567 /* ih end */
1568
1569 /* traversal all IPs except NBIO to query error counter */
1570 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1571 {
1572         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1573         struct ras_manager *obj;
1574
1575         if (!adev->ras_enabled || !con)
1576                 return;
1577
1578         list_for_each_entry(obj, &con->head, node) {
1579                 struct ras_query_if info = {
1580                         .head = obj->head,
1581                 };
1582
1583                 /*
1584                  * PCIE_BIF IP has one different isr by ras controller
1585                  * interrupt, the specific ras counter query will be
1586                  * done in that isr. So skip such block from common
1587                  * sync flood interrupt isr calling.
1588                  */
1589                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1590                         continue;
1591
1592                 amdgpu_ras_query_error_status(adev, &info);
1593         }
1594 }
1595
1596 /* Parse RdRspStatus and WrRspStatus */
1597 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1598                                           struct ras_query_if *info)
1599 {
1600         /*
1601          * Only two block need to query read/write
1602          * RspStatus at current state
1603          */
1604         switch (info->head.block) {
1605         case AMDGPU_RAS_BLOCK__GFX:
1606                 if (adev->gfx.ras_funcs &&
1607                     adev->gfx.ras_funcs->query_ras_error_status)
1608                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1609                 break;
1610         case AMDGPU_RAS_BLOCK__MMHUB:
1611                 if (adev->mmhub.ras_funcs &&
1612                     adev->mmhub.ras_funcs->query_ras_error_status)
1613                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1614                 break;
1615         default:
1616                 break;
1617         }
1618 }
1619
1620 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1621 {
1622         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1623         struct ras_manager *obj;
1624
1625         if (!adev->ras_enabled || !con)
1626                 return;
1627
1628         list_for_each_entry(obj, &con->head, node) {
1629                 struct ras_query_if info = {
1630                         .head = obj->head,
1631                 };
1632
1633                 amdgpu_ras_error_status_query(adev, &info);
1634         }
1635 }
1636
1637 /* recovery begin */
1638
1639 /* return 0 on success.
1640  * caller need free bps.
1641  */
1642 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1643                 struct ras_badpage **bps, unsigned int *count)
1644 {
1645         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1646         struct ras_err_handler_data *data;
1647         int i = 0;
1648         int ret = 0, status;
1649
1650         if (!con || !con->eh_data || !bps || !count)
1651                 return -EINVAL;
1652
1653         mutex_lock(&con->recovery_lock);
1654         data = con->eh_data;
1655         if (!data || data->count == 0) {
1656                 *bps = NULL;
1657                 ret = -EINVAL;
1658                 goto out;
1659         }
1660
1661         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1662         if (!*bps) {
1663                 ret = -ENOMEM;
1664                 goto out;
1665         }
1666
1667         for (; i < data->count; i++) {
1668                 (*bps)[i] = (struct ras_badpage){
1669                         .bp = data->bps[i].retired_page,
1670                         .size = AMDGPU_GPU_PAGE_SIZE,
1671                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1672                 };
1673                 status = amdgpu_vram_mgr_query_page_status(
1674                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1675                                 data->bps[i].retired_page);
1676                 if (status == -EBUSY)
1677                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1678                 else if (status == -ENOENT)
1679                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1680         }
1681
1682         *count = data->count;
1683 out:
1684         mutex_unlock(&con->recovery_lock);
1685         return ret;
1686 }
1687
1688 static void amdgpu_ras_do_recovery(struct work_struct *work)
1689 {
1690         struct amdgpu_ras *ras =
1691                 container_of(work, struct amdgpu_ras, recovery_work);
1692         struct amdgpu_device *remote_adev = NULL;
1693         struct amdgpu_device *adev = ras->adev;
1694         struct list_head device_list, *device_list_handle =  NULL;
1695
1696         if (!ras->disable_ras_err_cnt_harvest) {
1697                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1698
1699                 /* Build list of devices to query RAS related errors */
1700                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1701                         device_list_handle = &hive->device_list;
1702                 } else {
1703                         INIT_LIST_HEAD(&device_list);
1704                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1705                         device_list_handle = &device_list;
1706                 }
1707
1708                 list_for_each_entry(remote_adev,
1709                                 device_list_handle, gmc.xgmi.head) {
1710                         amdgpu_ras_query_err_status(remote_adev);
1711                         amdgpu_ras_log_on_err_counter(remote_adev);
1712                 }
1713
1714                 amdgpu_put_xgmi_hive(hive);
1715         }
1716
1717         if (amdgpu_device_should_recover_gpu(ras->adev))
1718                 amdgpu_device_gpu_recover(ras->adev, NULL);
1719         atomic_set(&ras->in_recovery, 0);
1720 }
1721
1722 /* alloc/realloc bps array */
1723 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1724                 struct ras_err_handler_data *data, int pages)
1725 {
1726         unsigned int old_space = data->count + data->space_left;
1727         unsigned int new_space = old_space + pages;
1728         unsigned int align_space = ALIGN(new_space, 512);
1729         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1730
1731         if (!bps) {
1732                 kfree(bps);
1733                 return -ENOMEM;
1734         }
1735
1736         if (data->bps) {
1737                 memcpy(bps, data->bps,
1738                                 data->count * sizeof(*data->bps));
1739                 kfree(data->bps);
1740         }
1741
1742         data->bps = bps;
1743         data->space_left += align_space - old_space;
1744         return 0;
1745 }
1746
1747 /* it deal with vram only. */
1748 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1749                 struct eeprom_table_record *bps, int pages)
1750 {
1751         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1752         struct ras_err_handler_data *data;
1753         int ret = 0;
1754         uint32_t i;
1755
1756         if (!con || !con->eh_data || !bps || pages <= 0)
1757                 return 0;
1758
1759         mutex_lock(&con->recovery_lock);
1760         data = con->eh_data;
1761         if (!data)
1762                 goto out;
1763
1764         for (i = 0; i < pages; i++) {
1765                 if (amdgpu_ras_check_bad_page_unlock(con,
1766                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1767                         continue;
1768
1769                 if (!data->space_left &&
1770                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1771                         ret = -ENOMEM;
1772                         goto out;
1773                 }
1774
1775                 amdgpu_vram_mgr_reserve_range(
1776                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1777                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1778                         AMDGPU_GPU_PAGE_SIZE);
1779
1780                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1781                 data->count++;
1782                 data->space_left--;
1783         }
1784 out:
1785         mutex_unlock(&con->recovery_lock);
1786
1787         return ret;
1788 }
1789
1790 /*
1791  * write error record array to eeprom, the function should be
1792  * protected by recovery_lock
1793  */
1794 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1795 {
1796         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1797         struct ras_err_handler_data *data;
1798         struct amdgpu_ras_eeprom_control *control;
1799         int save_count;
1800
1801         if (!con || !con->eh_data)
1802                 return 0;
1803
1804         control = &con->eeprom_control;
1805         data = con->eh_data;
1806         save_count = data->count - control->num_recs;
1807         /* only new entries are saved */
1808         if (save_count > 0) {
1809                 if (amdgpu_ras_eeprom_process_recods(control,
1810                                                         &data->bps[control->num_recs],
1811                                                         true,
1812                                                         save_count)) {
1813                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1814                         return -EIO;
1815                 }
1816
1817                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1818         }
1819
1820         return 0;
1821 }
1822
1823 /*
1824  * read error record array in eeprom and reserve enough space for
1825  * storing new bad pages
1826  */
1827 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1828 {
1829         struct amdgpu_ras_eeprom_control *control =
1830                                         &adev->psp.ras.ras->eeprom_control;
1831         struct eeprom_table_record *bps = NULL;
1832         int ret = 0;
1833
1834         /* no bad page record, skip eeprom access */
1835         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1836                 return ret;
1837
1838         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1839         if (!bps)
1840                 return -ENOMEM;
1841
1842         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1843                 control->num_recs)) {
1844                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1845                 ret = -EIO;
1846                 goto out;
1847         }
1848
1849         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1850
1851 out:
1852         kfree(bps);
1853         return ret;
1854 }
1855
1856 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1857                                 uint64_t addr)
1858 {
1859         struct ras_err_handler_data *data = con->eh_data;
1860         int i;
1861
1862         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1863         for (i = 0; i < data->count; i++)
1864                 if (addr == data->bps[i].retired_page)
1865                         return true;
1866
1867         return false;
1868 }
1869
1870 /*
1871  * check if an address belongs to bad page
1872  *
1873  * Note: this check is only for umc block
1874  */
1875 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1876                                 uint64_t addr)
1877 {
1878         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1879         bool ret = false;
1880
1881         if (!con || !con->eh_data)
1882                 return ret;
1883
1884         mutex_lock(&con->recovery_lock);
1885         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1886         mutex_unlock(&con->recovery_lock);
1887         return ret;
1888 }
1889
1890 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1891                                         uint32_t max_length)
1892 {
1893         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1894         int tmp_threshold = amdgpu_bad_page_threshold;
1895         u64 val;
1896
1897         /*
1898          * Justification of value bad_page_cnt_threshold in ras structure
1899          *
1900          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1901          * in eeprom, and introduce two scenarios accordingly.
1902          *
1903          * Bad page retirement enablement:
1904          *    - If amdgpu_bad_page_threshold = -1,
1905          *      bad_page_cnt_threshold = typical value by formula.
1906          *
1907          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1908          *      max record length in eeprom, use it directly.
1909          *
1910          * Bad page retirement disablement:
1911          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1912          *      functionality is disabled, and bad_page_cnt_threshold will
1913          *      take no effect.
1914          */
1915
1916         if (tmp_threshold < -1)
1917                 tmp_threshold = -1;
1918         else if (tmp_threshold > max_length)
1919                 tmp_threshold = max_length;
1920
1921         if (tmp_threshold == -1) {
1922                 val = adev->gmc.mc_vram_size;
1923                 do_div(val, RAS_BAD_PAGE_RATE);
1924                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1925                                                 max_length);
1926         } else {
1927                 con->bad_page_cnt_threshold = tmp_threshold;
1928         }
1929 }
1930
1931 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1932 {
1933         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1934         struct ras_err_handler_data **data;
1935         uint32_t max_eeprom_records_len = 0;
1936         bool exc_err_limit = false;
1937         int ret;
1938
1939         if (adev->ras_enabled && con)
1940                 data = &con->eh_data;
1941         else
1942                 return 0;
1943
1944         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1945         if (!*data) {
1946                 ret = -ENOMEM;
1947                 goto out;
1948         }
1949
1950         mutex_init(&con->recovery_lock);
1951         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1952         atomic_set(&con->in_recovery, 0);
1953         con->adev = adev;
1954
1955         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1956         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1957
1958         /* Todo: During test the SMU might fail to read the eeprom through I2C
1959          * when the GPU is pending on XGMI reset during probe time
1960          * (Mostly after second bus reset), skip it now
1961          */
1962         if (adev->gmc.xgmi.pending_reset)
1963                 return 0;
1964         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1965         /*
1966          * This calling fails when exc_err_limit is true or
1967          * ret != 0.
1968          */
1969         if (exc_err_limit || ret)
1970                 goto free;
1971
1972         if (con->eeprom_control.num_recs) {
1973                 ret = amdgpu_ras_load_bad_pages(adev);
1974                 if (ret)
1975                         goto free;
1976         }
1977
1978         return 0;
1979
1980 free:
1981         kfree((*data)->bps);
1982         kfree(*data);
1983         con->eh_data = NULL;
1984 out:
1985         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1986
1987         /*
1988          * Except error threshold exceeding case, other failure cases in this
1989          * function would not fail amdgpu driver init.
1990          */
1991         if (!exc_err_limit)
1992                 ret = 0;
1993         else
1994                 ret = -EINVAL;
1995
1996         return ret;
1997 }
1998
1999 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2000 {
2001         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2002         struct ras_err_handler_data *data = con->eh_data;
2003
2004         /* recovery_init failed to init it, fini is useless */
2005         if (!data)
2006                 return 0;
2007
2008         cancel_work_sync(&con->recovery_work);
2009
2010         mutex_lock(&con->recovery_lock);
2011         con->eh_data = NULL;
2012         kfree(data->bps);
2013         kfree(data);
2014         mutex_unlock(&con->recovery_lock);
2015
2016         return 0;
2017 }
2018 /* recovery end */
2019
2020 /* return 0 if ras will reset gpu and repost.*/
2021 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2022                 unsigned int block)
2023 {
2024         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2025
2026         if (!ras)
2027                 return -EINVAL;
2028
2029         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2030         return 0;
2031 }
2032
2033 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2034 {
2035         return adev->asic_type == CHIP_VEGA10 ||
2036                 adev->asic_type == CHIP_VEGA20 ||
2037                 adev->asic_type == CHIP_ARCTURUS ||
2038                 adev->asic_type == CHIP_ALDEBARAN ||
2039                 adev->asic_type == CHIP_SIENNA_CICHLID;
2040 }
2041
2042 /*
2043  * this is workaround for vega20 workstation sku,
2044  * force enable gfx ras, ignore vbios gfx ras flag
2045  * due to GC EDC can not write
2046  */
2047 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2048 {
2049         struct atom_context *ctx = adev->mode_info.atom_context;
2050
2051         if (!ctx)
2052                 return;
2053
2054         if (strnstr(ctx->vbios_version, "D16406",
2055                     sizeof(ctx->vbios_version)))
2056                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2057 }
2058
2059 /*
2060  * check hardware's ras ability which will be saved in hw_supported.
2061  * if hardware does not support ras, we can skip some ras initializtion and
2062  * forbid some ras operations from IP.
2063  * if software itself, say boot parameter, limit the ras ability. We still
2064  * need allow IP do some limited operations, like disable. In such case,
2065  * we have to initialize ras as normal. but need check if operation is
2066  * allowed or not in each function.
2067  */
2068 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2069 {
2070         adev->ras_hw_enabled = adev->ras_enabled = 0;
2071
2072         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2073             !amdgpu_ras_asic_supported(adev))
2074                 return;
2075
2076         if (!adev->gmc.xgmi.connected_to_cpu) {
2077                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2078                         dev_info(adev->dev, "MEM ECC is active.\n");
2079                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2080                                                    1 << AMDGPU_RAS_BLOCK__DF);
2081                 } else {
2082                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2083                 }
2084
2085                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2086                         dev_info(adev->dev, "SRAM ECC is active.\n");
2087                         adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2088                                                     1 << AMDGPU_RAS_BLOCK__DF);
2089                 } else {
2090                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2091                 }
2092         } else {
2093                 /* driver only manages a few IP blocks RAS feature
2094                  * when GPU is connected cpu through XGMI */
2095                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2096                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2097                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2098         }
2099
2100         amdgpu_ras_get_quirks(adev);
2101
2102         /* hw_supported needs to be aligned with RAS block mask. */
2103         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2104
2105         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2106                 adev->ras_hw_enabled & amdgpu_ras_mask;
2107 }
2108
2109 int amdgpu_ras_init(struct amdgpu_device *adev)
2110 {
2111         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2112         int r;
2113
2114         if (con)
2115                 return 0;
2116
2117         con = kmalloc(sizeof(struct amdgpu_ras) +
2118                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2119                         GFP_KERNEL|__GFP_ZERO);
2120         if (!con)
2121                 return -ENOMEM;
2122
2123         con->objs = (struct ras_manager *)(con + 1);
2124
2125         amdgpu_ras_set_context(adev, con);
2126
2127         amdgpu_ras_check_supported(adev);
2128
2129         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2130                 /* set gfx block ras context feature for VEGA20 Gaming
2131                  * send ras disable cmd to ras ta during ras late init.
2132                  */
2133                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2134                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2135
2136                         return 0;
2137                 }
2138
2139                 r = 0;
2140                 goto release_con;
2141         }
2142
2143         con->features = 0;
2144         INIT_LIST_HEAD(&con->head);
2145         /* Might need get this flag from vbios. */
2146         con->flags = RAS_DEFAULT_FLAGS;
2147
2148         /* initialize nbio ras function ahead of any other
2149          * ras functions so hardware fatal error interrupt
2150          * can be enabled as early as possible */
2151         switch (adev->asic_type) {
2152         case CHIP_VEGA20:
2153         case CHIP_ARCTURUS:
2154         case CHIP_ALDEBARAN:
2155                 if (!adev->gmc.xgmi.connected_to_cpu)
2156                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2157                 break;
2158         default:
2159                 /* nbio ras is not available */
2160                 break;
2161         }
2162
2163         if (adev->nbio.ras_funcs &&
2164             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2165                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2166                 if (r)
2167                         goto release_con;
2168         }
2169
2170         if (adev->nbio.ras_funcs &&
2171             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2172                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2173                 if (r)
2174                         goto release_con;
2175         }
2176
2177         if (amdgpu_ras_fs_init(adev)) {
2178                 r = -EINVAL;
2179                 goto release_con;
2180         }
2181
2182         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2183                  "hardware ability[%x] ras_mask[%x]\n",
2184                  adev->ras_hw_enabled, adev->ras_enabled);
2185
2186         return 0;
2187 release_con:
2188         amdgpu_ras_set_context(adev, NULL);
2189         kfree(con);
2190
2191         return r;
2192 }
2193
2194 static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2195 {
2196         if (adev->gmc.xgmi.connected_to_cpu)
2197                 return 1;
2198         return 0;
2199 }
2200
2201 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2202                                         struct ras_common_if *ras_block)
2203 {
2204         struct ras_query_if info = {
2205                 .head = *ras_block,
2206         };
2207
2208         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2209                 return 0;
2210
2211         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2212                 DRM_WARN("RAS init harvest failure");
2213
2214         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2215                 DRM_WARN("RAS init harvest reset failure");
2216
2217         return 0;
2218 }
2219
2220 /* helper function to handle common stuff in ip late init phase */
2221 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2222                          struct ras_common_if *ras_block,
2223                          struct ras_fs_if *fs_info,
2224                          struct ras_ih_if *ih_info)
2225 {
2226         int r;
2227
2228         /* disable RAS feature per IP block if it is not supported */
2229         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2230                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2231                 return 0;
2232         }
2233
2234         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2235         if (r) {
2236                 if (r == -EAGAIN) {
2237                         /* request gpu reset. will run again */
2238                         amdgpu_ras_request_reset_on_boot(adev,
2239                                         ras_block->block);
2240                         return 0;
2241                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2242                         /* in resume phase, if fail to enable ras,
2243                          * clean up all ras fs nodes, and disable ras */
2244                         goto cleanup;
2245                 } else
2246                         return r;
2247         }
2248
2249         /* check for errors on warm reset edc persisant supported ASIC */
2250         amdgpu_persistent_edc_harvesting(adev, ras_block);
2251
2252         /* in resume phase, no need to create ras fs node */
2253         if (adev->in_suspend || amdgpu_in_reset(adev))
2254                 return 0;
2255
2256         if (ih_info->cb) {
2257                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2258                 if (r)
2259                         goto interrupt;
2260         }
2261
2262         r = amdgpu_ras_sysfs_create(adev, fs_info);
2263         if (r)
2264                 goto sysfs;
2265
2266         return 0;
2267 cleanup:
2268         amdgpu_ras_sysfs_remove(adev, ras_block);
2269 sysfs:
2270         if (ih_info->cb)
2271                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2272 interrupt:
2273         amdgpu_ras_feature_enable(adev, ras_block, 0);
2274         return r;
2275 }
2276
2277 /* helper function to remove ras fs node and interrupt handler */
2278 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2279                           struct ras_common_if *ras_block,
2280                           struct ras_ih_if *ih_info)
2281 {
2282         if (!ras_block || !ih_info)
2283                 return;
2284
2285         amdgpu_ras_sysfs_remove(adev, ras_block);
2286         if (ih_info->cb)
2287                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2288         amdgpu_ras_feature_enable(adev, ras_block, 0);
2289 }
2290
2291 /* do some init work after IP late init as dependence.
2292  * and it runs in resume/gpu reset/booting up cases.
2293  */
2294 void amdgpu_ras_resume(struct amdgpu_device *adev)
2295 {
2296         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2297         struct ras_manager *obj, *tmp;
2298
2299         if (!adev->ras_enabled || !con) {
2300                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2301                 amdgpu_release_ras_context(adev);
2302
2303                 return;
2304         }
2305
2306         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2307                 /* Set up all other IPs which are not implemented. There is a
2308                  * tricky thing that IP's actual ras error type should be
2309                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2310                  * ERROR_NONE make sense anyway.
2311                  */
2312                 amdgpu_ras_enable_all_features(adev, 1);
2313
2314                 /* We enable ras on all hw_supported block, but as boot
2315                  * parameter might disable some of them and one or more IP has
2316                  * not implemented yet. So we disable them on behalf.
2317                  */
2318                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2319                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2320                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2321                                 /* there should be no any reference. */
2322                                 WARN_ON(alive_obj(obj));
2323                         }
2324                 }
2325         }
2326
2327         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2328                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2329                 /* setup ras obj state as disabled.
2330                  * for init_by_vbios case.
2331                  * if we want to enable ras, just enable it in a normal way.
2332                  * If we want do disable it, need setup ras obj as enabled,
2333                  * then issue another TA disable cmd.
2334                  * See feature_enable_on_boot
2335                  */
2336                 amdgpu_ras_disable_all_features(adev, 1);
2337                 amdgpu_ras_reset_gpu(adev);
2338         }
2339 }
2340
2341 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2342 {
2343         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2344
2345         if (!adev->ras_enabled || !con)
2346                 return;
2347
2348         amdgpu_ras_disable_all_features(adev, 0);
2349         /* Make sure all ras objects are disabled. */
2350         if (con->features)
2351                 amdgpu_ras_disable_all_features(adev, 1);
2352 }
2353
2354 /* do some fini work before IP fini as dependence */
2355 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2356 {
2357         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2358
2359         if (!adev->ras_enabled || !con)
2360                 return 0;
2361
2362         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2363         amdgpu_ras_disable_all_features(adev, 0);
2364         amdgpu_ras_recovery_fini(adev);
2365         return 0;
2366 }
2367
2368 int amdgpu_ras_fini(struct amdgpu_device *adev)
2369 {
2370         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2371
2372         if (!adev->ras_enabled || !con)
2373                 return 0;
2374
2375         amdgpu_ras_fs_fini(adev);
2376         amdgpu_ras_interrupt_remove_all(adev);
2377
2378         WARN(con->features, "Feature mask is not cleared");
2379
2380         if (con->features)
2381                 amdgpu_ras_disable_all_features(adev, 1);
2382
2383         amdgpu_ras_set_context(adev, NULL);
2384         kfree(con);
2385
2386         return 0;
2387 }
2388
2389 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2390 {
2391         amdgpu_ras_check_supported(adev);
2392         if (!adev->ras_hw_enabled)
2393                 return;
2394
2395         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2396                 dev_info(adev->dev, "uncorrectable hardware error"
2397                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2398
2399                 amdgpu_ras_reset_gpu(adev);
2400         }
2401 }
2402
2403 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2404 {
2405         if (adev->asic_type == CHIP_VEGA20 &&
2406             adev->pm.fw_version <= 0x283400) {
2407                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2408                                 amdgpu_ras_intr_triggered();
2409         }
2410
2411         return false;
2412 }
2413
2414 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2415 {
2416         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2417
2418         if (!con)
2419                 return;
2420
2421         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2422                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2423                 amdgpu_ras_set_context(adev, NULL);
2424                 kfree(con);
2425         }
2426 }