2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
28 #include <linux/reboot.h>
29 #include <linux/syscalls.h>
30 #include <linux/pm_runtime.h>
33 #include "amdgpu_ras.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_xgmi.h"
36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
39 static const char *RAS_FS_NAME = "ras";
41 const char *ras_error_string[] = {
45 "multi_uncorrectable",
49 const char *ras_block_string[] = {
66 #define ras_err_str(i) (ras_error_string[ffs(i)])
67 #define ras_block_str(i) (ras_block_string[i])
69 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
71 /* inject address is 52 bits */
72 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
74 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
75 #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL)
77 enum amdgpu_ras_retire_page_reservation {
78 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
79 AMDGPU_RAS_RETIRE_PAGE_PENDING,
80 AMDGPU_RAS_RETIRE_PAGE_FAULT,
83 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
85 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
87 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
90 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
92 if (adev && amdgpu_ras_get_context(adev))
93 amdgpu_ras_get_context(adev)->error_query_ready = ready;
96 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
98 if (adev && amdgpu_ras_get_context(adev))
99 return amdgpu_ras_get_context(adev)->error_query_ready;
104 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
106 struct ras_err_data err_data = {0, 0, 0, NULL};
107 struct eeprom_table_record err_rec;
109 if ((address >= adev->gmc.mc_vram_size) ||
110 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
112 "RAS WARN: input address 0x%llx is invalid.\n",
117 if (amdgpu_ras_check_bad_page(adev, address)) {
119 "RAS WARN: 0x%llx has already been marked as bad page!\n",
124 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
126 err_rec.address = address;
127 err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
128 err_rec.ts = (uint64_t)ktime_get_real_seconds();
129 err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
131 err_data.err_addr = &err_rec;
132 err_data.err_addr_cnt = 1;
134 if (amdgpu_bad_page_threshold != 0) {
135 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
136 err_data.err_addr_cnt);
137 amdgpu_ras_save_bad_pages(adev);
140 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
141 dev_warn(adev->dev, "Clear EEPROM:\n");
142 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
147 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
148 size_t size, loff_t *pos)
150 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
151 struct ras_query_if info = {
157 if (amdgpu_ras_query_error_status(obj->adev, &info))
160 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
162 "ce", info.ce_count);
167 s = min_t(u64, s, size);
170 if (copy_to_user(buf, &val[*pos], s))
178 static const struct file_operations amdgpu_ras_debugfs_ops = {
179 .owner = THIS_MODULE,
180 .read = amdgpu_ras_debugfs_read,
182 .llseek = default_llseek
185 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
189 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
191 if (strcmp(name, ras_block_str(i)) == 0)
197 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
198 const char __user *buf, size_t size,
199 loff_t *pos, struct ras_debug_if *data)
201 ssize_t s = min_t(u64, 64, size);
214 memset(str, 0, sizeof(str));
215 memset(data, 0, sizeof(*data));
217 if (copy_from_user(str, buf, s))
220 if (sscanf(str, "disable %32s", block_name) == 1)
222 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
224 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
226 else if (strstr(str, "retire_page") != NULL)
228 else if (str[0] && str[1] && str[2] && str[3])
229 /* ascii string, but commands are not matched. */
234 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
235 sscanf(str, "%*s %llu", &address) != 1)
239 data->inject.address = address;
244 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
247 data->head.block = block_id;
248 /* only ue and ce errors are supported */
249 if (!memcmp("ue", err, 2))
250 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
251 else if (!memcmp("ce", err, 2))
252 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
259 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
260 &sub_block, &address, &value) != 3 &&
261 sscanf(str, "%*s %*s %*s %u %llu %llu",
262 &sub_block, &address, &value) != 3)
264 data->head.sub_block_index = sub_block;
265 data->inject.address = address;
266 data->inject.value = value;
269 if (size < sizeof(*data))
272 if (copy_from_user(data, buf, sizeof(*data)))
280 * DOC: AMDGPU RAS debugfs control interface
282 * The control interface accepts struct ras_debug_if which has two members.
284 * First member: ras_debug_if::head or ras_debug_if::inject.
286 * head is used to indicate which IP block will be under control.
288 * head has four members, they are block, type, sub_block_index, name.
289 * block: which IP will be under control.
290 * type: what kind of error will be enabled/disabled/injected.
291 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
292 * name: the name of IP.
294 * inject has two more members than head, they are address, value.
295 * As their names indicate, inject operation will write the
296 * value to the address.
298 * The second member: struct ras_debug_if::op.
299 * It has three kinds of operations.
301 * - 0: disable RAS on the block. Take ::head as its data.
302 * - 1: enable RAS on the block. Take ::head as its data.
303 * - 2: inject errors on the block. Take ::inject as its data.
305 * How to use the interface?
309 * Copy the struct ras_debug_if in your code and initialize it.
310 * Write the struct to the control interface.
314 * .. code-block:: bash
316 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
317 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
318 * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
320 * Where N, is the card which you want to affect.
322 * "disable" requires only the block.
323 * "enable" requires the block and error type.
324 * "inject" requires the block, error type, address, and value.
326 * The block is one of: umc, sdma, gfx, etc.
327 * see ras_block_string[] for details
329 * The error type is one of: ue, ce, where,
330 * ue is multi-uncorrectable
331 * ce is single-correctable
333 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
334 * The address and value are hexadecimal numbers, leading 0x is optional.
338 * .. code-block:: bash
340 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
341 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
342 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
344 * How to check the result of the operation?
346 * To check disable/enable, see "ras" features at,
347 * /sys/class/drm/card[0/1/2...]/device/ras/features
349 * To check inject, see the corresponding error count at,
350 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
353 * Operations are only allowed on blocks which are supported.
354 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
355 * to see which blocks support RAS on a particular asic.
358 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
359 size_t size, loff_t *pos)
361 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
362 struct ras_debug_if data;
365 if (!amdgpu_ras_get_error_query_ready(adev)) {
366 dev_warn(adev->dev, "RAS WARN: error injection "
367 "currently inaccessible\n");
371 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
376 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
383 if (!amdgpu_ras_is_supported(adev, data.head.block))
388 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
391 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
394 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
395 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
396 dev_warn(adev->dev, "RAS WARN: input address "
397 "0x%llx is invalid.",
398 data.inject.address);
403 /* umc ce/ue error injection for a bad page is not allowed */
404 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
405 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
406 dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
407 "as bad before error injection!\n",
408 data.inject.address);
412 /* data.inject.address is offset instead of absolute gpu address */
413 ret = amdgpu_ras_error_inject(adev, &data.inject);
427 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
429 * Some boards contain an EEPROM which is used to persistently store a list of
430 * bad pages which experiences ECC errors in vram. This interface provides
431 * a way to reset the EEPROM, e.g., after testing error injection.
435 * .. code-block:: bash
437 * echo 1 > ../ras/ras_eeprom_reset
439 * will reset EEPROM table to 0 entries.
442 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
443 size_t size, loff_t *pos)
445 struct amdgpu_device *adev =
446 (struct amdgpu_device *)file_inode(f)->i_private;
449 ret = amdgpu_ras_eeprom_reset_table(
450 &(amdgpu_ras_get_context(adev)->eeprom_control));
453 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
460 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
461 .owner = THIS_MODULE,
463 .write = amdgpu_ras_debugfs_ctrl_write,
464 .llseek = default_llseek
467 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
468 .owner = THIS_MODULE,
470 .write = amdgpu_ras_debugfs_eeprom_write,
471 .llseek = default_llseek
475 * DOC: AMDGPU RAS sysfs Error Count Interface
477 * It allows the user to read the error count for each IP block on the gpu through
478 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
480 * It outputs the multiple lines which report the uncorrected (ue) and corrected
483 * The format of one line is below,
489 * .. code-block:: bash
495 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
496 struct device_attribute *attr, char *buf)
498 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
499 struct ras_query_if info = {
503 if (!amdgpu_ras_get_error_query_ready(obj->adev))
504 return sysfs_emit(buf, "Query currently inaccessible\n");
506 if (amdgpu_ras_query_error_status(obj->adev, &info))
510 if (obj->adev->asic_type == CHIP_ALDEBARAN) {
511 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
512 DRM_WARN("Failed to reset error counter and error status");
515 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
516 "ce", info.ce_count);
521 #define get_obj(obj) do { (obj)->use++; } while (0)
522 #define alive_obj(obj) ((obj)->use)
524 static inline void put_obj(struct ras_manager *obj)
526 if (obj && (--obj->use == 0))
527 list_del(&obj->node);
528 if (obj && (obj->use < 0))
529 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
532 /* make one obj and return it. */
533 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
534 struct ras_common_if *head)
536 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
537 struct ras_manager *obj;
539 if (!adev->ras_enabled || !con)
542 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
545 obj = &con->objs[head->block];
546 /* already exist. return obj? */
552 list_add(&obj->node, &con->head);
558 /* return an obj equal to head, or the first when head is NULL */
559 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
560 struct ras_common_if *head)
562 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
563 struct ras_manager *obj;
566 if (!adev->ras_enabled || !con)
570 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
573 obj = &con->objs[head->block];
575 if (alive_obj(obj)) {
576 WARN_ON(head->block != obj->head.block);
580 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
582 if (alive_obj(obj)) {
583 WARN_ON(i != obj->head.block);
593 /* feature ctl begin */
594 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
595 struct ras_common_if *head)
597 return adev->ras_hw_enabled & BIT(head->block);
600 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
601 struct ras_common_if *head)
603 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
605 return con->features & BIT(head->block);
609 * if obj is not created, then create one.
610 * set feature enable flag.
612 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
613 struct ras_common_if *head, int enable)
615 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
616 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
618 /* If hardware does not support ras, then do not create obj.
619 * But if hardware support ras, we can create the obj.
620 * Ras framework checks con->hw_supported to see if it need do
621 * corresponding initialization.
622 * IP checks con->support to see if it need disable ras.
624 if (!amdgpu_ras_is_feature_allowed(adev, head))
626 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
631 obj = amdgpu_ras_create_obj(adev, head);
635 /* In case we create obj somewhere else */
638 con->features |= BIT(head->block);
640 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
641 con->features &= ~BIT(head->block);
649 /* wrapper of psp_ras_enable_features */
650 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
651 struct ras_common_if *head, bool enable)
653 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
654 union ta_ras_cmd_input *info;
660 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
665 info->disable_features = (struct ta_ras_disable_features_input) {
666 .block_id = amdgpu_ras_block_to_ta(head->block),
667 .error_type = amdgpu_ras_error_to_ta(head->type),
670 info->enable_features = (struct ta_ras_enable_features_input) {
671 .block_id = amdgpu_ras_block_to_ta(head->block),
672 .error_type = amdgpu_ras_error_to_ta(head->type),
676 /* Do not enable if it is not allowed. */
677 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
678 /* Are we alerady in that state we are going to set? */
679 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
684 if (!amdgpu_ras_intr_triggered()) {
685 ret = psp_ras_enable_features(&adev->psp, info, enable);
687 dev_err(adev->dev, "ras %s %s failed %d\n",
688 enable ? "enable":"disable",
689 ras_block_str(head->block),
696 __amdgpu_ras_feature_enable(adev, head, enable);
703 /* Only used in device probe stage and called only once. */
704 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
705 struct ras_common_if *head, bool enable)
707 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
713 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
715 /* There is no harm to issue a ras TA cmd regardless of
716 * the currecnt ras state.
717 * If current state == target state, it will do nothing
718 * But sometimes it requests driver to reset and repost
719 * with error code -EAGAIN.
721 ret = amdgpu_ras_feature_enable(adev, head, 1);
722 /* With old ras TA, we might fail to enable ras.
723 * Log it and just setup the object.
724 * TODO need remove this WA in the future.
726 if (ret == -EINVAL) {
727 ret = __amdgpu_ras_feature_enable(adev, head, 1);
730 "RAS INFO: %s setup object\n",
731 ras_block_str(head->block));
734 /* setup the object then issue a ras TA disable cmd.*/
735 ret = __amdgpu_ras_feature_enable(adev, head, 1);
739 /* gfx block ras dsiable cmd must send to ras-ta */
740 if (head->block == AMDGPU_RAS_BLOCK__GFX)
741 con->features |= BIT(head->block);
743 ret = amdgpu_ras_feature_enable(adev, head, 0);
745 /* clean gfx block ras features flag */
746 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
747 con->features &= ~BIT(head->block);
750 ret = amdgpu_ras_feature_enable(adev, head, enable);
755 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
758 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
759 struct ras_manager *obj, *tmp;
761 list_for_each_entry_safe(obj, tmp, &con->head, node) {
763 * aka just release the obj and corresponding flags
766 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
769 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
774 return con->features;
777 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
780 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
781 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
783 const enum amdgpu_ras_error_type default_ras_type =
784 AMDGPU_RAS_ERROR__NONE;
786 for (i = 0; i < ras_block_count; i++) {
787 struct ras_common_if head = {
789 .type = default_ras_type,
790 .sub_block_index = 0,
792 strcpy(head.name, ras_block_str(i));
795 * bypass psp. vbios enable ras for us.
796 * so just create the obj
798 if (__amdgpu_ras_feature_enable(adev, &head, 1))
801 if (amdgpu_ras_feature_enable(adev, &head, 1))
806 return con->features;
808 /* feature ctl end */
810 /* query/inject/cure begin */
811 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
812 struct ras_query_if *info)
814 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
815 struct ras_err_data err_data = {0, 0, 0, NULL};
821 switch (info->head.block) {
822 case AMDGPU_RAS_BLOCK__UMC:
823 if (adev->umc.ras_funcs &&
824 adev->umc.ras_funcs->query_ras_error_count)
825 adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
826 /* umc query_ras_error_address is also responsible for clearing
829 if (adev->umc.ras_funcs &&
830 adev->umc.ras_funcs->query_ras_error_address)
831 adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
833 case AMDGPU_RAS_BLOCK__SDMA:
834 if (adev->sdma.funcs->query_ras_error_count) {
835 for (i = 0; i < adev->sdma.num_instances; i++)
836 adev->sdma.funcs->query_ras_error_count(adev, i,
840 case AMDGPU_RAS_BLOCK__GFX:
841 if (adev->gfx.ras_funcs &&
842 adev->gfx.ras_funcs->query_ras_error_count)
843 adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
845 if (adev->gfx.ras_funcs &&
846 adev->gfx.ras_funcs->query_ras_error_status)
847 adev->gfx.ras_funcs->query_ras_error_status(adev);
849 case AMDGPU_RAS_BLOCK__MMHUB:
850 if (adev->mmhub.ras_funcs &&
851 adev->mmhub.ras_funcs->query_ras_error_count)
852 adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
854 if (adev->mmhub.ras_funcs &&
855 adev->mmhub.ras_funcs->query_ras_error_status)
856 adev->mmhub.ras_funcs->query_ras_error_status(adev);
858 case AMDGPU_RAS_BLOCK__PCIE_BIF:
859 if (adev->nbio.ras_funcs &&
860 adev->nbio.ras_funcs->query_ras_error_count)
861 adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
863 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
864 if (adev->gmc.xgmi.ras_funcs &&
865 adev->gmc.xgmi.ras_funcs->query_ras_error_count)
866 adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
868 case AMDGPU_RAS_BLOCK__HDP:
869 if (adev->hdp.ras_funcs &&
870 adev->hdp.ras_funcs->query_ras_error_count)
871 adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
877 obj->err_data.ue_count += err_data.ue_count;
878 obj->err_data.ce_count += err_data.ce_count;
880 info->ue_count = obj->err_data.ue_count;
881 info->ce_count = obj->err_data.ce_count;
883 if (err_data.ce_count) {
884 if (adev->smuio.funcs &&
885 adev->smuio.funcs->get_socket_id &&
886 adev->smuio.funcs->get_die_id) {
887 dev_info(adev->dev, "socket: %d, die: %d "
888 "%ld correctable hardware errors "
889 "detected in %s block, no user "
890 "action is needed.\n",
891 adev->smuio.funcs->get_socket_id(adev),
892 adev->smuio.funcs->get_die_id(adev),
893 obj->err_data.ce_count,
894 ras_block_str(info->head.block));
896 dev_info(adev->dev, "%ld correctable hardware errors "
897 "detected in %s block, no user "
898 "action is needed.\n",
899 obj->err_data.ce_count,
900 ras_block_str(info->head.block));
903 if (err_data.ue_count) {
904 if (adev->smuio.funcs &&
905 adev->smuio.funcs->get_socket_id &&
906 adev->smuio.funcs->get_die_id) {
907 dev_info(adev->dev, "socket: %d, die: %d "
908 "%ld uncorrectable hardware errors "
909 "detected in %s block\n",
910 adev->smuio.funcs->get_socket_id(adev),
911 adev->smuio.funcs->get_die_id(adev),
912 obj->err_data.ue_count,
913 ras_block_str(info->head.block));
915 dev_info(adev->dev, "%ld uncorrectable hardware errors "
916 "detected in %s block\n",
917 obj->err_data.ue_count,
918 ras_block_str(info->head.block));
925 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
926 enum amdgpu_ras_block block)
928 if (!amdgpu_ras_is_supported(adev, block))
932 case AMDGPU_RAS_BLOCK__GFX:
933 if (adev->gfx.ras_funcs &&
934 adev->gfx.ras_funcs->reset_ras_error_count)
935 adev->gfx.ras_funcs->reset_ras_error_count(adev);
937 if (adev->gfx.ras_funcs &&
938 adev->gfx.ras_funcs->reset_ras_error_status)
939 adev->gfx.ras_funcs->reset_ras_error_status(adev);
941 case AMDGPU_RAS_BLOCK__MMHUB:
942 if (adev->mmhub.ras_funcs &&
943 adev->mmhub.ras_funcs->reset_ras_error_count)
944 adev->mmhub.ras_funcs->reset_ras_error_count(adev);
946 if (adev->mmhub.ras_funcs &&
947 adev->mmhub.ras_funcs->reset_ras_error_status)
948 adev->mmhub.ras_funcs->reset_ras_error_status(adev);
950 case AMDGPU_RAS_BLOCK__SDMA:
951 if (adev->sdma.funcs->reset_ras_error_count)
952 adev->sdma.funcs->reset_ras_error_count(adev);
954 case AMDGPU_RAS_BLOCK__HDP:
955 if (adev->hdp.ras_funcs &&
956 adev->hdp.ras_funcs->reset_ras_error_count)
957 adev->hdp.ras_funcs->reset_ras_error_count(adev);
966 /* Trigger XGMI/WAFL error */
967 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
968 struct ta_ras_trigger_error_input *block_info)
972 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
973 dev_warn(adev->dev, "Failed to disallow df cstate");
975 if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
976 dev_warn(adev->dev, "Failed to disallow XGMI power down");
978 ret = psp_ras_trigger_error(&adev->psp, block_info);
980 if (amdgpu_ras_intr_triggered())
983 if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
984 dev_warn(adev->dev, "Failed to allow XGMI power down");
986 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
987 dev_warn(adev->dev, "Failed to allow df cstate");
992 /* wrapper of psp_ras_trigger_error */
993 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
994 struct ras_inject_if *info)
996 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
997 struct ta_ras_trigger_error_input block_info = {
998 .block_id = amdgpu_ras_block_to_ta(info->head.block),
999 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1000 .sub_block_index = info->head.sub_block_index,
1001 .address = info->address,
1002 .value = info->value,
1009 /* Calculate XGMI relative offset */
1010 if (adev->gmc.xgmi.num_physical_nodes > 1) {
1011 block_info.address =
1012 amdgpu_xgmi_get_relative_phy_addr(adev,
1013 block_info.address);
1016 switch (info->head.block) {
1017 case AMDGPU_RAS_BLOCK__GFX:
1018 if (adev->gfx.ras_funcs &&
1019 adev->gfx.ras_funcs->ras_error_inject)
1020 ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1024 case AMDGPU_RAS_BLOCK__UMC:
1025 case AMDGPU_RAS_BLOCK__SDMA:
1026 case AMDGPU_RAS_BLOCK__MMHUB:
1027 case AMDGPU_RAS_BLOCK__PCIE_BIF:
1028 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1030 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1031 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1034 dev_info(adev->dev, "%s error injection is not supported yet\n",
1035 ras_block_str(info->head.block));
1040 dev_err(adev->dev, "ras inject %s failed %d\n",
1041 ras_block_str(info->head.block), ret);
1046 /* get the total error counts on all IPs */
1047 void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1048 unsigned long *ce_count,
1049 unsigned long *ue_count)
1051 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1052 struct ras_manager *obj;
1053 unsigned long ce, ue;
1055 if (!adev->ras_enabled || !con)
1060 list_for_each_entry(obj, &con->head, node) {
1061 struct ras_query_if info = {
1065 if (amdgpu_ras_query_error_status(adev, &info))
1068 ce += info.ce_count;
1069 ue += info.ue_count;
1078 /* query/inject/cure end */
1083 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1084 struct ras_badpage **bps, unsigned int *count);
1086 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1089 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1091 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1093 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1100 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1102 * It allows user to read the bad pages of vram on the gpu through
1103 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1105 * It outputs multiple lines, and each line stands for one gpu page.
1107 * The format of one line is below,
1108 * gpu pfn : gpu page size : flags
1110 * gpu pfn and gpu page size are printed in hex format.
1111 * flags can be one of below character,
1113 * R: reserved, this gpu page is reserved and not able to use.
1115 * P: pending for reserve, this gpu page is marked as bad, will be reserved
1116 * in next window of page_reserve.
1118 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1122 * .. code-block:: bash
1124 * 0x00000001 : 0x00001000 : R
1125 * 0x00000002 : 0x00001000 : P
1129 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1130 struct kobject *kobj, struct bin_attribute *attr,
1131 char *buf, loff_t ppos, size_t count)
1133 struct amdgpu_ras *con =
1134 container_of(attr, struct amdgpu_ras, badpages_attr);
1135 struct amdgpu_device *adev = con->adev;
1136 const unsigned int element_size =
1137 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1138 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1139 unsigned int end = div64_ul(ppos + count - 1, element_size);
1141 struct ras_badpage *bps = NULL;
1142 unsigned int bps_count = 0;
1144 memset(buf, 0, count);
1146 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1149 for (; start < end && start < bps_count; start++)
1150 s += scnprintf(&buf[s], element_size + 1,
1151 "0x%08x : 0x%08x : %1s\n",
1154 amdgpu_ras_badpage_flags_str(bps[start].flags));
1161 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1162 struct device_attribute *attr, char *buf)
1164 struct amdgpu_ras *con =
1165 container_of(attr, struct amdgpu_ras, features_attr);
1167 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1170 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1172 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1174 sysfs_remove_file_from_group(&adev->dev->kobj,
1175 &con->badpages_attr.attr,
1179 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1181 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1182 struct attribute *attrs[] = {
1183 &con->features_attr.attr,
1186 struct attribute_group group = {
1187 .name = RAS_FS_NAME,
1191 sysfs_remove_group(&adev->dev->kobj, &group);
1196 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1197 struct ras_fs_if *head)
1199 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1201 if (!obj || obj->attr_inuse)
1206 memcpy(obj->fs_data.sysfs_name,
1208 sizeof(obj->fs_data.sysfs_name));
1210 obj->sysfs_attr = (struct device_attribute){
1212 .name = obj->fs_data.sysfs_name,
1215 .show = amdgpu_ras_sysfs_read,
1217 sysfs_attr_init(&obj->sysfs_attr.attr);
1219 if (sysfs_add_file_to_group(&adev->dev->kobj,
1220 &obj->sysfs_attr.attr,
1226 obj->attr_inuse = 1;
1231 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1232 struct ras_common_if *head)
1234 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1236 if (!obj || !obj->attr_inuse)
1239 sysfs_remove_file_from_group(&adev->dev->kobj,
1240 &obj->sysfs_attr.attr,
1242 obj->attr_inuse = 0;
1248 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1250 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1251 struct ras_manager *obj, *tmp;
1253 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1254 amdgpu_ras_sysfs_remove(adev, &obj->head);
1257 if (amdgpu_bad_page_threshold != 0)
1258 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1260 amdgpu_ras_sysfs_remove_feature_node(adev);
1267 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1269 * Normally when there is an uncorrectable error, the driver will reset
1270 * the GPU to recover. However, in the event of an unrecoverable error,
1271 * the driver provides an interface to reboot the system automatically
1274 * The following file in debugfs provides that interface:
1275 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1279 * .. code-block:: bash
1281 * echo true > .../ras/auto_reboot
1285 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1287 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1288 struct drm_minor *minor = adev_to_drm(adev)->primary;
1291 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1292 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1293 &amdgpu_ras_debugfs_ctrl_ops);
1294 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1295 &amdgpu_ras_debugfs_eeprom_ops);
1296 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1297 &con->bad_page_cnt_threshold);
1298 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1299 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1302 * After one uncorrectable error happens, usually GPU recovery will
1303 * be scheduled. But due to the known problem in GPU recovery failing
1304 * to bring GPU back, below interface provides one direct way to
1305 * user to reboot system automatically in such case within
1306 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1307 * will never be called.
1309 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1312 * User could set this not to clean up hardware's error count register
1313 * of RAS IPs during ras recovery.
1315 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1316 &con->disable_ras_err_cnt_harvest);
1320 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1321 struct ras_fs_if *head,
1324 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1331 memcpy(obj->fs_data.debugfs_name,
1333 sizeof(obj->fs_data.debugfs_name));
1335 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1336 obj, &amdgpu_ras_debugfs_ops);
1339 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1341 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1343 struct ras_manager *obj;
1344 struct ras_fs_if fs_info;
1347 * it won't be called in resume path, no need to check
1348 * suspend and gpu reset status
1350 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1353 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1355 list_for_each_entry(obj, &con->head, node) {
1356 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1357 (obj->attr_inuse == 1)) {
1358 sprintf(fs_info.debugfs_name, "%s_err_inject",
1359 ras_block_str(obj->head.block));
1360 fs_info.head = obj->head;
1361 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1369 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1370 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1371 static DEVICE_ATTR(features, S_IRUGO,
1372 amdgpu_ras_sysfs_features_read, NULL);
1373 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1375 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1376 struct attribute_group group = {
1377 .name = RAS_FS_NAME,
1379 struct attribute *attrs[] = {
1380 &con->features_attr.attr,
1383 struct bin_attribute *bin_attrs[] = {
1389 /* add features entry */
1390 con->features_attr = dev_attr_features;
1391 group.attrs = attrs;
1392 sysfs_attr_init(attrs[0]);
1394 if (amdgpu_bad_page_threshold != 0) {
1395 /* add bad_page_features entry */
1396 bin_attr_gpu_vram_bad_pages.private = NULL;
1397 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1398 bin_attrs[0] = &con->badpages_attr;
1399 group.bin_attrs = bin_attrs;
1400 sysfs_bin_attr_init(bin_attrs[0]);
1403 r = sysfs_create_group(&adev->dev->kobj, &group);
1405 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1410 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1412 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1413 struct ras_manager *con_obj, *ip_obj, *tmp;
1415 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1416 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1417 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1423 amdgpu_ras_sysfs_remove_all(adev);
1429 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1431 struct ras_ih_data *data = &obj->ih_data;
1432 struct amdgpu_iv_entry entry;
1434 struct ras_err_data err_data = {0, 0, 0, NULL};
1436 while (data->rptr != data->wptr) {
1438 memcpy(&entry, &data->ring[data->rptr],
1439 data->element_size);
1442 data->rptr = (data->aligned_element_size +
1443 data->rptr) % data->ring_size;
1445 /* Let IP handle its data, maybe we need get the output
1446 * from the callback to udpate the error type/count, etc
1449 ret = data->cb(obj->adev, &err_data, &entry);
1450 /* ue will trigger an interrupt, and in that case
1451 * we need do a reset to recovery the whole system.
1452 * But leave IP do that recovery, here we just dispatch
1455 if (ret == AMDGPU_RAS_SUCCESS) {
1456 /* these counts could be left as 0 if
1457 * some blocks do not count error number
1459 obj->err_data.ue_count += err_data.ue_count;
1460 obj->err_data.ce_count += err_data.ce_count;
1466 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1468 struct ras_ih_data *data =
1469 container_of(work, struct ras_ih_data, ih_work);
1470 struct ras_manager *obj =
1471 container_of(data, struct ras_manager, ih_data);
1473 amdgpu_ras_interrupt_handler(obj);
1476 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1477 struct ras_dispatch_if *info)
1479 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1480 struct ras_ih_data *data = &obj->ih_data;
1485 if (data->inuse == 0)
1488 /* Might be overflow... */
1489 memcpy(&data->ring[data->wptr], info->entry,
1490 data->element_size);
1493 data->wptr = (data->aligned_element_size +
1494 data->wptr) % data->ring_size;
1496 schedule_work(&data->ih_work);
1501 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1502 struct ras_ih_if *info)
1504 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1505 struct ras_ih_data *data;
1510 data = &obj->ih_data;
1511 if (data->inuse == 0)
1514 cancel_work_sync(&data->ih_work);
1517 memset(data, 0, sizeof(*data));
1523 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1524 struct ras_ih_if *info)
1526 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1527 struct ras_ih_data *data;
1530 /* in case we registe the IH before enable ras feature */
1531 obj = amdgpu_ras_create_obj(adev, &info->head);
1537 data = &obj->ih_data;
1538 /* add the callback.etc */
1539 *data = (struct ras_ih_data) {
1542 .element_size = sizeof(struct amdgpu_iv_entry),
1547 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1549 data->aligned_element_size = ALIGN(data->element_size, 8);
1550 /* the ring can store 64 iv entries. */
1551 data->ring_size = 64 * data->aligned_element_size;
1552 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1564 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1566 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1567 struct ras_manager *obj, *tmp;
1569 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1570 struct ras_ih_if info = {
1573 amdgpu_ras_interrupt_remove_handler(adev, &info);
1580 /* traversal all IPs except NBIO to query error counter */
1581 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1583 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1584 struct ras_manager *obj;
1586 if (!adev->ras_enabled || !con)
1589 list_for_each_entry(obj, &con->head, node) {
1590 struct ras_query_if info = {
1595 * PCIE_BIF IP has one different isr by ras controller
1596 * interrupt, the specific ras counter query will be
1597 * done in that isr. So skip such block from common
1598 * sync flood interrupt isr calling.
1600 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1603 amdgpu_ras_query_error_status(adev, &info);
1607 /* Parse RdRspStatus and WrRspStatus */
1608 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1609 struct ras_query_if *info)
1612 * Only two block need to query read/write
1613 * RspStatus at current state
1615 switch (info->head.block) {
1616 case AMDGPU_RAS_BLOCK__GFX:
1617 if (adev->gfx.ras_funcs &&
1618 adev->gfx.ras_funcs->query_ras_error_status)
1619 adev->gfx.ras_funcs->query_ras_error_status(adev);
1621 case AMDGPU_RAS_BLOCK__MMHUB:
1622 if (adev->mmhub.ras_funcs &&
1623 adev->mmhub.ras_funcs->query_ras_error_status)
1624 adev->mmhub.ras_funcs->query_ras_error_status(adev);
1631 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1633 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1634 struct ras_manager *obj;
1636 if (!adev->ras_enabled || !con)
1639 list_for_each_entry(obj, &con->head, node) {
1640 struct ras_query_if info = {
1644 amdgpu_ras_error_status_query(adev, &info);
1648 /* recovery begin */
1650 /* return 0 on success.
1651 * caller need free bps.
1653 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1654 struct ras_badpage **bps, unsigned int *count)
1656 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1657 struct ras_err_handler_data *data;
1659 int ret = 0, status;
1661 if (!con || !con->eh_data || !bps || !count)
1664 mutex_lock(&con->recovery_lock);
1665 data = con->eh_data;
1666 if (!data || data->count == 0) {
1672 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1678 for (; i < data->count; i++) {
1679 (*bps)[i] = (struct ras_badpage){
1680 .bp = data->bps[i].retired_page,
1681 .size = AMDGPU_GPU_PAGE_SIZE,
1682 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1684 status = amdgpu_vram_mgr_query_page_status(
1685 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1686 data->bps[i].retired_page);
1687 if (status == -EBUSY)
1688 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1689 else if (status == -ENOENT)
1690 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1693 *count = data->count;
1695 mutex_unlock(&con->recovery_lock);
1699 static void amdgpu_ras_do_recovery(struct work_struct *work)
1701 struct amdgpu_ras *ras =
1702 container_of(work, struct amdgpu_ras, recovery_work);
1703 struct amdgpu_device *remote_adev = NULL;
1704 struct amdgpu_device *adev = ras->adev;
1705 struct list_head device_list, *device_list_handle = NULL;
1707 if (!ras->disable_ras_err_cnt_harvest) {
1708 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1710 /* Build list of devices to query RAS related errors */
1711 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1712 device_list_handle = &hive->device_list;
1714 INIT_LIST_HEAD(&device_list);
1715 list_add_tail(&adev->gmc.xgmi.head, &device_list);
1716 device_list_handle = &device_list;
1719 list_for_each_entry(remote_adev,
1720 device_list_handle, gmc.xgmi.head) {
1721 amdgpu_ras_query_err_status(remote_adev);
1722 amdgpu_ras_log_on_err_counter(remote_adev);
1725 amdgpu_put_xgmi_hive(hive);
1728 if (amdgpu_device_should_recover_gpu(ras->adev))
1729 amdgpu_device_gpu_recover(ras->adev, NULL);
1730 atomic_set(&ras->in_recovery, 0);
1733 /* alloc/realloc bps array */
1734 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1735 struct ras_err_handler_data *data, int pages)
1737 unsigned int old_space = data->count + data->space_left;
1738 unsigned int new_space = old_space + pages;
1739 unsigned int align_space = ALIGN(new_space, 512);
1740 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1748 memcpy(bps, data->bps,
1749 data->count * sizeof(*data->bps));
1754 data->space_left += align_space - old_space;
1758 /* it deal with vram only. */
1759 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1760 struct eeprom_table_record *bps, int pages)
1762 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1763 struct ras_err_handler_data *data;
1767 if (!con || !con->eh_data || !bps || pages <= 0)
1770 mutex_lock(&con->recovery_lock);
1771 data = con->eh_data;
1775 for (i = 0; i < pages; i++) {
1776 if (amdgpu_ras_check_bad_page_unlock(con,
1777 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1780 if (!data->space_left &&
1781 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1786 amdgpu_vram_mgr_reserve_range(
1787 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1788 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1789 AMDGPU_GPU_PAGE_SIZE);
1791 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1796 mutex_unlock(&con->recovery_lock);
1802 * write error record array to eeprom, the function should be
1803 * protected by recovery_lock
1805 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1807 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1808 struct ras_err_handler_data *data;
1809 struct amdgpu_ras_eeprom_control *control;
1812 if (!con || !con->eh_data)
1815 control = &con->eeprom_control;
1816 data = con->eh_data;
1817 save_count = data->count - control->num_recs;
1818 /* only new entries are saved */
1819 if (save_count > 0) {
1820 if (amdgpu_ras_eeprom_process_recods(control,
1821 &data->bps[control->num_recs],
1824 dev_err(adev->dev, "Failed to save EEPROM table data!");
1828 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1835 * read error record array in eeprom and reserve enough space for
1836 * storing new bad pages
1838 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1840 struct amdgpu_ras_eeprom_control *control =
1841 &adev->psp.ras.ras->eeprom_control;
1842 struct eeprom_table_record *bps = NULL;
1845 /* no bad page record, skip eeprom access */
1846 if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1849 bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1853 if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1854 control->num_recs)) {
1855 dev_err(adev->dev, "Failed to load EEPROM table records!");
1860 ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1867 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1870 struct ras_err_handler_data *data = con->eh_data;
1873 addr >>= AMDGPU_GPU_PAGE_SHIFT;
1874 for (i = 0; i < data->count; i++)
1875 if (addr == data->bps[i].retired_page)
1882 * check if an address belongs to bad page
1884 * Note: this check is only for umc block
1886 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1889 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1892 if (!con || !con->eh_data)
1895 mutex_lock(&con->recovery_lock);
1896 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1897 mutex_unlock(&con->recovery_lock);
1901 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1902 uint32_t max_length)
1904 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1905 int tmp_threshold = amdgpu_bad_page_threshold;
1909 * Justification of value bad_page_cnt_threshold in ras structure
1911 * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1912 * in eeprom, and introduce two scenarios accordingly.
1914 * Bad page retirement enablement:
1915 * - If amdgpu_bad_page_threshold = -1,
1916 * bad_page_cnt_threshold = typical value by formula.
1918 * - When the value from user is 0 < amdgpu_bad_page_threshold <
1919 * max record length in eeprom, use it directly.
1921 * Bad page retirement disablement:
1922 * - If amdgpu_bad_page_threshold = 0, bad page retirement
1923 * functionality is disabled, and bad_page_cnt_threshold will
1927 if (tmp_threshold < -1)
1929 else if (tmp_threshold > max_length)
1930 tmp_threshold = max_length;
1932 if (tmp_threshold == -1) {
1933 val = adev->gmc.mc_vram_size;
1934 do_div(val, RAS_BAD_PAGE_RATE);
1935 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1938 con->bad_page_cnt_threshold = tmp_threshold;
1942 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1944 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1945 struct ras_err_handler_data **data;
1946 uint32_t max_eeprom_records_len = 0;
1947 bool exc_err_limit = false;
1950 if (adev->ras_enabled && con)
1951 data = &con->eh_data;
1955 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1961 mutex_init(&con->recovery_lock);
1962 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1963 atomic_set(&con->in_recovery, 0);
1966 max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1967 amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1969 /* Todo: During test the SMU might fail to read the eeprom through I2C
1970 * when the GPU is pending on XGMI reset during probe time
1971 * (Mostly after second bus reset), skip it now
1973 if (adev->gmc.xgmi.pending_reset)
1975 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1977 * This calling fails when exc_err_limit is true or
1980 if (exc_err_limit || ret)
1983 if (con->eeprom_control.num_recs) {
1984 ret = amdgpu_ras_load_bad_pages(adev);
1992 kfree((*data)->bps);
1994 con->eh_data = NULL;
1996 dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1999 * Except error threshold exceeding case, other failure cases in this
2000 * function would not fail amdgpu driver init.
2010 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2012 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2013 struct ras_err_handler_data *data = con->eh_data;
2015 /* recovery_init failed to init it, fini is useless */
2019 cancel_work_sync(&con->recovery_work);
2021 mutex_lock(&con->recovery_lock);
2022 con->eh_data = NULL;
2025 mutex_unlock(&con->recovery_lock);
2031 /* return 0 if ras will reset gpu and repost.*/
2032 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2035 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2040 ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2044 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2046 return adev->asic_type == CHIP_VEGA10 ||
2047 adev->asic_type == CHIP_VEGA20 ||
2048 adev->asic_type == CHIP_ARCTURUS ||
2049 adev->asic_type == CHIP_ALDEBARAN ||
2050 adev->asic_type == CHIP_SIENNA_CICHLID;
2054 * this is workaround for vega20 workstation sku,
2055 * force enable gfx ras, ignore vbios gfx ras flag
2056 * due to GC EDC can not write
2058 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2060 struct atom_context *ctx = adev->mode_info.atom_context;
2065 if (strnstr(ctx->vbios_version, "D16406",
2066 sizeof(ctx->vbios_version)))
2067 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2071 * check hardware's ras ability which will be saved in hw_supported.
2072 * if hardware does not support ras, we can skip some ras initializtion and
2073 * forbid some ras operations from IP.
2074 * if software itself, say boot parameter, limit the ras ability. We still
2075 * need allow IP do some limited operations, like disable. In such case,
2076 * we have to initialize ras as normal. but need check if operation is
2077 * allowed or not in each function.
2079 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2081 adev->ras_hw_enabled = adev->ras_enabled = 0;
2083 if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2084 !amdgpu_ras_asic_supported(adev))
2087 if (!adev->gmc.xgmi.connected_to_cpu) {
2088 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2089 dev_info(adev->dev, "MEM ECC is active.\n");
2090 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2091 1 << AMDGPU_RAS_BLOCK__DF);
2093 dev_info(adev->dev, "MEM ECC is not presented.\n");
2096 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2097 dev_info(adev->dev, "SRAM ECC is active.\n");
2098 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2099 1 << AMDGPU_RAS_BLOCK__DF);
2101 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2104 /* driver only manages a few IP blocks RAS feature
2105 * when GPU is connected cpu through XGMI */
2106 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2107 1 << AMDGPU_RAS_BLOCK__SDMA |
2108 1 << AMDGPU_RAS_BLOCK__MMHUB);
2111 amdgpu_ras_get_quirks(adev);
2113 /* hw_supported needs to be aligned with RAS block mask. */
2114 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2116 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2117 adev->ras_hw_enabled & amdgpu_ras_mask;
2120 static void amdgpu_ras_counte_dw(struct work_struct *work)
2122 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2123 ras_counte_delay_work.work);
2124 struct amdgpu_device *adev = con->adev;
2125 struct drm_device *dev = &adev->ddev;
2126 unsigned long ce_count, ue_count;
2129 res = pm_runtime_get_sync(dev->dev);
2133 /* Cache new values.
2135 amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
2136 atomic_set(&con->ras_ce_count, ce_count);
2137 atomic_set(&con->ras_ue_count, ue_count);
2139 pm_runtime_mark_last_busy(dev->dev);
2141 pm_runtime_put_autosuspend(dev->dev);
2144 int amdgpu_ras_init(struct amdgpu_device *adev)
2146 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2152 con = kmalloc(sizeof(struct amdgpu_ras) +
2153 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2154 GFP_KERNEL|__GFP_ZERO);
2159 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2160 atomic_set(&con->ras_ce_count, 0);
2161 atomic_set(&con->ras_ue_count, 0);
2163 con->objs = (struct ras_manager *)(con + 1);
2165 amdgpu_ras_set_context(adev, con);
2167 amdgpu_ras_check_supported(adev);
2169 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2170 /* set gfx block ras context feature for VEGA20 Gaming
2171 * send ras disable cmd to ras ta during ras late init.
2173 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2174 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2184 INIT_LIST_HEAD(&con->head);
2185 /* Might need get this flag from vbios. */
2186 con->flags = RAS_DEFAULT_FLAGS;
2188 /* initialize nbio ras function ahead of any other
2189 * ras functions so hardware fatal error interrupt
2190 * can be enabled as early as possible */
2191 switch (adev->asic_type) {
2194 case CHIP_ALDEBARAN:
2195 if (!adev->gmc.xgmi.connected_to_cpu)
2196 adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2199 /* nbio ras is not available */
2203 if (adev->nbio.ras_funcs &&
2204 adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2205 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2210 if (adev->nbio.ras_funcs &&
2211 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2212 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2217 if (amdgpu_ras_fs_init(adev)) {
2222 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2223 "hardware ability[%x] ras_mask[%x]\n",
2224 adev->ras_hw_enabled, adev->ras_enabled);
2228 amdgpu_ras_set_context(adev, NULL);
2234 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2236 if (adev->gmc.xgmi.connected_to_cpu)
2241 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2242 struct ras_common_if *ras_block)
2244 struct ras_query_if info = {
2248 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2251 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2252 DRM_WARN("RAS init harvest failure");
2254 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2255 DRM_WARN("RAS init harvest reset failure");
2260 /* helper function to handle common stuff in ip late init phase */
2261 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2262 struct ras_common_if *ras_block,
2263 struct ras_fs_if *fs_info,
2264 struct ras_ih_if *ih_info)
2266 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2267 unsigned long ue_count, ce_count;
2270 /* disable RAS feature per IP block if it is not supported */
2271 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2272 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2276 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2279 /* request gpu reset. will run again */
2280 amdgpu_ras_request_reset_on_boot(adev,
2283 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2284 /* in resume phase, if fail to enable ras,
2285 * clean up all ras fs nodes, and disable ras */
2291 /* check for errors on warm reset edc persisant supported ASIC */
2292 amdgpu_persistent_edc_harvesting(adev, ras_block);
2294 /* in resume phase, no need to create ras fs node */
2295 if (adev->in_suspend || amdgpu_in_reset(adev))
2299 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2304 r = amdgpu_ras_sysfs_create(adev, fs_info);
2308 /* Those are the cached values at init.
2310 amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
2311 atomic_set(&con->ras_ce_count, ce_count);
2312 atomic_set(&con->ras_ue_count, ue_count);
2316 amdgpu_ras_sysfs_remove(adev, ras_block);
2319 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2321 amdgpu_ras_feature_enable(adev, ras_block, 0);
2325 /* helper function to remove ras fs node and interrupt handler */
2326 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2327 struct ras_common_if *ras_block,
2328 struct ras_ih_if *ih_info)
2330 if (!ras_block || !ih_info)
2333 amdgpu_ras_sysfs_remove(adev, ras_block);
2335 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2336 amdgpu_ras_feature_enable(adev, ras_block, 0);
2339 /* do some init work after IP late init as dependence.
2340 * and it runs in resume/gpu reset/booting up cases.
2342 void amdgpu_ras_resume(struct amdgpu_device *adev)
2344 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2345 struct ras_manager *obj, *tmp;
2347 if (!adev->ras_enabled || !con) {
2348 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2349 amdgpu_release_ras_context(adev);
2354 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2355 /* Set up all other IPs which are not implemented. There is a
2356 * tricky thing that IP's actual ras error type should be
2357 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2358 * ERROR_NONE make sense anyway.
2360 amdgpu_ras_enable_all_features(adev, 1);
2362 /* We enable ras on all hw_supported block, but as boot
2363 * parameter might disable some of them and one or more IP has
2364 * not implemented yet. So we disable them on behalf.
2366 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2367 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2368 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2369 /* there should be no any reference. */
2370 WARN_ON(alive_obj(obj));
2375 if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2376 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2377 /* setup ras obj state as disabled.
2378 * for init_by_vbios case.
2379 * if we want to enable ras, just enable it in a normal way.
2380 * If we want do disable it, need setup ras obj as enabled,
2381 * then issue another TA disable cmd.
2382 * See feature_enable_on_boot
2384 amdgpu_ras_disable_all_features(adev, 1);
2385 amdgpu_ras_reset_gpu(adev);
2389 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2391 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2393 if (!adev->ras_enabled || !con)
2396 amdgpu_ras_disable_all_features(adev, 0);
2397 /* Make sure all ras objects are disabled. */
2399 amdgpu_ras_disable_all_features(adev, 1);
2402 /* do some fini work before IP fini as dependence */
2403 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2405 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2407 if (!adev->ras_enabled || !con)
2411 /* Need disable ras on all IPs here before ip [hw/sw]fini */
2412 amdgpu_ras_disable_all_features(adev, 0);
2413 amdgpu_ras_recovery_fini(adev);
2417 int amdgpu_ras_fini(struct amdgpu_device *adev)
2419 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2421 if (!adev->ras_enabled || !con)
2424 amdgpu_ras_fs_fini(adev);
2425 amdgpu_ras_interrupt_remove_all(adev);
2427 WARN(con->features, "Feature mask is not cleared");
2430 amdgpu_ras_disable_all_features(adev, 1);
2432 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2434 amdgpu_ras_set_context(adev, NULL);
2440 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2442 amdgpu_ras_check_supported(adev);
2443 if (!adev->ras_hw_enabled)
2446 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2447 dev_info(adev->dev, "uncorrectable hardware error"
2448 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2450 amdgpu_ras_reset_gpu(adev);
2454 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2456 if (adev->asic_type == CHIP_VEGA20 &&
2457 adev->pm.fw_version <= 0x283400) {
2458 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2459 amdgpu_ras_intr_triggered();
2465 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2467 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2472 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2473 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2474 amdgpu_ras_set_context(adev, NULL);