drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "atom.h"
  38
  39 static const char *RAS_FS_NAME = "ras";
  40
  41 const char *ras_error_string[] = {
  42         "none",
  43         "parity",
  44         "single_correctable",
  45         "multi_uncorrectable",
  46         "poison",
  47 };
  48
  49 const char *ras_block_string[] = {
  50         "umc",
  51         "sdma",
  52         "gfx",
  53         "mmhub",
  54         "athub",
  55         "pcie_bif",
  56         "hdp",
  57         "xgmi_wafl",
  58         "df",
  59         "smn",
  60         "sem",
  61         "mp0",
  62         "mp1",
  63         "fuse",
  64 };
  65
  66 #define ras_err_str(i) (ras_error_string[ffs(i)])
  67 #define ras_block_str(i) (ras_block_string[i])
  68
  69 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  70
  71 /* inject address is 52 bits */
  72 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  73
  74 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
  75 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
  76
  77 enum amdgpu_ras_retire_page_reservation {
  78         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  79         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  80         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  81 };
  82
  83 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  84
  85 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  86                                 uint64_t addr);
  87 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  88                                 uint64_t addr);
  89
  90 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  91 {
  92         if (adev && amdgpu_ras_get_context(adev))
  93                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  94 }
  95
  96 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  97 {
  98         if (adev && amdgpu_ras_get_context(adev))
  99                 return amdgpu_ras_get_context(adev)->error_query_ready;
 100
 101         return false;
 102 }
 103
 104 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 105 {
 106         struct ras_err_data err_data = {0, 0, 0, NULL};
 107         struct eeprom_table_record err_rec;
 108
 109         if ((address >= adev->gmc.mc_vram_size) ||
 110             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 111                 dev_warn(adev->dev,
 112                          "RAS WARN: input address 0x%llx is invalid.\n",
 113                          address);
 114                 return -EINVAL;
 115         }
 116
 117         if (amdgpu_ras_check_bad_page(adev, address)) {
 118                 dev_warn(adev->dev,
 119                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 120                          address);
 121                 return 0;
 122         }
 123
 124         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 125
 126         err_rec.address = address;
 127         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 128         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 129         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 130
 131         err_data.err_addr = &err_rec;
 132         err_data.err_addr_cnt = 1;
 133
 134         if (amdgpu_bad_page_threshold != 0) {
 135                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 136                                          err_data.err_addr_cnt);
 137                 amdgpu_ras_save_bad_pages(adev);
 138         }
 139
 140         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 141         dev_warn(adev->dev, "Clear EEPROM:\n");
 142         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 143
 144         return 0;
 145 }
 146
 147 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 148                                         size_t size, loff_t *pos)
 149 {
 150         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 151         struct ras_query_if info = {
 152                 .head = obj->head,
 153         };
 154         ssize_t s;
 155         char val[128];
 156
 157         if (amdgpu_ras_query_error_status(obj->adev, &info))
 158                 return -EINVAL;
 159
 160         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 161                         "ue", info.ue_count,
 162                         "ce", info.ce_count);
 163         if (*pos >= s)
 164                 return 0;
 165
 166         s -= *pos;
 167         s = min_t(u64, s, size);
 168
 169
 170         if (copy_to_user(buf, &val[*pos], s))
 171                 return -EINVAL;
 172
 173         *pos += s;
 174
 175         return s;
 176 }
 177
 178 static const struct file_operations amdgpu_ras_debugfs_ops = {
 179         .owner = THIS_MODULE,
 180         .read = amdgpu_ras_debugfs_read,
 181         .write = NULL,
 182         .llseek = default_llseek
 183 };
 184
 185 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 186 {
 187         int i;
 188
 189         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 190                 *block_id = i;
 191                 if (strcmp(name, ras_block_str(i)) == 0)
 192                         return 0;
 193         }
 194         return -EINVAL;
 195 }
 196
 197 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 198                 const char __user *buf, size_t size,
 199                 loff_t *pos, struct ras_debug_if *data)
 200 {
 201         ssize_t s = min_t(u64, 64, size);
 202         char str[65];
 203         char block_name[33];
 204         char err[9] = "ue";
 205         int op = -1;
 206         int block_id;
 207         uint32_t sub_block;
 208         u64 address, value;
 209
 210         if (*pos)
 211                 return -EINVAL;
 212         *pos = size;
 213
 214         memset(str, 0, sizeof(str));
 215         memset(data, 0, sizeof(*data));
 216
 217         if (copy_from_user(str, buf, s))
 218                 return -EINVAL;
 219
 220         if (sscanf(str, "disable %32s", block_name) == 1)
 221                 op = 0;
 222         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 223                 op = 1;
 224         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 225                 op = 2;
 226         else if (strstr(str, "retire_page") != NULL)
 227                 op = 3;
 228         else if (str[0] && str[1] && str[2] && str[3])
 229                 /* ascii string, but commands are not matched. */
 230                 return -EINVAL;
 231
 232         if (op != -1) {
 233                 if (op == 3) {
 234                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 235                             sscanf(str, "%*s %llu", &address) != 1)
 236                                 return -EINVAL;
 237
 238                         data->op = op;
 239                         data->inject.address = address;
 240
 241                         return 0;
 242                 }
 243
 244                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 245                         return -EINVAL;
 246
 247                 data->head.block = block_id;
 248                 /* only ue and ce errors are supported */
 249                 if (!memcmp("ue", err, 2))
 250                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 251                 else if (!memcmp("ce", err, 2))
 252                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 253                 else
 254                         return -EINVAL;
 255
 256                 data->op = op;
 257
 258                 if (op == 2) {
 259                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 260                                    &sub_block, &address, &value) != 3 &&
 261                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 262                                    &sub_block, &address, &value) != 3)
 263                                 return -EINVAL;
 264                         data->head.sub_block_index = sub_block;
 265                         data->inject.address = address;
 266                         data->inject.value = value;
 267                 }
 268         } else {
 269                 if (size < sizeof(*data))
 270                         return -EINVAL;
 271
 272                 if (copy_from_user(data, buf, sizeof(*data)))
 273                         return -EINVAL;
 274         }
 275
 276         return 0;
 277 }
 278
 279 /**
 280  * DOC: AMDGPU RAS debugfs control interface
 281  *
 282  * The control interface accepts struct ras_debug_if which has two members.
 283  *
 284  * First member: ras_debug_if::head or ras_debug_if::inject.
 285  *
 286  * head is used to indicate which IP block will be under control.
 287  *
 288  * head has four members, they are block, type, sub_block_index, name.
 289  * block: which IP will be under control.
 290  * type: what kind of error will be enabled/disabled/injected.
 291  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 292  * name: the name of IP.
 293  *
 294  * inject has two more members than head, they are address, value.
 295  * As their names indicate, inject operation will write the
 296  * value to the address.
 297  *
 298  * The second member: struct ras_debug_if::op.
 299  * It has three kinds of operations.
 300  *
 301  * - 0: disable RAS on the block. Take ::head as its data.
 302  * - 1: enable RAS on the block. Take ::head as its data.
 303  * - 2: inject errors on the block. Take ::inject as its data.
 304  *
 305  * How to use the interface?
 306  *
 307  * In a program
 308  *
 309  * Copy the struct ras_debug_if in your code and initialize it.
 310  * Write the struct to the control interface.
 311  *
 312  * From shell
 313  *
 314  * .. code-block:: bash
 315  *
 316  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 317  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 318  *      echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 319  *
 320  * Where N, is the card which you want to affect.
 321  *
 322  * "disable" requires only the block.
 323  * "enable" requires the block and error type.
 324  * "inject" requires the block, error type, address, and value.
 325  *
 326  * The block is one of: umc, sdma, gfx, etc.
 327  *      see ras_block_string[] for details
 328  *
 329  * The error type is one of: ue, ce, where,
 330  *      ue is multi-uncorrectable
 331  *      ce is single-correctable
 332  *
 333  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 334  * The address and value are hexadecimal numbers, leading 0x is optional.
 335  *
 336  * For instance,
 337  *
 338  * .. code-block:: bash
 339  *
 340  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 341  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 342  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 343  *
 344  * How to check the result of the operation?
 345  *
 346  * To check disable/enable, see "ras" features at,
 347  * /sys/class/drm/card[0/1/2...]/device/ras/features
 348  *
 349  * To check inject, see the corresponding error count at,
 350  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 351  *
 352  * .. note::
 353  *      Operations are only allowed on blocks which are supported.
 354  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 355  *      to see which blocks support RAS on a particular asic.
 356  *
 357  */
 358 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 359                                              const char __user *buf,
 360                                              size_t size, loff_t *pos)
 361 {
 362         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 363         struct ras_debug_if data;
 364         int ret = 0;
 365
 366         if (!amdgpu_ras_get_error_query_ready(adev)) {
 367                 dev_warn(adev->dev, "RAS WARN: error injection "
 368                                 "currently inaccessible\n");
 369                 return size;
 370         }
 371
 372         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 373         if (ret)
 374                 return ret;
 375
 376         if (data.op == 3) {
 377                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 378                 if (!ret)
 379                         return size;
 380                 else
 381                         return ret;
 382         }
 383
 384         if (!amdgpu_ras_is_supported(adev, data.head.block))
 385                 return -EINVAL;
 386
 387         switch (data.op) {
 388         case 0:
 389                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 390                 break;
 391         case 1:
 392                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 393                 break;
 394         case 2:
 395                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 396                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 397                         dev_warn(adev->dev, "RAS WARN: input address "
 398                                         "0x%llx is invalid.",
 399                                         data.inject.address);
 400                         ret = -EINVAL;
 401                         break;
 402                 }
 403
 404                 /* umc ce/ue error injection for a bad page is not allowed */
 405                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 406                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 407                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 408                                         "as bad before error injection!\n",
 409                                         data.inject.address);
 410                         break;
 411                 }
 412
 413                 /* data.inject.address is offset instead of absolute gpu address */
 414                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 415                 break;
 416         default:
 417                 ret = -EINVAL;
 418                 break;
 419         }
 420
 421         if (ret)
 422                 return -EINVAL;
 423
 424         return size;
 425 }
 426
 427 /**
 428  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 429  *
 430  * Some boards contain an EEPROM which is used to persistently store a list of
 431  * bad pages which experiences ECC errors in vram.  This interface provides
 432  * a way to reset the EEPROM, e.g., after testing error injection.
 433  *
 434  * Usage:
 435  *
 436  * .. code-block:: bash
 437  *
 438  *      echo 1 > ../ras/ras_eeprom_reset
 439  *
 440  * will reset EEPROM table to 0 entries.
 441  *
 442  */
 443 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 444                                                const char __user *buf,
 445                                                size_t size, loff_t *pos)
 446 {
 447         struct amdgpu_device *adev =
 448                 (struct amdgpu_device *)file_inode(f)->i_private;
 449         int ret;
 450
 451         ret = amdgpu_ras_eeprom_reset_table(
 452                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 453
 454         if (ret > 0) {
 455                 /* Something was written to EEPROM.
 456                  */
 457                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 458                 return size;
 459         } else {
 460                 return ret;
 461         }
 462 }
 463
 464 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 465         .owner = THIS_MODULE,
 466         .read = NULL,
 467         .write = amdgpu_ras_debugfs_ctrl_write,
 468         .llseek = default_llseek
 469 };
 470
 471 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 472         .owner = THIS_MODULE,
 473         .read = NULL,
 474         .write = amdgpu_ras_debugfs_eeprom_write,
 475         .llseek = default_llseek
 476 };
 477
 478 /**
 479  * DOC: AMDGPU RAS sysfs Error Count Interface
 480  *
 481  * It allows the user to read the error count for each IP block on the gpu through
 482  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 483  *
 484  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 485  * (ce) error counts.
 486  *
 487  * The format of one line is below,
 488  *
 489  * [ce|ue]: count
 490  *
 491  * Example:
 492  *
 493  * .. code-block:: bash
 494  *
 495  *      ue: 0
 496  *      ce: 1
 497  *
 498  */
 499 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 500                 struct device_attribute *attr, char *buf)
 501 {
 502         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 503         struct ras_query_if info = {
 504                 .head = obj->head,
 505         };
 506
 507         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 508                 return sysfs_emit(buf, "Query currently inaccessible\n");
 509
 510         if (amdgpu_ras_query_error_status(obj->adev, &info))
 511                 return -EINVAL;
 512
 513
 514         if (obj->adev->asic_type == CHIP_ALDEBARAN) {
 515                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 516                         DRM_WARN("Failed to reset error counter and error status");
 517         }
 518
 519         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 520                           "ce", info.ce_count);
 521 }
 522
 523 /* obj begin */
 524
 525 #define get_obj(obj) do { (obj)->use++; } while (0)
 526 #define alive_obj(obj) ((obj)->use)
 527
 528 static inline void put_obj(struct ras_manager *obj)
 529 {
 530         if (obj && (--obj->use == 0))
 531                 list_del(&obj->node);
 532         if (obj && (obj->use < 0))
 533                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 534 }
 535
 536 /* make one obj and return it. */
 537 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 538                 struct ras_common_if *head)
 539 {
 540         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 541         struct ras_manager *obj;
 542
 543         if (!adev->ras_enabled || !con)
 544                 return NULL;
 545
 546         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 547                 return NULL;
 548
 549         obj = &con->objs[head->block];
 550         /* already exist. return obj? */
 551         if (alive_obj(obj))
 552                 return NULL;
 553
 554         obj->head = *head;
 555         obj->adev = adev;
 556         list_add(&obj->node, &con->head);
 557         get_obj(obj);
 558
 559         return obj;
 560 }
 561
 562 /* return an obj equal to head, or the first when head is NULL */
 563 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 564                 struct ras_common_if *head)
 565 {
 566         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 567         struct ras_manager *obj;
 568         int i;
 569
 570         if (!adev->ras_enabled || !con)
 571                 return NULL;
 572
 573         if (head) {
 574                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 575                         return NULL;
 576
 577                 obj = &con->objs[head->block];
 578
 579                 if (alive_obj(obj)) {
 580                         WARN_ON(head->block != obj->head.block);
 581                         return obj;
 582                 }
 583         } else {
 584                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 585                         obj = &con->objs[i];
 586                         if (alive_obj(obj)) {
 587                                 WARN_ON(i != obj->head.block);
 588                                 return obj;
 589                         }
 590                 }
 591         }
 592
 593         return NULL;
 594 }
 595 /* obj end */
 596
 597 /* feature ctl begin */
 598 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 599                                          struct ras_common_if *head)
 600 {
 601         return adev->ras_hw_enabled & BIT(head->block);
 602 }
 603
 604 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 605                 struct ras_common_if *head)
 606 {
 607         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 608
 609         return con->features & BIT(head->block);
 610 }
 611
 612 /*
 613  * if obj is not created, then create one.
 614  * set feature enable flag.
 615  */
 616 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 617                 struct ras_common_if *head, int enable)
 618 {
 619         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 620         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 621
 622         /* If hardware does not support ras, then do not create obj.
 623          * But if hardware support ras, we can create the obj.
 624          * Ras framework checks con->hw_supported to see if it need do
 625          * corresponding initialization.
 626          * IP checks con->support to see if it need disable ras.
 627          */
 628         if (!amdgpu_ras_is_feature_allowed(adev, head))
 629                 return 0;
 630         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 631                 return 0;
 632
 633         if (enable) {
 634                 if (!obj) {
 635                         obj = amdgpu_ras_create_obj(adev, head);
 636                         if (!obj)
 637                                 return -EINVAL;
 638                 } else {
 639                         /* In case we create obj somewhere else */
 640                         get_obj(obj);
 641                 }
 642                 con->features |= BIT(head->block);
 643         } else {
 644                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 645                         con->features &= ~BIT(head->block);
 646                         put_obj(obj);
 647                 }
 648         }
 649
 650         return 0;
 651 }
 652
 653 /* wrapper of psp_ras_enable_features */
 654 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 655                 struct ras_common_if *head, bool enable)
 656 {
 657         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 658         union ta_ras_cmd_input *info;
 659         int ret;
 660
 661         if (!con)
 662                 return -EINVAL;
 663
 664         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 665         if (!info)
 666                 return -ENOMEM;
 667
 668         if (!enable) {
 669                 info->disable_features = (struct ta_ras_disable_features_input) {
 670                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 671                         .error_type = amdgpu_ras_error_to_ta(head->type),
 672                 };
 673         } else {
 674                 info->enable_features = (struct ta_ras_enable_features_input) {
 675                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 676                         .error_type = amdgpu_ras_error_to_ta(head->type),
 677                 };
 678         }
 679
 680         /* Do not enable if it is not allowed. */
 681         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 682         /* Are we alerady in that state we are going to set? */
 683         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 684                 ret = 0;
 685                 goto out;
 686         }
 687
 688         if (!amdgpu_ras_intr_triggered()) {
 689                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 690                 if (ret) {
 691                         dev_err(adev->dev, "ras %s %s failed %d\n",
 692                                 enable ? "enable":"disable",
 693                                 ras_block_str(head->block),
 694                                 ret);
 695                         goto out;
 696                 }
 697         }
 698
 699         /* setup the obj */
 700         __amdgpu_ras_feature_enable(adev, head, enable);
 701         ret = 0;
 702 out:
 703         kfree(info);
 704         return ret;
 705 }
 706
 707 /* Only used in device probe stage and called only once. */
 708 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 709                 struct ras_common_if *head, bool enable)
 710 {
 711         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 712         int ret;
 713
 714         if (!con)
 715                 return -EINVAL;
 716
 717         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 718                 if (enable) {
 719                         /* There is no harm to issue a ras TA cmd regardless of
 720                          * the currecnt ras state.
 721                          * If current state == target state, it will do nothing
 722                          * But sometimes it requests driver to reset and repost
 723                          * with error code -EAGAIN.
 724                          */
 725                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 726                         /* With old ras TA, we might fail to enable ras.
 727                          * Log it and just setup the object.
 728                          * TODO need remove this WA in the future.
 729                          */
 730                         if (ret == -EINVAL) {
 731                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 732                                 if (!ret)
 733                                         dev_info(adev->dev,
 734                                                 "RAS INFO: %s setup object\n",
 735                                                 ras_block_str(head->block));
 736                         }
 737                 } else {
 738                         /* setup the object then issue a ras TA disable cmd.*/
 739                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 740                         if (ret)
 741                                 return ret;
 742
 743                         /* gfx block ras dsiable cmd must send to ras-ta */
 744                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 745                                 con->features |= BIT(head->block);
 746
 747                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 748
 749                         /* clean gfx block ras features flag */
 750                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 751                                 con->features &= ~BIT(head->block);
 752                 }
 753         } else
 754                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 755
 756         return ret;
 757 }
 758
 759 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 760                 bool bypass)
 761 {
 762         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 763         struct ras_manager *obj, *tmp;
 764
 765         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 766                 /* bypass psp.
 767                  * aka just release the obj and corresponding flags
 768                  */
 769                 if (bypass) {
 770                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 771                                 break;
 772                 } else {
 773                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 774                                 break;
 775                 }
 776         }
 777
 778         return con->features;
 779 }
 780
 781 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 782                 bool bypass)
 783 {
 784         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 785         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 786         int i;
 787         const enum amdgpu_ras_error_type default_ras_type =
 788                 AMDGPU_RAS_ERROR__NONE;
 789
 790         for (i = 0; i < ras_block_count; i++) {
 791                 struct ras_common_if head = {
 792                         .block = i,
 793                         .type = default_ras_type,
 794                         .sub_block_index = 0,
 795                 };
 796                 strcpy(head.name, ras_block_str(i));
 797                 if (bypass) {
 798                         /*
 799                          * bypass psp. vbios enable ras for us.
 800                          * so just create the obj
 801                          */
 802                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 803                                 break;
 804                 } else {
 805                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 806                                 break;
 807                 }
 808         }
 809
 810         return con->features;
 811 }
 812 /* feature ctl end */
 813
 814 /* query/inject/cure begin */
 815 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 816         struct ras_query_if *info)
 817 {
 818         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 819         struct ras_err_data err_data = {0, 0, 0, NULL};
 820         int i;
 821
 822         if (!obj)
 823                 return -EINVAL;
 824
 825         switch (info->head.block) {
 826         case AMDGPU_RAS_BLOCK__UMC:
 827                 if (adev->umc.ras_funcs &&
 828                     adev->umc.ras_funcs->query_ras_error_count)
 829                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 830                 /* umc query_ras_error_address is also responsible for clearing
 831                  * error status
 832                  */
 833                 if (adev->umc.ras_funcs &&
 834                     adev->umc.ras_funcs->query_ras_error_address)
 835                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 836                 break;
 837         case AMDGPU_RAS_BLOCK__SDMA:
 838                 if (adev->sdma.funcs->query_ras_error_count) {
 839                         for (i = 0; i < adev->sdma.num_instances; i++)
 840                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 841                                                                         &err_data);
 842                 }
 843                 break;
 844         case AMDGPU_RAS_BLOCK__GFX:
 845                 if (adev->gfx.ras_funcs &&
 846                     adev->gfx.ras_funcs->query_ras_error_count)
 847                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 848
 849                 if (adev->gfx.ras_funcs &&
 850                     adev->gfx.ras_funcs->query_ras_error_status)
 851                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 852                 break;
 853         case AMDGPU_RAS_BLOCK__MMHUB:
 854                 if (adev->mmhub.ras_funcs &&
 855                     adev->mmhub.ras_funcs->query_ras_error_count)
 856                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 857
 858                 if (adev->mmhub.ras_funcs &&
 859                     adev->mmhub.ras_funcs->query_ras_error_status)
 860                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 861                 break;
 862         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 863                 if (adev->nbio.ras_funcs &&
 864                     adev->nbio.ras_funcs->query_ras_error_count)
 865                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 866                 break;
 867         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 868                 if (adev->gmc.xgmi.ras_funcs &&
 869                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 870                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 871                 break;
 872         case AMDGPU_RAS_BLOCK__HDP:
 873                 if (adev->hdp.ras_funcs &&
 874                     adev->hdp.ras_funcs->query_ras_error_count)
 875                         adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
 876                 break;
 877         default:
 878                 break;
 879         }
 880
 881         obj->err_data.ue_count += err_data.ue_count;
 882         obj->err_data.ce_count += err_data.ce_count;
 883
 884         info->ue_count = obj->err_data.ue_count;
 885         info->ce_count = obj->err_data.ce_count;
 886
 887         if (err_data.ce_count) {
 888                 if (adev->smuio.funcs &&
 889                     adev->smuio.funcs->get_socket_id &&
 890                     adev->smuio.funcs->get_die_id) {
 891                         dev_info(adev->dev, "socket: %d, die: %d "
 892                                         "%ld correctable hardware errors "
 893                                         "detected in %s block, no user "
 894                                         "action is needed.\n",
 895                                         adev->smuio.funcs->get_socket_id(adev),
 896                                         adev->smuio.funcs->get_die_id(adev),
 897                                         obj->err_data.ce_count,
 898                                         ras_block_str(info->head.block));
 899                 } else {
 900                         dev_info(adev->dev, "%ld correctable hardware errors "
 901                                         "detected in %s block, no user "
 902                                         "action is needed.\n",
 903                                         obj->err_data.ce_count,
 904                                         ras_block_str(info->head.block));
 905                 }
 906         }
 907         if (err_data.ue_count) {
 908                 if (adev->smuio.funcs &&
 909                     adev->smuio.funcs->get_socket_id &&
 910                     adev->smuio.funcs->get_die_id) {
 911                         dev_info(adev->dev, "socket: %d, die: %d "
 912                                         "%ld uncorrectable hardware errors "
 913                                         "detected in %s block\n",
 914                                         adev->smuio.funcs->get_socket_id(adev),
 915                                         adev->smuio.funcs->get_die_id(adev),
 916                                         obj->err_data.ue_count,
 917                                         ras_block_str(info->head.block));
 918                 } else {
 919                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
 920                                         "detected in %s block\n",
 921                                         obj->err_data.ue_count,
 922                                         ras_block_str(info->head.block));
 923                 }
 924         }
 925
 926         return 0;
 927 }
 928
 929 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 930                 enum amdgpu_ras_block block)
 931 {
 932         if (!amdgpu_ras_is_supported(adev, block))
 933                 return -EINVAL;
 934
 935         switch (block) {
 936         case AMDGPU_RAS_BLOCK__GFX:
 937                 if (adev->gfx.ras_funcs &&
 938                     adev->gfx.ras_funcs->reset_ras_error_count)
 939                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
 940
 941                 if (adev->gfx.ras_funcs &&
 942                     adev->gfx.ras_funcs->reset_ras_error_status)
 943                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
 944                 break;
 945         case AMDGPU_RAS_BLOCK__MMHUB:
 946                 if (adev->mmhub.ras_funcs &&
 947                     adev->mmhub.ras_funcs->reset_ras_error_count)
 948                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
 949
 950                 if (adev->mmhub.ras_funcs &&
 951                     adev->mmhub.ras_funcs->reset_ras_error_status)
 952                         adev->mmhub.ras_funcs->reset_ras_error_status(adev);
 953                 break;
 954         case AMDGPU_RAS_BLOCK__SDMA:
 955                 if (adev->sdma.funcs->reset_ras_error_count)
 956                         adev->sdma.funcs->reset_ras_error_count(adev);
 957                 break;
 958         case AMDGPU_RAS_BLOCK__HDP:
 959                 if (adev->hdp.ras_funcs &&
 960                     adev->hdp.ras_funcs->reset_ras_error_count)
 961                         adev->hdp.ras_funcs->reset_ras_error_count(adev);
 962                 break;
 963         default:
 964                 break;
 965         }
 966
 967         return 0;
 968 }
 969
 970 /* Trigger XGMI/WAFL error */
 971 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 972                                  struct ta_ras_trigger_error_input *block_info)
 973 {
 974         int ret;
 975
 976         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 977                 dev_warn(adev->dev, "Failed to disallow df cstate");
 978
 979         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 980                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 981
 982         ret = psp_ras_trigger_error(&adev->psp, block_info);
 983
 984         if (amdgpu_ras_intr_triggered())
 985                 return ret;
 986
 987         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 988                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 989
 990         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 991                 dev_warn(adev->dev, "Failed to allow df cstate");
 992
 993         return ret;
 994 }
 995
 996 /* wrapper of psp_ras_trigger_error */
 997 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 998                 struct ras_inject_if *info)
 999 {
1000         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1001         struct ta_ras_trigger_error_input block_info = {
1002                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1003                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1004                 .sub_block_index = info->head.sub_block_index,
1005                 .address = info->address,
1006                 .value = info->value,
1007         };
1008         int ret = 0;
1009
1010         if (!obj)
1011                 return -EINVAL;
1012
1013         /* Calculate XGMI relative offset */
1014         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1015                 block_info.address =
1016                         amdgpu_xgmi_get_relative_phy_addr(adev,
1017                                                           block_info.address);
1018         }
1019
1020         switch (info->head.block) {
1021         case AMDGPU_RAS_BLOCK__GFX:
1022                 if (adev->gfx.ras_funcs &&
1023                     adev->gfx.ras_funcs->ras_error_inject)
1024                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1025                 else
1026                         ret = -EINVAL;
1027                 break;
1028         case AMDGPU_RAS_BLOCK__UMC:
1029         case AMDGPU_RAS_BLOCK__SDMA:
1030         case AMDGPU_RAS_BLOCK__MMHUB:
1031         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1032                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1033                 break;
1034         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1035                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1036                 break;
1037         default:
1038                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1039                          ras_block_str(info->head.block));
1040                 ret = -EINVAL;
1041         }
1042
1043         if (ret)
1044                 dev_err(adev->dev, "ras inject %s failed %d\n",
1045                         ras_block_str(info->head.block), ret);
1046
1047         return ret;
1048 }
1049
1050 /* get the total error counts on all IPs */
1051 void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1052                                   unsigned long *ce_count,
1053                                   unsigned long *ue_count)
1054 {
1055         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1056         struct ras_manager *obj;
1057         unsigned long ce, ue;
1058
1059         if (!adev->ras_enabled || !con)
1060                 return;
1061
1062         ce = 0;
1063         ue = 0;
1064         list_for_each_entry(obj, &con->head, node) {
1065                 struct ras_query_if info = {
1066                         .head = obj->head,
1067                 };
1068
1069                 if (amdgpu_ras_query_error_status(adev, &info))
1070                         return;
1071
1072                 ce += info.ce_count;
1073                 ue += info.ue_count;
1074         }
1075
1076         if (ce_count)
1077                 *ce_count = ce;
1078
1079         if (ue_count)
1080                 *ue_count = ue;
1081 }
1082 /* query/inject/cure end */
1083
1084
1085 /* sysfs begin */
1086
1087 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1088                 struct ras_badpage **bps, unsigned int *count);
1089
1090 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1091 {
1092         switch (flags) {
1093         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1094                 return "R";
1095         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1096                 return "P";
1097         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1098         default:
1099                 return "F";
1100         }
1101 }
1102
1103 /**
1104  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1105  *
1106  * It allows user to read the bad pages of vram on the gpu through
1107  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1108  *
1109  * It outputs multiple lines, and each line stands for one gpu page.
1110  *
1111  * The format of one line is below,
1112  * gpu pfn : gpu page size : flags
1113  *
1114  * gpu pfn and gpu page size are printed in hex format.
1115  * flags can be one of below character,
1116  *
1117  * R: reserved, this gpu page is reserved and not able to use.
1118  *
1119  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1120  * in next window of page_reserve.
1121  *
1122  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1123  *
1124  * Examples:
1125  *
1126  * .. code-block:: bash
1127  *
1128  *      0x00000001 : 0x00001000 : R
1129  *      0x00000002 : 0x00001000 : P
1130  *
1131  */
1132
1133 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1134                 struct kobject *kobj, struct bin_attribute *attr,
1135                 char *buf, loff_t ppos, size_t count)
1136 {
1137         struct amdgpu_ras *con =
1138                 container_of(attr, struct amdgpu_ras, badpages_attr);
1139         struct amdgpu_device *adev = con->adev;
1140         const unsigned int element_size =
1141                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1142         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1143         unsigned int end = div64_ul(ppos + count - 1, element_size);
1144         ssize_t s = 0;
1145         struct ras_badpage *bps = NULL;
1146         unsigned int bps_count = 0;
1147
1148         memset(buf, 0, count);
1149
1150         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1151                 return 0;
1152
1153         for (; start < end && start < bps_count; start++)
1154                 s += scnprintf(&buf[s], element_size + 1,
1155                                 "0x%08x : 0x%08x : %1s\n",
1156                                 bps[start].bp,
1157                                 bps[start].size,
1158                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1159
1160         kfree(bps);
1161
1162         return s;
1163 }
1164
1165 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1166                 struct device_attribute *attr, char *buf)
1167 {
1168         struct amdgpu_ras *con =
1169                 container_of(attr, struct amdgpu_ras, features_attr);
1170
1171         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1172 }
1173
1174 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1175 {
1176         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1177
1178         sysfs_remove_file_from_group(&adev->dev->kobj,
1179                                 &con->badpages_attr.attr,
1180                                 RAS_FS_NAME);
1181 }
1182
1183 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1184 {
1185         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1186         struct attribute *attrs[] = {
1187                 &con->features_attr.attr,
1188                 NULL
1189         };
1190         struct attribute_group group = {
1191                 .name = RAS_FS_NAME,
1192                 .attrs = attrs,
1193         };
1194
1195         sysfs_remove_group(&adev->dev->kobj, &group);
1196
1197         return 0;
1198 }
1199
1200 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1201                 struct ras_fs_if *head)
1202 {
1203         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1204
1205         if (!obj || obj->attr_inuse)
1206                 return -EINVAL;
1207
1208         get_obj(obj);
1209
1210         memcpy(obj->fs_data.sysfs_name,
1211                         head->sysfs_name,
1212                         sizeof(obj->fs_data.sysfs_name));
1213
1214         obj->sysfs_attr = (struct device_attribute){
1215                 .attr = {
1216                         .name = obj->fs_data.sysfs_name,
1217                         .mode = S_IRUGO,
1218                 },
1219                         .show = amdgpu_ras_sysfs_read,
1220         };
1221         sysfs_attr_init(&obj->sysfs_attr.attr);
1222
1223         if (sysfs_add_file_to_group(&adev->dev->kobj,
1224                                 &obj->sysfs_attr.attr,
1225                                 RAS_FS_NAME)) {
1226                 put_obj(obj);
1227                 return -EINVAL;
1228         }
1229
1230         obj->attr_inuse = 1;
1231
1232         return 0;
1233 }
1234
1235 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1236                 struct ras_common_if *head)
1237 {
1238         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1239
1240         if (!obj || !obj->attr_inuse)
1241                 return -EINVAL;
1242
1243         sysfs_remove_file_from_group(&adev->dev->kobj,
1244                                 &obj->sysfs_attr.attr,
1245                                 RAS_FS_NAME);
1246         obj->attr_inuse = 0;
1247         put_obj(obj);
1248
1249         return 0;
1250 }
1251
1252 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1253 {
1254         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1255         struct ras_manager *obj, *tmp;
1256
1257         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1258                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1259         }
1260
1261         if (amdgpu_bad_page_threshold != 0)
1262                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1263
1264         amdgpu_ras_sysfs_remove_feature_node(adev);
1265
1266         return 0;
1267 }
1268 /* sysfs end */
1269
1270 /**
1271  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1272  *
1273  * Normally when there is an uncorrectable error, the driver will reset
1274  * the GPU to recover.  However, in the event of an unrecoverable error,
1275  * the driver provides an interface to reboot the system automatically
1276  * in that event.
1277  *
1278  * The following file in debugfs provides that interface:
1279  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1280  *
1281  * Usage:
1282  *
1283  * .. code-block:: bash
1284  *
1285  *      echo true > .../ras/auto_reboot
1286  *
1287  */
1288 /* debugfs begin */
1289 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1290 {
1291         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1292         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1293         struct dentry     *dir;
1294
1295         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1296         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1297                             &amdgpu_ras_debugfs_ctrl_ops);
1298         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1299                             &amdgpu_ras_debugfs_eeprom_ops);
1300         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1301                            &con->bad_page_cnt_threshold);
1302         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1303         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1304
1305         /*
1306          * After one uncorrectable error happens, usually GPU recovery will
1307          * be scheduled. But due to the known problem in GPU recovery failing
1308          * to bring GPU back, below interface provides one direct way to
1309          * user to reboot system automatically in such case within
1310          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1311          * will never be called.
1312          */
1313         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1314
1315         /*
1316          * User could set this not to clean up hardware's error count register
1317          * of RAS IPs during ras recovery.
1318          */
1319         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1320                             &con->disable_ras_err_cnt_harvest);
1321         return dir;
1322 }
1323
1324 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1325                                       struct ras_fs_if *head,
1326                                       struct dentry *dir)
1327 {
1328         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1329
1330         if (!obj || !dir)
1331                 return;
1332
1333         get_obj(obj);
1334
1335         memcpy(obj->fs_data.debugfs_name,
1336                         head->debugfs_name,
1337                         sizeof(obj->fs_data.debugfs_name));
1338
1339         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1340                             obj, &amdgpu_ras_debugfs_ops);
1341 }
1342
1343 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1344 {
1345         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1346         struct dentry *dir;
1347         struct ras_manager *obj;
1348         struct ras_fs_if fs_info;
1349
1350         /*
1351          * it won't be called in resume path, no need to check
1352          * suspend and gpu reset status
1353          */
1354         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1355                 return;
1356
1357         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1358
1359         list_for_each_entry(obj, &con->head, node) {
1360                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1361                         (obj->attr_inuse == 1)) {
1362                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1363                                         ras_block_str(obj->head.block));
1364                         fs_info.head = obj->head;
1365                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1366                 }
1367         }
1368 }
1369
1370 /* debugfs end */
1371
1372 /* ras fs */
1373 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1374                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1375 static DEVICE_ATTR(features, S_IRUGO,
1376                 amdgpu_ras_sysfs_features_read, NULL);
1377 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1378 {
1379         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1380         struct attribute_group group = {
1381                 .name = RAS_FS_NAME,
1382         };
1383         struct attribute *attrs[] = {
1384                 &con->features_attr.attr,
1385                 NULL
1386         };
1387         struct bin_attribute *bin_attrs[] = {
1388                 NULL,
1389                 NULL,
1390         };
1391         int r;
1392
1393         /* add features entry */
1394         con->features_attr = dev_attr_features;
1395         group.attrs = attrs;
1396         sysfs_attr_init(attrs[0]);
1397
1398         if (amdgpu_bad_page_threshold != 0) {
1399                 /* add bad_page_features entry */
1400                 bin_attr_gpu_vram_bad_pages.private = NULL;
1401                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1402                 bin_attrs[0] = &con->badpages_attr;
1403                 group.bin_attrs = bin_attrs;
1404                 sysfs_bin_attr_init(bin_attrs[0]);
1405         }
1406
1407         r = sysfs_create_group(&adev->dev->kobj, &group);
1408         if (r)
1409                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1410
1411         return 0;
1412 }
1413
1414 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1415 {
1416         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1417         struct ras_manager *con_obj, *ip_obj, *tmp;
1418
1419         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1420                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1421                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1422                         if (ip_obj)
1423                                 put_obj(ip_obj);
1424                 }
1425         }
1426
1427         amdgpu_ras_sysfs_remove_all(adev);
1428         return 0;
1429 }
1430 /* ras fs end */
1431
1432 /* ih begin */
1433 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1434 {
1435         struct ras_ih_data *data = &obj->ih_data;
1436         struct amdgpu_iv_entry entry;
1437         int ret;
1438         struct ras_err_data err_data = {0, 0, 0, NULL};
1439
1440         while (data->rptr != data->wptr) {
1441                 rmb();
1442                 memcpy(&entry, &data->ring[data->rptr],
1443                                 data->element_size);
1444
1445                 wmb();
1446                 data->rptr = (data->aligned_element_size +
1447                                 data->rptr) % data->ring_size;
1448
1449                 /* Let IP handle its data, maybe we need get the output
1450                  * from the callback to udpate the error type/count, etc
1451                  */
1452                 if (data->cb) {
1453                         ret = data->cb(obj->adev, &err_data, &entry);
1454                         /* ue will trigger an interrupt, and in that case
1455                          * we need do a reset to recovery the whole system.
1456                          * But leave IP do that recovery, here we just dispatch
1457                          * the error.
1458                          */
1459                         if (ret == AMDGPU_RAS_SUCCESS) {
1460                                 /* these counts could be left as 0 if
1461                                  * some blocks do not count error number
1462                                  */
1463                                 obj->err_data.ue_count += err_data.ue_count;
1464                                 obj->err_data.ce_count += err_data.ce_count;
1465                         }
1466                 }
1467         }
1468 }
1469
1470 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1471 {
1472         struct ras_ih_data *data =
1473                 container_of(work, struct ras_ih_data, ih_work);
1474         struct ras_manager *obj =
1475                 container_of(data, struct ras_manager, ih_data);
1476
1477         amdgpu_ras_interrupt_handler(obj);
1478 }
1479
1480 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1481                 struct ras_dispatch_if *info)
1482 {
1483         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1484         struct ras_ih_data *data = &obj->ih_data;
1485
1486         if (!obj)
1487                 return -EINVAL;
1488
1489         if (data->inuse == 0)
1490                 return 0;
1491
1492         /* Might be overflow... */
1493         memcpy(&data->ring[data->wptr], info->entry,
1494                         data->element_size);
1495
1496         wmb();
1497         data->wptr = (data->aligned_element_size +
1498                         data->wptr) % data->ring_size;
1499
1500         schedule_work(&data->ih_work);
1501
1502         return 0;
1503 }
1504
1505 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1506                 struct ras_ih_if *info)
1507 {
1508         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1509         struct ras_ih_data *data;
1510
1511         if (!obj)
1512                 return -EINVAL;
1513
1514         data = &obj->ih_data;
1515         if (data->inuse == 0)
1516                 return 0;
1517
1518         cancel_work_sync(&data->ih_work);
1519
1520         kfree(data->ring);
1521         memset(data, 0, sizeof(*data));
1522         put_obj(obj);
1523
1524         return 0;
1525 }
1526
1527 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1528                 struct ras_ih_if *info)
1529 {
1530         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1531         struct ras_ih_data *data;
1532
1533         if (!obj) {
1534                 /* in case we registe the IH before enable ras feature */
1535                 obj = amdgpu_ras_create_obj(adev, &info->head);
1536                 if (!obj)
1537                         return -EINVAL;
1538         } else
1539                 get_obj(obj);
1540
1541         data = &obj->ih_data;
1542         /* add the callback.etc */
1543         *data = (struct ras_ih_data) {
1544                 .inuse = 0,
1545                 .cb = info->cb,
1546                 .element_size = sizeof(struct amdgpu_iv_entry),
1547                 .rptr = 0,
1548                 .wptr = 0,
1549         };
1550
1551         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1552
1553         data->aligned_element_size = ALIGN(data->element_size, 8);
1554         /* the ring can store 64 iv entries. */
1555         data->ring_size = 64 * data->aligned_element_size;
1556         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1557         if (!data->ring) {
1558                 put_obj(obj);
1559                 return -ENOMEM;
1560         }
1561
1562         /* IH is ready */
1563         data->inuse = 1;
1564
1565         return 0;
1566 }
1567
1568 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1569 {
1570         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1571         struct ras_manager *obj, *tmp;
1572
1573         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1574                 struct ras_ih_if info = {
1575                         .head = obj->head,
1576                 };
1577                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1578         }
1579
1580         return 0;
1581 }
1582 /* ih end */
1583
1584 /* traversal all IPs except NBIO to query error counter */
1585 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1586 {
1587         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1588         struct ras_manager *obj;
1589
1590         if (!adev->ras_enabled || !con)
1591                 return;
1592
1593         list_for_each_entry(obj, &con->head, node) {
1594                 struct ras_query_if info = {
1595                         .head = obj->head,
1596                 };
1597
1598                 /*
1599                  * PCIE_BIF IP has one different isr by ras controller
1600                  * interrupt, the specific ras counter query will be
1601                  * done in that isr. So skip such block from common
1602                  * sync flood interrupt isr calling.
1603                  */
1604                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1605                         continue;
1606
1607                 amdgpu_ras_query_error_status(adev, &info);
1608         }
1609 }
1610
1611 /* Parse RdRspStatus and WrRspStatus */
1612 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1613                                           struct ras_query_if *info)
1614 {
1615         /*
1616          * Only two block need to query read/write
1617          * RspStatus at current state
1618          */
1619         switch (info->head.block) {
1620         case AMDGPU_RAS_BLOCK__GFX:
1621                 if (adev->gfx.ras_funcs &&
1622                     adev->gfx.ras_funcs->query_ras_error_status)
1623                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1624                 break;
1625         case AMDGPU_RAS_BLOCK__MMHUB:
1626                 if (adev->mmhub.ras_funcs &&
1627                     adev->mmhub.ras_funcs->query_ras_error_status)
1628                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1629                 break;
1630         default:
1631                 break;
1632         }
1633 }
1634
1635 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1636 {
1637         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1638         struct ras_manager *obj;
1639
1640         if (!adev->ras_enabled || !con)
1641                 return;
1642
1643         list_for_each_entry(obj, &con->head, node) {
1644                 struct ras_query_if info = {
1645                         .head = obj->head,
1646                 };
1647
1648                 amdgpu_ras_error_status_query(adev, &info);
1649         }
1650 }
1651
1652 /* recovery begin */
1653
1654 /* return 0 on success.
1655  * caller need free bps.
1656  */
1657 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1658                 struct ras_badpage **bps, unsigned int *count)
1659 {
1660         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1661         struct ras_err_handler_data *data;
1662         int i = 0;
1663         int ret = 0, status;
1664
1665         if (!con || !con->eh_data || !bps || !count)
1666                 return -EINVAL;
1667
1668         mutex_lock(&con->recovery_lock);
1669         data = con->eh_data;
1670         if (!data || data->count == 0) {
1671                 *bps = NULL;
1672                 ret = -EINVAL;
1673                 goto out;
1674         }
1675
1676         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1677         if (!*bps) {
1678                 ret = -ENOMEM;
1679                 goto out;
1680         }
1681
1682         for (; i < data->count; i++) {
1683                 (*bps)[i] = (struct ras_badpage){
1684                         .bp = data->bps[i].retired_page,
1685                         .size = AMDGPU_GPU_PAGE_SIZE,
1686                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1687                 };
1688                 status = amdgpu_vram_mgr_query_page_status(
1689                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1690                                 data->bps[i].retired_page);
1691                 if (status == -EBUSY)
1692                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1693                 else if (status == -ENOENT)
1694                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1695         }
1696
1697         *count = data->count;
1698 out:
1699         mutex_unlock(&con->recovery_lock);
1700         return ret;
1701 }
1702
1703 static void amdgpu_ras_do_recovery(struct work_struct *work)
1704 {
1705         struct amdgpu_ras *ras =
1706                 container_of(work, struct amdgpu_ras, recovery_work);
1707         struct amdgpu_device *remote_adev = NULL;
1708         struct amdgpu_device *adev = ras->adev;
1709         struct list_head device_list, *device_list_handle =  NULL;
1710
1711         if (!ras->disable_ras_err_cnt_harvest) {
1712                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1713
1714                 /* Build list of devices to query RAS related errors */
1715                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1716                         device_list_handle = &hive->device_list;
1717                 } else {
1718                         INIT_LIST_HEAD(&device_list);
1719                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1720                         device_list_handle = &device_list;
1721                 }
1722
1723                 list_for_each_entry(remote_adev,
1724                                 device_list_handle, gmc.xgmi.head) {
1725                         amdgpu_ras_query_err_status(remote_adev);
1726                         amdgpu_ras_log_on_err_counter(remote_adev);
1727                 }
1728
1729                 amdgpu_put_xgmi_hive(hive);
1730         }
1731
1732         if (amdgpu_device_should_recover_gpu(ras->adev))
1733                 amdgpu_device_gpu_recover(ras->adev, NULL);
1734         atomic_set(&ras->in_recovery, 0);
1735 }
1736
1737 /* alloc/realloc bps array */
1738 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1739                 struct ras_err_handler_data *data, int pages)
1740 {
1741         unsigned int old_space = data->count + data->space_left;
1742         unsigned int new_space = old_space + pages;
1743         unsigned int align_space = ALIGN(new_space, 512);
1744         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1745
1746         if (!bps) {
1747                 kfree(bps);
1748                 return -ENOMEM;
1749         }
1750
1751         if (data->bps) {
1752                 memcpy(bps, data->bps,
1753                                 data->count * sizeof(*data->bps));
1754                 kfree(data->bps);
1755         }
1756
1757         data->bps = bps;
1758         data->space_left += align_space - old_space;
1759         return 0;
1760 }
1761
1762 /* it deal with vram only. */
1763 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1764                 struct eeprom_table_record *bps, int pages)
1765 {
1766         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1767         struct ras_err_handler_data *data;
1768         int ret = 0;
1769         uint32_t i;
1770
1771         if (!con || !con->eh_data || !bps || pages <= 0)
1772                 return 0;
1773
1774         mutex_lock(&con->recovery_lock);
1775         data = con->eh_data;
1776         if (!data)
1777                 goto out;
1778
1779         for (i = 0; i < pages; i++) {
1780                 if (amdgpu_ras_check_bad_page_unlock(con,
1781                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1782                         continue;
1783
1784                 if (!data->space_left &&
1785                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1786                         ret = -ENOMEM;
1787                         goto out;
1788                 }
1789
1790                 amdgpu_vram_mgr_reserve_range(
1791                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1792                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1793                         AMDGPU_GPU_PAGE_SIZE);
1794
1795                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1796                 data->count++;
1797                 data->space_left--;
1798         }
1799 out:
1800         mutex_unlock(&con->recovery_lock);
1801
1802         return ret;
1803 }
1804
1805 /*
1806  * write error record array to eeprom, the function should be
1807  * protected by recovery_lock
1808  */
1809 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1810 {
1811         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1812         struct ras_err_handler_data *data;
1813         struct amdgpu_ras_eeprom_control *control;
1814         int save_count;
1815
1816         if (!con || !con->eh_data)
1817                 return 0;
1818
1819         control = &con->eeprom_control;
1820         data = con->eh_data;
1821         save_count = data->count - control->num_recs;
1822         /* only new entries are saved */
1823         if (save_count > 0) {
1824                 if (amdgpu_ras_eeprom_write(control,
1825                                             &data->bps[control->num_recs],
1826                                             save_count)) {
1827                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1828                         return -EIO;
1829                 }
1830
1831                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1832         }
1833
1834         return 0;
1835 }
1836
1837 /*
1838  * read error record array in eeprom and reserve enough space for
1839  * storing new bad pages
1840  */
1841 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1842 {
1843         struct amdgpu_ras_eeprom_control *control =
1844                 &adev->psp.ras.ras->eeprom_control;
1845         struct eeprom_table_record *bps;
1846         int ret;
1847
1848         /* no bad page record, skip eeprom access */
1849         if (control->num_recs == 0 || amdgpu_bad_page_threshold == 0)
1850                 return 0;
1851
1852         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1853         if (!bps)
1854                 return -ENOMEM;
1855
1856         ret = amdgpu_ras_eeprom_read(control, bps, control->num_recs);
1857         if (ret)
1858                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1859         else
1860                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1861
1862         kfree(bps);
1863         return ret;
1864 }
1865
1866 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1867                                 uint64_t addr)
1868 {
1869         struct ras_err_handler_data *data = con->eh_data;
1870         int i;
1871
1872         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1873         for (i = 0; i < data->count; i++)
1874                 if (addr == data->bps[i].retired_page)
1875                         return true;
1876
1877         return false;
1878 }
1879
1880 /*
1881  * check if an address belongs to bad page
1882  *
1883  * Note: this check is only for umc block
1884  */
1885 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1886                                 uint64_t addr)
1887 {
1888         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1889         bool ret = false;
1890
1891         if (!con || !con->eh_data)
1892                 return ret;
1893
1894         mutex_lock(&con->recovery_lock);
1895         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1896         mutex_unlock(&con->recovery_lock);
1897         return ret;
1898 }
1899
1900 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1901                                           uint32_t max_count)
1902 {
1903         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1904
1905         /*
1906          * Justification of value bad_page_cnt_threshold in ras structure
1907          *
1908          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1909          * in eeprom, and introduce two scenarios accordingly.
1910          *
1911          * Bad page retirement enablement:
1912          *    - If amdgpu_bad_page_threshold = -1,
1913          *      bad_page_cnt_threshold = typical value by formula.
1914          *
1915          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1916          *      max record length in eeprom, use it directly.
1917          *
1918          * Bad page retirement disablement:
1919          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1920          *      functionality is disabled, and bad_page_cnt_threshold will
1921          *      take no effect.
1922          */
1923
1924         if (amdgpu_bad_page_threshold < 0) {
1925                 u64 val = adev->gmc.mc_vram_size;
1926
1927                 do_div(val, RAS_BAD_PAGE_COVER);
1928                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1929                                                   max_count);
1930         } else {
1931                 con->bad_page_cnt_threshold = min_t(int, max_count,
1932                                                     amdgpu_bad_page_threshold);
1933         }
1934 }
1935
1936 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1937 {
1938         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1939         struct ras_err_handler_data **data;
1940         u32  max_eeprom_records_count = 0;
1941         bool exc_err_limit = false;
1942         int ret;
1943
1944         if (adev->ras_enabled && con)
1945                 data = &con->eh_data;
1946         else
1947                 return 0;
1948
1949         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1950         if (!*data) {
1951                 ret = -ENOMEM;
1952                 goto out;
1953         }
1954
1955         mutex_init(&con->recovery_lock);
1956         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1957         atomic_set(&con->in_recovery, 0);
1958         con->adev = adev;
1959
1960         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
1961         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
1962
1963         /* Todo: During test the SMU might fail to read the eeprom through I2C
1964          * when the GPU is pending on XGMI reset during probe time
1965          * (Mostly after second bus reset), skip it now
1966          */
1967         if (adev->gmc.xgmi.pending_reset)
1968                 return 0;
1969         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1970         /*
1971          * This calling fails when exc_err_limit is true or
1972          * ret != 0.
1973          */
1974         if (exc_err_limit || ret)
1975                 goto free;
1976
1977         if (con->eeprom_control.num_recs) {
1978                 ret = amdgpu_ras_load_bad_pages(adev);
1979                 if (ret)
1980                         goto free;
1981
1982                 if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
1983                         adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
1984         }
1985
1986         return 0;
1987
1988 free:
1989         kfree((*data)->bps);
1990         kfree(*data);
1991         con->eh_data = NULL;
1992 out:
1993         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
1994
1995         /*
1996          * Except error threshold exceeding case, other failure cases in this
1997          * function would not fail amdgpu driver init.
1998          */
1999         if (!exc_err_limit)
2000                 ret = 0;
2001         else
2002                 ret = -EINVAL;
2003
2004         return ret;
2005 }
2006
2007 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2008 {
2009         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2010         struct ras_err_handler_data *data = con->eh_data;
2011
2012         /* recovery_init failed to init it, fini is useless */
2013         if (!data)
2014                 return 0;
2015
2016         cancel_work_sync(&con->recovery_work);
2017
2018         mutex_lock(&con->recovery_lock);
2019         con->eh_data = NULL;
2020         kfree(data->bps);
2021         kfree(data);
2022         mutex_unlock(&con->recovery_lock);
2023
2024         return 0;
2025 }
2026 /* recovery end */
2027
2028 /* return 0 if ras will reset gpu and repost.*/
2029 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2030                 unsigned int block)
2031 {
2032         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2033
2034         if (!ras)
2035                 return -EINVAL;
2036
2037         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2038         return 0;
2039 }
2040
2041 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2042 {
2043         return adev->asic_type == CHIP_VEGA10 ||
2044                 adev->asic_type == CHIP_VEGA20 ||
2045                 adev->asic_type == CHIP_ARCTURUS ||
2046                 adev->asic_type == CHIP_ALDEBARAN ||
2047                 adev->asic_type == CHIP_SIENNA_CICHLID;
2048 }
2049
2050 /*
2051  * this is workaround for vega20 workstation sku,
2052  * force enable gfx ras, ignore vbios gfx ras flag
2053  * due to GC EDC can not write
2054  */
2055 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2056 {
2057         struct atom_context *ctx = adev->mode_info.atom_context;
2058
2059         if (!ctx)
2060                 return;
2061
2062         if (strnstr(ctx->vbios_version, "D16406",
2063                     sizeof(ctx->vbios_version)) ||
2064                 strnstr(ctx->vbios_version, "D36002",
2065                         sizeof(ctx->vbios_version)))
2066                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2067 }
2068
2069 /*
2070  * check hardware's ras ability which will be saved in hw_supported.
2071  * if hardware does not support ras, we can skip some ras initializtion and
2072  * forbid some ras operations from IP.
2073  * if software itself, say boot parameter, limit the ras ability. We still
2074  * need allow IP do some limited operations, like disable. In such case,
2075  * we have to initialize ras as normal. but need check if operation is
2076  * allowed or not in each function.
2077  */
2078 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2079 {
2080         adev->ras_hw_enabled = adev->ras_enabled = 0;
2081
2082         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2083             !amdgpu_ras_asic_supported(adev))
2084                 return;
2085
2086         if (!adev->gmc.xgmi.connected_to_cpu) {
2087                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2088                         dev_info(adev->dev, "MEM ECC is active.\n");
2089                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2090                                                    1 << AMDGPU_RAS_BLOCK__DF);
2091                 } else {
2092                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2093                 }
2094
2095                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2096                         dev_info(adev->dev, "SRAM ECC is active.\n");
2097                         adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2098                                                     1 << AMDGPU_RAS_BLOCK__DF);
2099                 } else {
2100                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2101                 }
2102         } else {
2103                 /* driver only manages a few IP blocks RAS feature
2104                  * when GPU is connected cpu through XGMI */
2105                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2106                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2107                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2108         }
2109
2110         amdgpu_ras_get_quirks(adev);
2111
2112         /* hw_supported needs to be aligned with RAS block mask. */
2113         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2114
2115         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2116                 adev->ras_hw_enabled & amdgpu_ras_mask;
2117 }
2118
2119 static void amdgpu_ras_counte_dw(struct work_struct *work)
2120 {
2121         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2122                                               ras_counte_delay_work.work);
2123         struct amdgpu_device *adev = con->adev;
2124         struct drm_device *dev = adev_to_drm(adev);
2125         unsigned long ce_count, ue_count;
2126         int res;
2127
2128         res = pm_runtime_get_sync(dev->dev);
2129         if (res < 0)
2130                 goto Out;
2131
2132         /* Cache new values.
2133          */
2134         amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
2135         atomic_set(&con->ras_ce_count, ce_count);
2136         atomic_set(&con->ras_ue_count, ue_count);
2137
2138         pm_runtime_mark_last_busy(dev->dev);
2139 Out:
2140         pm_runtime_put_autosuspend(dev->dev);
2141 }
2142
2143 int amdgpu_ras_init(struct amdgpu_device *adev)
2144 {
2145         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2146         int r;
2147
2148         if (con)
2149                 return 0;
2150
2151         con = kmalloc(sizeof(struct amdgpu_ras) +
2152                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2153                         GFP_KERNEL|__GFP_ZERO);
2154         if (!con)
2155                 return -ENOMEM;
2156
2157         con->adev = adev;
2158         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2159         atomic_set(&con->ras_ce_count, 0);
2160         atomic_set(&con->ras_ue_count, 0);
2161
2162         con->objs = (struct ras_manager *)(con + 1);
2163
2164         amdgpu_ras_set_context(adev, con);
2165
2166         amdgpu_ras_check_supported(adev);
2167
2168         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2169                 /* set gfx block ras context feature for VEGA20 Gaming
2170                  * send ras disable cmd to ras ta during ras late init.
2171                  */
2172                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2173                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2174
2175                         return 0;
2176                 }
2177
2178                 r = 0;
2179                 goto release_con;
2180         }
2181
2182         con->features = 0;
2183         INIT_LIST_HEAD(&con->head);
2184         /* Might need get this flag from vbios. */
2185         con->flags = RAS_DEFAULT_FLAGS;
2186
2187         /* initialize nbio ras function ahead of any other
2188          * ras functions so hardware fatal error interrupt
2189          * can be enabled as early as possible */
2190         switch (adev->asic_type) {
2191         case CHIP_VEGA20:
2192         case CHIP_ARCTURUS:
2193         case CHIP_ALDEBARAN:
2194                 if (!adev->gmc.xgmi.connected_to_cpu)
2195                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2196                 break;
2197         default:
2198                 /* nbio ras is not available */
2199                 break;
2200         }
2201
2202         if (adev->nbio.ras_funcs &&
2203             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2204                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2205                 if (r)
2206                         goto release_con;
2207         }
2208
2209         if (adev->nbio.ras_funcs &&
2210             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2211                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2212                 if (r)
2213                         goto release_con;
2214         }
2215
2216         if (amdgpu_ras_fs_init(adev)) {
2217                 r = -EINVAL;
2218                 goto release_con;
2219         }
2220
2221         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2222                  "hardware ability[%x] ras_mask[%x]\n",
2223                  adev->ras_hw_enabled, adev->ras_enabled);
2224
2225         return 0;
2226 release_con:
2227         amdgpu_ras_set_context(adev, NULL);
2228         kfree(con);
2229
2230         return r;
2231 }
2232
2233 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2234 {
2235         if (adev->gmc.xgmi.connected_to_cpu)
2236                 return 1;
2237         return 0;
2238 }
2239
2240 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2241                                         struct ras_common_if *ras_block)
2242 {
2243         struct ras_query_if info = {
2244                 .head = *ras_block,
2245         };
2246
2247         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2248                 return 0;
2249
2250         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2251                 DRM_WARN("RAS init harvest failure");
2252
2253         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2254                 DRM_WARN("RAS init harvest reset failure");
2255
2256         return 0;
2257 }
2258
2259 /* helper function to handle common stuff in ip late init phase */
2260 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2261                          struct ras_common_if *ras_block,
2262                          struct ras_fs_if *fs_info,
2263                          struct ras_ih_if *ih_info)
2264 {
2265         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2266         unsigned long ue_count, ce_count;
2267         int r;
2268
2269         /* disable RAS feature per IP block if it is not supported */
2270         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2271                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2272                 return 0;
2273         }
2274
2275         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2276         if (r) {
2277                 if (r == -EAGAIN) {
2278                         /* request gpu reset. will run again */
2279                         amdgpu_ras_request_reset_on_boot(adev,
2280                                         ras_block->block);
2281                         return 0;
2282                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2283                         /* in resume phase, if fail to enable ras,
2284                          * clean up all ras fs nodes, and disable ras */
2285                         goto cleanup;
2286                 } else
2287                         return r;
2288         }
2289
2290         /* check for errors on warm reset edc persisant supported ASIC */
2291         amdgpu_persistent_edc_harvesting(adev, ras_block);
2292
2293         /* in resume phase, no need to create ras fs node */
2294         if (adev->in_suspend || amdgpu_in_reset(adev))
2295                 return 0;
2296
2297         if (ih_info->cb) {
2298                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2299                 if (r)
2300                         goto interrupt;
2301         }
2302
2303         r = amdgpu_ras_sysfs_create(adev, fs_info);
2304         if (r)
2305                 goto sysfs;
2306
2307         /* Those are the cached values at init.
2308          */
2309         amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
2310         atomic_set(&con->ras_ce_count, ce_count);
2311         atomic_set(&con->ras_ue_count, ue_count);
2312
2313         return 0;
2314 cleanup:
2315         amdgpu_ras_sysfs_remove(adev, ras_block);
2316 sysfs:
2317         if (ih_info->cb)
2318                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2319 interrupt:
2320         amdgpu_ras_feature_enable(adev, ras_block, 0);
2321         return r;
2322 }
2323
2324 /* helper function to remove ras fs node and interrupt handler */
2325 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2326                           struct ras_common_if *ras_block,
2327                           struct ras_ih_if *ih_info)
2328 {
2329         if (!ras_block || !ih_info)
2330                 return;
2331
2332         amdgpu_ras_sysfs_remove(adev, ras_block);
2333         if (ih_info->cb)
2334                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2335         amdgpu_ras_feature_enable(adev, ras_block, 0);
2336 }
2337
2338 /* do some init work after IP late init as dependence.
2339  * and it runs in resume/gpu reset/booting up cases.
2340  */
2341 void amdgpu_ras_resume(struct amdgpu_device *adev)
2342 {
2343         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2344         struct ras_manager *obj, *tmp;
2345
2346         if (!adev->ras_enabled || !con) {
2347                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2348                 amdgpu_release_ras_context(adev);
2349
2350                 return;
2351         }
2352
2353         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2354                 /* Set up all other IPs which are not implemented. There is a
2355                  * tricky thing that IP's actual ras error type should be
2356                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2357                  * ERROR_NONE make sense anyway.
2358                  */
2359                 amdgpu_ras_enable_all_features(adev, 1);
2360
2361                 /* We enable ras on all hw_supported block, but as boot
2362                  * parameter might disable some of them and one or more IP has
2363                  * not implemented yet. So we disable them on behalf.
2364                  */
2365                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2366                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2367                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2368                                 /* there should be no any reference. */
2369                                 WARN_ON(alive_obj(obj));
2370                         }
2371                 }
2372         }
2373
2374         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2375                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2376                 /* setup ras obj state as disabled.
2377                  * for init_by_vbios case.
2378                  * if we want to enable ras, just enable it in a normal way.
2379                  * If we want do disable it, need setup ras obj as enabled,
2380                  * then issue another TA disable cmd.
2381                  * See feature_enable_on_boot
2382                  */
2383                 amdgpu_ras_disable_all_features(adev, 1);
2384                 amdgpu_ras_reset_gpu(adev);
2385         }
2386 }
2387
2388 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2389 {
2390         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2391
2392         if (!adev->ras_enabled || !con)
2393                 return;
2394
2395         amdgpu_ras_disable_all_features(adev, 0);
2396         /* Make sure all ras objects are disabled. */
2397         if (con->features)
2398                 amdgpu_ras_disable_all_features(adev, 1);
2399 }
2400
2401 /* do some fini work before IP fini as dependence */
2402 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2403 {
2404         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2405
2406         if (!adev->ras_enabled || !con)
2407                 return 0;
2408
2409
2410         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2411         amdgpu_ras_disable_all_features(adev, 0);
2412         amdgpu_ras_recovery_fini(adev);
2413         return 0;
2414 }
2415
2416 int amdgpu_ras_fini(struct amdgpu_device *adev)
2417 {
2418         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2419
2420         if (!adev->ras_enabled || !con)
2421                 return 0;
2422
2423         amdgpu_ras_fs_fini(adev);
2424         amdgpu_ras_interrupt_remove_all(adev);
2425
2426         WARN(con->features, "Feature mask is not cleared");
2427
2428         if (con->features)
2429                 amdgpu_ras_disable_all_features(adev, 1);
2430
2431         cancel_delayed_work_sync(&con->ras_counte_delay_work);
2432
2433         amdgpu_ras_set_context(adev, NULL);
2434         kfree(con);
2435
2436         return 0;
2437 }
2438
2439 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2440 {
2441         amdgpu_ras_check_supported(adev);
2442         if (!adev->ras_hw_enabled)
2443                 return;
2444
2445         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2446                 dev_info(adev->dev, "uncorrectable hardware error"
2447                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2448
2449                 amdgpu_ras_reset_gpu(adev);
2450         }
2451 }
2452
2453 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2454 {
2455         if (adev->asic_type == CHIP_VEGA20 &&
2456             adev->pm.fw_version <= 0x283400) {
2457                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2458                                 amdgpu_ras_intr_triggered();
2459         }
2460
2461         return false;
2462 }
2463
2464 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2465 {
2466         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2467
2468         if (!con)
2469                 return;
2470
2471         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2472                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2473                 amdgpu_ras_set_context(adev, NULL);
2474                 kfree(con);
2475         }
2476 }