2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
30 #include "amdgpu_ras.h"
31 #include "amdgpu_atomfirmware.h"
34 /* interrupt bottom half */
35 struct work_struct ih_work;
41 unsigned int ring_size;
42 unsigned int element_size;
43 unsigned int aligned_element_size;
50 char debugfs_name[32];
54 unsigned long ue_count;
55 unsigned long ce_count;
58 struct ras_err_handler_data {
59 /* point to bad pages array */
64 /* the count of entries */
66 /* the space can place new entries */
68 /* last reserved entry's index + 1 */
73 struct ras_common_if head;
77 struct list_head node;
79 struct amdgpu_device *adev;
83 struct device_attribute sysfs_attr;
87 struct ras_fs_data fs_data;
90 struct ras_ih_data ih_data;
92 struct ras_err_data err_data;
101 const char *ras_error_string[] = {
104 "single_correctable",
105 "multi_uncorrectable",
109 const char *ras_block_string[] = {
126 #define ras_err_str(i) (ras_error_string[ffs(i)])
127 #define ras_block_str(i) (ras_block_string[i])
129 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1
130 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2
131 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
133 static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
134 uint64_t offset, uint64_t size,
135 struct amdgpu_bo **bo_ptr);
136 static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
137 struct amdgpu_bo **bo_ptr);
139 static void amdgpu_ras_self_test(struct amdgpu_device *adev)
144 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
145 size_t size, loff_t *pos)
147 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
148 struct ras_query_if info = {
154 if (amdgpu_ras_error_query(obj->adev, &info))
157 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
159 "ce", info.ce_count);
164 s = min_t(u64, s, size);
167 if (copy_to_user(buf, &val[*pos], s))
175 static const struct file_operations amdgpu_ras_debugfs_ops = {
176 .owner = THIS_MODULE,
177 .read = amdgpu_ras_debugfs_read,
179 .llseek = default_llseek
182 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
186 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
188 if (strcmp(name, ras_block_str(i)) == 0)
194 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
195 const char __user *buf, size_t size,
196 loff_t *pos, struct ras_debug_if *data)
198 ssize_t s = min_t(u64, 64, size);
210 memset(str, 0, sizeof(str));
211 memset(data, 0, sizeof(*data));
213 if (copy_from_user(str, buf, s))
216 if (sscanf(str, "disable %32s", block_name) == 1)
218 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
220 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
222 else if (str[0] && str[1] && str[2] && str[3])
223 /* ascii string, but commands are not matched. */
227 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
230 data->head.block = block_id;
231 data->head.type = memcmp("ue", err, 2) == 0 ?
232 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE :
233 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
237 if (sscanf(str, "%*s %*s %*s %llu %llu",
238 &address, &value) != 2)
239 if (sscanf(str, "%*s %*s %*s 0x%llx 0x%llx",
240 &address, &value) != 2)
242 data->inject.address = address;
243 data->inject.value = value;
246 if (size < sizeof(*data))
249 if (copy_from_user(data, buf, sizeof(*data)))
256 * DOC: AMDGPU RAS debugfs control interface
258 * It accepts struct ras_debug_if who has two members.
260 * First member: ras_debug_if::head or ras_debug_if::inject.
262 * head is used to indicate which IP block will be under control.
264 * head has four members, they are block, type, sub_block_index, name.
265 * block: which IP will be under control.
266 * type: what kind of error will be enabled/disabled/injected.
267 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
268 * name: the name of IP.
270 * inject has two more members than head, they are address, value.
271 * As their names indicate, inject operation will write the
272 * value to the address.
274 * Second member: struct ras_debug_if::op.
275 * It has three kinds of operations.
276 * 0: disable RAS on the block. Take ::head as its data.
277 * 1: enable RAS on the block. Take ::head as its data.
278 * 2: inject errors on the block. Take ::inject as its data.
280 * How to use the interface?
282 * copy the struct ras_debug_if in your codes and initialize it.
283 * write the struct to the control node.
286 * echo op block [error [address value]] > .../ras/ras_ctrl
287 * op: disable, enable, inject
288 * disable: only block is needed
289 * enable: block and error are needed
290 * inject: error, address, value are needed
291 * block: umc, smda, gfx, .........
292 * see ras_block_string[] for details
294 * ue: multi_uncorrectable
295 * ce: single_correctable
297 * here are some examples for bash commands,
298 * echo inject umc ue 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
299 * echo inject umc ce 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
300 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
302 * How to check the result?
304 * For disable/enable, please check ras features at
305 * /sys/class/drm/card[0/1/2...]/device/ras/features
307 * For inject, please check corresponding err count at
308 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
310 * NOTE: operation is only allowed on blocks which are supported.
311 * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
313 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
314 size_t size, loff_t *pos)
316 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
317 struct ras_debug_if data;
318 struct amdgpu_bo *bo;
321 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
325 if (!amdgpu_ras_is_supported(adev, data.head.block))
330 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
333 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
336 ret = amdgpu_ras_reserve_vram(adev,
337 data.inject.address, PAGE_SIZE, &bo);
339 /* address was offset, now it is absolute.*/
340 data.inject.address += adev->gmc.vram_start;
341 if (data.inject.address > adev->gmc.vram_end)
344 data.inject.address = amdgpu_bo_gpu_offset(bo);
345 ret = amdgpu_ras_error_inject(adev, &data.inject);
346 amdgpu_ras_release_vram(adev, &bo);
359 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
360 .owner = THIS_MODULE,
362 .write = amdgpu_ras_debugfs_ctrl_write,
363 .llseek = default_llseek
366 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
367 struct device_attribute *attr, char *buf)
369 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
370 struct ras_query_if info = {
374 if (amdgpu_ras_error_query(obj->adev, &info))
377 return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
379 "ce", info.ce_count);
384 #define get_obj(obj) do { (obj)->use++; } while (0)
385 #define alive_obj(obj) ((obj)->use)
387 static inline void put_obj(struct ras_manager *obj)
389 if (obj && --obj->use == 0)
390 list_del(&obj->node);
391 if (obj && obj->use < 0) {
392 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
396 /* make one obj and return it. */
397 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
398 struct ras_common_if *head)
400 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
401 struct ras_manager *obj;
406 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
409 obj = &con->objs[head->block];
410 /* already exist. return obj? */
416 list_add(&obj->node, &con->head);
422 /* return an obj equal to head, or the first when head is NULL */
423 static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
424 struct ras_common_if *head)
426 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
427 struct ras_manager *obj;
434 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
437 obj = &con->objs[head->block];
439 if (alive_obj(obj)) {
440 WARN_ON(head->block != obj->head.block);
444 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
446 if (alive_obj(obj)) {
447 WARN_ON(i != obj->head.block);
457 /* feature ctl begin */
458 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
459 struct ras_common_if *head)
461 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
463 return con->hw_supported & BIT(head->block);
466 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
467 struct ras_common_if *head)
469 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
471 return con->features & BIT(head->block);
475 * if obj is not created, then create one.
476 * set feature enable flag.
478 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
479 struct ras_common_if *head, int enable)
481 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
482 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
484 /* If hardware does not support ras, then do not create obj.
485 * But if hardware support ras, we can create the obj.
486 * Ras framework checks con->hw_supported to see if it need do
487 * corresponding initialization.
488 * IP checks con->support to see if it need disable ras.
490 if (!amdgpu_ras_is_feature_allowed(adev, head))
492 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
497 obj = amdgpu_ras_create_obj(adev, head);
501 /* In case we create obj somewhere else */
504 con->features |= BIT(head->block);
506 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
507 con->features &= ~BIT(head->block);
515 /* wrapper of psp_ras_enable_features */
516 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
517 struct ras_common_if *head, bool enable)
519 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
520 union ta_ras_cmd_input info;
527 info.disable_features = (struct ta_ras_disable_features_input) {
528 .block_id = amdgpu_ras_block_to_ta(head->block),
529 .error_type = amdgpu_ras_error_to_ta(head->type),
532 info.enable_features = (struct ta_ras_enable_features_input) {
533 .block_id = amdgpu_ras_block_to_ta(head->block),
534 .error_type = amdgpu_ras_error_to_ta(head->type),
538 /* Do not enable if it is not allowed. */
539 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
540 /* Are we alerady in that state we are going to set? */
541 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
544 ret = psp_ras_enable_features(&adev->psp, &info, enable);
546 DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
547 enable ? "enable":"disable",
548 ras_block_str(head->block),
550 if (ret == TA_RAS_STATUS__RESET_NEEDED)
556 __amdgpu_ras_feature_enable(adev, head, enable);
561 /* Only used in device probe stage and called only once. */
562 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
563 struct ras_common_if *head, bool enable)
565 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
571 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
573 /* There is no harm to issue a ras TA cmd regardless of
574 * the currecnt ras state.
575 * If current state == target state, it will do nothing
576 * But sometimes it requests driver to reset and repost
577 * with error code -EAGAIN.
579 ret = amdgpu_ras_feature_enable(adev, head, 1);
580 /* With old ras TA, we might fail to enable ras.
581 * Log it and just setup the object.
582 * TODO need remove this WA in the future.
584 if (ret == -EINVAL) {
585 ret = __amdgpu_ras_feature_enable(adev, head, 1);
587 DRM_INFO("RAS INFO: %s setup object\n",
588 ras_block_str(head->block));
591 /* setup the object then issue a ras TA disable cmd.*/
592 ret = __amdgpu_ras_feature_enable(adev, head, 1);
596 ret = amdgpu_ras_feature_enable(adev, head, 0);
599 ret = amdgpu_ras_feature_enable(adev, head, enable);
604 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
607 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
608 struct ras_manager *obj, *tmp;
610 list_for_each_entry_safe(obj, tmp, &con->head, node) {
612 * aka just release the obj and corresponding flags
615 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
618 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
623 return con->features;
626 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
629 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
630 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
632 const enum amdgpu_ras_error_type default_ras_type =
633 AMDGPU_RAS_ERROR__NONE;
635 for (i = 0; i < ras_block_count; i++) {
636 struct ras_common_if head = {
638 .type = default_ras_type,
639 .sub_block_index = 0,
641 strcpy(head.name, ras_block_str(i));
644 * bypass psp. vbios enable ras for us.
645 * so just create the obj
647 if (__amdgpu_ras_feature_enable(adev, &head, 1))
650 if (amdgpu_ras_feature_enable(adev, &head, 1))
655 return con->features;
657 /* feature ctl end */
659 /* query/inject/cure begin */
660 int amdgpu_ras_error_query(struct amdgpu_device *adev,
661 struct ras_query_if *info)
663 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
667 /* TODO might read the register to read the count */
669 info->ue_count = obj->err_data.ue_count;
670 info->ce_count = obj->err_data.ce_count;
675 /* wrapper of psp_ras_trigger_error */
676 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
677 struct ras_inject_if *info)
679 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
680 struct ta_ras_trigger_error_input block_info = {
681 .block_id = amdgpu_ras_block_to_ta(info->head.block),
682 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
683 .sub_block_index = info->head.sub_block_index,
684 .address = info->address,
685 .value = info->value,
692 ret = psp_ras_trigger_error(&adev->psp, &block_info);
694 DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
695 ras_block_str(info->head.block),
701 int amdgpu_ras_error_cure(struct amdgpu_device *adev,
702 struct ras_cure_if *info)
704 /* psp fw has no cure interface for now. */
708 /* get the total error counts on all IPs */
709 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
712 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
713 struct ras_manager *obj;
714 struct ras_err_data data = {0, 0};
719 list_for_each_entry(obj, &con->head, node) {
720 struct ras_query_if info = {
724 if (amdgpu_ras_error_query(adev, &info))
727 data.ce_count += info.ce_count;
728 data.ue_count += info.ue_count;
731 return is_ce ? data.ce_count : data.ue_count;
733 /* query/inject/cure end */
738 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
739 struct ras_badpage **bps, unsigned int *count);
741 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
755 * DOC: ras sysfs gpu_vram_bad_pages interface
757 * It allows user to read the bad pages of vram on the gpu through
758 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
760 * It outputs multiple lines, and each line stands for one gpu page.
762 * The format of one line is below,
763 * gpu pfn : gpu page size : flags
765 * gpu pfn and gpu page size are printed in hex format.
766 * flags can be one of below character,
767 * R: reserved, this gpu page is reserved and not able to use.
768 * P: pending for reserve, this gpu page is marked as bad, will be reserved
769 * in next window of page_reserve.
770 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
773 * 0x00000001 : 0x00001000 : R
774 * 0x00000002 : 0x00001000 : P
777 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
778 struct kobject *kobj, struct bin_attribute *attr,
779 char *buf, loff_t ppos, size_t count)
781 struct amdgpu_ras *con =
782 container_of(attr, struct amdgpu_ras, badpages_attr);
783 struct amdgpu_device *adev = con->adev;
784 const unsigned int element_size =
785 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
786 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
787 unsigned int end = div64_ul(ppos + count - 1, element_size);
789 struct ras_badpage *bps = NULL;
790 unsigned int bps_count = 0;
792 memset(buf, 0, count);
794 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
797 for (; start < end && start < bps_count; start++)
798 s += scnprintf(&buf[s], element_size + 1,
799 "0x%08x : 0x%08x : %1s\n",
802 amdgpu_ras_badpage_flags_str(bps[start].flags));
809 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
810 struct device_attribute *attr, char *buf)
812 struct amdgpu_ras *con =
813 container_of(attr, struct amdgpu_ras, features_attr);
814 struct drm_device *ddev = dev_get_drvdata(dev);
815 struct amdgpu_device *adev = ddev->dev_private;
816 struct ras_common_if head;
817 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
820 struct ras_manager *obj;
822 s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
824 for (i = 0; i < ras_block_count; i++) {
827 if (amdgpu_ras_is_feature_enabled(adev, &head)) {
828 obj = amdgpu_ras_find_obj(adev, &head);
829 s += scnprintf(&buf[s], PAGE_SIZE - s,
832 ras_err_str(obj->head.type));
834 s += scnprintf(&buf[s], PAGE_SIZE - s,
842 static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev)
844 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
845 struct attribute *attrs[] = {
846 &con->features_attr.attr,
849 struct bin_attribute *bin_attrs[] = {
853 struct attribute_group group = {
856 .bin_attrs = bin_attrs,
859 con->features_attr = (struct device_attribute) {
864 .show = amdgpu_ras_sysfs_features_read,
867 con->badpages_attr = (struct bin_attribute) {
869 .name = "gpu_vram_bad_pages",
874 .read = amdgpu_ras_sysfs_badpages_read,
877 sysfs_attr_init(attrs[0]);
878 sysfs_bin_attr_init(bin_attrs[0]);
880 return sysfs_create_group(&adev->dev->kobj, &group);
883 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
885 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
886 struct attribute *attrs[] = {
887 &con->features_attr.attr,
890 struct bin_attribute *bin_attrs[] = {
894 struct attribute_group group = {
897 .bin_attrs = bin_attrs,
900 sysfs_remove_group(&adev->dev->kobj, &group);
905 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
906 struct ras_fs_if *head)
908 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
910 if (!obj || obj->attr_inuse)
915 memcpy(obj->fs_data.sysfs_name,
917 sizeof(obj->fs_data.sysfs_name));
919 obj->sysfs_attr = (struct device_attribute){
921 .name = obj->fs_data.sysfs_name,
924 .show = amdgpu_ras_sysfs_read,
926 sysfs_attr_init(&obj->sysfs_attr.attr);
928 if (sysfs_add_file_to_group(&adev->dev->kobj,
929 &obj->sysfs_attr.attr,
940 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
941 struct ras_common_if *head)
943 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
945 if (!obj || !obj->attr_inuse)
948 sysfs_remove_file_from_group(&adev->dev->kobj,
949 &obj->sysfs_attr.attr,
957 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
959 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
960 struct ras_manager *obj, *tmp;
962 list_for_each_entry_safe(obj, tmp, &con->head, node) {
963 amdgpu_ras_sysfs_remove(adev, &obj->head);
966 amdgpu_ras_sysfs_remove_feature_node(adev);
973 static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
975 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
976 struct drm_minor *minor = adev->ddev->primary;
978 con->dir = debugfs_create_dir("ras", minor->debugfs_root);
979 con->ent = debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
980 adev, &amdgpu_ras_debugfs_ctrl_ops);
983 void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
984 struct ras_fs_if *head)
986 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
987 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
989 if (!obj || obj->ent)
994 memcpy(obj->fs_data.debugfs_name,
996 sizeof(obj->fs_data.debugfs_name));
998 obj->ent = debugfs_create_file(obj->fs_data.debugfs_name,
999 S_IWUGO | S_IRUGO, con->dir, obj,
1000 &amdgpu_ras_debugfs_ops);
1003 void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
1004 struct ras_common_if *head)
1006 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1008 if (!obj || !obj->ent)
1011 debugfs_remove(obj->ent);
1016 static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
1018 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1019 struct ras_manager *obj, *tmp;
1021 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1022 amdgpu_ras_debugfs_remove(adev, &obj->head);
1025 debugfs_remove(con->ent);
1026 debugfs_remove(con->dir);
1034 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1036 amdgpu_ras_sysfs_create_feature_node(adev);
1037 amdgpu_ras_debugfs_create_ctrl_node(adev);
1042 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1044 amdgpu_ras_debugfs_remove_all(adev);
1045 amdgpu_ras_sysfs_remove_all(adev);
1051 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1053 struct ras_ih_data *data = &obj->ih_data;
1054 struct amdgpu_iv_entry entry;
1057 while (data->rptr != data->wptr) {
1059 memcpy(&entry, &data->ring[data->rptr],
1060 data->element_size);
1063 data->rptr = (data->aligned_element_size +
1064 data->rptr) % data->ring_size;
1066 /* Let IP handle its data, maybe we need get the output
1067 * from the callback to udpate the error type/count, etc
1070 ret = data->cb(obj->adev, &entry);
1071 /* ue will trigger an interrupt, and in that case
1072 * we need do a reset to recovery the whole system.
1073 * But leave IP do that recovery, here we just dispatch
1076 if (ret == AMDGPU_RAS_UE) {
1077 obj->err_data.ue_count++;
1079 /* Might need get ce count by register, but not all IP
1080 * saves ce count, some IP just use one bit or two bits
1081 * to indicate ce happened.
1087 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1089 struct ras_ih_data *data =
1090 container_of(work, struct ras_ih_data, ih_work);
1091 struct ras_manager *obj =
1092 container_of(data, struct ras_manager, ih_data);
1094 amdgpu_ras_interrupt_handler(obj);
1097 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1098 struct ras_dispatch_if *info)
1100 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1101 struct ras_ih_data *data = &obj->ih_data;
1106 if (data->inuse == 0)
1109 /* Might be overflow... */
1110 memcpy(&data->ring[data->wptr], info->entry,
1111 data->element_size);
1114 data->wptr = (data->aligned_element_size +
1115 data->wptr) % data->ring_size;
1117 schedule_work(&data->ih_work);
1122 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1123 struct ras_ih_if *info)
1125 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1126 struct ras_ih_data *data;
1131 data = &obj->ih_data;
1132 if (data->inuse == 0)
1135 cancel_work_sync(&data->ih_work);
1138 memset(data, 0, sizeof(*data));
1144 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1145 struct ras_ih_if *info)
1147 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1148 struct ras_ih_data *data;
1151 /* in case we registe the IH before enable ras feature */
1152 obj = amdgpu_ras_create_obj(adev, &info->head);
1158 data = &obj->ih_data;
1159 /* add the callback.etc */
1160 *data = (struct ras_ih_data) {
1163 .element_size = sizeof(struct amdgpu_iv_entry),
1168 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1170 data->aligned_element_size = ALIGN(data->element_size, 8);
1171 /* the ring can store 64 iv entries. */
1172 data->ring_size = 64 * data->aligned_element_size;
1173 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1185 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1187 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1188 struct ras_manager *obj, *tmp;
1190 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1191 struct ras_ih_if info = {
1194 amdgpu_ras_interrupt_remove_handler(adev, &info);
1201 /* recovery begin */
1203 /* return 0 on success.
1204 * caller need free bps.
1206 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1207 struct ras_badpage **bps, unsigned int *count)
1209 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1210 struct ras_err_handler_data *data;
1214 if (!con || !con->eh_data || !bps || !count)
1217 mutex_lock(&con->recovery_lock);
1218 data = con->eh_data;
1219 if (!data || data->count == 0) {
1224 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1230 for (; i < data->count; i++) {
1231 (*bps)[i] = (struct ras_badpage){
1232 .bp = data->bps[i].bp,
1233 .size = AMDGPU_GPU_PAGE_SIZE,
1237 if (data->last_reserved <= i)
1238 (*bps)[i].flags = 1;
1239 else if (data->bps[i].bo == NULL)
1240 (*bps)[i].flags = 2;
1243 *count = data->count;
1245 mutex_unlock(&con->recovery_lock);
1249 static void amdgpu_ras_do_recovery(struct work_struct *work)
1251 struct amdgpu_ras *ras =
1252 container_of(work, struct amdgpu_ras, recovery_work);
1254 amdgpu_device_gpu_recover(ras->adev, 0);
1255 atomic_set(&ras->in_recovery, 0);
1258 static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
1259 struct amdgpu_bo **bo_ptr)
1261 /* no need to free it actually. */
1262 amdgpu_bo_free_kernel(bo_ptr, NULL, NULL);
1266 /* reserve vram with size@offset */
1267 static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
1268 uint64_t offset, uint64_t size,
1269 struct amdgpu_bo **bo_ptr)
1271 struct ttm_operation_ctx ctx = { false, false };
1272 struct amdgpu_bo_param bp;
1275 struct amdgpu_bo *bo;
1279 memset(&bp, 0, sizeof(bp));
1281 bp.byte_align = PAGE_SIZE;
1282 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1283 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1284 AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1285 bp.type = ttm_bo_type_kernel;
1288 r = amdgpu_bo_create(adev, &bp, &bo);
1292 r = amdgpu_bo_reserve(bo, false);
1296 offset = ALIGN(offset, PAGE_SIZE);
1297 for (i = 0; i < bo->placement.num_placement; ++i) {
1298 bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1299 bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1302 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1303 r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx);
1307 r = amdgpu_bo_pin_restricted(bo,
1308 AMDGPU_GEM_DOMAIN_VRAM,
1317 amdgpu_bo_unreserve(bo);
1321 amdgpu_bo_unreserve(bo);
1323 amdgpu_bo_unref(&bo);
1327 /* alloc/realloc bps array */
1328 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1329 struct ras_err_handler_data *data, int pages)
1331 unsigned int old_space = data->count + data->space_left;
1332 unsigned int new_space = old_space + pages;
1333 unsigned int align_space = ALIGN(new_space, 1024);
1334 void *tmp = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1340 memcpy(tmp, data->bps,
1341 data->count * sizeof(*data->bps));
1346 data->space_left += align_space - old_space;
1350 /* it deal with vram only. */
1351 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1352 unsigned long *bps, int pages)
1354 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1355 struct ras_err_handler_data *data;
1359 if (!con || !con->eh_data || !bps || pages <= 0)
1362 mutex_lock(&con->recovery_lock);
1363 data = con->eh_data;
1367 if (data->space_left <= pages)
1368 if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
1374 data->bps[data->count++].bp = bps[i];
1376 data->space_left -= pages;
1378 mutex_unlock(&con->recovery_lock);
1383 /* called in gpu recovery/init */
1384 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
1386 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1387 struct ras_err_handler_data *data;
1389 struct amdgpu_bo *bo;
1392 if (!con || !con->eh_data)
1395 mutex_lock(&con->recovery_lock);
1396 data = con->eh_data;
1399 /* reserve vram at driver post stage. */
1400 for (i = data->last_reserved; i < data->count; i++) {
1401 bp = data->bps[i].bp;
1403 if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
1405 DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
1407 data->bps[i].bo = bo;
1408 data->last_reserved = i + 1;
1411 mutex_unlock(&con->recovery_lock);
1415 /* called when driver unload */
1416 static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
1418 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1419 struct ras_err_handler_data *data;
1420 struct amdgpu_bo *bo;
1423 if (!con || !con->eh_data)
1426 mutex_lock(&con->recovery_lock);
1427 data = con->eh_data;
1431 for (i = data->last_reserved - 1; i >= 0; i--) {
1432 bo = data->bps[i].bo;
1434 amdgpu_ras_release_vram(adev, &bo);
1436 data->bps[i].bo = bo;
1437 data->last_reserved = i;
1440 mutex_unlock(&con->recovery_lock);
1444 static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1447 * write the array to eeprom when SMU disabled.
1452 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1455 * read the array to eeprom when SMU disabled.
1460 static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1462 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1463 struct ras_err_handler_data **data = &con->eh_data;
1465 *data = kmalloc(sizeof(**data),
1466 GFP_KERNEL|__GFP_ZERO);
1470 mutex_init(&con->recovery_lock);
1471 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1472 atomic_set(&con->in_recovery, 0);
1475 amdgpu_ras_load_bad_pages(adev);
1476 amdgpu_ras_reserve_bad_pages(adev);
1481 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1483 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1484 struct ras_err_handler_data *data = con->eh_data;
1486 cancel_work_sync(&con->recovery_work);
1487 amdgpu_ras_save_bad_pages(adev);
1488 amdgpu_ras_release_bad_pages(adev);
1490 mutex_lock(&con->recovery_lock);
1491 con->eh_data = NULL;
1494 mutex_unlock(&con->recovery_lock);
1500 /* return 0 if ras will reset gpu and repost.*/
1501 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1504 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1509 ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1514 * check hardware's ras ability which will be saved in hw_supported.
1515 * if hardware does not support ras, we can skip some ras initializtion and
1516 * forbid some ras operations from IP.
1517 * if software itself, say boot parameter, limit the ras ability. We still
1518 * need allow IP do some limited operations, like disable. In such case,
1519 * we have to initialize ras as normal. but need check if operation is
1520 * allowed or not in each function.
1522 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1523 uint32_t *hw_supported, uint32_t *supported)
1528 if (amdgpu_sriov_vf(adev) ||
1529 adev->asic_type != CHIP_VEGA20)
1532 if (adev->is_atom_fw &&
1533 (amdgpu_atomfirmware_mem_ecc_supported(adev) ||
1534 amdgpu_atomfirmware_sram_ecc_supported(adev)))
1535 *hw_supported = AMDGPU_RAS_BLOCK_MASK;
1537 *supported = amdgpu_ras_enable == 0 ?
1538 0 : *hw_supported & amdgpu_ras_mask;
1541 int amdgpu_ras_init(struct amdgpu_device *adev)
1543 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1548 con = kmalloc(sizeof(struct amdgpu_ras) +
1549 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1550 GFP_KERNEL|__GFP_ZERO);
1554 con->objs = (struct ras_manager *)(con + 1);
1556 amdgpu_ras_set_context(adev, con);
1558 amdgpu_ras_check_supported(adev, &con->hw_supported,
1561 INIT_LIST_HEAD(&con->head);
1562 /* Might need get this flag from vbios. */
1563 con->flags = RAS_DEFAULT_FLAGS;
1565 if (amdgpu_ras_recovery_init(adev))
1568 amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
1570 if (amdgpu_ras_fs_init(adev))
1573 amdgpu_ras_self_test(adev);
1575 DRM_INFO("RAS INFO: ras initialized successfully, "
1576 "hardware ability[%x] ras_mask[%x]\n",
1577 con->hw_supported, con->supported);
1580 amdgpu_ras_recovery_fini(adev);
1582 amdgpu_ras_set_context(adev, NULL);
1588 /* do some init work after IP late init as dependence.
1589 * and it runs in resume/gpu reset/booting up cases.
1591 void amdgpu_ras_resume(struct amdgpu_device *adev)
1593 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1594 struct ras_manager *obj, *tmp;
1599 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
1600 /* Set up all other IPs which are not implemented. There is a
1601 * tricky thing that IP's actual ras error type should be
1602 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
1603 * ERROR_NONE make sense anyway.
1605 amdgpu_ras_enable_all_features(adev, 1);
1607 /* We enable ras on all hw_supported block, but as boot
1608 * parameter might disable some of them and one or more IP has
1609 * not implemented yet. So we disable them on behalf.
1611 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1612 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
1613 amdgpu_ras_feature_enable(adev, &obj->head, 0);
1614 /* there should be no any reference. */
1615 WARN_ON(alive_obj(obj));
1620 if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
1621 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1622 /* setup ras obj state as disabled.
1623 * for init_by_vbios case.
1624 * if we want to enable ras, just enable it in a normal way.
1625 * If we want do disable it, need setup ras obj as enabled,
1626 * then issue another TA disable cmd.
1627 * See feature_enable_on_boot
1629 amdgpu_ras_disable_all_features(adev, 1);
1630 amdgpu_ras_reset_gpu(adev, 0);
1634 void amdgpu_ras_suspend(struct amdgpu_device *adev)
1636 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1641 amdgpu_ras_disable_all_features(adev, 0);
1642 /* Make sure all ras objects are disabled. */
1644 amdgpu_ras_disable_all_features(adev, 1);
1647 /* do some fini work before IP fini as dependence */
1648 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
1650 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1655 /* Need disable ras on all IPs here before ip [hw/sw]fini */
1656 amdgpu_ras_disable_all_features(adev, 0);
1657 amdgpu_ras_recovery_fini(adev);
1661 int amdgpu_ras_fini(struct amdgpu_device *adev)
1663 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1668 amdgpu_ras_fs_fini(adev);
1669 amdgpu_ras_interrupt_remove_all(adev);
1671 WARN(con->features, "Feature mask is not cleared");
1674 amdgpu_ras_disable_all_features(adev, 1);
1676 amdgpu_ras_set_context(adev, NULL);