drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25 #ifndef __AMDGPU_PSP_H__
  26 #define __AMDGPU_PSP_H__
  27
  28 #include "amdgpu.h"
  29 #include "psp_gfx_if.h"
  30 #include "ta_xgmi_if.h"
  31 #include "ta_ras_if.h"
  32 #include "ta_rap_if.h"
  33
  34 #define PSP_FENCE_BUFFER_SIZE   0x1000
  35 #define PSP_CMD_BUFFER_SIZE     0x1000
  36 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
  37 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
  38 #define PSP_1_MEG               0x100000
  39 #define PSP_TMR_SIZE    0x400000
  40 #define PSP_HDCP_SHARED_MEM_SIZE        0x4000
  41 #define PSP_DTM_SHARED_MEM_SIZE 0x4000
  42 #define PSP_RAP_SHARED_MEM_SIZE 0x4000
  43 #define PSP_SHARED_MEM_SIZE             0x4000
  44 #define PSP_FW_NAME_LEN         0x24
  45
  46 struct psp_context;
  47 struct psp_xgmi_node_info;
  48 struct psp_xgmi_topology_info;
  49
  50 enum psp_bootloader_cmd {
  51         PSP_BL__LOAD_SYSDRV             = 0x10000,
  52         PSP_BL__LOAD_SOSDRV             = 0x20000,
  53         PSP_BL__LOAD_KEY_DATABASE       = 0x80000,
  54         PSP_BL__DRAM_LONG_TRAIN         = 0x100000,
  55         PSP_BL__DRAM_SHORT_TRAIN        = 0x200000,
  56         PSP_BL__LOAD_TOS_SPL_TABLE      = 0x10000000,
  57 };
  58
  59 enum psp_ring_type
  60 {
  61         PSP_RING_TYPE__INVALID = 0,
  62         /*
  63          * These values map to the way the PSP kernel identifies the
  64          * rings.
  65          */
  66         PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
  67         PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
  68 };
  69
  70 struct psp_ring
  71 {
  72         enum psp_ring_type              ring_type;
  73         struct psp_gfx_rb_frame         *ring_mem;
  74         uint64_t                        ring_mem_mc_addr;
  75         void                            *ring_mem_handle;
  76         uint32_t                        ring_size;
  77 };
  78
  79 /* More registers may will be supported */
  80 enum psp_reg_prog_id {
  81         PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
  82         PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
  83         PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
  84         PSP_REG_LAST
  85 };
  86
  87 struct psp_funcs
  88 {
  89         int (*init_microcode)(struct psp_context *psp);
  90         int (*bootloader_load_kdb)(struct psp_context *psp);
  91         int (*bootloader_load_spl)(struct psp_context *psp);
  92         int (*bootloader_load_sysdrv)(struct psp_context *psp);
  93         int (*bootloader_load_sos)(struct psp_context *psp);
  94         int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
  95         int (*ring_create)(struct psp_context *psp,
  96                            enum psp_ring_type ring_type);
  97         int (*ring_stop)(struct psp_context *psp,
  98                             enum psp_ring_type ring_type);
  99         int (*ring_destroy)(struct psp_context *psp,
 100                             enum psp_ring_type ring_type);
 101         bool (*smu_reload_quirk)(struct psp_context *psp);
 102         int (*mode1_reset)(struct psp_context *psp);
 103         int (*mem_training)(struct psp_context *psp, uint32_t ops);
 104         uint32_t (*ring_get_wptr)(struct psp_context *psp);
 105         void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
 106         int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr);
 107         int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
 108 };
 109
 110 #define AMDGPU_XGMI_MAX_CONNECTED_NODES         64
 111 struct psp_xgmi_node_info {
 112         uint64_t                                node_id;
 113         uint8_t                                 num_hops;
 114         uint8_t                                 is_sharing_enabled;
 115         enum ta_xgmi_assigned_sdma_engine       sdma_engine;
 116 };
 117
 118 struct psp_xgmi_topology_info {
 119         uint32_t                        num_nodes;
 120         struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 121 };
 122
 123 struct psp_asd_context {
 124         bool                    asd_initialized;
 125         uint32_t                session_id;
 126 };
 127
 128 struct psp_xgmi_context {
 129         uint8_t                         initialized;
 130         uint32_t                        session_id;
 131         struct amdgpu_bo                *xgmi_shared_bo;
 132         uint64_t                        xgmi_shared_mc_addr;
 133         void                            *xgmi_shared_buf;
 134         struct psp_xgmi_topology_info   top_info;
 135 };
 136
 137 struct psp_ras_context {
 138         /*ras fw*/
 139         bool                    ras_initialized;
 140         uint32_t                session_id;
 141         struct amdgpu_bo        *ras_shared_bo;
 142         uint64_t                ras_shared_mc_addr;
 143         void                    *ras_shared_buf;
 144         struct amdgpu_ras       *ras;
 145 };
 146
 147 struct psp_hdcp_context {
 148         bool                    hdcp_initialized;
 149         uint32_t                session_id;
 150         struct amdgpu_bo        *hdcp_shared_bo;
 151         uint64_t                hdcp_shared_mc_addr;
 152         void                    *hdcp_shared_buf;
 153         struct mutex            mutex;
 154 };
 155
 156 struct psp_dtm_context {
 157         bool                    dtm_initialized;
 158         uint32_t                session_id;
 159         struct amdgpu_bo        *dtm_shared_bo;
 160         uint64_t                dtm_shared_mc_addr;
 161         void                    *dtm_shared_buf;
 162         struct mutex            mutex;
 163 };
 164
 165 struct psp_rap_context {
 166         bool                    rap_initialized;
 167         uint32_t                session_id;
 168         struct amdgpu_bo        *rap_shared_bo;
 169         uint64_t                rap_shared_mc_addr;
 170         void                    *rap_shared_buf;
 171         struct mutex            mutex;
 172 };
 173
 174 #define MEM_TRAIN_SYSTEM_SIGNATURE              0x54534942
 175 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES   0x1000
 176 #define GDDR6_MEM_TRAINING_OFFSET               0x8000
 177 /*Define the VRAM size that will be encroached by BIST training.*/
 178 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE      0x2000000
 179
 180 enum psp_memory_training_init_flag {
 181         PSP_MEM_TRAIN_NOT_SUPPORT       = 0x0,
 182         PSP_MEM_TRAIN_SUPPORT           = 0x1,
 183         PSP_MEM_TRAIN_INIT_FAILED       = 0x2,
 184         PSP_MEM_TRAIN_RESERVE_SUCCESS   = 0x4,
 185         PSP_MEM_TRAIN_INIT_SUCCESS      = 0x8,
 186 };
 187
 188 enum psp_memory_training_ops {
 189         PSP_MEM_TRAIN_SEND_LONG_MSG     = 0x1,
 190         PSP_MEM_TRAIN_SAVE              = 0x2,
 191         PSP_MEM_TRAIN_RESTORE           = 0x4,
 192         PSP_MEM_TRAIN_SEND_SHORT_MSG    = 0x8,
 193         PSP_MEM_TRAIN_COLD_BOOT         = PSP_MEM_TRAIN_SEND_LONG_MSG,
 194         PSP_MEM_TRAIN_RESUME            = PSP_MEM_TRAIN_SEND_SHORT_MSG,
 195 };
 196
 197 struct psp_memory_training_context {
 198         /*training data size*/
 199         u64 train_data_size;
 200         /*
 201          * sys_cache
 202          * cpu virtual address
 203          * system memory buffer that used to store the training data.
 204          */
 205         void *sys_cache;
 206
 207         /*vram offset of the p2c training data*/
 208         u64 p2c_train_data_offset;
 209
 210         /*vram offset of the c2p training data*/
 211         u64 c2p_train_data_offset;
 212         struct amdgpu_bo *c2p_bo;
 213
 214         enum psp_memory_training_init_flag init;
 215         u32 training_cnt;
 216 };
 217
 218 struct psp_context
 219 {
 220         struct amdgpu_device            *adev;
 221         struct psp_ring                 km_ring;
 222         struct psp_gfx_cmd_resp         *cmd;
 223
 224         const struct psp_funcs          *funcs;
 225
 226         /* firmware buffer */
 227         struct amdgpu_bo                *fw_pri_bo;
 228         uint64_t                        fw_pri_mc_addr;
 229         void                            *fw_pri_buf;
 230
 231         /* sos firmware */
 232         const struct firmware           *sos_fw;
 233         uint32_t                        sos_fw_version;
 234         uint32_t                        sos_feature_version;
 235         uint32_t                        sys_bin_size;
 236         uint32_t                        sos_bin_size;
 237         uint32_t                        toc_bin_size;
 238         uint32_t                        kdb_bin_size;
 239         uint32_t                        spl_bin_size;
 240         uint8_t                         *sys_start_addr;
 241         uint8_t                         *sos_start_addr;
 242         uint8_t                         *toc_start_addr;
 243         uint8_t                         *kdb_start_addr;
 244         uint8_t                         *spl_start_addr;
 245
 246         /* tmr buffer */
 247         struct amdgpu_bo                *tmr_bo;
 248         uint64_t                        tmr_mc_addr;
 249
 250         /* asd firmware */
 251         const struct firmware           *asd_fw;
 252         uint32_t                        asd_fw_version;
 253         uint32_t                        asd_feature_version;
 254         uint32_t                        asd_ucode_size;
 255         uint8_t                         *asd_start_addr;
 256
 257         /* toc firmware */
 258         const struct firmware           *toc_fw;
 259         uint32_t                        toc_fw_version;
 260         uint32_t                        toc_feature_version;
 261
 262         /* fence buffer */
 263         struct amdgpu_bo                *fence_buf_bo;
 264         uint64_t                        fence_buf_mc_addr;
 265         void                            *fence_buf;
 266
 267         /* cmd buffer */
 268         struct amdgpu_bo                *cmd_buf_bo;
 269         uint64_t                        cmd_buf_mc_addr;
 270         struct psp_gfx_cmd_resp         *cmd_buf_mem;
 271
 272         /* fence value associated with cmd buffer */
 273         atomic_t                        fence_value;
 274         /* flag to mark whether gfx fw autoload is supported or not */
 275         bool                            autoload_supported;
 276         /* flag to mark whether df cstate management centralized to PMFW */
 277         bool                            pmfw_centralized_cstate_management;
 278
 279         /* xgmi ta firmware and buffer */
 280         const struct firmware           *ta_fw;
 281         uint32_t                        ta_fw_version;
 282         uint32_t                        ta_xgmi_ucode_version;
 283         uint32_t                        ta_xgmi_ucode_size;
 284         uint8_t                         *ta_xgmi_start_addr;
 285         uint32_t                        ta_ras_ucode_version;
 286         uint32_t                        ta_ras_ucode_size;
 287         uint8_t                         *ta_ras_start_addr;
 288
 289         uint32_t                        ta_hdcp_ucode_version;
 290         uint32_t                        ta_hdcp_ucode_size;
 291         uint8_t                         *ta_hdcp_start_addr;
 292
 293         uint32_t                        ta_dtm_ucode_version;
 294         uint32_t                        ta_dtm_ucode_size;
 295         uint8_t                         *ta_dtm_start_addr;
 296
 297         uint32_t                        ta_rap_ucode_version;
 298         uint32_t                        ta_rap_ucode_size;
 299         uint8_t                         *ta_rap_start_addr;
 300
 301         struct psp_asd_context          asd_context;
 302         struct psp_xgmi_context         xgmi_context;
 303         struct psp_ras_context          ras;
 304         struct psp_hdcp_context         hdcp_context;
 305         struct psp_dtm_context          dtm_context;
 306         struct psp_rap_context          rap_context;
 307         struct mutex                    mutex;
 308         struct psp_memory_training_context mem_train_ctx;
 309 };
 310
 311 struct amdgpu_psp_funcs {
 312         bool (*check_fw_loading_status)(struct amdgpu_device *adev,
 313                                         enum AMDGPU_UCODE_ID);
 314 };
 315
 316
 317 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
 318 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 319 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
 320 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
 321 #define psp_init_microcode(psp) \
 322                 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
 323 #define psp_bootloader_load_kdb(psp) \
 324                 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
 325 #define psp_bootloader_load_spl(psp) \
 326                 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
 327 #define psp_bootloader_load_sysdrv(psp) \
 328                 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
 329 #define psp_bootloader_load_sos(psp) \
 330                 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
 331 #define psp_smu_reload_quirk(psp) \
 332                 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
 333 #define psp_mode1_reset(psp) \
 334                 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
 335 #define psp_mem_training(psp, ops) \
 336         ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
 337
 338 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
 339 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
 340
 341 #define psp_load_usbc_pd_fw(psp, dma_addr) \
 342         ((psp)->funcs->load_usbc_pd_fw ? \
 343         (psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL)
 344
 345 #define psp_read_usbc_pd_fw(psp, fw_ver) \
 346         ((psp)->funcs->read_usbc_pd_fw ? \
 347         (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
 348
 349 extern const struct amd_ip_funcs psp_ip_funcs;
 350
 351 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
 352 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 353                         uint32_t field_val, uint32_t mask, bool check_changed);
 354
 355 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
 356 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
 357
 358 int psp_gpu_reset(struct amdgpu_device *adev);
 359 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
 360                         uint64_t cmd_gpu_addr, int cmd_size);
 361
 362 int psp_xgmi_initialize(struct psp_context *psp);
 363 int psp_xgmi_terminate(struct psp_context *psp);
 364 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 365 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
 366 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
 367 int psp_xgmi_get_topology_info(struct psp_context *psp,
 368                                int number_devices,
 369                                struct psp_xgmi_topology_info *topology);
 370 int psp_xgmi_set_topology_info(struct psp_context *psp,
 371                                int number_devices,
 372                                struct psp_xgmi_topology_info *topology);
 373
 374 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 375 int psp_ras_enable_features(struct psp_context *psp,
 376                 union ta_ras_cmd_input *info, bool enable);
 377 int psp_ras_trigger_error(struct psp_context *psp,
 378                           struct ta_ras_trigger_error_input *info);
 379
 380 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 381 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 382 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 383
 384 int psp_rlc_autoload_start(struct psp_context *psp);
 385
 386 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
 387 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 388                 uint32_t value);
 389 int psp_ring_cmd_submit(struct psp_context *psp,
 390                         uint64_t cmd_buf_mc_addr,
 391                         uint64_t fence_mc_addr,
 392                         int index);
 393 int psp_init_asd_microcode(struct psp_context *psp,
 394                            const char *chip_name);
 395 int psp_init_toc_microcode(struct psp_context *psp,
 396                            const char *chip_name);
 397 int psp_init_sos_microcode(struct psp_context *psp,
 398                            const char *chip_name);
 399 int psp_init_ta_microcode(struct psp_context *psp,
 400                           const char *chip_name);
 401 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 402                                         uint64_t *output_ptr);
 403 #endif