2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __AMDGPU_PSP_H__
26 #define __AMDGPU_PSP_H__
29 #include "psp_gfx_if.h"
30 #include "ta_xgmi_if.h"
31 #include "ta_ras_if.h"
32 #include "ta_rap_if.h"
33 #include "ta_secureDisplay_if.h"
35 #define PSP_FENCE_BUFFER_SIZE 0x1000
36 #define PSP_CMD_BUFFER_SIZE 0x1000
37 #define PSP_1_MEG 0x100000
38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39 #define PSP_TMR_ALIGNMENT 0x100000
40 #define PSP_FW_NAME_LEN 0x24
42 extern const struct attribute_group amdgpu_flash_attr_group;
44 enum psp_shared_mem_size {
45 PSP_ASD_SHARED_MEM_SIZE = 0x0,
46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
47 PSP_RAS_SHARED_MEM_SIZE = 0x4000,
48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
49 PSP_DTM_SHARED_MEM_SIZE = 0x4000,
50 PSP_RAP_SHARED_MEM_SIZE = 0x4000,
51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
60 TA_TYPE_SECUREDISPLAY,
66 struct psp_xgmi_node_info;
67 struct psp_xgmi_topology_info;
70 enum psp_bootloader_cmd {
71 PSP_BL__LOAD_SYSDRV = 0x10000,
72 PSP_BL__LOAD_SOSDRV = 0x20000,
73 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
74 PSP_BL__LOAD_SOCDRV = 0xB0000,
75 PSP_BL__LOAD_DBGDRV = 0xC0000,
76 PSP_BL__LOAD_INTFDRV = 0xD0000,
77 PSP_BL__LOAD_RASDRV = 0xE0000,
78 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
79 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
80 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
84 PSP_RING_TYPE__INVALID = 0,
86 * These values map to the way the PSP kernel identifies the
89 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
90 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
94 enum psp_ring_type ring_type;
95 struct psp_gfx_rb_frame *ring_mem;
96 uint64_t ring_mem_mc_addr;
97 void *ring_mem_handle;
102 /* More registers may will be supported */
103 enum psp_reg_prog_id {
104 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
105 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
106 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
111 int (*init_microcode)(struct psp_context *psp);
112 int (*wait_for_bootloader)(struct psp_context *psp);
113 int (*bootloader_load_kdb)(struct psp_context *psp);
114 int (*bootloader_load_spl)(struct psp_context *psp);
115 int (*bootloader_load_sysdrv)(struct psp_context *psp);
116 int (*bootloader_load_soc_drv)(struct psp_context *psp);
117 int (*bootloader_load_intf_drv)(struct psp_context *psp);
118 int (*bootloader_load_dbg_drv)(struct psp_context *psp);
119 int (*bootloader_load_ras_drv)(struct psp_context *psp);
120 int (*bootloader_load_sos)(struct psp_context *psp);
121 int (*ring_create)(struct psp_context *psp,
122 enum psp_ring_type ring_type);
123 int (*ring_stop)(struct psp_context *psp,
124 enum psp_ring_type ring_type);
125 int (*ring_destroy)(struct psp_context *psp,
126 enum psp_ring_type ring_type);
127 bool (*smu_reload_quirk)(struct psp_context *psp);
128 int (*mode1_reset)(struct psp_context *psp);
129 int (*mem_training)(struct psp_context *psp, uint32_t ops);
130 uint32_t (*ring_get_wptr)(struct psp_context *psp);
131 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
132 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
133 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
134 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
135 int (*vbflash_stat)(struct psp_context *psp);
136 int (*fatal_error_recovery_quirk)(struct psp_context *psp);
137 int (*query_boot_status)(struct psp_context *psp);
141 int (*fn_ta_initialize)(struct psp_context *psp);
142 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
143 int (*fn_ta_terminate)(struct psp_context *psp);
146 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
147 struct psp_xgmi_node_info {
150 uint8_t is_sharing_enabled;
151 enum ta_xgmi_assigned_sdma_engine sdma_engine;
153 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM];
156 struct psp_xgmi_topology_info {
158 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
161 struct psp_bin_desc {
163 uint32_t feature_version;
168 struct ta_mem_context {
169 struct amdgpu_bo *shared_bo;
170 uint64_t shared_mc_addr;
172 enum psp_shared_mem_size shared_mem_size;
178 uint32_t resp_status;
179 struct ta_mem_context mem_context;
180 struct psp_bin_desc bin_desc;
181 enum psp_gfx_cmd_id ta_load_type;
182 enum ta_type_id ta_type;
185 struct ta_cp_context {
186 struct ta_context context;
190 struct psp_xgmi_context {
191 struct ta_context context;
192 struct psp_xgmi_topology_info top_info;
193 bool supports_extended_data;
194 uint8_t xgmi_ta_caps;
197 struct psp_ras_context {
198 struct ta_context context;
199 struct amdgpu_ras *ras;
202 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
203 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
204 #define GDDR6_MEM_TRAINING_OFFSET 0x8000
205 /*Define the VRAM size that will be encroached by BIST training.*/
206 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
208 enum psp_memory_training_init_flag {
209 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
210 PSP_MEM_TRAIN_SUPPORT = 0x1,
211 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
212 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
213 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
216 enum psp_memory_training_ops {
217 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
218 PSP_MEM_TRAIN_SAVE = 0x2,
219 PSP_MEM_TRAIN_RESTORE = 0x4,
220 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
221 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
222 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
225 struct psp_memory_training_context {
226 /*training data size*/
230 * cpu virtual address
231 * system memory buffer that used to store the training data.
235 /*vram offset of the p2c training data*/
236 u64 p2c_train_data_offset;
238 /*vram offset of the c2p training data*/
239 u64 c2p_train_data_offset;
240 struct amdgpu_bo *c2p_bo;
242 enum psp_memory_training_init_flag init;
244 bool enable_mem_training;
247 /** PSP runtime DB **/
248 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
249 #define PSP_RUNTIME_DB_OFFSET 0x100000
250 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
251 #define PSP_RUNTIME_DB_VER_1 0x0100
252 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
254 enum psp_runtime_entry_type {
255 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
256 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
257 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
258 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
259 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
260 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
261 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
264 /* PSP runtime DB header */
265 struct psp_runtime_data_header {
266 /* determine the existence of runtime db */
268 /* version of runtime db */
272 /* PSP runtime DB entry */
273 struct psp_runtime_entry {
274 /* type of runtime db entry */
276 /* offset of entry in bytes */
278 /* size of entry in bytes */
282 /* PSP runtime DB directory */
283 struct psp_runtime_data_directory {
284 /* number of valid entries */
285 uint16_t entry_count;
287 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
290 /* PSP runtime DB boot config feature bitmask */
291 enum psp_runtime_boot_cfg_feature {
292 BOOT_CFG_FEATURE_GECC = 0x1,
293 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
296 /* PSP run time DB SCPM authentication defines */
297 enum psp_runtime_scpm_authentication {
300 SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
303 /* PSP runtime DB boot config entry */
304 struct psp_runtime_boot_cfg_entry {
305 uint32_t boot_cfg_bitmask;
309 /* PSP runtime DB SCPM entry */
310 struct psp_runtime_scpm_entry {
311 enum psp_runtime_scpm_authentication scpm_status;
315 struct amdgpu_device *adev;
316 struct psp_ring km_ring;
317 struct psp_gfx_cmd_resp *cmd;
319 const struct psp_funcs *funcs;
320 const struct ta_funcs *ta_funcs;
322 /* firmware buffer */
323 struct amdgpu_bo *fw_pri_bo;
324 uint64_t fw_pri_mc_addr;
328 const struct firmware *sos_fw;
329 struct psp_bin_desc sys;
330 struct psp_bin_desc sos;
331 struct psp_bin_desc toc;
332 struct psp_bin_desc kdb;
333 struct psp_bin_desc spl;
334 struct psp_bin_desc rl;
335 struct psp_bin_desc soc_drv;
336 struct psp_bin_desc intf_drv;
337 struct psp_bin_desc dbg_drv;
338 struct psp_bin_desc ras_drv;
341 struct amdgpu_bo *tmr_bo;
342 uint64_t tmr_mc_addr;
345 const struct firmware *asd_fw;
348 const struct firmware *toc_fw;
351 const struct firmware *cap_fw;
354 struct amdgpu_bo *fence_buf_bo;
355 uint64_t fence_buf_mc_addr;
359 struct amdgpu_bo *cmd_buf_bo;
360 uint64_t cmd_buf_mc_addr;
361 struct psp_gfx_cmd_resp *cmd_buf_mem;
363 /* fence value associated with cmd buffer */
364 atomic_t fence_value;
365 /* flag to mark whether gfx fw autoload is supported or not */
366 bool autoload_supported;
367 /* flag to mark whether df cstate management centralized to PMFW */
368 bool pmfw_centralized_cstate_management;
370 /* xgmi ta firmware and buffer */
371 const struct firmware *ta_fw;
372 uint32_t ta_fw_version;
374 uint32_t cap_fw_version;
375 uint32_t cap_feature_version;
376 uint32_t cap_ucode_size;
378 struct ta_context asd_context;
379 struct psp_xgmi_context xgmi_context;
380 struct psp_ras_context ras_context;
381 struct ta_cp_context hdcp_context;
382 struct ta_cp_context dtm_context;
383 struct ta_cp_context rap_context;
384 struct ta_cp_context securedisplay_context;
386 struct psp_memory_training_context mem_train_ctx;
388 uint32_t boot_cfg_bitmask;
390 /* firmware upgrades supported */
394 char *vbflash_tmp_buf;
395 size_t vbflash_image_size;
399 struct amdgpu_psp_funcs {
400 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
401 enum AMDGPU_UCODE_ID);
405 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
406 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
407 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
408 #define psp_init_microcode(psp) \
409 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
410 #define psp_bootloader_load_kdb(psp) \
411 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
412 #define psp_bootloader_load_spl(psp) \
413 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
414 #define psp_bootloader_load_sysdrv(psp) \
415 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
416 #define psp_bootloader_load_soc_drv(psp) \
417 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
418 #define psp_bootloader_load_intf_drv(psp) \
419 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
420 #define psp_bootloader_load_dbg_drv(psp) \
421 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
422 #define psp_bootloader_load_ras_drv(psp) \
423 ((psp)->funcs->bootloader_load_ras_drv ? \
424 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
425 #define psp_bootloader_load_sos(psp) \
426 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
427 #define psp_smu_reload_quirk(psp) \
428 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
429 #define psp_mode1_reset(psp) \
430 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
431 #define psp_mem_training(psp, ops) \
432 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
434 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
435 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
437 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
438 ((psp)->funcs->load_usbc_pd_fw ? \
439 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
441 #define psp_read_usbc_pd_fw(psp, fw_ver) \
442 ((psp)->funcs->read_usbc_pd_fw ? \
443 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
445 #define psp_update_spirom(psp, fw_pri_mc_addr) \
446 ((psp)->funcs->update_spirom ? \
447 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
449 #define psp_vbflash_status(psp) \
450 ((psp)->funcs->vbflash_stat ? \
451 (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
453 #define psp_fatal_error_recovery_quirk(psp) \
454 ((psp)->funcs->fatal_error_recovery_quirk ? \
455 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)
457 extern const struct amd_ip_funcs psp_ip_funcs;
459 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
460 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
461 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
462 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
463 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
464 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
465 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
467 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
468 uint32_t field_val, uint32_t mask, bool check_changed);
469 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
470 uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
472 int psp_execute_ip_fw_load(struct psp_context *psp,
473 struct amdgpu_firmware_info *ucode);
475 int psp_gpu_reset(struct amdgpu_device *adev);
477 int psp_ta_init_shared_buf(struct psp_context *psp,
478 struct ta_mem_context *mem_ctx);
479 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
480 int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
481 int psp_ta_load(struct psp_context *psp, struct ta_context *context);
482 int psp_ta_invoke(struct psp_context *psp,
484 struct ta_context *context);
486 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
487 int psp_xgmi_terminate(struct psp_context *psp);
488 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
489 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
490 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
491 int psp_xgmi_get_topology_info(struct psp_context *psp,
493 struct psp_xgmi_topology_info *topology,
494 bool get_extended_data);
495 int psp_xgmi_set_topology_info(struct psp_context *psp,
497 struct psp_xgmi_topology_info *topology);
498 int psp_ras_initialize(struct psp_context *psp);
499 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
500 int psp_ras_enable_features(struct psp_context *psp,
501 union ta_ras_cmd_input *info, bool enable);
502 int psp_ras_trigger_error(struct psp_context *psp,
503 struct ta_ras_trigger_error_input *info, uint32_t instance_mask);
504 int psp_ras_terminate(struct psp_context *psp);
506 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
507 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
508 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
509 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
511 int psp_rlc_autoload_start(struct psp_context *psp);
513 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
515 int psp_ring_cmd_submit(struct psp_context *psp,
516 uint64_t cmd_buf_mc_addr,
517 uint64_t fence_mc_addr,
519 int psp_init_asd_microcode(struct psp_context *psp,
520 const char *chip_name);
521 int psp_init_toc_microcode(struct psp_context *psp,
522 const char *chip_name);
523 int psp_init_sos_microcode(struct psp_context *psp,
524 const char *chip_name);
525 int psp_init_ta_microcode(struct psp_context *psp,
526 const char *chip_name);
527 int psp_init_cap_microcode(struct psp_context *psp,
528 const char *chip_name);
529 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
530 uint64_t *output_ptr);
532 int psp_load_fw_list(struct psp_context *psp,
533 struct amdgpu_firmware_info **ucode_list, int ucode_count);
534 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
536 int psp_spatial_partition(struct psp_context *psp, int mode);
538 int is_psp_fw_valid(struct psp_bin_desc bin);
540 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
542 int amdgpu_psp_query_boot_status(struct amdgpu_device *adev);