2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <linux/dma-mapping.h>
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "soc15_common.h"
34 #include "psp_v10_0.h"
35 #include "psp_v11_0.h"
36 #include "psp_v12_0.h"
38 #include "amdgpu_ras.h"
40 static int psp_sysfs_init(struct amdgpu_device *adev);
41 static void psp_sysfs_fini(struct amdgpu_device *adev);
43 static int psp_load_smu_fw(struct psp_context *psp);
46 * Due to DF Cstate management centralized to PMFW, the firmware
47 * loading sequence will be updated as below:
53 * - Load other non-psp fw
55 * - Load XGMI/RAS/HDCP/DTM TA if any
57 * This new sequence is required for
59 * - Navi12 and onwards
61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
63 struct amdgpu_device *adev = psp->adev;
65 psp->pmfw_centralized_cstate_management = false;
67 if (amdgpu_sriov_vf(adev))
70 if (adev->flags & AMD_IS_APU)
73 if ((adev->asic_type == CHIP_ARCTURUS) ||
74 (adev->asic_type >= CHIP_NAVI12))
75 psp->pmfw_centralized_cstate_management = true;
78 static int psp_early_init(void *handle)
80 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
81 struct psp_context *psp = &adev->psp;
83 switch (adev->asic_type) {
86 psp_v3_1_set_psp_funcs(psp);
87 psp->autoload_supported = false;
90 psp_v10_0_set_psp_funcs(psp);
91 psp->autoload_supported = false;
95 psp_v11_0_set_psp_funcs(psp);
96 psp->autoload_supported = false;
101 case CHIP_SIENNA_CICHLID:
102 case CHIP_NAVY_FLOUNDER:
103 psp_v11_0_set_psp_funcs(psp);
104 psp->autoload_supported = true;
107 psp_v12_0_set_psp_funcs(psp);
115 psp_check_pmfw_centralized_cstate_management(psp);
120 static void psp_memory_training_fini(struct psp_context *psp)
122 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
124 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
125 kfree(ctx->sys_cache);
126 ctx->sys_cache = NULL;
129 static int psp_memory_training_init(struct psp_context *psp)
132 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
134 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
135 DRM_DEBUG("memory training is not supported!\n");
139 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
140 if (ctx->sys_cache == NULL) {
141 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
146 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
147 ctx->train_data_size,
148 ctx->p2c_train_data_offset,
149 ctx->c2p_train_data_offset);
150 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
154 psp_memory_training_fini(psp);
158 static int psp_sw_init(void *handle)
160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
161 struct psp_context *psp = &adev->psp;
164 ret = psp_init_microcode(psp);
166 DRM_ERROR("Failed to load psp firmware!\n");
170 ret = psp_memory_training_init(psp);
172 DRM_ERROR("Failed to initialize memory training!\n");
175 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
177 DRM_ERROR("Failed to process memory training!\n");
181 if (adev->asic_type == CHIP_NAVI10) {
182 ret= psp_sysfs_init(adev);
191 static int psp_sw_fini(void *handle)
193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
195 psp_memory_training_fini(&adev->psp);
196 if (adev->psp.sos_fw) {
197 release_firmware(adev->psp.sos_fw);
198 adev->psp.sos_fw = NULL;
200 if (adev->psp.asd_fw) {
201 release_firmware(adev->psp.asd_fw);
202 adev->psp.asd_fw = NULL;
204 if (adev->psp.ta_fw) {
205 release_firmware(adev->psp.ta_fw);
206 adev->psp.ta_fw = NULL;
209 if (adev->asic_type == CHIP_NAVI10)
210 psp_sysfs_fini(adev);
215 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
216 uint32_t reg_val, uint32_t mask, bool check_changed)
220 struct amdgpu_device *adev = psp->adev;
222 for (i = 0; i < adev->usec_timeout; i++) {
223 val = RREG32(reg_index);
228 if ((val & mask) == reg_val)
238 psp_cmd_submit_buf(struct psp_context *psp,
239 struct amdgpu_firmware_info *ucode,
240 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
245 bool ras_intr = false;
246 bool skip_unsupport = false;
248 mutex_lock(&psp->mutex);
250 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
252 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
254 index = atomic_inc_return(&psp->fence_value);
255 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
257 atomic_dec(&psp->fence_value);
258 mutex_unlock(&psp->mutex);
262 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
263 while (*((unsigned int *)psp->fence_buf) != index) {
267 * Shouldn't wait for timeout when err_event_athub occurs,
268 * because gpu reset thread triggered and lock resource should
269 * be released for psp resume sequence.
271 ras_intr = amdgpu_ras_intr_triggered();
275 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
278 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
279 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
280 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
282 /* In some cases, psp response status is not 0 even there is no
283 * problem while the command is submitted. Some version of PSP FW
284 * doesn't write 0 to that field.
285 * So here we would like to only print a warning instead of an error
286 * during psp initialization to avoid breaking hw_init and it doesn't
289 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
291 DRM_WARN("failed to load ucode id (%d) ",
293 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
294 psp->cmd_buf_mem->cmd_id,
295 psp->cmd_buf_mem->resp.status);
297 mutex_unlock(&psp->mutex);
302 /* get xGMI session id from response buffer */
303 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
306 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
307 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
309 mutex_unlock(&psp->mutex);
314 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
315 struct psp_gfx_cmd_resp *cmd,
316 uint64_t tmr_mc, uint32_t size)
318 if (amdgpu_sriov_vf(psp->adev))
319 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
321 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
322 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
323 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
324 cmd->cmd.cmd_setup_tmr.buf_size = size;
327 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
328 uint64_t pri_buf_mc, uint32_t size)
330 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
331 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
332 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
333 cmd->cmd.cmd_load_toc.toc_size = size;
336 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
337 static int psp_load_toc(struct psp_context *psp,
341 struct psp_gfx_cmd_resp *cmd;
343 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
346 /* Copy toc to psp firmware private buffer */
347 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
348 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
350 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
352 ret = psp_cmd_submit_buf(psp, NULL, cmd,
353 psp->fence_buf_mc_addr);
355 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
360 /* Set up Trusted Memory Region */
361 static int psp_tmr_init(struct psp_context *psp)
369 * According to HW engineer, they prefer the TMR address be "naturally
370 * aligned" , e.g. the start address be an integer divide of TMR size.
372 * Note: this memory need be reserved till the driver
375 tmr_size = PSP_TMR_SIZE;
377 /* For ASICs support RLC autoload, psp will parse the toc
378 * and calculate the total size of TMR needed */
379 if (!amdgpu_sriov_vf(psp->adev) &&
380 psp->toc_start_addr &&
383 ret = psp_load_toc(psp, &tmr_size);
385 DRM_ERROR("Failed to load toc\n");
390 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
391 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
392 AMDGPU_GEM_DOMAIN_VRAM,
393 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
398 static int psp_clear_vf_fw(struct psp_context *psp)
401 struct psp_gfx_cmd_resp *cmd;
403 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12)
406 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
410 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW;
412 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
418 static bool psp_skip_tmr(struct psp_context *psp)
420 switch (psp->adev->asic_type) {
422 case CHIP_SIENNA_CICHLID:
429 static int psp_tmr_load(struct psp_context *psp)
432 struct psp_gfx_cmd_resp *cmd;
434 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
435 * Already set up by host driver.
437 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
440 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
444 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
445 amdgpu_bo_size(psp->tmr_bo));
446 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
447 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
449 ret = psp_cmd_submit_buf(psp, NULL, cmd,
450 psp->fence_buf_mc_addr);
457 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
458 struct psp_gfx_cmd_resp *cmd)
460 if (amdgpu_sriov_vf(psp->adev))
461 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
463 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
466 static int psp_tmr_unload(struct psp_context *psp)
469 struct psp_gfx_cmd_resp *cmd;
471 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
475 psp_prep_tmr_unload_cmd_buf(psp, cmd);
476 DRM_INFO("free PSP TMR buffer\n");
478 ret = psp_cmd_submit_buf(psp, NULL, cmd,
479 psp->fence_buf_mc_addr);
486 static int psp_tmr_terminate(struct psp_context *psp)
492 ret = psp_tmr_unload(psp);
496 /* free TMR memory buffer */
497 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
498 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
503 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
504 uint64_t asd_mc, uint32_t size)
506 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
507 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
508 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
509 cmd->cmd.cmd_load_ta.app_len = size;
511 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
512 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
513 cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
516 static int psp_asd_load(struct psp_context *psp)
519 struct psp_gfx_cmd_resp *cmd;
521 /* If PSP version doesn't match ASD version, asd loading will be failed.
522 * add workaround to bypass it for sriov now.
523 * TODO: add version check to make it common
525 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)
528 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
532 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
533 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
535 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
536 psp->asd_ucode_size);
538 ret = psp_cmd_submit_buf(psp, NULL, cmd,
539 psp->fence_buf_mc_addr);
541 psp->asd_context.asd_initialized = true;
542 psp->asd_context.session_id = cmd->resp.session_id;
550 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
553 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
554 cmd->cmd.cmd_unload_ta.session_id = session_id;
557 static int psp_asd_unload(struct psp_context *psp)
560 struct psp_gfx_cmd_resp *cmd;
562 if (amdgpu_sriov_vf(psp->adev))
565 if (!psp->asd_context.asd_initialized)
568 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
572 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
574 ret = psp_cmd_submit_buf(psp, NULL, cmd,
575 psp->fence_buf_mc_addr);
577 psp->asd_context.asd_initialized = false;
584 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
585 uint32_t id, uint32_t value)
587 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
588 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
589 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
592 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
595 struct psp_gfx_cmd_resp *cmd = NULL;
598 if (reg >= PSP_REG_LAST)
601 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
605 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
606 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
612 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
614 uint32_t ta_bin_size,
615 uint64_t ta_shared_mc,
616 uint32_t ta_shared_size)
618 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
619 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
620 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
621 cmd->cmd.cmd_load_ta.app_len = ta_bin_size;
623 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
624 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
625 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size;
628 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
633 * Allocate 16k memory aligned to 4k from Frame Buffer (local
634 * physical) for xgmi ta <-> Driver
636 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
637 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
638 &psp->xgmi_context.xgmi_shared_bo,
639 &psp->xgmi_context.xgmi_shared_mc_addr,
640 &psp->xgmi_context.xgmi_shared_buf);
645 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
649 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
650 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
651 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
654 static int psp_ta_invoke(struct psp_context *psp,
659 struct psp_gfx_cmd_resp *cmd;
661 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
665 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
667 ret = psp_cmd_submit_buf(psp, NULL, cmd,
668 psp->fence_buf_mc_addr);
675 static int psp_xgmi_load(struct psp_context *psp)
678 struct psp_gfx_cmd_resp *cmd;
681 * TODO: bypass the loading in sriov for now
684 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
688 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
689 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
691 psp_prep_ta_load_cmd_buf(cmd,
693 psp->ta_xgmi_ucode_size,
694 psp->xgmi_context.xgmi_shared_mc_addr,
695 PSP_XGMI_SHARED_MEM_SIZE);
697 ret = psp_cmd_submit_buf(psp, NULL, cmd,
698 psp->fence_buf_mc_addr);
701 psp->xgmi_context.initialized = 1;
702 psp->xgmi_context.session_id = cmd->resp.session_id;
710 static int psp_xgmi_unload(struct psp_context *psp)
713 struct psp_gfx_cmd_resp *cmd;
714 struct amdgpu_device *adev = psp->adev;
716 /* XGMI TA unload currently is not supported on Arcturus */
717 if (adev->asic_type == CHIP_ARCTURUS)
721 * TODO: bypass the unloading in sriov for now
724 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
728 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
730 ret = psp_cmd_submit_buf(psp, NULL, cmd,
731 psp->fence_buf_mc_addr);
738 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
740 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
743 int psp_xgmi_terminate(struct psp_context *psp)
747 if (!psp->xgmi_context.initialized)
750 ret = psp_xgmi_unload(psp);
754 psp->xgmi_context.initialized = 0;
756 /* free xgmi shared memory */
757 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
758 &psp->xgmi_context.xgmi_shared_mc_addr,
759 &psp->xgmi_context.xgmi_shared_buf);
764 int psp_xgmi_initialize(struct psp_context *psp)
766 struct ta_xgmi_shared_memory *xgmi_cmd;
769 if (!psp->adev->psp.ta_fw ||
770 !psp->adev->psp.ta_xgmi_ucode_size ||
771 !psp->adev->psp.ta_xgmi_start_addr)
774 if (!psp->xgmi_context.initialized) {
775 ret = psp_xgmi_init_shared_buf(psp);
781 ret = psp_xgmi_load(psp);
785 /* Initialize XGMI session */
786 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
787 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
788 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
790 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
795 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
797 struct ta_xgmi_shared_memory *xgmi_cmd;
800 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
801 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
803 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
805 /* Invoke xgmi ta to get hive id */
806 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
810 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
815 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
817 struct ta_xgmi_shared_memory *xgmi_cmd;
820 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
821 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
823 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
825 /* Invoke xgmi ta to get the node id */
826 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
830 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
835 int psp_xgmi_get_topology_info(struct psp_context *psp,
837 struct psp_xgmi_topology_info *topology)
839 struct ta_xgmi_shared_memory *xgmi_cmd;
840 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
841 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
845 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
848 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
849 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
851 /* Fill in the shared memory with topology information as input */
852 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
853 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
854 topology_info_input->num_nodes = number_devices;
856 for (i = 0; i < topology_info_input->num_nodes; i++) {
857 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
858 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
859 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
860 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
863 /* Invoke xgmi ta to get the topology information */
864 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
868 /* Read the output topology information from the shared memory */
869 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
870 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
871 for (i = 0; i < topology->num_nodes; i++) {
872 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
873 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
874 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
875 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
881 int psp_xgmi_set_topology_info(struct psp_context *psp,
883 struct psp_xgmi_topology_info *topology)
885 struct ta_xgmi_shared_memory *xgmi_cmd;
886 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
889 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
892 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
893 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
895 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
896 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
897 topology_info_input->num_nodes = number_devices;
899 for (i = 0; i < topology_info_input->num_nodes; i++) {
900 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
901 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
902 topology_info_input->nodes[i].is_sharing_enabled = 1;
903 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
906 /* Invoke xgmi ta to set topology information */
907 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
911 static int psp_ras_init_shared_buf(struct psp_context *psp)
916 * Allocate 16k memory aligned to 4k from Frame Buffer (local
917 * physical) for ras ta <-> Driver
919 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
920 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
921 &psp->ras.ras_shared_bo,
922 &psp->ras.ras_shared_mc_addr,
923 &psp->ras.ras_shared_buf);
928 static int psp_ras_load(struct psp_context *psp)
931 struct psp_gfx_cmd_resp *cmd;
934 * TODO: bypass the loading in sriov for now
936 if (amdgpu_sriov_vf(psp->adev))
939 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
943 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
944 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
946 psp_prep_ta_load_cmd_buf(cmd,
948 psp->ta_ras_ucode_size,
949 psp->ras.ras_shared_mc_addr,
950 PSP_RAS_SHARED_MEM_SIZE);
952 ret = psp_cmd_submit_buf(psp, NULL, cmd,
953 psp->fence_buf_mc_addr);
956 psp->ras.ras_initialized = true;
957 psp->ras.session_id = cmd->resp.session_id;
965 static int psp_ras_unload(struct psp_context *psp)
968 struct psp_gfx_cmd_resp *cmd;
971 * TODO: bypass the unloading in sriov for now
973 if (amdgpu_sriov_vf(psp->adev))
976 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
980 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
982 ret = psp_cmd_submit_buf(psp, NULL, cmd,
983 psp->fence_buf_mc_addr);
990 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
992 struct ta_ras_shared_memory *ras_cmd;
995 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
998 * TODO: bypass the loading in sriov for now
1000 if (amdgpu_sriov_vf(psp->adev))
1003 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1005 if (amdgpu_ras_intr_triggered())
1008 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1010 DRM_WARN("RAS: Unsupported Interface");
1015 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1016 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1018 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1020 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1021 dev_warn(psp->adev->dev,
1022 "RAS internal register access blocked\n");
1028 int psp_ras_enable_features(struct psp_context *psp,
1029 union ta_ras_cmd_input *info, bool enable)
1031 struct ta_ras_shared_memory *ras_cmd;
1034 if (!psp->ras.ras_initialized)
1037 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1038 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1041 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1043 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1045 ras_cmd->ras_in_message = *info;
1047 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1051 return ras_cmd->ras_status;
1054 static int psp_ras_terminate(struct psp_context *psp)
1059 * TODO: bypass the terminate in sriov for now
1061 if (amdgpu_sriov_vf(psp->adev))
1064 if (!psp->ras.ras_initialized)
1067 ret = psp_ras_unload(psp);
1071 psp->ras.ras_initialized = false;
1073 /* free ras shared memory */
1074 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1075 &psp->ras.ras_shared_mc_addr,
1076 &psp->ras.ras_shared_buf);
1081 static int psp_ras_initialize(struct psp_context *psp)
1086 * TODO: bypass the initialize in sriov for now
1088 if (amdgpu_sriov_vf(psp->adev))
1091 if (!psp->adev->psp.ta_ras_ucode_size ||
1092 !psp->adev->psp.ta_ras_start_addr) {
1093 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
1097 if (!psp->ras.ras_initialized) {
1098 ret = psp_ras_init_shared_buf(psp);
1103 ret = psp_ras_load(psp);
1110 int psp_ras_trigger_error(struct psp_context *psp,
1111 struct ta_ras_trigger_error_input *info)
1113 struct ta_ras_shared_memory *ras_cmd;
1116 if (!psp->ras.ras_initialized)
1119 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1120 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1122 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1123 ras_cmd->ras_in_message.trigger_error = *info;
1125 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1129 /* If err_event_athub occurs error inject was successful, however
1130 return status from TA is no long reliable */
1131 if (amdgpu_ras_intr_triggered())
1134 return ras_cmd->ras_status;
1139 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1144 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1145 * physical) for hdcp ta <-> Driver
1147 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1148 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1149 &psp->hdcp_context.hdcp_shared_bo,
1150 &psp->hdcp_context.hdcp_shared_mc_addr,
1151 &psp->hdcp_context.hdcp_shared_buf);
1156 static int psp_hdcp_load(struct psp_context *psp)
1159 struct psp_gfx_cmd_resp *cmd;
1162 * TODO: bypass the loading in sriov for now
1164 if (amdgpu_sriov_vf(psp->adev))
1167 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1171 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1172 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
1173 psp->ta_hdcp_ucode_size);
1175 psp_prep_ta_load_cmd_buf(cmd,
1176 psp->fw_pri_mc_addr,
1177 psp->ta_hdcp_ucode_size,
1178 psp->hdcp_context.hdcp_shared_mc_addr,
1179 PSP_HDCP_SHARED_MEM_SIZE);
1181 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1184 psp->hdcp_context.hdcp_initialized = true;
1185 psp->hdcp_context.session_id = cmd->resp.session_id;
1186 mutex_init(&psp->hdcp_context.mutex);
1193 static int psp_hdcp_initialize(struct psp_context *psp)
1198 * TODO: bypass the initialize in sriov for now
1200 if (amdgpu_sriov_vf(psp->adev))
1203 if (!psp->adev->psp.ta_hdcp_ucode_size ||
1204 !psp->adev->psp.ta_hdcp_start_addr) {
1205 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1209 if (!psp->hdcp_context.hdcp_initialized) {
1210 ret = psp_hdcp_init_shared_buf(psp);
1215 ret = psp_hdcp_load(psp);
1222 static int psp_hdcp_unload(struct psp_context *psp)
1225 struct psp_gfx_cmd_resp *cmd;
1228 * TODO: bypass the unloading in sriov for now
1230 if (amdgpu_sriov_vf(psp->adev))
1233 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1237 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1239 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1246 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1249 * TODO: bypass the loading in sriov for now
1251 if (amdgpu_sriov_vf(psp->adev))
1254 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1257 static int psp_hdcp_terminate(struct psp_context *psp)
1262 * TODO: bypass the terminate in sriov for now
1264 if (amdgpu_sriov_vf(psp->adev))
1267 if (!psp->hdcp_context.hdcp_initialized)
1270 ret = psp_hdcp_unload(psp);
1274 psp->hdcp_context.hdcp_initialized = false;
1276 /* free hdcp shared memory */
1277 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1278 &psp->hdcp_context.hdcp_shared_mc_addr,
1279 &psp->hdcp_context.hdcp_shared_buf);
1286 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1291 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1292 * physical) for dtm ta <-> Driver
1294 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1295 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1296 &psp->dtm_context.dtm_shared_bo,
1297 &psp->dtm_context.dtm_shared_mc_addr,
1298 &psp->dtm_context.dtm_shared_buf);
1303 static int psp_dtm_load(struct psp_context *psp)
1306 struct psp_gfx_cmd_resp *cmd;
1309 * TODO: bypass the loading in sriov for now
1311 if (amdgpu_sriov_vf(psp->adev))
1314 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1318 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1319 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1321 psp_prep_ta_load_cmd_buf(cmd,
1322 psp->fw_pri_mc_addr,
1323 psp->ta_dtm_ucode_size,
1324 psp->dtm_context.dtm_shared_mc_addr,
1325 PSP_DTM_SHARED_MEM_SIZE);
1327 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1330 psp->dtm_context.dtm_initialized = true;
1331 psp->dtm_context.session_id = cmd->resp.session_id;
1332 mutex_init(&psp->dtm_context.mutex);
1340 static int psp_dtm_initialize(struct psp_context *psp)
1345 * TODO: bypass the initialize in sriov for now
1347 if (amdgpu_sriov_vf(psp->adev))
1350 if (!psp->adev->psp.ta_dtm_ucode_size ||
1351 !psp->adev->psp.ta_dtm_start_addr) {
1352 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1356 if (!psp->dtm_context.dtm_initialized) {
1357 ret = psp_dtm_init_shared_buf(psp);
1362 ret = psp_dtm_load(psp);
1369 static int psp_dtm_unload(struct psp_context *psp)
1372 struct psp_gfx_cmd_resp *cmd;
1375 * TODO: bypass the unloading in sriov for now
1377 if (amdgpu_sriov_vf(psp->adev))
1380 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1384 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1386 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1393 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1396 * TODO: bypass the loading in sriov for now
1398 if (amdgpu_sriov_vf(psp->adev))
1401 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1404 static int psp_dtm_terminate(struct psp_context *psp)
1409 * TODO: bypass the terminate in sriov for now
1411 if (amdgpu_sriov_vf(psp->adev))
1414 if (!psp->dtm_context.dtm_initialized)
1417 ret = psp_dtm_unload(psp);
1421 psp->dtm_context.dtm_initialized = false;
1423 /* free hdcp shared memory */
1424 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1425 &psp->dtm_context.dtm_shared_mc_addr,
1426 &psp->dtm_context.dtm_shared_buf);
1433 static int psp_rap_init_shared_buf(struct psp_context *psp)
1438 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1439 * physical) for rap ta <-> Driver
1441 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1442 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1443 &psp->rap_context.rap_shared_bo,
1444 &psp->rap_context.rap_shared_mc_addr,
1445 &psp->rap_context.rap_shared_buf);
1450 static int psp_rap_load(struct psp_context *psp)
1453 struct psp_gfx_cmd_resp *cmd;
1455 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1459 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1460 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1462 psp_prep_ta_load_cmd_buf(cmd,
1463 psp->fw_pri_mc_addr,
1464 psp->ta_rap_ucode_size,
1465 psp->rap_context.rap_shared_mc_addr,
1466 PSP_RAP_SHARED_MEM_SIZE);
1468 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1471 psp->rap_context.rap_initialized = true;
1472 psp->rap_context.session_id = cmd->resp.session_id;
1473 mutex_init(&psp->rap_context.mutex);
1481 static int psp_rap_unload(struct psp_context *psp)
1484 struct psp_gfx_cmd_resp *cmd;
1486 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1490 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1492 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1499 static int psp_rap_initialize(struct psp_context *psp)
1504 * TODO: bypass the initialize in sriov for now
1506 if (amdgpu_sriov_vf(psp->adev))
1509 if (!psp->adev->psp.ta_rap_ucode_size ||
1510 !psp->adev->psp.ta_rap_start_addr) {
1511 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1515 if (!psp->rap_context.rap_initialized) {
1516 ret = psp_rap_init_shared_buf(psp);
1521 ret = psp_rap_load(psp);
1525 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE);
1526 if (ret != TA_RAP_STATUS__SUCCESS) {
1527 psp_rap_unload(psp);
1529 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1530 &psp->rap_context.rap_shared_mc_addr,
1531 &psp->rap_context.rap_shared_buf);
1533 psp->rap_context.rap_initialized = false;
1535 dev_warn(psp->adev->dev, "RAP TA initialize fail.\n");
1542 static int psp_rap_terminate(struct psp_context *psp)
1546 if (!psp->rap_context.rap_initialized)
1549 ret = psp_rap_unload(psp);
1551 psp->rap_context.rap_initialized = false;
1553 /* free rap shared memory */
1554 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1555 &psp->rap_context.rap_shared_mc_addr,
1556 &psp->rap_context.rap_shared_buf);
1561 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1563 struct ta_rap_shared_memory *rap_cmd;
1566 if (!psp->rap_context.rap_initialized)
1569 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1570 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1573 mutex_lock(&psp->rap_context.mutex);
1575 rap_cmd = (struct ta_rap_shared_memory *)
1576 psp->rap_context.rap_shared_buf;
1577 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1579 rap_cmd->cmd_id = ta_cmd_id;
1580 rap_cmd->validation_method_id = METHOD_A;
1582 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1584 mutex_unlock(&psp->rap_context.mutex);
1588 mutex_unlock(&psp->rap_context.mutex);
1590 return rap_cmd->rap_status;
1594 static int psp_hw_start(struct psp_context *psp)
1596 struct amdgpu_device *adev = psp->adev;
1599 if (!amdgpu_sriov_vf(adev)) {
1600 if (psp->kdb_bin_size &&
1601 (psp->funcs->bootloader_load_kdb != NULL)) {
1602 ret = psp_bootloader_load_kdb(psp);
1604 DRM_ERROR("PSP load kdb failed!\n");
1609 if (psp->spl_bin_size) {
1610 ret = psp_bootloader_load_spl(psp);
1612 DRM_ERROR("PSP load spl failed!\n");
1617 ret = psp_bootloader_load_sysdrv(psp);
1619 DRM_ERROR("PSP load sysdrv failed!\n");
1623 ret = psp_bootloader_load_sos(psp);
1625 DRM_ERROR("PSP load sos failed!\n");
1630 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1632 DRM_ERROR("PSP create ring failed!\n");
1636 ret = psp_clear_vf_fw(psp);
1638 DRM_ERROR("PSP clear vf fw!\n");
1642 ret = psp_tmr_init(psp);
1644 DRM_ERROR("PSP tmr init failed!\n");
1649 * For ASICs with DF Cstate management centralized
1650 * to PMFW, TMR setup should be performed after PMFW
1651 * loaded and before other non-psp firmware loaded.
1653 if (psp->pmfw_centralized_cstate_management) {
1654 ret = psp_load_smu_fw(psp);
1659 ret = psp_tmr_load(psp);
1661 DRM_ERROR("PSP load tmr failed!\n");
1668 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1669 enum psp_gfx_fw_type *type)
1671 switch (ucode->ucode_id) {
1672 case AMDGPU_UCODE_ID_SDMA0:
1673 *type = GFX_FW_TYPE_SDMA0;
1675 case AMDGPU_UCODE_ID_SDMA1:
1676 *type = GFX_FW_TYPE_SDMA1;
1678 case AMDGPU_UCODE_ID_SDMA2:
1679 *type = GFX_FW_TYPE_SDMA2;
1681 case AMDGPU_UCODE_ID_SDMA3:
1682 *type = GFX_FW_TYPE_SDMA3;
1684 case AMDGPU_UCODE_ID_SDMA4:
1685 *type = GFX_FW_TYPE_SDMA4;
1687 case AMDGPU_UCODE_ID_SDMA5:
1688 *type = GFX_FW_TYPE_SDMA5;
1690 case AMDGPU_UCODE_ID_SDMA6:
1691 *type = GFX_FW_TYPE_SDMA6;
1693 case AMDGPU_UCODE_ID_SDMA7:
1694 *type = GFX_FW_TYPE_SDMA7;
1696 case AMDGPU_UCODE_ID_CP_MES:
1697 *type = GFX_FW_TYPE_CP_MES;
1699 case AMDGPU_UCODE_ID_CP_MES_DATA:
1700 *type = GFX_FW_TYPE_MES_STACK;
1702 case AMDGPU_UCODE_ID_CP_CE:
1703 *type = GFX_FW_TYPE_CP_CE;
1705 case AMDGPU_UCODE_ID_CP_PFP:
1706 *type = GFX_FW_TYPE_CP_PFP;
1708 case AMDGPU_UCODE_ID_CP_ME:
1709 *type = GFX_FW_TYPE_CP_ME;
1711 case AMDGPU_UCODE_ID_CP_MEC1:
1712 *type = GFX_FW_TYPE_CP_MEC;
1714 case AMDGPU_UCODE_ID_CP_MEC1_JT:
1715 *type = GFX_FW_TYPE_CP_MEC_ME1;
1717 case AMDGPU_UCODE_ID_CP_MEC2:
1718 *type = GFX_FW_TYPE_CP_MEC;
1720 case AMDGPU_UCODE_ID_CP_MEC2_JT:
1721 *type = GFX_FW_TYPE_CP_MEC_ME2;
1723 case AMDGPU_UCODE_ID_RLC_G:
1724 *type = GFX_FW_TYPE_RLC_G;
1726 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1727 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
1729 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
1730 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
1732 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
1733 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
1735 case AMDGPU_UCODE_ID_SMC:
1736 *type = GFX_FW_TYPE_SMU;
1738 case AMDGPU_UCODE_ID_UVD:
1739 *type = GFX_FW_TYPE_UVD;
1741 case AMDGPU_UCODE_ID_UVD1:
1742 *type = GFX_FW_TYPE_UVD1;
1744 case AMDGPU_UCODE_ID_VCE:
1745 *type = GFX_FW_TYPE_VCE;
1747 case AMDGPU_UCODE_ID_VCN:
1748 *type = GFX_FW_TYPE_VCN;
1750 case AMDGPU_UCODE_ID_VCN1:
1751 *type = GFX_FW_TYPE_VCN1;
1753 case AMDGPU_UCODE_ID_DMCU_ERAM:
1754 *type = GFX_FW_TYPE_DMCU_ERAM;
1756 case AMDGPU_UCODE_ID_DMCU_INTV:
1757 *type = GFX_FW_TYPE_DMCU_ISR;
1759 case AMDGPU_UCODE_ID_VCN0_RAM:
1760 *type = GFX_FW_TYPE_VCN0_RAM;
1762 case AMDGPU_UCODE_ID_VCN1_RAM:
1763 *type = GFX_FW_TYPE_VCN1_RAM;
1765 case AMDGPU_UCODE_ID_DMCUB:
1766 *type = GFX_FW_TYPE_DMUB;
1768 case AMDGPU_UCODE_ID_MAXIMUM:
1776 static void psp_print_fw_hdr(struct psp_context *psp,
1777 struct amdgpu_firmware_info *ucode)
1779 struct amdgpu_device *adev = psp->adev;
1780 struct common_firmware_header *hdr;
1782 switch (ucode->ucode_id) {
1783 case AMDGPU_UCODE_ID_SDMA0:
1784 case AMDGPU_UCODE_ID_SDMA1:
1785 case AMDGPU_UCODE_ID_SDMA2:
1786 case AMDGPU_UCODE_ID_SDMA3:
1787 case AMDGPU_UCODE_ID_SDMA4:
1788 case AMDGPU_UCODE_ID_SDMA5:
1789 case AMDGPU_UCODE_ID_SDMA6:
1790 case AMDGPU_UCODE_ID_SDMA7:
1791 hdr = (struct common_firmware_header *)
1792 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1793 amdgpu_ucode_print_sdma_hdr(hdr);
1795 case AMDGPU_UCODE_ID_CP_CE:
1796 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1797 amdgpu_ucode_print_gfx_hdr(hdr);
1799 case AMDGPU_UCODE_ID_CP_PFP:
1800 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1801 amdgpu_ucode_print_gfx_hdr(hdr);
1803 case AMDGPU_UCODE_ID_CP_ME:
1804 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1805 amdgpu_ucode_print_gfx_hdr(hdr);
1807 case AMDGPU_UCODE_ID_CP_MEC1:
1808 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1809 amdgpu_ucode_print_gfx_hdr(hdr);
1811 case AMDGPU_UCODE_ID_RLC_G:
1812 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1813 amdgpu_ucode_print_rlc_hdr(hdr);
1815 case AMDGPU_UCODE_ID_SMC:
1816 hdr = (struct common_firmware_header *)adev->pm.fw->data;
1817 amdgpu_ucode_print_smc_hdr(hdr);
1824 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1825 struct psp_gfx_cmd_resp *cmd)
1828 uint64_t fw_mem_mc_addr = ucode->mc_addr;
1830 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1832 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1833 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1834 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1835 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1837 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1839 DRM_ERROR("Unknown firmware type\n");
1844 static int psp_execute_np_fw_load(struct psp_context *psp,
1845 struct amdgpu_firmware_info *ucode)
1849 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1853 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1854 psp->fence_buf_mc_addr);
1859 static int psp_load_smu_fw(struct psp_context *psp)
1862 struct amdgpu_device* adev = psp->adev;
1863 struct amdgpu_firmware_info *ucode =
1864 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1865 struct amdgpu_ras *ras = psp->ras.ras;
1867 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
1871 if (amdgpu_in_reset(adev) && ras && ras->supported) {
1872 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
1874 DRM_WARN("Failed to set MP1 state prepare for reload\n");
1878 ret = psp_execute_np_fw_load(psp, ucode);
1881 DRM_ERROR("PSP load smu failed!\n");
1886 static bool fw_load_skip_check(struct psp_context *psp,
1887 struct amdgpu_firmware_info *ucode)
1892 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1893 (psp_smu_reload_quirk(psp) ||
1894 psp->autoload_supported ||
1895 psp->pmfw_centralized_cstate_management))
1898 if (amdgpu_sriov_vf(psp->adev) &&
1899 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1900 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1901 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1902 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1903 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1904 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1905 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1906 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1907 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
1908 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
1909 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
1910 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
1911 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
1912 /*skip ucode loading in SRIOV VF */
1915 if (psp->autoload_supported &&
1916 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1917 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1918 /* skip mec JT when autoload is enabled */
1924 static int psp_np_fw_load(struct psp_context *psp)
1927 struct amdgpu_firmware_info *ucode;
1928 struct amdgpu_device* adev = psp->adev;
1930 if (psp->autoload_supported &&
1931 !psp->pmfw_centralized_cstate_management) {
1932 ret = psp_load_smu_fw(psp);
1937 for (i = 0; i < adev->firmware.max_ucodes; i++) {
1938 ucode = &adev->firmware.ucode[i];
1940 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1941 !fw_load_skip_check(psp, ucode)) {
1942 ret = psp_load_smu_fw(psp);
1948 if (fw_load_skip_check(psp, ucode))
1951 if (psp->autoload_supported &&
1952 (adev->asic_type == CHIP_SIENNA_CICHLID ||
1953 adev->asic_type == CHIP_NAVY_FLOUNDER) &&
1954 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
1955 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
1956 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
1957 /* PSP only receive one SDMA fw for sienna_cichlid,
1958 * as all four sdma fw are same */
1961 psp_print_fw_hdr(psp, ucode);
1963 ret = psp_execute_np_fw_load(psp, ucode);
1967 /* Start rlc autoload after psp recieved all the gfx firmware */
1968 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1969 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1970 ret = psp_rlc_autoload_start(psp);
1972 DRM_ERROR("Failed to start rlc autoload\n");
1981 static int psp_load_fw(struct amdgpu_device *adev)
1984 struct psp_context *psp = &adev->psp;
1986 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
1987 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1991 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1995 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1996 AMDGPU_GEM_DOMAIN_GTT,
1998 &psp->fw_pri_mc_addr,
2003 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2004 AMDGPU_GEM_DOMAIN_VRAM,
2006 &psp->fence_buf_mc_addr,
2011 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2012 AMDGPU_GEM_DOMAIN_VRAM,
2013 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2014 (void **)&psp->cmd_buf_mem);
2018 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2020 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2022 DRM_ERROR("PSP ring init failed!\n");
2027 ret = psp_hw_start(psp);
2031 ret = psp_np_fw_load(psp);
2035 ret = psp_asd_load(psp);
2037 DRM_ERROR("PSP load asd failed!\n");
2041 if (psp->adev->psp.ta_fw) {
2042 ret = psp_ras_initialize(psp);
2044 dev_err(psp->adev->dev,
2045 "RAS: Failed to initialize RAS\n");
2047 ret = psp_hdcp_initialize(psp);
2049 dev_err(psp->adev->dev,
2050 "HDCP: Failed to initialize HDCP\n");
2052 ret = psp_dtm_initialize(psp);
2054 dev_err(psp->adev->dev,
2055 "DTM: Failed to initialize DTM\n");
2057 ret = psp_rap_initialize(psp);
2059 dev_err(psp->adev->dev,
2060 "RAP: Failed to initialize RAP\n");
2067 * all cleanup jobs (xgmi terminate, ras terminate,
2068 * ring destroy, cmd/fence/fw buffers destory,
2069 * psp->cmd destory) are delayed to psp_hw_fini
2074 static int psp_hw_init(void *handle)
2077 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2079 mutex_lock(&adev->firmware.mutex);
2081 * This sequence is just used on hw_init only once, no need on
2084 ret = amdgpu_ucode_init_bo(adev);
2088 ret = psp_load_fw(adev);
2090 DRM_ERROR("PSP firmware loading failed\n");
2094 mutex_unlock(&adev->firmware.mutex);
2098 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2099 mutex_unlock(&adev->firmware.mutex);
2103 static int psp_hw_fini(void *handle)
2105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2106 struct psp_context *psp = &adev->psp;
2109 if (psp->adev->psp.ta_fw) {
2110 psp_ras_terminate(psp);
2111 psp_rap_terminate(psp);
2112 psp_dtm_terminate(psp);
2113 psp_hdcp_terminate(psp);
2116 psp_asd_unload(psp);
2117 ret = psp_clear_vf_fw(psp);
2119 DRM_ERROR("PSP clear vf fw!\n");
2123 psp_tmr_terminate(psp);
2124 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2126 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2127 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2128 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2129 &psp->fence_buf_mc_addr, &psp->fence_buf);
2130 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2131 (void **)&psp->cmd_buf_mem);
2139 static int psp_suspend(void *handle)
2142 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2143 struct psp_context *psp = &adev->psp;
2145 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2146 psp->xgmi_context.initialized == 1) {
2147 ret = psp_xgmi_terminate(psp);
2149 DRM_ERROR("Failed to terminate xgmi ta\n");
2154 if (psp->adev->psp.ta_fw) {
2155 ret = psp_ras_terminate(psp);
2157 DRM_ERROR("Failed to terminate ras ta\n");
2160 ret = psp_hdcp_terminate(psp);
2162 DRM_ERROR("Failed to terminate hdcp ta\n");
2165 ret = psp_dtm_terminate(psp);
2167 DRM_ERROR("Failed to terminate dtm ta\n");
2170 ret = psp_rap_terminate(psp);
2172 DRM_ERROR("Failed to terminate rap ta\n");
2177 ret = psp_asd_unload(psp);
2179 DRM_ERROR("Failed to unload asd\n");
2183 ret = psp_tmr_terminate(psp);
2185 DRM_ERROR("Failed to terminate tmr\n");
2189 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2191 DRM_ERROR("PSP ring stop failed\n");
2198 static int psp_resume(void *handle)
2201 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2202 struct psp_context *psp = &adev->psp;
2204 DRM_INFO("PSP is resuming...\n");
2206 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2208 DRM_ERROR("Failed to process memory training!\n");
2212 mutex_lock(&adev->firmware.mutex);
2214 ret = psp_hw_start(psp);
2218 ret = psp_np_fw_load(psp);
2222 ret = psp_asd_load(psp);
2224 DRM_ERROR("PSP load asd failed!\n");
2228 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2229 ret = psp_xgmi_initialize(psp);
2230 /* Warning the XGMI seesion initialize failure
2231 * Instead of stop driver initialization
2234 dev_err(psp->adev->dev,
2235 "XGMI: Failed to initialize XGMI session\n");
2238 if (psp->adev->psp.ta_fw) {
2239 ret = psp_ras_initialize(psp);
2241 dev_err(psp->adev->dev,
2242 "RAS: Failed to initialize RAS\n");
2244 ret = psp_hdcp_initialize(psp);
2246 dev_err(psp->adev->dev,
2247 "HDCP: Failed to initialize HDCP\n");
2249 ret = psp_dtm_initialize(psp);
2251 dev_err(psp->adev->dev,
2252 "DTM: Failed to initialize DTM\n");
2254 ret = psp_rap_initialize(psp);
2256 dev_err(psp->adev->dev,
2257 "RAP: Failed to initialize RAP\n");
2260 mutex_unlock(&adev->firmware.mutex);
2265 DRM_ERROR("PSP resume failed\n");
2266 mutex_unlock(&adev->firmware.mutex);
2270 int psp_gpu_reset(struct amdgpu_device *adev)
2274 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2277 mutex_lock(&adev->psp.mutex);
2278 ret = psp_mode1_reset(&adev->psp);
2279 mutex_unlock(&adev->psp.mutex);
2284 int psp_rlc_autoload_start(struct psp_context *psp)
2287 struct psp_gfx_cmd_resp *cmd;
2289 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2293 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2295 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2296 psp->fence_buf_mc_addr);
2301 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2302 uint64_t cmd_gpu_addr, int cmd_size)
2304 struct amdgpu_firmware_info ucode = {0};
2306 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2307 AMDGPU_UCODE_ID_VCN0_RAM;
2308 ucode.mc_addr = cmd_gpu_addr;
2309 ucode.ucode_size = cmd_size;
2311 return psp_execute_np_fw_load(&adev->psp, &ucode);
2314 int psp_ring_cmd_submit(struct psp_context *psp,
2315 uint64_t cmd_buf_mc_addr,
2316 uint64_t fence_mc_addr,
2319 unsigned int psp_write_ptr_reg = 0;
2320 struct psp_gfx_rb_frame *write_frame;
2321 struct psp_ring *ring = &psp->km_ring;
2322 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2323 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2324 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2325 struct amdgpu_device *adev = psp->adev;
2326 uint32_t ring_size_dw = ring->ring_size / 4;
2327 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2329 /* KM (GPCOM) prepare write pointer */
2330 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2332 /* Update KM RB frame pointer to new frame */
2333 /* write_frame ptr increments by size of rb_frame in bytes */
2334 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2335 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2336 write_frame = ring_buffer_start;
2338 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2339 /* Check invalid write_frame ptr address */
2340 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2341 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2342 ring_buffer_start, ring_buffer_end, write_frame);
2343 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2347 /* Initialize KM RB frame */
2348 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2350 /* Update KM RB frame */
2351 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2352 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2353 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2354 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2355 write_frame->fence_value = index;
2356 amdgpu_asic_flush_hdp(adev, NULL);
2358 /* Update the write Pointer in DWORDs */
2359 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2360 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2364 int psp_init_asd_microcode(struct psp_context *psp,
2365 const char *chip_name)
2367 struct amdgpu_device *adev = psp->adev;
2369 const struct psp_firmware_header_v1_0 *asd_hdr;
2373 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2377 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2378 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2382 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2386 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2387 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2388 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
2389 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2390 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2391 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2394 dev_err(adev->dev, "fail to initialize asd microcode\n");
2395 release_firmware(adev->psp.asd_fw);
2396 adev->psp.asd_fw = NULL;
2400 int psp_init_sos_microcode(struct psp_context *psp,
2401 const char *chip_name)
2403 struct amdgpu_device *adev = psp->adev;
2405 const struct psp_firmware_header_v1_0 *sos_hdr;
2406 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2407 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2408 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2412 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2416 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2417 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2421 err = amdgpu_ucode_validate(adev->psp.sos_fw);
2425 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2426 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2428 switch (sos_hdr->header.header_version_major) {
2430 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2431 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
2432 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
2433 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
2434 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2435 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2436 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2437 le32_to_cpu(sos_hdr->sos_offset_bytes);
2438 if (sos_hdr->header.header_version_minor == 1) {
2439 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2440 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
2441 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2442 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
2443 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
2444 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2445 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
2447 if (sos_hdr->header.header_version_minor == 2) {
2448 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2449 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
2450 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2451 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
2453 if (sos_hdr->header.header_version_minor == 3) {
2454 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2455 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
2456 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2457 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
2458 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
2459 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2460 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
2461 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
2462 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2463 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
2468 "unsupported psp sos firmware\n");
2476 "failed to init sos firmware\n");
2477 release_firmware(adev->psp.sos_fw);
2478 adev->psp.sos_fw = NULL;
2483 int parse_ta_bin_descriptor(struct psp_context *psp,
2484 const struct ta_fw_bin_desc *desc,
2485 const struct ta_firmware_header_v2_0 *ta_hdr)
2487 uint8_t *ucode_start_addr = NULL;
2489 if (!psp || !desc || !ta_hdr)
2492 ucode_start_addr = (uint8_t *)ta_hdr +
2493 le32_to_cpu(desc->offset_bytes) +
2494 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2496 switch (desc->fw_type) {
2497 case TA_FW_TYPE_PSP_ASD:
2498 psp->asd_fw_version = le32_to_cpu(desc->fw_version);
2499 psp->asd_feature_version = le32_to_cpu(desc->fw_version);
2500 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes);
2501 psp->asd_start_addr = ucode_start_addr;
2503 case TA_FW_TYPE_PSP_XGMI:
2504 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
2505 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes);
2506 psp->ta_xgmi_start_addr = ucode_start_addr;
2508 case TA_FW_TYPE_PSP_RAS:
2509 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version);
2510 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes);
2511 psp->ta_ras_start_addr = ucode_start_addr;
2513 case TA_FW_TYPE_PSP_HDCP:
2514 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
2515 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes);
2516 psp->ta_hdcp_start_addr = ucode_start_addr;
2518 case TA_FW_TYPE_PSP_DTM:
2519 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version);
2520 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes);
2521 psp->ta_dtm_start_addr = ucode_start_addr;
2523 case TA_FW_TYPE_PSP_RAP:
2524 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version);
2525 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes);
2526 psp->ta_rap_start_addr = ucode_start_addr;
2529 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
2536 int psp_init_ta_microcode(struct psp_context *psp,
2537 const char *chip_name)
2539 struct amdgpu_device *adev = psp->adev;
2541 const struct ta_firmware_header_v2_0 *ta_hdr;
2546 dev_err(adev->dev, "invalid chip name for ta microcode\n");
2550 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
2551 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
2555 err = amdgpu_ucode_validate(adev->psp.ta_fw);
2559 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
2561 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
2562 dev_err(adev->dev, "unsupported TA header version\n");
2567 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
2568 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
2573 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
2574 err = parse_ta_bin_descriptor(psp,
2575 &ta_hdr->ta_fw_bin[ta_index],
2583 dev_err(adev->dev, "fail to initialize ta microcode\n");
2584 release_firmware(adev->psp.ta_fw);
2585 adev->psp.ta_fw = NULL;
2589 static int psp_set_clockgating_state(void *handle,
2590 enum amd_clockgating_state state)
2595 static int psp_set_powergating_state(void *handle,
2596 enum amd_powergating_state state)
2601 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
2602 struct device_attribute *attr,
2605 struct drm_device *ddev = dev_get_drvdata(dev);
2606 struct amdgpu_device *adev = drm_to_adev(ddev);
2610 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2611 DRM_INFO("PSP block is not ready yet.");
2615 mutex_lock(&adev->psp.mutex);
2616 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
2617 mutex_unlock(&adev->psp.mutex);
2620 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
2624 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver);
2627 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
2628 struct device_attribute *attr,
2632 struct drm_device *ddev = dev_get_drvdata(dev);
2633 struct amdgpu_device *adev = drm_to_adev(ddev);
2635 dma_addr_t dma_addr;
2638 const struct firmware *usbc_pd_fw;
2640 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2641 DRM_INFO("PSP block is not ready yet.");
2645 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
2646 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
2650 /* We need contiguous physical mem to place the FW for psp to access */
2651 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
2653 ret = dma_mapping_error(adev->dev, dma_addr);
2657 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
2660 * x86 specific workaround.
2661 * Without it the buffer is invisible in PSP.
2663 * TODO Remove once PSP starts snooping CPU cache
2666 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
2669 mutex_lock(&adev->psp.mutex);
2670 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
2671 mutex_unlock(&adev->psp.mutex);
2674 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
2675 release_firmware(usbc_pd_fw);
2679 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
2686 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
2687 psp_usbc_pd_fw_sysfs_read,
2688 psp_usbc_pd_fw_sysfs_write);
2692 const struct amd_ip_funcs psp_ip_funcs = {
2694 .early_init = psp_early_init,
2696 .sw_init = psp_sw_init,
2697 .sw_fini = psp_sw_fini,
2698 .hw_init = psp_hw_init,
2699 .hw_fini = psp_hw_fini,
2700 .suspend = psp_suspend,
2701 .resume = psp_resume,
2703 .check_soft_reset = NULL,
2704 .wait_for_idle = NULL,
2706 .set_clockgating_state = psp_set_clockgating_state,
2707 .set_powergating_state = psp_set_powergating_state,
2710 static int psp_sysfs_init(struct amdgpu_device *adev)
2712 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
2715 DRM_ERROR("Failed to create USBC PD FW control file!");
2720 static void psp_sysfs_fini(struct amdgpu_device *adev)
2722 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
2725 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
2727 .type = AMD_IP_BLOCK_TYPE_PSP,
2731 .funcs = &psp_ip_funcs,
2734 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
2736 .type = AMD_IP_BLOCK_TYPE_PSP,
2740 .funcs = &psp_ip_funcs,
2743 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
2745 .type = AMD_IP_BLOCK_TYPE_PSP,
2749 .funcs = &psp_ip_funcs,
2752 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
2754 .type = AMD_IP_BLOCK_TYPE_PSP,
2758 .funcs = &psp_ip_funcs,