2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
40 #include "psp_v13_0_4.h"
42 #include "amdgpu_ras.h"
43 #include "amdgpu_securedisplay.h"
44 #include "amdgpu_atomfirmware.h"
46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
48 static int psp_load_smu_fw(struct psp_context *psp);
49 static int psp_rap_terminate(struct psp_context *psp);
50 static int psp_securedisplay_terminate(struct psp_context *psp);
52 static int psp_ring_init(struct psp_context *psp,
53 enum psp_ring_type ring_type)
56 struct psp_ring *ring;
57 struct amdgpu_device *adev = psp->adev;
61 ring->ring_type = ring_type;
63 /* allocate 4k Page of Local Frame Buffer memory for ring */
64 ring->ring_size = 0x1000;
65 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
66 AMDGPU_GEM_DOMAIN_VRAM |
67 AMDGPU_GEM_DOMAIN_GTT,
69 &ring->ring_mem_mc_addr,
70 (void **)&ring->ring_mem);
80 * Due to DF Cstate management centralized to PMFW, the firmware
81 * loading sequence will be updated as below:
87 * - Load other non-psp fw
89 * - Load XGMI/RAS/HDCP/DTM TA if any
91 * This new sequence is required for
92 * - Arcturus and onwards
94 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
96 struct amdgpu_device *adev = psp->adev;
98 if (amdgpu_sriov_vf(adev)) {
99 psp->pmfw_centralized_cstate_management = false;
103 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
104 case IP_VERSION(11, 0, 0):
105 case IP_VERSION(11, 0, 4):
106 case IP_VERSION(11, 0, 5):
107 case IP_VERSION(11, 0, 7):
108 case IP_VERSION(11, 0, 9):
109 case IP_VERSION(11, 0, 11):
110 case IP_VERSION(11, 0, 12):
111 case IP_VERSION(11, 0, 13):
112 case IP_VERSION(13, 0, 0):
113 case IP_VERSION(13, 0, 2):
114 case IP_VERSION(13, 0, 7):
115 psp->pmfw_centralized_cstate_management = true;
118 psp->pmfw_centralized_cstate_management = false;
123 static int psp_init_sriov_microcode(struct psp_context *psp)
125 struct amdgpu_device *adev = psp->adev;
126 char ucode_prefix[30];
129 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
131 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
132 case IP_VERSION(9, 0, 0):
133 case IP_VERSION(11, 0, 7):
134 case IP_VERSION(11, 0, 9):
135 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
136 ret = psp_init_cap_microcode(psp, ucode_prefix);
138 case IP_VERSION(13, 0, 2):
139 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
140 ret = psp_init_cap_microcode(psp, ucode_prefix);
141 ret &= psp_init_ta_microcode(psp, ucode_prefix);
143 case IP_VERSION(13, 0, 0):
144 adev->virt.autoload_ucode_id = 0;
146 case IP_VERSION(13, 0, 6):
147 ret = psp_init_cap_microcode(psp, ucode_prefix);
148 ret &= psp_init_ta_microcode(psp, ucode_prefix);
150 case IP_VERSION(13, 0, 10):
151 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
152 ret = psp_init_cap_microcode(psp, ucode_prefix);
160 static int psp_early_init(void *handle)
162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
163 struct psp_context *psp = &adev->psp;
165 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
166 case IP_VERSION(9, 0, 0):
167 psp_v3_1_set_psp_funcs(psp);
168 psp->autoload_supported = false;
170 case IP_VERSION(10, 0, 0):
171 case IP_VERSION(10, 0, 1):
172 psp_v10_0_set_psp_funcs(psp);
173 psp->autoload_supported = false;
175 case IP_VERSION(11, 0, 2):
176 case IP_VERSION(11, 0, 4):
177 psp_v11_0_set_psp_funcs(psp);
178 psp->autoload_supported = false;
180 case IP_VERSION(11, 0, 0):
181 case IP_VERSION(11, 0, 7):
182 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev);
184 case IP_VERSION(11, 0, 5):
185 case IP_VERSION(11, 0, 9):
186 case IP_VERSION(11, 0, 11):
187 case IP_VERSION(11, 5, 0):
188 case IP_VERSION(11, 0, 12):
189 case IP_VERSION(11, 0, 13):
190 psp_v11_0_set_psp_funcs(psp);
191 psp->autoload_supported = true;
193 case IP_VERSION(11, 0, 3):
194 case IP_VERSION(12, 0, 1):
195 psp_v12_0_set_psp_funcs(psp);
197 case IP_VERSION(13, 0, 2):
198 case IP_VERSION(13, 0, 6):
199 psp_v13_0_set_psp_funcs(psp);
201 case IP_VERSION(13, 0, 1):
202 case IP_VERSION(13, 0, 3):
203 case IP_VERSION(13, 0, 5):
204 case IP_VERSION(13, 0, 8):
205 case IP_VERSION(13, 0, 11):
206 case IP_VERSION(14, 0, 0):
207 psp_v13_0_set_psp_funcs(psp);
208 psp->autoload_supported = true;
210 case IP_VERSION(11, 0, 8):
211 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
212 psp_v11_0_8_set_psp_funcs(psp);
213 psp->autoload_supported = false;
216 case IP_VERSION(13, 0, 0):
217 case IP_VERSION(13, 0, 7):
218 case IP_VERSION(13, 0, 10):
219 psp_v13_0_set_psp_funcs(psp);
220 psp->autoload_supported = true;
221 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
223 case IP_VERSION(13, 0, 4):
224 psp_v13_0_4_set_psp_funcs(psp);
225 psp->autoload_supported = true;
233 psp_check_pmfw_centralized_cstate_management(psp);
235 if (amdgpu_sriov_vf(adev))
236 return psp_init_sriov_microcode(psp);
238 return psp_init_microcode(psp);
241 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
243 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
244 &mem_ctx->shared_buf);
245 mem_ctx->shared_bo = NULL;
248 static void psp_free_shared_bufs(struct psp_context *psp)
253 /* free TMR memory buffer */
254 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
255 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
258 /* free xgmi shared memory */
259 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
261 /* free ras shared memory */
262 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
264 /* free hdcp shared memory */
265 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
267 /* free dtm shared memory */
268 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
270 /* free rap shared memory */
271 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
273 /* free securedisplay shared memory */
274 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
279 static void psp_memory_training_fini(struct psp_context *psp)
281 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
283 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
284 kfree(ctx->sys_cache);
285 ctx->sys_cache = NULL;
288 static int psp_memory_training_init(struct psp_context *psp)
291 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
293 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
294 DRM_DEBUG("memory training is not supported!\n");
298 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
299 if (ctx->sys_cache == NULL) {
300 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
305 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
306 ctx->train_data_size,
307 ctx->p2c_train_data_offset,
308 ctx->c2p_train_data_offset);
309 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
313 psp_memory_training_fini(psp);
318 * Helper funciton to query psp runtime database entry
320 * @adev: amdgpu_device pointer
321 * @entry_type: the type of psp runtime database entry
322 * @db_entry: runtime database entry pointer
324 * Return false if runtime database doesn't exit or entry is invalid
325 * or true if the specific database entry is found, and copy to @db_entry
327 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
328 enum psp_runtime_entry_type entry_type,
331 uint64_t db_header_pos, db_dir_pos;
332 struct psp_runtime_data_header db_header = {0};
333 struct psp_runtime_data_directory db_dir = {0};
337 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6))
340 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
341 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
343 /* read runtime db header from vram */
344 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
345 sizeof(struct psp_runtime_data_header), false);
347 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
348 /* runtime db doesn't exist, exit */
349 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
353 /* read runtime database entry from vram */
354 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
355 sizeof(struct psp_runtime_data_directory), false);
357 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
358 /* invalid db entry count, exit */
359 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
363 /* look up for requested entry type */
364 for (i = 0; i < db_dir.entry_count && !ret; i++) {
365 if (db_dir.entry_list[i].entry_type == entry_type) {
366 switch (entry_type) {
367 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
368 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
369 /* invalid db entry size */
370 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
373 /* read runtime database entry */
374 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
375 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
378 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
379 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
380 /* invalid db entry size */
381 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
384 /* read runtime database entry */
385 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
386 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
399 static int psp_sw_init(void *handle)
401 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
402 struct psp_context *psp = &adev->psp;
404 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
405 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
406 struct psp_runtime_scpm_entry scpm_entry;
408 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
410 DRM_ERROR("Failed to allocate memory to command buffer!\n");
414 adev->psp.xgmi_context.supports_extended_data =
415 !adev->gmc.xgmi.connected_to_cpu &&
416 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2);
418 memset(&scpm_entry, 0, sizeof(scpm_entry));
419 if ((psp_get_runtime_db_entry(adev,
420 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
422 (scpm_entry.scpm_status != SCPM_DISABLE)) {
423 adev->scpm_enabled = true;
424 adev->scpm_status = scpm_entry.scpm_status;
426 adev->scpm_enabled = false;
427 adev->scpm_status = SCPM_DISABLE;
430 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
432 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
433 if (psp_get_runtime_db_entry(adev,
434 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
436 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
437 if ((psp->boot_cfg_bitmask) &
438 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
439 /* If psp runtime database exists, then
440 * only enable two stage memory training
441 * when TWO_STAGE_DRAM_TRAINING bit is set
442 * in runtime database
444 mem_training_ctx->enable_mem_training = true;
448 /* If psp runtime database doesn't exist or is
449 * invalid, force enable two stage memory training
451 mem_training_ctx->enable_mem_training = true;
454 if (mem_training_ctx->enable_mem_training) {
455 ret = psp_memory_training_init(psp);
457 DRM_ERROR("Failed to initialize memory training!\n");
461 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
463 DRM_ERROR("Failed to process memory training!\n");
468 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
469 amdgpu_sriov_vf(adev) ?
470 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
472 &psp->fw_pri_mc_addr,
477 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
478 AMDGPU_GEM_DOMAIN_VRAM |
479 AMDGPU_GEM_DOMAIN_GTT,
481 &psp->fence_buf_mc_addr,
486 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
487 AMDGPU_GEM_DOMAIN_VRAM |
488 AMDGPU_GEM_DOMAIN_GTT,
489 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
490 (void **)&psp->cmd_buf_mem);
497 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
498 &psp->fence_buf_mc_addr, &psp->fence_buf);
500 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
501 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
505 static int psp_sw_fini(void *handle)
507 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
508 struct psp_context *psp = &adev->psp;
509 struct psp_gfx_cmd_resp *cmd = psp->cmd;
511 psp_memory_training_fini(psp);
513 amdgpu_ucode_release(&psp->sos_fw);
514 amdgpu_ucode_release(&psp->asd_fw);
515 amdgpu_ucode_release(&psp->ta_fw);
516 amdgpu_ucode_release(&psp->cap_fw);
517 amdgpu_ucode_release(&psp->toc_fw);
522 psp_free_shared_bufs(psp);
524 if (psp->km_ring.ring_mem)
525 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
526 &psp->km_ring.ring_mem_mc_addr,
527 (void **)&psp->km_ring.ring_mem);
529 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
530 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
531 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
532 &psp->fence_buf_mc_addr, &psp->fence_buf);
533 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
534 (void **)&psp->cmd_buf_mem);
539 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
540 uint32_t reg_val, uint32_t mask, bool check_changed)
544 struct amdgpu_device *adev = psp->adev;
546 if (psp->adev->no_hw_access)
549 for (i = 0; i < adev->usec_timeout; i++) {
550 val = RREG32(reg_index);
555 if ((val & mask) == reg_val)
564 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
565 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
569 struct amdgpu_device *adev = psp->adev;
571 if (psp->adev->no_hw_access)
574 for (i = 0; i < msec_timeout; i++) {
575 val = RREG32(reg_index);
576 if ((val & mask) == reg_val)
584 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
587 case GFX_CMD_ID_LOAD_TA:
589 case GFX_CMD_ID_UNLOAD_TA:
591 case GFX_CMD_ID_INVOKE_CMD:
593 case GFX_CMD_ID_LOAD_ASD:
595 case GFX_CMD_ID_SETUP_TMR:
597 case GFX_CMD_ID_LOAD_IP_FW:
599 case GFX_CMD_ID_DESTROY_TMR:
600 return "DESTROY_TMR";
601 case GFX_CMD_ID_SAVE_RESTORE:
602 return "SAVE_RESTORE_IP_FW";
603 case GFX_CMD_ID_SETUP_VMR:
605 case GFX_CMD_ID_DESTROY_VMR:
606 return "DESTROY_VMR";
607 case GFX_CMD_ID_PROG_REG:
609 case GFX_CMD_ID_GET_FW_ATTESTATION:
610 return "GET_FW_ATTESTATION";
611 case GFX_CMD_ID_LOAD_TOC:
612 return "ID_LOAD_TOC";
613 case GFX_CMD_ID_AUTOLOAD_RLC:
614 return "AUTOLOAD_RLC";
615 case GFX_CMD_ID_BOOT_CFG:
618 return "UNKNOWN CMD";
623 psp_cmd_submit_buf(struct psp_context *psp,
624 struct amdgpu_firmware_info *ucode,
625 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
630 bool ras_intr = false;
631 bool skip_unsupport = false;
633 if (psp->adev->no_hw_access)
636 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
638 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
640 index = atomic_inc_return(&psp->fence_value);
641 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
643 atomic_dec(&psp->fence_value);
647 amdgpu_device_invalidate_hdp(psp->adev, NULL);
648 while (*((unsigned int *)psp->fence_buf) != index) {
652 * Shouldn't wait for timeout when err_event_athub occurs,
653 * because gpu reset thread triggered and lock resource should
654 * be released for psp resume sequence.
656 ras_intr = amdgpu_ras_intr_triggered();
659 usleep_range(10, 100);
660 amdgpu_device_invalidate_hdp(psp->adev, NULL);
663 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
664 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
665 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
667 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
669 /* In some cases, psp response status is not 0 even there is no
670 * problem while the command is submitted. Some version of PSP FW
671 * doesn't write 0 to that field.
672 * So here we would like to only print a warning instead of an error
673 * during psp initialization to avoid breaking hw_init and it doesn't
676 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
678 DRM_WARN("failed to load ucode %s(0x%X) ",
679 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
680 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
681 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
682 psp->cmd_buf_mem->resp.status);
683 /* If any firmware (including CAP) load fails under SRIOV, it should
684 * return failure to stop the VF from initializing.
685 * Also return failure in case of timeout
687 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
694 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
695 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
702 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
704 struct psp_gfx_cmd_resp *cmd = psp->cmd;
706 mutex_lock(&psp->mutex);
708 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
713 static void release_psp_cmd_buf(struct psp_context *psp)
715 mutex_unlock(&psp->mutex);
718 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
719 struct psp_gfx_cmd_resp *cmd,
720 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
722 struct amdgpu_device *adev = psp->adev;
727 size = amdgpu_bo_size(tmr_bo);
728 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
731 if (amdgpu_sriov_vf(psp->adev))
732 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
734 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
735 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
736 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
737 cmd->cmd.cmd_setup_tmr.buf_size = size;
738 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
739 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
740 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
743 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
744 uint64_t pri_buf_mc, uint32_t size)
746 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
747 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
748 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
749 cmd->cmd.cmd_load_toc.toc_size = size;
752 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
753 static int psp_load_toc(struct psp_context *psp,
757 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
759 /* Copy toc to psp firmware private buffer */
760 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
762 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
764 ret = psp_cmd_submit_buf(psp, NULL, cmd,
765 psp->fence_buf_mc_addr);
767 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
769 release_psp_cmd_buf(psp);
774 static bool psp_boottime_tmr(struct psp_context *psp)
776 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
777 case IP_VERSION(13, 0, 6):
784 /* Set up Trusted Memory Region */
785 static int psp_tmr_init(struct psp_context *psp)
793 * According to HW engineer, they prefer the TMR address be "naturally
794 * aligned" , e.g. the start address be an integer divide of TMR size.
796 * Note: this memory need be reserved till the driver
799 tmr_size = PSP_TMR_SIZE(psp->adev);
801 /* For ASICs support RLC autoload, psp will parse the toc
802 * and calculate the total size of TMR needed
804 if (!amdgpu_sriov_vf(psp->adev) &&
805 psp->toc.start_addr &&
806 psp->toc.size_bytes &&
808 ret = psp_load_toc(psp, &tmr_size);
810 DRM_ERROR("Failed to load toc\n");
816 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
817 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
819 AMDGPU_HAS_VRAM(psp->adev) ?
820 AMDGPU_GEM_DOMAIN_VRAM :
821 AMDGPU_GEM_DOMAIN_GTT,
822 &psp->tmr_bo, &psp->tmr_mc_addr,
829 static bool psp_skip_tmr(struct psp_context *psp)
831 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
832 case IP_VERSION(11, 0, 9):
833 case IP_VERSION(11, 0, 7):
834 case IP_VERSION(13, 0, 2):
835 case IP_VERSION(13, 0, 6):
836 case IP_VERSION(13, 0, 10):
843 static int psp_tmr_load(struct psp_context *psp)
846 struct psp_gfx_cmd_resp *cmd;
848 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
849 * Already set up by host driver.
851 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
854 cmd = acquire_psp_cmd_buf(psp);
856 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
858 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
859 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
861 ret = psp_cmd_submit_buf(psp, NULL, cmd,
862 psp->fence_buf_mc_addr);
864 release_psp_cmd_buf(psp);
869 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
870 struct psp_gfx_cmd_resp *cmd)
872 if (amdgpu_sriov_vf(psp->adev))
873 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
875 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
878 static int psp_tmr_unload(struct psp_context *psp)
881 struct psp_gfx_cmd_resp *cmd;
883 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
884 * as TMR is not loaded at all
886 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
889 cmd = acquire_psp_cmd_buf(psp);
891 psp_prep_tmr_unload_cmd_buf(psp, cmd);
892 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
894 ret = psp_cmd_submit_buf(psp, NULL, cmd,
895 psp->fence_buf_mc_addr);
897 release_psp_cmd_buf(psp);
902 static int psp_tmr_terminate(struct psp_context *psp)
904 return psp_tmr_unload(psp);
907 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
908 uint64_t *output_ptr)
911 struct psp_gfx_cmd_resp *cmd;
916 if (amdgpu_sriov_vf(psp->adev))
919 cmd = acquire_psp_cmd_buf(psp);
921 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
923 ret = psp_cmd_submit_buf(psp, NULL, cmd,
924 psp->fence_buf_mc_addr);
927 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
928 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
931 release_psp_cmd_buf(psp);
936 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
938 struct psp_context *psp = &adev->psp;
939 struct psp_gfx_cmd_resp *cmd;
942 if (amdgpu_sriov_vf(adev))
945 cmd = acquire_psp_cmd_buf(psp);
947 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
948 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
950 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
953 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
956 release_psp_cmd_buf(psp);
961 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
964 struct psp_context *psp = &adev->psp;
965 struct psp_gfx_cmd_resp *cmd;
967 if (amdgpu_sriov_vf(adev))
970 cmd = acquire_psp_cmd_buf(psp);
972 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
973 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
974 cmd->cmd.boot_cfg.boot_config = boot_cfg;
975 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
977 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
979 release_psp_cmd_buf(psp);
984 static int psp_rl_load(struct amdgpu_device *adev)
987 struct psp_context *psp = &adev->psp;
988 struct psp_gfx_cmd_resp *cmd;
990 if (!is_psp_fw_valid(psp->rl))
993 cmd = acquire_psp_cmd_buf(psp);
995 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
996 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
998 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
999 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
1000 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
1001 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
1002 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1004 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1006 release_psp_cmd_buf(psp);
1011 int psp_spatial_partition(struct psp_context *psp, int mode)
1013 struct psp_gfx_cmd_resp *cmd;
1016 if (amdgpu_sriov_vf(psp->adev))
1019 cmd = acquire_psp_cmd_buf(psp);
1021 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1022 cmd->cmd.cmd_spatial_part.mode = mode;
1024 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1025 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1027 release_psp_cmd_buf(psp);
1032 static int psp_asd_initialize(struct psp_context *psp)
1036 /* If PSP version doesn't match ASD version, asd loading will be failed.
1037 * add workaround to bypass it for sriov now.
1038 * TODO: add version check to make it common
1040 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1043 psp->asd_context.mem_context.shared_mc_addr = 0;
1044 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1045 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
1047 ret = psp_ta_load(psp, &psp->asd_context);
1049 psp->asd_context.initialized = true;
1054 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1055 uint32_t session_id)
1057 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1058 cmd->cmd.cmd_unload_ta.session_id = session_id;
1061 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1064 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1066 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1068 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1070 context->resp_status = cmd->resp.status;
1072 release_psp_cmd_buf(psp);
1077 static int psp_asd_terminate(struct psp_context *psp)
1081 if (amdgpu_sriov_vf(psp->adev))
1084 if (!psp->asd_context.initialized)
1087 ret = psp_ta_unload(psp, &psp->asd_context);
1089 psp->asd_context.initialized = false;
1094 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1095 uint32_t id, uint32_t value)
1097 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1098 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1099 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1102 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1105 struct psp_gfx_cmd_resp *cmd;
1108 if (reg >= PSP_REG_LAST)
1111 cmd = acquire_psp_cmd_buf(psp);
1113 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1114 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1116 DRM_ERROR("PSP failed to program reg id %d", reg);
1118 release_psp_cmd_buf(psp);
1123 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1125 struct ta_context *context)
1127 cmd->cmd_id = context->ta_load_type;
1128 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1129 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1130 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1132 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1133 lower_32_bits(context->mem_context.shared_mc_addr);
1134 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1135 upper_32_bits(context->mem_context.shared_mc_addr);
1136 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1139 int psp_ta_init_shared_buf(struct psp_context *psp,
1140 struct ta_mem_context *mem_ctx)
1143 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1144 * physical) for ta to host memory
1146 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1147 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1148 AMDGPU_GEM_DOMAIN_GTT,
1149 &mem_ctx->shared_bo,
1150 &mem_ctx->shared_mc_addr,
1151 &mem_ctx->shared_buf);
1154 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1156 uint32_t session_id)
1158 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1159 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1160 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1163 int psp_ta_invoke(struct psp_context *psp,
1165 struct ta_context *context)
1168 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1170 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1172 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1173 psp->fence_buf_mc_addr);
1175 context->resp_status = cmd->resp.status;
1177 release_psp_cmd_buf(psp);
1182 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1185 struct psp_gfx_cmd_resp *cmd;
1187 cmd = acquire_psp_cmd_buf(psp);
1189 psp_copy_fw(psp, context->bin_desc.start_addr,
1190 context->bin_desc.size_bytes);
1192 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1194 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1195 psp->fence_buf_mc_addr);
1197 context->resp_status = cmd->resp.status;
1200 context->session_id = cmd->resp.session_id;
1202 release_psp_cmd_buf(psp);
1207 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1209 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1212 int psp_xgmi_terminate(struct psp_context *psp)
1215 struct amdgpu_device *adev = psp->adev;
1217 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1218 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
1219 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
1220 adev->gmc.xgmi.connected_to_cpu))
1223 if (!psp->xgmi_context.context.initialized)
1226 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1228 psp->xgmi_context.context.initialized = false;
1233 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1235 struct ta_xgmi_shared_memory *xgmi_cmd;
1239 !psp->xgmi_context.context.bin_desc.size_bytes ||
1240 !psp->xgmi_context.context.bin_desc.start_addr)
1246 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1247 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1249 if (!psp->xgmi_context.context.mem_context.shared_buf) {
1250 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1256 ret = psp_ta_load(psp, &psp->xgmi_context.context);
1258 psp->xgmi_context.context.initialized = true;
1263 /* Initialize XGMI session */
1264 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1265 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1266 xgmi_cmd->flag_extend_link_record = set_extended_data;
1267 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1269 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1270 /* note down the capbility flag for XGMI TA */
1271 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag;
1276 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1278 struct ta_xgmi_shared_memory *xgmi_cmd;
1281 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1282 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1284 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1286 /* Invoke xgmi ta to get hive id */
1287 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1291 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1296 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1298 struct ta_xgmi_shared_memory *xgmi_cmd;
1301 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1302 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1304 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1306 /* Invoke xgmi ta to get the node id */
1307 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1311 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1316 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1318 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1319 IP_VERSION(13, 0, 2) &&
1320 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1321 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >=
1322 IP_VERSION(13, 0, 6);
1326 * Chips that support extended topology information require the driver to
1327 * reflect topology information in the opposite direction. This is
1328 * because the TA has already exceeded its link record limit and if the
1329 * TA holds bi-directional information, the driver would have to do
1330 * multiple fetches instead of just two.
1332 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1333 struct psp_xgmi_node_info node_info)
1335 struct amdgpu_device *mirror_adev;
1336 struct amdgpu_hive_info *hive;
1337 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1338 uint64_t dst_node_id = node_info.node_id;
1339 uint8_t dst_num_hops = node_info.num_hops;
1340 uint8_t dst_num_links = node_info.num_links;
1342 hive = amdgpu_get_xgmi_hive(psp->adev);
1343 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1344 struct psp_xgmi_topology_info *mirror_top_info;
1347 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1350 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1351 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1352 if (mirror_top_info->nodes[j].node_id != src_node_id)
1355 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1357 * prevent 0 num_links value re-reflection since reflection
1358 * criteria is based on num_hops (direct or indirect).
1362 mirror_top_info->nodes[j].num_links = dst_num_links;
1370 amdgpu_put_xgmi_hive(hive);
1373 int psp_xgmi_get_topology_info(struct psp_context *psp,
1375 struct psp_xgmi_topology_info *topology,
1376 bool get_extended_data)
1378 struct ta_xgmi_shared_memory *xgmi_cmd;
1379 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1380 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1384 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1387 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1388 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1389 xgmi_cmd->flag_extend_link_record = get_extended_data;
1391 /* Fill in the shared memory with topology information as input */
1392 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1393 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO;
1394 topology_info_input->num_nodes = number_devices;
1396 for (i = 0; i < topology_info_input->num_nodes; i++) {
1397 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1398 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1399 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1400 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1403 /* Invoke xgmi ta to get the topology information */
1404 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO);
1408 /* Read the output topology information from the shared memory */
1409 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1410 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1411 for (i = 0; i < topology->num_nodes; i++) {
1412 /* extended data will either be 0 or equal to non-extended data */
1413 if (topology_info_output->nodes[i].num_hops)
1414 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1416 /* non-extended data gets everything here so no need to update */
1417 if (!get_extended_data) {
1418 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1419 topology->nodes[i].is_sharing_enabled =
1420 topology_info_output->nodes[i].is_sharing_enabled;
1421 topology->nodes[i].sdma_engine =
1422 topology_info_output->nodes[i].sdma_engine;
1427 /* Invoke xgmi ta again to get the link information */
1428 if (psp_xgmi_peer_link_info_supported(psp)) {
1429 struct ta_xgmi_cmd_get_peer_link_info *link_info_output;
1430 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output;
1431 bool requires_reflection =
1432 (psp->xgmi_context.supports_extended_data &&
1433 get_extended_data) ||
1434 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1435 IP_VERSION(13, 0, 6);
1436 bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps &
1437 EXTEND_PEER_LINK_INFO_CMD_FLAG;
1439 /* popluate the shared output buffer rather than the cmd input buffer
1440 * with node_ids as the input for GET_PEER_LINKS command execution.
1441 * This is required for GET_PEER_LINKS per xgmi ta implementation.
1442 * The same requirement for GET_EXTEND_PEER_LINKS command.
1444 if (ta_port_num_support) {
1445 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info;
1447 for (i = 0; i < topology->num_nodes; i++)
1448 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id;
1450 link_extend_info_output->num_nodes = topology->num_nodes;
1451 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS;
1453 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1455 for (i = 0; i < topology->num_nodes; i++)
1456 link_info_output->nodes[i].node_id = topology->nodes[i].node_id;
1458 link_info_output->num_nodes = topology->num_nodes;
1459 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1462 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1466 for (i = 0; i < topology->num_nodes; i++) {
1467 uint8_t node_num_links = ta_port_num_support ?
1468 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links;
1469 /* accumulate num_links on extended data */
1470 if (get_extended_data) {
1471 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links;
1473 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ?
1474 topology->nodes[i].num_links : node_num_links;
1477 /* reflect the topology information for bi-directionality */
1478 if (requires_reflection && topology->nodes[i].num_hops)
1479 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1486 int psp_xgmi_set_topology_info(struct psp_context *psp,
1488 struct psp_xgmi_topology_info *topology)
1490 struct ta_xgmi_shared_memory *xgmi_cmd;
1491 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1494 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1497 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1498 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1500 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1501 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1502 topology_info_input->num_nodes = number_devices;
1504 for (i = 0; i < topology_info_input->num_nodes; i++) {
1505 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1506 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1507 topology_info_input->nodes[i].is_sharing_enabled = 1;
1508 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1511 /* Invoke xgmi ta to set topology information */
1512 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1516 static void psp_ras_ta_check_status(struct psp_context *psp)
1518 struct ta_ras_shared_memory *ras_cmd =
1519 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1521 switch (ras_cmd->ras_status) {
1522 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1523 dev_warn(psp->adev->dev,
1524 "RAS WARNING: cmd failed due to unsupported ip\n");
1526 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1527 dev_warn(psp->adev->dev,
1528 "RAS WARNING: cmd failed due to unsupported error injection\n");
1530 case TA_RAS_STATUS__SUCCESS:
1532 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1533 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1534 dev_warn(psp->adev->dev,
1535 "RAS WARNING: Inject error to critical region is not allowed\n");
1538 dev_warn(psp->adev->dev,
1539 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1544 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1546 struct ta_ras_shared_memory *ras_cmd;
1549 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1552 * TODO: bypass the loading in sriov for now
1554 if (amdgpu_sriov_vf(psp->adev))
1557 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1559 if (amdgpu_ras_intr_triggered())
1562 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1563 DRM_WARN("RAS: Unsupported Interface");
1568 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1569 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1571 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1572 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1573 dev_warn(psp->adev->dev,
1574 "RAS internal register access blocked\n");
1576 psp_ras_ta_check_status(psp);
1582 int psp_ras_enable_features(struct psp_context *psp,
1583 union ta_ras_cmd_input *info, bool enable)
1585 struct ta_ras_shared_memory *ras_cmd;
1588 if (!psp->ras_context.context.initialized)
1591 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1592 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1595 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1597 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1599 ras_cmd->ras_in_message = *info;
1601 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1608 int psp_ras_terminate(struct psp_context *psp)
1613 * TODO: bypass the terminate in sriov for now
1615 if (amdgpu_sriov_vf(psp->adev))
1618 if (!psp->ras_context.context.initialized)
1621 ret = psp_ta_unload(psp, &psp->ras_context.context);
1623 psp->ras_context.context.initialized = false;
1628 int psp_ras_initialize(struct psp_context *psp)
1631 uint32_t boot_cfg = 0xFF;
1632 struct amdgpu_device *adev = psp->adev;
1633 struct ta_ras_shared_memory *ras_cmd;
1636 * TODO: bypass the initialize in sriov for now
1638 if (amdgpu_sriov_vf(adev))
1641 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1642 !adev->psp.ras_context.context.bin_desc.start_addr) {
1643 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1647 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1648 /* query GECC enablement status from boot config
1649 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1651 ret = psp_boot_config_get(adev, &boot_cfg);
1653 dev_warn(adev->dev, "PSP get boot config failed\n");
1655 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1657 dev_info(adev->dev, "GECC is disabled\n");
1659 /* disable GECC in next boot cycle if ras is
1660 * disabled by module parameter amdgpu_ras_enable
1661 * and/or amdgpu_ras_mask, or boot_config_get call
1664 ret = psp_boot_config_set(adev, 0);
1666 dev_warn(adev->dev, "PSP set boot config failed\n");
1668 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1671 if (boot_cfg == 1) {
1672 dev_info(adev->dev, "GECC is enabled\n");
1674 /* enable GECC in next boot cycle if it is disabled
1675 * in boot config, or force enable GECC if failed to
1676 * get boot configuration
1678 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1680 dev_warn(adev->dev, "PSP set boot config failed\n");
1682 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1687 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1688 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1690 if (!psp->ras_context.context.mem_context.shared_buf) {
1691 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1696 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1697 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1699 if (amdgpu_ras_is_poison_mode_supported(adev))
1700 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1701 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1702 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1703 ras_cmd->ras_in_message.init_flags.xcc_mask =
1705 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1707 ret = psp_ta_load(psp, &psp->ras_context.context);
1709 if (!ret && !ras_cmd->ras_status)
1710 psp->ras_context.context.initialized = true;
1712 if (ras_cmd->ras_status)
1713 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1715 /* fail to load RAS TA */
1716 psp->ras_context.context.initialized = false;
1722 int psp_ras_trigger_error(struct psp_context *psp,
1723 struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1725 struct ta_ras_shared_memory *ras_cmd;
1726 struct amdgpu_device *adev = psp->adev;
1730 if (!psp->ras_context.context.initialized)
1733 switch (info->block_id) {
1734 case TA_RAS_BLOCK__GFX:
1735 dev_mask = GET_MASK(GC, instance_mask);
1737 case TA_RAS_BLOCK__SDMA:
1738 dev_mask = GET_MASK(SDMA0, instance_mask);
1740 case TA_RAS_BLOCK__VCN:
1741 case TA_RAS_BLOCK__JPEG:
1742 dev_mask = GET_MASK(VCN, instance_mask);
1745 dev_mask = instance_mask;
1749 /* reuse sub_block_index for backward compatibility */
1750 dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1751 dev_mask &= AMDGPU_RAS_INST_MASK;
1752 info->sub_block_index |= dev_mask;
1754 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1755 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1757 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1758 ras_cmd->ras_in_message.trigger_error = *info;
1760 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1764 /* If err_event_athub occurs error inject was successful, however
1765 * return status from TA is no long reliable
1767 if (amdgpu_ras_intr_triggered())
1770 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1772 else if (ras_cmd->ras_status)
1780 static int psp_hdcp_initialize(struct psp_context *psp)
1785 * TODO: bypass the initialize in sriov for now
1787 if (amdgpu_sriov_vf(psp->adev))
1790 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1791 !psp->hdcp_context.context.bin_desc.start_addr) {
1792 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1796 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1797 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1799 if (!psp->hdcp_context.context.mem_context.shared_buf) {
1800 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1805 ret = psp_ta_load(psp, &psp->hdcp_context.context);
1807 psp->hdcp_context.context.initialized = true;
1808 mutex_init(&psp->hdcp_context.mutex);
1814 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1817 * TODO: bypass the loading in sriov for now
1819 if (amdgpu_sriov_vf(psp->adev))
1822 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1825 static int psp_hdcp_terminate(struct psp_context *psp)
1830 * TODO: bypass the terminate in sriov for now
1832 if (amdgpu_sriov_vf(psp->adev))
1835 if (!psp->hdcp_context.context.initialized)
1838 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1840 psp->hdcp_context.context.initialized = false;
1847 static int psp_dtm_initialize(struct psp_context *psp)
1852 * TODO: bypass the initialize in sriov for now
1854 if (amdgpu_sriov_vf(psp->adev))
1857 if (!psp->dtm_context.context.bin_desc.size_bytes ||
1858 !psp->dtm_context.context.bin_desc.start_addr) {
1859 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1863 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1864 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1866 if (!psp->dtm_context.context.mem_context.shared_buf) {
1867 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1872 ret = psp_ta_load(psp, &psp->dtm_context.context);
1874 psp->dtm_context.context.initialized = true;
1875 mutex_init(&psp->dtm_context.mutex);
1881 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1884 * TODO: bypass the loading in sriov for now
1886 if (amdgpu_sriov_vf(psp->adev))
1889 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1892 static int psp_dtm_terminate(struct psp_context *psp)
1897 * TODO: bypass the terminate in sriov for now
1899 if (amdgpu_sriov_vf(psp->adev))
1902 if (!psp->dtm_context.context.initialized)
1905 ret = psp_ta_unload(psp, &psp->dtm_context.context);
1907 psp->dtm_context.context.initialized = false;
1914 static int psp_rap_initialize(struct psp_context *psp)
1917 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1920 * TODO: bypass the initialize in sriov for now
1922 if (amdgpu_sriov_vf(psp->adev))
1925 if (!psp->rap_context.context.bin_desc.size_bytes ||
1926 !psp->rap_context.context.bin_desc.start_addr) {
1927 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1931 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1932 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1934 if (!psp->rap_context.context.mem_context.shared_buf) {
1935 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1940 ret = psp_ta_load(psp, &psp->rap_context.context);
1942 psp->rap_context.context.initialized = true;
1943 mutex_init(&psp->rap_context.mutex);
1947 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1948 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1949 psp_rap_terminate(psp);
1950 /* free rap shared memory */
1951 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1953 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1962 static int psp_rap_terminate(struct psp_context *psp)
1966 if (!psp->rap_context.context.initialized)
1969 ret = psp_ta_unload(psp, &psp->rap_context.context);
1971 psp->rap_context.context.initialized = false;
1976 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1978 struct ta_rap_shared_memory *rap_cmd;
1981 if (!psp->rap_context.context.initialized)
1984 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1985 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1988 mutex_lock(&psp->rap_context.mutex);
1990 rap_cmd = (struct ta_rap_shared_memory *)
1991 psp->rap_context.context.mem_context.shared_buf;
1992 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1994 rap_cmd->cmd_id = ta_cmd_id;
1995 rap_cmd->validation_method_id = METHOD_A;
1997 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
2002 *status = rap_cmd->rap_status;
2005 mutex_unlock(&psp->rap_context.mutex);
2011 /* securedisplay start */
2012 static int psp_securedisplay_initialize(struct psp_context *psp)
2015 struct ta_securedisplay_cmd *securedisplay_cmd;
2018 * TODO: bypass the initialize in sriov for now
2020 if (amdgpu_sriov_vf(psp->adev))
2023 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
2024 !psp->securedisplay_context.context.bin_desc.start_addr) {
2025 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2029 psp->securedisplay_context.context.mem_context.shared_mem_size =
2030 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
2031 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2033 if (!psp->securedisplay_context.context.initialized) {
2034 ret = psp_ta_init_shared_buf(psp,
2035 &psp->securedisplay_context.context.mem_context);
2040 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2042 psp->securedisplay_context.context.initialized = true;
2043 mutex_init(&psp->securedisplay_context.mutex);
2047 mutex_lock(&psp->securedisplay_context.mutex);
2049 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2050 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2052 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2054 mutex_unlock(&psp->securedisplay_context.mutex);
2057 psp_securedisplay_terminate(psp);
2058 /* free securedisplay shared memory */
2059 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2060 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2064 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2065 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2066 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2067 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2068 /* don't try again */
2069 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2075 static int psp_securedisplay_terminate(struct psp_context *psp)
2080 * TODO:bypass the terminate in sriov for now
2082 if (amdgpu_sriov_vf(psp->adev))
2085 if (!psp->securedisplay_context.context.initialized)
2088 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2090 psp->securedisplay_context.context.initialized = false;
2095 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2099 if (!psp->securedisplay_context.context.initialized)
2102 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2103 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2106 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2110 /* SECUREDISPLAY end */
2112 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev)
2114 struct psp_context *psp = &adev->psp;
2117 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL)
2118 ret = psp->funcs->wait_for_bootloader(psp);
2123 static int psp_hw_start(struct psp_context *psp)
2125 struct amdgpu_device *adev = psp->adev;
2128 if (!amdgpu_sriov_vf(adev)) {
2129 if ((is_psp_fw_valid(psp->kdb)) &&
2130 (psp->funcs->bootloader_load_kdb != NULL)) {
2131 ret = psp_bootloader_load_kdb(psp);
2133 DRM_ERROR("PSP load kdb failed!\n");
2138 if ((is_psp_fw_valid(psp->spl)) &&
2139 (psp->funcs->bootloader_load_spl != NULL)) {
2140 ret = psp_bootloader_load_spl(psp);
2142 DRM_ERROR("PSP load spl failed!\n");
2147 if ((is_psp_fw_valid(psp->sys)) &&
2148 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2149 ret = psp_bootloader_load_sysdrv(psp);
2151 DRM_ERROR("PSP load sys drv failed!\n");
2156 if ((is_psp_fw_valid(psp->soc_drv)) &&
2157 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2158 ret = psp_bootloader_load_soc_drv(psp);
2160 DRM_ERROR("PSP load soc drv failed!\n");
2165 if ((is_psp_fw_valid(psp->intf_drv)) &&
2166 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2167 ret = psp_bootloader_load_intf_drv(psp);
2169 DRM_ERROR("PSP load intf drv failed!\n");
2174 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2175 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2176 ret = psp_bootloader_load_dbg_drv(psp);
2178 DRM_ERROR("PSP load dbg drv failed!\n");
2183 if ((is_psp_fw_valid(psp->ras_drv)) &&
2184 (psp->funcs->bootloader_load_ras_drv != NULL)) {
2185 ret = psp_bootloader_load_ras_drv(psp);
2187 DRM_ERROR("PSP load ras_drv failed!\n");
2192 if ((is_psp_fw_valid(psp->sos)) &&
2193 (psp->funcs->bootloader_load_sos != NULL)) {
2194 ret = psp_bootloader_load_sos(psp);
2196 DRM_ERROR("PSP load sos failed!\n");
2202 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2204 DRM_ERROR("PSP create ring failed!\n");
2208 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2211 if (!psp_boottime_tmr(psp)) {
2212 ret = psp_tmr_init(psp);
2214 DRM_ERROR("PSP tmr init failed!\n");
2221 * For ASICs with DF Cstate management centralized
2222 * to PMFW, TMR setup should be performed after PMFW
2223 * loaded and before other non-psp firmware loaded.
2225 if (psp->pmfw_centralized_cstate_management) {
2226 ret = psp_load_smu_fw(psp);
2231 ret = psp_tmr_load(psp);
2233 DRM_ERROR("PSP load tmr failed!\n");
2240 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2241 enum psp_gfx_fw_type *type)
2243 switch (ucode->ucode_id) {
2244 case AMDGPU_UCODE_ID_CAP:
2245 *type = GFX_FW_TYPE_CAP;
2247 case AMDGPU_UCODE_ID_SDMA0:
2248 *type = GFX_FW_TYPE_SDMA0;
2250 case AMDGPU_UCODE_ID_SDMA1:
2251 *type = GFX_FW_TYPE_SDMA1;
2253 case AMDGPU_UCODE_ID_SDMA2:
2254 *type = GFX_FW_TYPE_SDMA2;
2256 case AMDGPU_UCODE_ID_SDMA3:
2257 *type = GFX_FW_TYPE_SDMA3;
2259 case AMDGPU_UCODE_ID_SDMA4:
2260 *type = GFX_FW_TYPE_SDMA4;
2262 case AMDGPU_UCODE_ID_SDMA5:
2263 *type = GFX_FW_TYPE_SDMA5;
2265 case AMDGPU_UCODE_ID_SDMA6:
2266 *type = GFX_FW_TYPE_SDMA6;
2268 case AMDGPU_UCODE_ID_SDMA7:
2269 *type = GFX_FW_TYPE_SDMA7;
2271 case AMDGPU_UCODE_ID_CP_MES:
2272 *type = GFX_FW_TYPE_CP_MES;
2274 case AMDGPU_UCODE_ID_CP_MES_DATA:
2275 *type = GFX_FW_TYPE_MES_STACK;
2277 case AMDGPU_UCODE_ID_CP_MES1:
2278 *type = GFX_FW_TYPE_CP_MES_KIQ;
2280 case AMDGPU_UCODE_ID_CP_MES1_DATA:
2281 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2283 case AMDGPU_UCODE_ID_CP_CE:
2284 *type = GFX_FW_TYPE_CP_CE;
2286 case AMDGPU_UCODE_ID_CP_PFP:
2287 *type = GFX_FW_TYPE_CP_PFP;
2289 case AMDGPU_UCODE_ID_CP_ME:
2290 *type = GFX_FW_TYPE_CP_ME;
2292 case AMDGPU_UCODE_ID_CP_MEC1:
2293 *type = GFX_FW_TYPE_CP_MEC;
2295 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2296 *type = GFX_FW_TYPE_CP_MEC_ME1;
2298 case AMDGPU_UCODE_ID_CP_MEC2:
2299 *type = GFX_FW_TYPE_CP_MEC;
2301 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2302 *type = GFX_FW_TYPE_CP_MEC_ME2;
2304 case AMDGPU_UCODE_ID_RLC_P:
2305 *type = GFX_FW_TYPE_RLC_P;
2307 case AMDGPU_UCODE_ID_RLC_V:
2308 *type = GFX_FW_TYPE_RLC_V;
2310 case AMDGPU_UCODE_ID_RLC_G:
2311 *type = GFX_FW_TYPE_RLC_G;
2313 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2314 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2316 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2317 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2319 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2320 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2322 case AMDGPU_UCODE_ID_RLC_IRAM:
2323 *type = GFX_FW_TYPE_RLC_IRAM;
2325 case AMDGPU_UCODE_ID_RLC_DRAM:
2326 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2328 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2329 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2331 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2332 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2334 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2335 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2337 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2338 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2340 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2341 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2343 case AMDGPU_UCODE_ID_SMC:
2344 *type = GFX_FW_TYPE_SMU;
2346 case AMDGPU_UCODE_ID_PPTABLE:
2347 *type = GFX_FW_TYPE_PPTABLE;
2349 case AMDGPU_UCODE_ID_UVD:
2350 *type = GFX_FW_TYPE_UVD;
2352 case AMDGPU_UCODE_ID_UVD1:
2353 *type = GFX_FW_TYPE_UVD1;
2355 case AMDGPU_UCODE_ID_VCE:
2356 *type = GFX_FW_TYPE_VCE;
2358 case AMDGPU_UCODE_ID_VCN:
2359 *type = GFX_FW_TYPE_VCN;
2361 case AMDGPU_UCODE_ID_VCN1:
2362 *type = GFX_FW_TYPE_VCN1;
2364 case AMDGPU_UCODE_ID_DMCU_ERAM:
2365 *type = GFX_FW_TYPE_DMCU_ERAM;
2367 case AMDGPU_UCODE_ID_DMCU_INTV:
2368 *type = GFX_FW_TYPE_DMCU_ISR;
2370 case AMDGPU_UCODE_ID_VCN0_RAM:
2371 *type = GFX_FW_TYPE_VCN0_RAM;
2373 case AMDGPU_UCODE_ID_VCN1_RAM:
2374 *type = GFX_FW_TYPE_VCN1_RAM;
2376 case AMDGPU_UCODE_ID_DMCUB:
2377 *type = GFX_FW_TYPE_DMUB;
2379 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2380 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2382 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2383 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2385 case AMDGPU_UCODE_ID_IMU_I:
2386 *type = GFX_FW_TYPE_IMU_I;
2388 case AMDGPU_UCODE_ID_IMU_D:
2389 *type = GFX_FW_TYPE_IMU_D;
2391 case AMDGPU_UCODE_ID_CP_RS64_PFP:
2392 *type = GFX_FW_TYPE_RS64_PFP;
2394 case AMDGPU_UCODE_ID_CP_RS64_ME:
2395 *type = GFX_FW_TYPE_RS64_ME;
2397 case AMDGPU_UCODE_ID_CP_RS64_MEC:
2398 *type = GFX_FW_TYPE_RS64_MEC;
2400 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2401 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2403 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2404 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2406 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2407 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2409 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2410 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2412 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2413 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2415 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2416 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2418 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2419 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2421 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2422 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2424 case AMDGPU_UCODE_ID_VPE_CTX:
2425 *type = GFX_FW_TYPE_VPEC_FW1;
2427 case AMDGPU_UCODE_ID_VPE_CTL:
2428 *type = GFX_FW_TYPE_VPEC_FW2;
2430 case AMDGPU_UCODE_ID_VPE:
2431 *type = GFX_FW_TYPE_VPE;
2433 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
2434 *type = GFX_FW_TYPE_UMSCH_UCODE;
2436 case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
2437 *type = GFX_FW_TYPE_UMSCH_DATA;
2439 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
2440 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER;
2442 case AMDGPU_UCODE_ID_P2S_TABLE:
2443 *type = GFX_FW_TYPE_P2S_TABLE;
2445 case AMDGPU_UCODE_ID_MAXIMUM:
2453 static void psp_print_fw_hdr(struct psp_context *psp,
2454 struct amdgpu_firmware_info *ucode)
2456 struct amdgpu_device *adev = psp->adev;
2457 struct common_firmware_header *hdr;
2459 switch (ucode->ucode_id) {
2460 case AMDGPU_UCODE_ID_SDMA0:
2461 case AMDGPU_UCODE_ID_SDMA1:
2462 case AMDGPU_UCODE_ID_SDMA2:
2463 case AMDGPU_UCODE_ID_SDMA3:
2464 case AMDGPU_UCODE_ID_SDMA4:
2465 case AMDGPU_UCODE_ID_SDMA5:
2466 case AMDGPU_UCODE_ID_SDMA6:
2467 case AMDGPU_UCODE_ID_SDMA7:
2468 hdr = (struct common_firmware_header *)
2469 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2470 amdgpu_ucode_print_sdma_hdr(hdr);
2472 case AMDGPU_UCODE_ID_CP_CE:
2473 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2474 amdgpu_ucode_print_gfx_hdr(hdr);
2476 case AMDGPU_UCODE_ID_CP_PFP:
2477 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2478 amdgpu_ucode_print_gfx_hdr(hdr);
2480 case AMDGPU_UCODE_ID_CP_ME:
2481 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2482 amdgpu_ucode_print_gfx_hdr(hdr);
2484 case AMDGPU_UCODE_ID_CP_MEC1:
2485 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2486 amdgpu_ucode_print_gfx_hdr(hdr);
2488 case AMDGPU_UCODE_ID_RLC_G:
2489 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2490 amdgpu_ucode_print_rlc_hdr(hdr);
2492 case AMDGPU_UCODE_ID_SMC:
2493 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2494 amdgpu_ucode_print_smc_hdr(hdr);
2501 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2502 struct psp_gfx_cmd_resp *cmd)
2505 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2507 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2508 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2509 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2510 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2512 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2514 DRM_ERROR("Unknown firmware type\n");
2519 int psp_execute_ip_fw_load(struct psp_context *psp,
2520 struct amdgpu_firmware_info *ucode)
2523 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2525 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2527 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2528 psp->fence_buf_mc_addr);
2531 release_psp_cmd_buf(psp);
2536 static int psp_load_p2s_table(struct psp_context *psp)
2539 struct amdgpu_device *adev = psp->adev;
2540 struct amdgpu_firmware_info *ucode =
2541 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
2543 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2546 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {
2547 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D :
2549 if (psp->sos.fw_version < supp_vers)
2553 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2556 ret = psp_execute_ip_fw_load(psp, ucode);
2561 static int psp_load_smu_fw(struct psp_context *psp)
2564 struct amdgpu_device *adev = psp->adev;
2565 struct amdgpu_firmware_info *ucode =
2566 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2567 struct amdgpu_ras *ras = psp->ras_context.ras;
2570 * Skip SMU FW reloading in case of using BACO for runpm only,
2571 * as SMU is always alive.
2573 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2576 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2579 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled &&
2580 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
2581 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) {
2582 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2584 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2587 ret = psp_execute_ip_fw_load(psp, ucode);
2590 DRM_ERROR("PSP load smu failed!\n");
2595 static bool fw_load_skip_check(struct psp_context *psp,
2596 struct amdgpu_firmware_info *ucode)
2598 if (!ucode->fw || !ucode->ucode_size)
2601 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE)
2604 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2605 (psp_smu_reload_quirk(psp) ||
2606 psp->autoload_supported ||
2607 psp->pmfw_centralized_cstate_management))
2610 if (amdgpu_sriov_vf(psp->adev) &&
2611 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2614 if (psp->autoload_supported &&
2615 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2616 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2617 /* skip mec JT when autoload is enabled */
2623 int psp_load_fw_list(struct psp_context *psp,
2624 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2627 struct amdgpu_firmware_info *ucode;
2629 for (i = 0; i < ucode_count; ++i) {
2630 ucode = ucode_list[i];
2631 psp_print_fw_hdr(psp, ucode);
2632 ret = psp_execute_ip_fw_load(psp, ucode);
2639 static int psp_load_non_psp_fw(struct psp_context *psp)
2642 struct amdgpu_firmware_info *ucode;
2643 struct amdgpu_device *adev = psp->adev;
2645 if (psp->autoload_supported &&
2646 !psp->pmfw_centralized_cstate_management) {
2647 ret = psp_load_smu_fw(psp);
2652 /* Load P2S table first if it's available */
2653 psp_load_p2s_table(psp);
2655 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2656 ucode = &adev->firmware.ucode[i];
2658 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2659 !fw_load_skip_check(psp, ucode)) {
2660 ret = psp_load_smu_fw(psp);
2666 if (fw_load_skip_check(psp, ucode))
2669 if (psp->autoload_supported &&
2670 (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2671 IP_VERSION(11, 0, 7) ||
2672 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2673 IP_VERSION(11, 0, 11) ||
2674 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2675 IP_VERSION(11, 0, 12)) &&
2676 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2677 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2678 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2679 /* PSP only receive one SDMA fw for sienna_cichlid,
2680 * as all four sdma fw are same
2684 psp_print_fw_hdr(psp, ucode);
2686 ret = psp_execute_ip_fw_load(psp, ucode);
2690 /* Start rlc autoload after psp recieved all the gfx firmware */
2691 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2692 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2693 ret = psp_rlc_autoload_start(psp);
2695 DRM_ERROR("Failed to start rlc autoload\n");
2704 static int psp_load_fw(struct amdgpu_device *adev)
2707 struct psp_context *psp = &adev->psp;
2709 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2710 /* should not destroy ring, only stop */
2711 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2713 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2715 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2717 DRM_ERROR("PSP ring init failed!\n");
2722 ret = psp_hw_start(psp);
2726 ret = psp_load_non_psp_fw(psp);
2730 ret = psp_asd_initialize(psp);
2732 DRM_ERROR("PSP load asd failed!\n");
2736 ret = psp_rl_load(adev);
2738 DRM_ERROR("PSP load RL failed!\n");
2742 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2743 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2744 ret = psp_xgmi_initialize(psp, false, true);
2745 /* Warning the XGMI seesion initialize failure
2746 * Instead of stop driver initialization
2749 dev_err(psp->adev->dev,
2750 "XGMI: Failed to initialize XGMI session\n");
2755 ret = psp_ras_initialize(psp);
2757 dev_err(psp->adev->dev,
2758 "RAS: Failed to initialize RAS\n");
2760 ret = psp_hdcp_initialize(psp);
2762 dev_err(psp->adev->dev,
2763 "HDCP: Failed to initialize HDCP\n");
2765 ret = psp_dtm_initialize(psp);
2767 dev_err(psp->adev->dev,
2768 "DTM: Failed to initialize DTM\n");
2770 ret = psp_rap_initialize(psp);
2772 dev_err(psp->adev->dev,
2773 "RAP: Failed to initialize RAP\n");
2775 ret = psp_securedisplay_initialize(psp);
2777 dev_err(psp->adev->dev,
2778 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2784 psp_free_shared_bufs(psp);
2787 * all cleanup jobs (xgmi terminate, ras terminate,
2788 * ring destroy, cmd/fence/fw buffers destory,
2789 * psp->cmd destory) are delayed to psp_hw_fini
2791 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2795 static int psp_hw_init(void *handle)
2798 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2800 mutex_lock(&adev->firmware.mutex);
2802 * This sequence is just used on hw_init only once, no need on
2805 ret = amdgpu_ucode_init_bo(adev);
2809 ret = psp_load_fw(adev);
2811 DRM_ERROR("PSP firmware loading failed\n");
2815 mutex_unlock(&adev->firmware.mutex);
2819 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2820 mutex_unlock(&adev->firmware.mutex);
2824 static int psp_hw_fini(void *handle)
2826 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2827 struct psp_context *psp = &adev->psp;
2830 psp_ras_terminate(psp);
2831 psp_securedisplay_terminate(psp);
2832 psp_rap_terminate(psp);
2833 psp_dtm_terminate(psp);
2834 psp_hdcp_terminate(psp);
2836 if (adev->gmc.xgmi.num_physical_nodes > 1)
2837 psp_xgmi_terminate(psp);
2840 psp_asd_terminate(psp);
2841 psp_tmr_terminate(psp);
2843 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2848 static int psp_suspend(void *handle)
2851 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2852 struct psp_context *psp = &adev->psp;
2854 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2855 psp->xgmi_context.context.initialized) {
2856 ret = psp_xgmi_terminate(psp);
2858 DRM_ERROR("Failed to terminate xgmi ta\n");
2864 ret = psp_ras_terminate(psp);
2866 DRM_ERROR("Failed to terminate ras ta\n");
2869 ret = psp_hdcp_terminate(psp);
2871 DRM_ERROR("Failed to terminate hdcp ta\n");
2874 ret = psp_dtm_terminate(psp);
2876 DRM_ERROR("Failed to terminate dtm ta\n");
2879 ret = psp_rap_terminate(psp);
2881 DRM_ERROR("Failed to terminate rap ta\n");
2884 ret = psp_securedisplay_terminate(psp);
2886 DRM_ERROR("Failed to terminate securedisplay ta\n");
2891 ret = psp_asd_terminate(psp);
2893 DRM_ERROR("Failed to terminate asd\n");
2897 ret = psp_tmr_terminate(psp);
2899 DRM_ERROR("Failed to terminate tmr\n");
2903 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2905 DRM_ERROR("PSP ring stop failed\n");
2911 static int psp_resume(void *handle)
2914 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2915 struct psp_context *psp = &adev->psp;
2917 DRM_INFO("PSP is resuming...\n");
2919 if (psp->mem_train_ctx.enable_mem_training) {
2920 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2922 DRM_ERROR("Failed to process memory training!\n");
2927 mutex_lock(&adev->firmware.mutex);
2929 ret = psp_hw_start(psp);
2933 ret = psp_load_non_psp_fw(psp);
2937 ret = psp_asd_initialize(psp);
2939 DRM_ERROR("PSP load asd failed!\n");
2943 ret = psp_rl_load(adev);
2945 dev_err(adev->dev, "PSP load RL failed!\n");
2949 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2950 ret = psp_xgmi_initialize(psp, false, true);
2951 /* Warning the XGMI seesion initialize failure
2952 * Instead of stop driver initialization
2955 dev_err(psp->adev->dev,
2956 "XGMI: Failed to initialize XGMI session\n");
2960 ret = psp_ras_initialize(psp);
2962 dev_err(psp->adev->dev,
2963 "RAS: Failed to initialize RAS\n");
2965 ret = psp_hdcp_initialize(psp);
2967 dev_err(psp->adev->dev,
2968 "HDCP: Failed to initialize HDCP\n");
2970 ret = psp_dtm_initialize(psp);
2972 dev_err(psp->adev->dev,
2973 "DTM: Failed to initialize DTM\n");
2975 ret = psp_rap_initialize(psp);
2977 dev_err(psp->adev->dev,
2978 "RAP: Failed to initialize RAP\n");
2980 ret = psp_securedisplay_initialize(psp);
2982 dev_err(psp->adev->dev,
2983 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2986 mutex_unlock(&adev->firmware.mutex);
2991 DRM_ERROR("PSP resume failed\n");
2992 mutex_unlock(&adev->firmware.mutex);
2996 int psp_gpu_reset(struct amdgpu_device *adev)
3000 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
3003 mutex_lock(&adev->psp.mutex);
3004 ret = psp_mode1_reset(&adev->psp);
3005 mutex_unlock(&adev->psp.mutex);
3010 int psp_rlc_autoload_start(struct psp_context *psp)
3013 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
3015 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
3017 ret = psp_cmd_submit_buf(psp, NULL, cmd,
3018 psp->fence_buf_mc_addr);
3020 release_psp_cmd_buf(psp);
3025 int psp_ring_cmd_submit(struct psp_context *psp,
3026 uint64_t cmd_buf_mc_addr,
3027 uint64_t fence_mc_addr,
3030 unsigned int psp_write_ptr_reg = 0;
3031 struct psp_gfx_rb_frame *write_frame;
3032 struct psp_ring *ring = &psp->km_ring;
3033 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
3034 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
3035 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
3036 struct amdgpu_device *adev = psp->adev;
3037 uint32_t ring_size_dw = ring->ring_size / 4;
3038 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
3040 /* KM (GPCOM) prepare write pointer */
3041 psp_write_ptr_reg = psp_ring_get_wptr(psp);
3043 /* Update KM RB frame pointer to new frame */
3044 /* write_frame ptr increments by size of rb_frame in bytes */
3045 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
3046 if ((psp_write_ptr_reg % ring_size_dw) == 0)
3047 write_frame = ring_buffer_start;
3049 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
3050 /* Check invalid write_frame ptr address */
3051 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
3052 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
3053 ring_buffer_start, ring_buffer_end, write_frame);
3054 DRM_ERROR("write_frame is pointing to address out of bounds\n");
3058 /* Initialize KM RB frame */
3059 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
3061 /* Update KM RB frame */
3062 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
3063 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
3064 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
3065 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
3066 write_frame->fence_value = index;
3067 amdgpu_device_flush_hdp(adev, NULL);
3069 /* Update the write Pointer in DWORDs */
3070 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
3071 psp_ring_set_wptr(psp, psp_write_ptr_reg);
3075 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
3077 struct amdgpu_device *adev = psp->adev;
3078 char fw_name[PSP_FW_NAME_LEN];
3079 const struct psp_firmware_header_v1_0 *asd_hdr;
3082 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
3083 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
3087 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
3088 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3089 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3090 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3091 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
3092 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3095 amdgpu_ucode_release(&adev->psp.asd_fw);
3099 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
3101 struct amdgpu_device *adev = psp->adev;
3102 char fw_name[PSP_FW_NAME_LEN];
3103 const struct psp_firmware_header_v1_0 *toc_hdr;
3106 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3107 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
3111 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3112 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3113 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3114 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3115 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3116 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3119 amdgpu_ucode_release(&adev->psp.toc_fw);
3123 static int parse_sos_bin_descriptor(struct psp_context *psp,
3124 const struct psp_fw_bin_desc *desc,
3125 const struct psp_firmware_header_v2_0 *sos_hdr)
3127 uint8_t *ucode_start_addr = NULL;
3129 if (!psp || !desc || !sos_hdr)
3132 ucode_start_addr = (uint8_t *)sos_hdr +
3133 le32_to_cpu(desc->offset_bytes) +
3134 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3136 switch (desc->fw_type) {
3137 case PSP_FW_TYPE_PSP_SOS:
3138 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3139 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3140 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
3141 psp->sos.start_addr = ucode_start_addr;
3143 case PSP_FW_TYPE_PSP_SYS_DRV:
3144 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3145 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3146 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3147 psp->sys.start_addr = ucode_start_addr;
3149 case PSP_FW_TYPE_PSP_KDB:
3150 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3151 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3152 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3153 psp->kdb.start_addr = ucode_start_addr;
3155 case PSP_FW_TYPE_PSP_TOC:
3156 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3157 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3158 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3159 psp->toc.start_addr = ucode_start_addr;
3161 case PSP_FW_TYPE_PSP_SPL:
3162 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3163 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3164 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3165 psp->spl.start_addr = ucode_start_addr;
3167 case PSP_FW_TYPE_PSP_RL:
3168 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3169 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3170 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3171 psp->rl.start_addr = ucode_start_addr;
3173 case PSP_FW_TYPE_PSP_SOC_DRV:
3174 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3175 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3176 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3177 psp->soc_drv.start_addr = ucode_start_addr;
3179 case PSP_FW_TYPE_PSP_INTF_DRV:
3180 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3181 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3182 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3183 psp->intf_drv.start_addr = ucode_start_addr;
3185 case PSP_FW_TYPE_PSP_DBG_DRV:
3186 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3187 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3188 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3189 psp->dbg_drv.start_addr = ucode_start_addr;
3191 case PSP_FW_TYPE_PSP_RAS_DRV:
3192 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version);
3193 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version);
3194 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3195 psp->ras_drv.start_addr = ucode_start_addr;
3198 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3205 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3207 const struct psp_firmware_header_v1_0 *sos_hdr;
3208 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3209 uint8_t *ucode_array_start_addr;
3211 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3212 ucode_array_start_addr = (uint8_t *)sos_hdr +
3213 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3215 if (adev->gmc.xgmi.connected_to_cpu ||
3216 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) {
3217 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3218 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3220 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3221 adev->psp.sys.start_addr = ucode_array_start_addr;
3223 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3224 adev->psp.sos.start_addr = ucode_array_start_addr +
3225 le32_to_cpu(sos_hdr->sos.offset_bytes);
3227 /* Load alternate PSP SOS FW */
3228 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3230 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3231 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3233 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3234 adev->psp.sys.start_addr = ucode_array_start_addr +
3235 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3237 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3238 adev->psp.sos.start_addr = ucode_array_start_addr +
3239 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3242 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3243 dev_warn(adev->dev, "PSP SOS FW not available");
3250 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3252 struct amdgpu_device *adev = psp->adev;
3253 char fw_name[PSP_FW_NAME_LEN];
3254 const struct psp_firmware_header_v1_0 *sos_hdr;
3255 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3256 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3257 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3258 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3260 uint8_t *ucode_array_start_addr;
3263 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3264 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3268 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3269 ucode_array_start_addr = (uint8_t *)sos_hdr +
3270 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3271 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3273 switch (sos_hdr->header.header_version_major) {
3275 err = psp_init_sos_base_fw(adev);
3279 if (sos_hdr->header.header_version_minor == 1) {
3280 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3281 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3282 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3283 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3284 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3285 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3286 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3288 if (sos_hdr->header.header_version_minor == 2) {
3289 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3290 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3291 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3292 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3294 if (sos_hdr->header.header_version_minor == 3) {
3295 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3296 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3297 adev->psp.toc.start_addr = ucode_array_start_addr +
3298 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3299 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3300 adev->psp.kdb.start_addr = ucode_array_start_addr +
3301 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3302 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3303 adev->psp.spl.start_addr = ucode_array_start_addr +
3304 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3305 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3306 adev->psp.rl.start_addr = ucode_array_start_addr +
3307 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3311 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3313 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3314 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3319 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3320 err = parse_sos_bin_descriptor(psp,
3321 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3329 "unsupported psp sos firmware\n");
3336 amdgpu_ucode_release(&adev->psp.sos_fw);
3341 static int parse_ta_bin_descriptor(struct psp_context *psp,
3342 const struct psp_fw_bin_desc *desc,
3343 const struct ta_firmware_header_v2_0 *ta_hdr)
3345 uint8_t *ucode_start_addr = NULL;
3347 if (!psp || !desc || !ta_hdr)
3350 ucode_start_addr = (uint8_t *)ta_hdr +
3351 le32_to_cpu(desc->offset_bytes) +
3352 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3354 switch (desc->fw_type) {
3355 case TA_FW_TYPE_PSP_ASD:
3356 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3357 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3358 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3359 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
3361 case TA_FW_TYPE_PSP_XGMI:
3362 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3363 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3364 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
3366 case TA_FW_TYPE_PSP_RAS:
3367 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3368 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3369 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
3371 case TA_FW_TYPE_PSP_HDCP:
3372 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3373 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3374 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
3376 case TA_FW_TYPE_PSP_DTM:
3377 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3378 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3379 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
3381 case TA_FW_TYPE_PSP_RAP:
3382 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3383 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3384 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
3386 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3387 psp->securedisplay_context.context.bin_desc.fw_version =
3388 le32_to_cpu(desc->fw_version);
3389 psp->securedisplay_context.context.bin_desc.size_bytes =
3390 le32_to_cpu(desc->size_bytes);
3391 psp->securedisplay_context.context.bin_desc.start_addr =
3395 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3402 static int parse_ta_v1_microcode(struct psp_context *psp)
3404 const struct ta_firmware_header_v1_0 *ta_hdr;
3405 struct amdgpu_device *adev = psp->adev;
3407 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3409 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3412 adev->psp.xgmi_context.context.bin_desc.fw_version =
3413 le32_to_cpu(ta_hdr->xgmi.fw_version);
3414 adev->psp.xgmi_context.context.bin_desc.size_bytes =
3415 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3416 adev->psp.xgmi_context.context.bin_desc.start_addr =
3418 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3420 adev->psp.ras_context.context.bin_desc.fw_version =
3421 le32_to_cpu(ta_hdr->ras.fw_version);
3422 adev->psp.ras_context.context.bin_desc.size_bytes =
3423 le32_to_cpu(ta_hdr->ras.size_bytes);
3424 adev->psp.ras_context.context.bin_desc.start_addr =
3425 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3426 le32_to_cpu(ta_hdr->ras.offset_bytes);
3428 adev->psp.hdcp_context.context.bin_desc.fw_version =
3429 le32_to_cpu(ta_hdr->hdcp.fw_version);
3430 adev->psp.hdcp_context.context.bin_desc.size_bytes =
3431 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3432 adev->psp.hdcp_context.context.bin_desc.start_addr =
3434 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3436 adev->psp.dtm_context.context.bin_desc.fw_version =
3437 le32_to_cpu(ta_hdr->dtm.fw_version);
3438 adev->psp.dtm_context.context.bin_desc.size_bytes =
3439 le32_to_cpu(ta_hdr->dtm.size_bytes);
3440 adev->psp.dtm_context.context.bin_desc.start_addr =
3441 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3442 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3444 adev->psp.securedisplay_context.context.bin_desc.fw_version =
3445 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3446 adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3447 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3448 adev->psp.securedisplay_context.context.bin_desc.start_addr =
3449 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3450 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3452 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3457 static int parse_ta_v2_microcode(struct psp_context *psp)
3459 const struct ta_firmware_header_v2_0 *ta_hdr;
3460 struct amdgpu_device *adev = psp->adev;
3464 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3466 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3469 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3470 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3474 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3475 err = parse_ta_bin_descriptor(psp,
3476 &ta_hdr->ta_fw_bin[ta_index],
3485 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3487 const struct common_firmware_header *hdr;
3488 struct amdgpu_device *adev = psp->adev;
3489 char fw_name[PSP_FW_NAME_LEN];
3492 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3493 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3497 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3498 switch (le16_to_cpu(hdr->header_version_major)) {
3500 err = parse_ta_v1_microcode(psp);
3503 err = parse_ta_v2_microcode(psp);
3506 dev_err(adev->dev, "unsupported TA header version\n");
3511 amdgpu_ucode_release(&adev->psp.ta_fw);
3516 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3518 struct amdgpu_device *adev = psp->adev;
3519 char fw_name[PSP_FW_NAME_LEN];
3520 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3521 struct amdgpu_firmware_info *info = NULL;
3524 if (!amdgpu_sriov_vf(adev)) {
3525 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3529 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3530 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3532 if (err == -ENODEV) {
3533 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3537 dev_err(adev->dev, "fail to initialize cap microcode\n");
3540 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3541 info->ucode_id = AMDGPU_UCODE_ID_CAP;
3542 info->fw = adev->psp.cap_fw;
3543 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3544 adev->psp.cap_fw->data;
3545 adev->firmware.fw_size += ALIGN(
3546 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3547 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3548 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3549 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3554 amdgpu_ucode_release(&adev->psp.cap_fw);
3558 static int psp_set_clockgating_state(void *handle,
3559 enum amd_clockgating_state state)
3564 static int psp_set_powergating_state(void *handle,
3565 enum amd_powergating_state state)
3570 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3571 struct device_attribute *attr,
3574 struct drm_device *ddev = dev_get_drvdata(dev);
3575 struct amdgpu_device *adev = drm_to_adev(ddev);
3579 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3580 DRM_INFO("PSP block is not ready yet.");
3584 mutex_lock(&adev->psp.mutex);
3585 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3586 mutex_unlock(&adev->psp.mutex);
3589 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3593 return sysfs_emit(buf, "%x\n", fw_ver);
3596 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3597 struct device_attribute *attr,
3601 struct drm_device *ddev = dev_get_drvdata(dev);
3602 struct amdgpu_device *adev = drm_to_adev(ddev);
3605 const struct firmware *usbc_pd_fw;
3606 struct amdgpu_bo *fw_buf_bo = NULL;
3607 uint64_t fw_pri_mc_addr;
3608 void *fw_pri_cpu_addr;
3610 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3611 DRM_INFO("PSP block is not ready yet.");
3615 if (!drm_dev_enter(ddev, &idx))
3618 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3619 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3623 /* LFB address which is aligned to 1MB boundary per PSP request */
3624 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3625 AMDGPU_GEM_DOMAIN_VRAM |
3626 AMDGPU_GEM_DOMAIN_GTT,
3627 &fw_buf_bo, &fw_pri_mc_addr,
3632 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3634 mutex_lock(&adev->psp.mutex);
3635 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3636 mutex_unlock(&adev->psp.mutex);
3638 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3641 release_firmware(usbc_pd_fw);
3644 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3652 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3656 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3659 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3660 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3667 * Reading from this file will retrieve the USB-C PD firmware version. Writing to
3668 * this file will trigger the update process.
3670 static DEVICE_ATTR(usbc_pd_fw, 0644,
3671 psp_usbc_pd_fw_sysfs_read,
3672 psp_usbc_pd_fw_sysfs_write);
3674 int is_psp_fw_valid(struct psp_bin_desc bin)
3676 return bin.size_bytes;
3679 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3680 struct bin_attribute *bin_attr,
3681 char *buffer, loff_t pos, size_t count)
3683 struct device *dev = kobj_to_dev(kobj);
3684 struct drm_device *ddev = dev_get_drvdata(dev);
3685 struct amdgpu_device *adev = drm_to_adev(ddev);
3687 adev->psp.vbflash_done = false;
3689 /* Safeguard against memory drain */
3690 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3691 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3692 kvfree(adev->psp.vbflash_tmp_buf);
3693 adev->psp.vbflash_tmp_buf = NULL;
3694 adev->psp.vbflash_image_size = 0;
3698 /* TODO Just allocate max for now and optimize to realloc later if needed */
3699 if (!adev->psp.vbflash_tmp_buf) {
3700 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3701 if (!adev->psp.vbflash_tmp_buf)
3705 mutex_lock(&adev->psp.mutex);
3706 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3707 adev->psp.vbflash_image_size += count;
3708 mutex_unlock(&adev->psp.mutex);
3710 dev_dbg(adev->dev, "IFWI staged for update");
3715 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3716 struct bin_attribute *bin_attr, char *buffer,
3717 loff_t pos, size_t count)
3719 struct device *dev = kobj_to_dev(kobj);
3720 struct drm_device *ddev = dev_get_drvdata(dev);
3721 struct amdgpu_device *adev = drm_to_adev(ddev);
3722 struct amdgpu_bo *fw_buf_bo = NULL;
3723 uint64_t fw_pri_mc_addr;
3724 void *fw_pri_cpu_addr;
3727 if (adev->psp.vbflash_image_size == 0)
3730 dev_dbg(adev->dev, "PSP IFWI flash process initiated");
3732 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3733 AMDGPU_GPU_PAGE_SIZE,
3734 AMDGPU_GEM_DOMAIN_VRAM,
3741 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3743 mutex_lock(&adev->psp.mutex);
3744 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3745 mutex_unlock(&adev->psp.mutex);
3747 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3750 kvfree(adev->psp.vbflash_tmp_buf);
3751 adev->psp.vbflash_tmp_buf = NULL;
3752 adev->psp.vbflash_image_size = 0;
3755 dev_err(adev->dev, "Failed to load IFWI, err = %d", ret);
3759 dev_dbg(adev->dev, "PSP IFWI flash process done");
3765 * Writing to this file will stage an IFWI for update. Reading from this file
3766 * will trigger the update process.
3768 static struct bin_attribute psp_vbflash_bin_attr = {
3769 .attr = {.name = "psp_vbflash", .mode = 0660},
3771 .write = amdgpu_psp_vbflash_write,
3772 .read = amdgpu_psp_vbflash_read,
3776 * DOC: psp_vbflash_status
3777 * The status of the flash process.
3778 * 0: IFWI flash not complete.
3779 * 1: IFWI flash complete.
3781 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3782 struct device_attribute *attr,
3785 struct drm_device *ddev = dev_get_drvdata(dev);
3786 struct amdgpu_device *adev = drm_to_adev(ddev);
3787 uint32_t vbflash_status;
3789 vbflash_status = psp_vbflash_status(&adev->psp);
3790 if (!adev->psp.vbflash_done)
3792 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3795 return sysfs_emit(buf, "0x%x\n", vbflash_status);
3797 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3799 static struct bin_attribute *bin_flash_attrs[] = {
3800 &psp_vbflash_bin_attr,
3804 static struct attribute *flash_attrs[] = {
3805 &dev_attr_psp_vbflash_status.attr,
3806 &dev_attr_usbc_pd_fw.attr,
3810 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
3812 struct device *dev = kobj_to_dev(kobj);
3813 struct drm_device *ddev = dev_get_drvdata(dev);
3814 struct amdgpu_device *adev = drm_to_adev(ddev);
3816 if (attr == &dev_attr_usbc_pd_fw.attr)
3817 return adev->psp.sup_pd_fw_up ? 0660 : 0;
3819 return adev->psp.sup_ifwi_up ? 0440 : 0;
3822 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj,
3823 struct bin_attribute *attr,
3826 struct device *dev = kobj_to_dev(kobj);
3827 struct drm_device *ddev = dev_get_drvdata(dev);
3828 struct amdgpu_device *adev = drm_to_adev(ddev);
3830 return adev->psp.sup_ifwi_up ? 0660 : 0;
3833 const struct attribute_group amdgpu_flash_attr_group = {
3834 .attrs = flash_attrs,
3835 .bin_attrs = bin_flash_attrs,
3836 .is_bin_visible = amdgpu_bin_flash_attr_is_visible,
3837 .is_visible = amdgpu_flash_attr_is_visible,
3840 const struct amd_ip_funcs psp_ip_funcs = {
3842 .early_init = psp_early_init,
3844 .sw_init = psp_sw_init,
3845 .sw_fini = psp_sw_fini,
3846 .hw_init = psp_hw_init,
3847 .hw_fini = psp_hw_fini,
3848 .suspend = psp_suspend,
3849 .resume = psp_resume,
3851 .check_soft_reset = NULL,
3852 .wait_for_idle = NULL,
3854 .set_clockgating_state = psp_set_clockgating_state,
3855 .set_powergating_state = psp_set_powergating_state,
3858 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3859 .type = AMD_IP_BLOCK_TYPE_PSP,
3863 .funcs = &psp_ip_funcs,
3866 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3867 .type = AMD_IP_BLOCK_TYPE_PSP,
3871 .funcs = &psp_ip_funcs,
3874 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3875 .type = AMD_IP_BLOCK_TYPE_PSP,
3879 .funcs = &psp_ip_funcs,
3882 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3883 .type = AMD_IP_BLOCK_TYPE_PSP,
3887 .funcs = &psp_ip_funcs,
3890 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3891 .type = AMD_IP_BLOCK_TYPE_PSP,
3895 .funcs = &psp_ip_funcs,
3898 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3899 .type = AMD_IP_BLOCK_TYPE_PSP,
3903 .funcs = &psp_ip_funcs,
3906 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3907 .type = AMD_IP_BLOCK_TYPE_PSP,
3911 .funcs = &psp_ip_funcs,