2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <linux/dma-mapping.h>
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "soc15_common.h"
34 #include "psp_v10_0.h"
35 #include "psp_v11_0.h"
36 #include "psp_v12_0.h"
38 #include "amdgpu_ras.h"
40 static int psp_sysfs_init(struct amdgpu_device *adev);
41 static void psp_sysfs_fini(struct amdgpu_device *adev);
43 static int psp_load_smu_fw(struct psp_context *psp);
46 * Due to DF Cstate management centralized to PMFW, the firmware
47 * loading sequence will be updated as below:
53 * - Load other non-psp fw
55 * - Load XGMI/RAS/HDCP/DTM TA if any
57 * This new sequence is required for
59 * - Navi12 and onwards
61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
63 struct amdgpu_device *adev = psp->adev;
65 psp->pmfw_centralized_cstate_management = false;
67 if (amdgpu_sriov_vf(adev))
70 if (adev->flags & AMD_IS_APU)
73 if ((adev->asic_type == CHIP_ARCTURUS) ||
74 (adev->asic_type >= CHIP_NAVI12))
75 psp->pmfw_centralized_cstate_management = true;
78 static int psp_early_init(void *handle)
80 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
81 struct psp_context *psp = &adev->psp;
83 switch (adev->asic_type) {
86 psp_v3_1_set_psp_funcs(psp);
87 psp->autoload_supported = false;
90 psp_v10_0_set_psp_funcs(psp);
91 psp->autoload_supported = false;
95 psp_v11_0_set_psp_funcs(psp);
96 psp->autoload_supported = false;
101 case CHIP_SIENNA_CICHLID:
102 case CHIP_NAVY_FLOUNDER:
103 psp_v11_0_set_psp_funcs(psp);
104 psp->autoload_supported = true;
107 psp_v12_0_set_psp_funcs(psp);
115 psp_check_pmfw_centralized_cstate_management(psp);
120 static void psp_memory_training_fini(struct psp_context *psp)
122 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
124 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
125 kfree(ctx->sys_cache);
126 ctx->sys_cache = NULL;
129 static int psp_memory_training_init(struct psp_context *psp)
132 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
134 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
135 DRM_DEBUG("memory training is not supported!\n");
139 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
140 if (ctx->sys_cache == NULL) {
141 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
146 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
147 ctx->train_data_size,
148 ctx->p2c_train_data_offset,
149 ctx->c2p_train_data_offset);
150 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
154 psp_memory_training_fini(psp);
158 static int psp_sw_init(void *handle)
160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
161 struct psp_context *psp = &adev->psp;
164 ret = psp_init_microcode(psp);
166 DRM_ERROR("Failed to load psp firmware!\n");
170 ret = psp_memory_training_init(psp);
172 DRM_ERROR("Failed to initialize memory training!\n");
175 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
177 DRM_ERROR("Failed to process memory training!\n");
181 if (adev->asic_type == CHIP_NAVI10) {
182 ret= psp_sysfs_init(adev);
191 static int psp_sw_fini(void *handle)
193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
195 psp_memory_training_fini(&adev->psp);
196 release_firmware(adev->psp.sos_fw);
197 adev->psp.sos_fw = NULL;
198 release_firmware(adev->psp.asd_fw);
199 adev->psp.asd_fw = NULL;
200 release_firmware(adev->psp.ta_fw);
201 adev->psp.ta_fw = NULL;
203 if (adev->asic_type == CHIP_NAVI10)
204 psp_sysfs_fini(adev);
209 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
210 uint32_t reg_val, uint32_t mask, bool check_changed)
214 struct amdgpu_device *adev = psp->adev;
216 for (i = 0; i < adev->usec_timeout; i++) {
217 val = RREG32(reg_index);
222 if ((val & mask) == reg_val)
232 psp_cmd_submit_buf(struct psp_context *psp,
233 struct amdgpu_firmware_info *ucode,
234 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
239 bool ras_intr = false;
240 bool skip_unsupport = false;
242 mutex_lock(&psp->mutex);
244 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
246 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
248 index = atomic_inc_return(&psp->fence_value);
249 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
251 atomic_dec(&psp->fence_value);
252 mutex_unlock(&psp->mutex);
256 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
257 while (*((unsigned int *)psp->fence_buf) != index) {
261 * Shouldn't wait for timeout when err_event_athub occurs,
262 * because gpu reset thread triggered and lock resource should
263 * be released for psp resume sequence.
265 ras_intr = amdgpu_ras_intr_triggered();
269 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
272 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
273 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
274 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
276 /* In some cases, psp response status is not 0 even there is no
277 * problem while the command is submitted. Some version of PSP FW
278 * doesn't write 0 to that field.
279 * So here we would like to only print a warning instead of an error
280 * during psp initialization to avoid breaking hw_init and it doesn't
283 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
285 DRM_WARN("failed to load ucode id (%d) ",
287 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
288 psp->cmd_buf_mem->cmd_id,
289 psp->cmd_buf_mem->resp.status);
291 mutex_unlock(&psp->mutex);
296 /* get xGMI session id from response buffer */
297 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
300 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
301 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
303 mutex_unlock(&psp->mutex);
308 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
309 struct psp_gfx_cmd_resp *cmd,
310 uint64_t tmr_mc, uint32_t size)
312 if (amdgpu_sriov_vf(psp->adev))
313 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
315 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
316 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
317 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
318 cmd->cmd.cmd_setup_tmr.buf_size = size;
321 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
322 uint64_t pri_buf_mc, uint32_t size)
324 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
325 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
326 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
327 cmd->cmd.cmd_load_toc.toc_size = size;
330 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
331 static int psp_load_toc(struct psp_context *psp,
335 struct psp_gfx_cmd_resp *cmd;
337 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
340 /* Copy toc to psp firmware private buffer */
341 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
342 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
344 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
346 ret = psp_cmd_submit_buf(psp, NULL, cmd,
347 psp->fence_buf_mc_addr);
349 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
354 /* Set up Trusted Memory Region */
355 static int psp_tmr_init(struct psp_context *psp)
363 * According to HW engineer, they prefer the TMR address be "naturally
364 * aligned" , e.g. the start address be an integer divide of TMR size.
366 * Note: this memory need be reserved till the driver
369 tmr_size = PSP_TMR_SIZE;
371 /* For ASICs support RLC autoload, psp will parse the toc
372 * and calculate the total size of TMR needed */
373 if (!amdgpu_sriov_vf(psp->adev) &&
374 psp->toc_start_addr &&
377 ret = psp_load_toc(psp, &tmr_size);
379 DRM_ERROR("Failed to load toc\n");
384 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
385 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
386 AMDGPU_GEM_DOMAIN_VRAM,
387 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
392 static int psp_clear_vf_fw(struct psp_context *psp)
395 struct psp_gfx_cmd_resp *cmd;
397 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12)
400 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
404 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW;
406 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
412 static int psp_tmr_load(struct psp_context *psp)
415 struct psp_gfx_cmd_resp *cmd;
417 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
421 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
422 amdgpu_bo_size(psp->tmr_bo));
423 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
424 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
426 ret = psp_cmd_submit_buf(psp, NULL, cmd,
427 psp->fence_buf_mc_addr);
434 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
435 struct psp_gfx_cmd_resp *cmd)
437 if (amdgpu_sriov_vf(psp->adev))
438 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
440 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
443 static int psp_tmr_unload(struct psp_context *psp)
446 struct psp_gfx_cmd_resp *cmd;
448 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
452 psp_prep_tmr_unload_cmd_buf(psp, cmd);
453 DRM_INFO("free PSP TMR buffer\n");
455 ret = psp_cmd_submit_buf(psp, NULL, cmd,
456 psp->fence_buf_mc_addr);
463 static int psp_tmr_terminate(struct psp_context *psp)
469 ret = psp_tmr_unload(psp);
473 /* free TMR memory buffer */
474 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
475 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
480 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
481 uint64_t asd_mc, uint32_t size)
483 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
484 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
485 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
486 cmd->cmd.cmd_load_ta.app_len = size;
488 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
489 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
490 cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
493 static int psp_asd_load(struct psp_context *psp)
496 struct psp_gfx_cmd_resp *cmd;
498 /* If PSP version doesn't match ASD version, asd loading will be failed.
499 * add workaround to bypass it for sriov now.
500 * TODO: add version check to make it common
502 if (amdgpu_sriov_vf(psp->adev) ||
503 (psp->adev->asic_type == CHIP_NAVY_FLOUNDER))
506 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
510 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
511 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
513 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
514 psp->asd_ucode_size);
516 ret = psp_cmd_submit_buf(psp, NULL, cmd,
517 psp->fence_buf_mc_addr);
519 psp->asd_context.asd_initialized = true;
520 psp->asd_context.session_id = cmd->resp.session_id;
528 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
531 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
532 cmd->cmd.cmd_unload_ta.session_id = session_id;
535 static int psp_asd_unload(struct psp_context *psp)
538 struct psp_gfx_cmd_resp *cmd;
540 if (amdgpu_sriov_vf(psp->adev))
543 if (!psp->asd_context.asd_initialized)
546 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
550 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
552 ret = psp_cmd_submit_buf(psp, NULL, cmd,
553 psp->fence_buf_mc_addr);
555 psp->asd_context.asd_initialized = false;
562 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
563 uint32_t id, uint32_t value)
565 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
566 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
567 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
570 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
573 struct psp_gfx_cmd_resp *cmd = NULL;
576 if (reg >= PSP_REG_LAST)
579 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
583 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
584 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
590 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
592 uint32_t ta_bin_size,
593 uint64_t ta_shared_mc,
594 uint32_t ta_shared_size)
596 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
597 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
598 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
599 cmd->cmd.cmd_load_ta.app_len = ta_bin_size;
601 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
602 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
603 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size;
606 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
611 * Allocate 16k memory aligned to 4k from Frame Buffer (local
612 * physical) for xgmi ta <-> Driver
614 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
615 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
616 &psp->xgmi_context.xgmi_shared_bo,
617 &psp->xgmi_context.xgmi_shared_mc_addr,
618 &psp->xgmi_context.xgmi_shared_buf);
623 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
627 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
628 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
629 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
632 static int psp_ta_invoke(struct psp_context *psp,
637 struct psp_gfx_cmd_resp *cmd;
639 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
643 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
645 ret = psp_cmd_submit_buf(psp, NULL, cmd,
646 psp->fence_buf_mc_addr);
653 static int psp_xgmi_load(struct psp_context *psp)
656 struct psp_gfx_cmd_resp *cmd;
659 * TODO: bypass the loading in sriov for now
662 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
666 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
667 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
669 psp_prep_ta_load_cmd_buf(cmd,
671 psp->ta_xgmi_ucode_size,
672 psp->xgmi_context.xgmi_shared_mc_addr,
673 PSP_XGMI_SHARED_MEM_SIZE);
675 ret = psp_cmd_submit_buf(psp, NULL, cmd,
676 psp->fence_buf_mc_addr);
679 psp->xgmi_context.initialized = 1;
680 psp->xgmi_context.session_id = cmd->resp.session_id;
688 static int psp_xgmi_unload(struct psp_context *psp)
691 struct psp_gfx_cmd_resp *cmd;
692 struct amdgpu_device *adev = psp->adev;
694 /* XGMI TA unload currently is not supported on Arcturus */
695 if (adev->asic_type == CHIP_ARCTURUS)
699 * TODO: bypass the unloading in sriov for now
702 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
706 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
708 ret = psp_cmd_submit_buf(psp, NULL, cmd,
709 psp->fence_buf_mc_addr);
716 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
718 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
721 int psp_xgmi_terminate(struct psp_context *psp)
725 if (!psp->xgmi_context.initialized)
728 ret = psp_xgmi_unload(psp);
732 psp->xgmi_context.initialized = 0;
734 /* free xgmi shared memory */
735 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
736 &psp->xgmi_context.xgmi_shared_mc_addr,
737 &psp->xgmi_context.xgmi_shared_buf);
742 int psp_xgmi_initialize(struct psp_context *psp)
744 struct ta_xgmi_shared_memory *xgmi_cmd;
747 if (!psp->adev->psp.ta_fw ||
748 !psp->adev->psp.ta_xgmi_ucode_size ||
749 !psp->adev->psp.ta_xgmi_start_addr)
752 if (!psp->xgmi_context.initialized) {
753 ret = psp_xgmi_init_shared_buf(psp);
759 ret = psp_xgmi_load(psp);
763 /* Initialize XGMI session */
764 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
765 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
766 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
768 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
773 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
775 struct ta_xgmi_shared_memory *xgmi_cmd;
778 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
779 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
781 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
783 /* Invoke xgmi ta to get hive id */
784 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
788 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
793 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
795 struct ta_xgmi_shared_memory *xgmi_cmd;
798 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
799 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
801 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
803 /* Invoke xgmi ta to get the node id */
804 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
808 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
813 int psp_xgmi_get_topology_info(struct psp_context *psp,
815 struct psp_xgmi_topology_info *topology)
817 struct ta_xgmi_shared_memory *xgmi_cmd;
818 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
819 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
823 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
826 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
827 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
829 /* Fill in the shared memory with topology information as input */
830 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
831 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
832 topology_info_input->num_nodes = number_devices;
834 for (i = 0; i < topology_info_input->num_nodes; i++) {
835 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
836 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
837 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
838 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
841 /* Invoke xgmi ta to get the topology information */
842 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
846 /* Read the output topology information from the shared memory */
847 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
848 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
849 for (i = 0; i < topology->num_nodes; i++) {
850 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
851 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
852 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
853 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
859 int psp_xgmi_set_topology_info(struct psp_context *psp,
861 struct psp_xgmi_topology_info *topology)
863 struct ta_xgmi_shared_memory *xgmi_cmd;
864 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
867 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
870 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
871 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
873 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
874 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
875 topology_info_input->num_nodes = number_devices;
877 for (i = 0; i < topology_info_input->num_nodes; i++) {
878 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
879 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
880 topology_info_input->nodes[i].is_sharing_enabled = 1;
881 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
884 /* Invoke xgmi ta to set topology information */
885 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
889 static int psp_ras_init_shared_buf(struct psp_context *psp)
894 * Allocate 16k memory aligned to 4k from Frame Buffer (local
895 * physical) for ras ta <-> Driver
897 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
898 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
899 &psp->ras.ras_shared_bo,
900 &psp->ras.ras_shared_mc_addr,
901 &psp->ras.ras_shared_buf);
906 static int psp_ras_load(struct psp_context *psp)
909 struct psp_gfx_cmd_resp *cmd;
912 * TODO: bypass the loading in sriov for now
914 if (amdgpu_sriov_vf(psp->adev))
917 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
921 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
922 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
924 psp_prep_ta_load_cmd_buf(cmd,
926 psp->ta_ras_ucode_size,
927 psp->ras.ras_shared_mc_addr,
928 PSP_RAS_SHARED_MEM_SIZE);
930 ret = psp_cmd_submit_buf(psp, NULL, cmd,
931 psp->fence_buf_mc_addr);
934 psp->ras.ras_initialized = true;
935 psp->ras.session_id = cmd->resp.session_id;
943 static int psp_ras_unload(struct psp_context *psp)
946 struct psp_gfx_cmd_resp *cmd;
949 * TODO: bypass the unloading in sriov for now
951 if (amdgpu_sriov_vf(psp->adev))
954 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
958 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
960 ret = psp_cmd_submit_buf(psp, NULL, cmd,
961 psp->fence_buf_mc_addr);
968 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
970 struct ta_ras_shared_memory *ras_cmd;
973 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
976 * TODO: bypass the loading in sriov for now
978 if (amdgpu_sriov_vf(psp->adev))
981 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
983 if (amdgpu_ras_intr_triggered())
986 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
988 DRM_WARN("RAS: Unsupported Interface");
993 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
994 dev_warn(psp->adev->dev, "ECC switch disabled\n");
996 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
998 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
999 dev_warn(psp->adev->dev,
1000 "RAS internal register access blocked\n");
1006 int psp_ras_enable_features(struct psp_context *psp,
1007 union ta_ras_cmd_input *info, bool enable)
1009 struct ta_ras_shared_memory *ras_cmd;
1012 if (!psp->ras.ras_initialized)
1015 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1016 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1019 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1021 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1023 ras_cmd->ras_in_message = *info;
1025 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1029 return ras_cmd->ras_status;
1032 static int psp_ras_terminate(struct psp_context *psp)
1037 * TODO: bypass the terminate in sriov for now
1039 if (amdgpu_sriov_vf(psp->adev))
1042 if (!psp->ras.ras_initialized)
1045 ret = psp_ras_unload(psp);
1049 psp->ras.ras_initialized = false;
1051 /* free ras shared memory */
1052 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1053 &psp->ras.ras_shared_mc_addr,
1054 &psp->ras.ras_shared_buf);
1059 static int psp_ras_initialize(struct psp_context *psp)
1064 * TODO: bypass the initialize in sriov for now
1066 if (amdgpu_sriov_vf(psp->adev))
1069 if (!psp->adev->psp.ta_ras_ucode_size ||
1070 !psp->adev->psp.ta_ras_start_addr) {
1071 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
1075 if (!psp->ras.ras_initialized) {
1076 ret = psp_ras_init_shared_buf(psp);
1081 ret = psp_ras_load(psp);
1088 int psp_ras_trigger_error(struct psp_context *psp,
1089 struct ta_ras_trigger_error_input *info)
1091 struct ta_ras_shared_memory *ras_cmd;
1094 if (!psp->ras.ras_initialized)
1097 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1098 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1100 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1101 ras_cmd->ras_in_message.trigger_error = *info;
1103 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1107 /* If err_event_athub occurs error inject was successful, however
1108 return status from TA is no long reliable */
1109 if (amdgpu_ras_intr_triggered())
1112 return ras_cmd->ras_status;
1117 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1122 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1123 * physical) for hdcp ta <-> Driver
1125 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1126 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1127 &psp->hdcp_context.hdcp_shared_bo,
1128 &psp->hdcp_context.hdcp_shared_mc_addr,
1129 &psp->hdcp_context.hdcp_shared_buf);
1134 static int psp_hdcp_load(struct psp_context *psp)
1137 struct psp_gfx_cmd_resp *cmd;
1140 * TODO: bypass the loading in sriov for now
1142 if (amdgpu_sriov_vf(psp->adev))
1145 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1149 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1150 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
1151 psp->ta_hdcp_ucode_size);
1153 psp_prep_ta_load_cmd_buf(cmd,
1154 psp->fw_pri_mc_addr,
1155 psp->ta_hdcp_ucode_size,
1156 psp->hdcp_context.hdcp_shared_mc_addr,
1157 PSP_HDCP_SHARED_MEM_SIZE);
1159 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1162 psp->hdcp_context.hdcp_initialized = true;
1163 psp->hdcp_context.session_id = cmd->resp.session_id;
1164 mutex_init(&psp->hdcp_context.mutex);
1171 static int psp_hdcp_initialize(struct psp_context *psp)
1176 * TODO: bypass the initialize in sriov for now
1178 if (amdgpu_sriov_vf(psp->adev))
1181 if (!psp->adev->psp.ta_hdcp_ucode_size ||
1182 !psp->adev->psp.ta_hdcp_start_addr) {
1183 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1187 if (!psp->hdcp_context.hdcp_initialized) {
1188 ret = psp_hdcp_init_shared_buf(psp);
1193 ret = psp_hdcp_load(psp);
1200 static int psp_hdcp_unload(struct psp_context *psp)
1203 struct psp_gfx_cmd_resp *cmd;
1206 * TODO: bypass the unloading in sriov for now
1208 if (amdgpu_sriov_vf(psp->adev))
1211 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1215 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1217 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1224 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1227 * TODO: bypass the loading in sriov for now
1229 if (amdgpu_sriov_vf(psp->adev))
1232 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1235 static int psp_hdcp_terminate(struct psp_context *psp)
1240 * TODO: bypass the terminate in sriov for now
1242 if (amdgpu_sriov_vf(psp->adev))
1245 if (!psp->hdcp_context.hdcp_initialized)
1248 ret = psp_hdcp_unload(psp);
1252 psp->hdcp_context.hdcp_initialized = false;
1254 /* free hdcp shared memory */
1255 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1256 &psp->hdcp_context.hdcp_shared_mc_addr,
1257 &psp->hdcp_context.hdcp_shared_buf);
1264 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1269 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1270 * physical) for dtm ta <-> Driver
1272 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1273 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1274 &psp->dtm_context.dtm_shared_bo,
1275 &psp->dtm_context.dtm_shared_mc_addr,
1276 &psp->dtm_context.dtm_shared_buf);
1281 static int psp_dtm_load(struct psp_context *psp)
1284 struct psp_gfx_cmd_resp *cmd;
1287 * TODO: bypass the loading in sriov for now
1289 if (amdgpu_sriov_vf(psp->adev))
1292 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1296 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1297 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1299 psp_prep_ta_load_cmd_buf(cmd,
1300 psp->fw_pri_mc_addr,
1301 psp->ta_dtm_ucode_size,
1302 psp->dtm_context.dtm_shared_mc_addr,
1303 PSP_DTM_SHARED_MEM_SIZE);
1305 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1308 psp->dtm_context.dtm_initialized = true;
1309 psp->dtm_context.session_id = cmd->resp.session_id;
1310 mutex_init(&psp->dtm_context.mutex);
1318 static int psp_dtm_initialize(struct psp_context *psp)
1323 * TODO: bypass the initialize in sriov for now
1325 if (amdgpu_sriov_vf(psp->adev))
1328 if (!psp->adev->psp.ta_dtm_ucode_size ||
1329 !psp->adev->psp.ta_dtm_start_addr) {
1330 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1334 if (!psp->dtm_context.dtm_initialized) {
1335 ret = psp_dtm_init_shared_buf(psp);
1340 ret = psp_dtm_load(psp);
1347 static int psp_dtm_unload(struct psp_context *psp)
1350 struct psp_gfx_cmd_resp *cmd;
1353 * TODO: bypass the unloading in sriov for now
1355 if (amdgpu_sriov_vf(psp->adev))
1358 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1362 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1364 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1371 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1374 * TODO: bypass the loading in sriov for now
1376 if (amdgpu_sriov_vf(psp->adev))
1379 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1382 static int psp_dtm_terminate(struct psp_context *psp)
1387 * TODO: bypass the terminate in sriov for now
1389 if (amdgpu_sriov_vf(psp->adev))
1392 if (!psp->dtm_context.dtm_initialized)
1395 ret = psp_dtm_unload(psp);
1399 psp->dtm_context.dtm_initialized = false;
1401 /* free hdcp shared memory */
1402 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1403 &psp->dtm_context.dtm_shared_mc_addr,
1404 &psp->dtm_context.dtm_shared_buf);
1410 static int psp_hw_start(struct psp_context *psp)
1412 struct amdgpu_device *adev = psp->adev;
1415 if (!amdgpu_sriov_vf(adev)) {
1416 if (psp->kdb_bin_size &&
1417 (psp->funcs->bootloader_load_kdb != NULL)) {
1418 ret = psp_bootloader_load_kdb(psp);
1420 DRM_ERROR("PSP load kdb failed!\n");
1425 if (psp->spl_bin_size) {
1426 ret = psp_bootloader_load_spl(psp);
1428 DRM_ERROR("PSP load spl failed!\n");
1433 ret = psp_bootloader_load_sysdrv(psp);
1435 DRM_ERROR("PSP load sysdrv failed!\n");
1439 ret = psp_bootloader_load_sos(psp);
1441 DRM_ERROR("PSP load sos failed!\n");
1446 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1448 DRM_ERROR("PSP create ring failed!\n");
1452 ret = psp_clear_vf_fw(psp);
1454 DRM_ERROR("PSP clear vf fw!\n");
1458 ret = psp_tmr_init(psp);
1460 DRM_ERROR("PSP tmr init failed!\n");
1465 * For ASICs with DF Cstate management centralized
1466 * to PMFW, TMR setup should be performed after PMFW
1467 * loaded and before other non-psp firmware loaded.
1469 if (psp->pmfw_centralized_cstate_management) {
1470 ret = psp_load_smu_fw(psp);
1475 ret = psp_tmr_load(psp);
1477 DRM_ERROR("PSP load tmr failed!\n");
1484 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1485 enum psp_gfx_fw_type *type)
1487 switch (ucode->ucode_id) {
1488 case AMDGPU_UCODE_ID_SDMA0:
1489 *type = GFX_FW_TYPE_SDMA0;
1491 case AMDGPU_UCODE_ID_SDMA1:
1492 *type = GFX_FW_TYPE_SDMA1;
1494 case AMDGPU_UCODE_ID_SDMA2:
1495 *type = GFX_FW_TYPE_SDMA2;
1497 case AMDGPU_UCODE_ID_SDMA3:
1498 *type = GFX_FW_TYPE_SDMA3;
1500 case AMDGPU_UCODE_ID_SDMA4:
1501 *type = GFX_FW_TYPE_SDMA4;
1503 case AMDGPU_UCODE_ID_SDMA5:
1504 *type = GFX_FW_TYPE_SDMA5;
1506 case AMDGPU_UCODE_ID_SDMA6:
1507 *type = GFX_FW_TYPE_SDMA6;
1509 case AMDGPU_UCODE_ID_SDMA7:
1510 *type = GFX_FW_TYPE_SDMA7;
1512 case AMDGPU_UCODE_ID_CP_MES:
1513 *type = GFX_FW_TYPE_CP_MES;
1515 case AMDGPU_UCODE_ID_CP_MES_DATA:
1516 *type = GFX_FW_TYPE_MES_STACK;
1518 case AMDGPU_UCODE_ID_CP_CE:
1519 *type = GFX_FW_TYPE_CP_CE;
1521 case AMDGPU_UCODE_ID_CP_PFP:
1522 *type = GFX_FW_TYPE_CP_PFP;
1524 case AMDGPU_UCODE_ID_CP_ME:
1525 *type = GFX_FW_TYPE_CP_ME;
1527 case AMDGPU_UCODE_ID_CP_MEC1:
1528 *type = GFX_FW_TYPE_CP_MEC;
1530 case AMDGPU_UCODE_ID_CP_MEC1_JT:
1531 *type = GFX_FW_TYPE_CP_MEC_ME1;
1533 case AMDGPU_UCODE_ID_CP_MEC2:
1534 *type = GFX_FW_TYPE_CP_MEC;
1536 case AMDGPU_UCODE_ID_CP_MEC2_JT:
1537 *type = GFX_FW_TYPE_CP_MEC_ME2;
1539 case AMDGPU_UCODE_ID_RLC_G:
1540 *type = GFX_FW_TYPE_RLC_G;
1542 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1543 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
1545 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
1546 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
1548 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
1549 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
1551 case AMDGPU_UCODE_ID_SMC:
1552 *type = GFX_FW_TYPE_SMU;
1554 case AMDGPU_UCODE_ID_UVD:
1555 *type = GFX_FW_TYPE_UVD;
1557 case AMDGPU_UCODE_ID_UVD1:
1558 *type = GFX_FW_TYPE_UVD1;
1560 case AMDGPU_UCODE_ID_VCE:
1561 *type = GFX_FW_TYPE_VCE;
1563 case AMDGPU_UCODE_ID_VCN:
1564 *type = GFX_FW_TYPE_VCN;
1566 case AMDGPU_UCODE_ID_VCN1:
1567 *type = GFX_FW_TYPE_VCN1;
1569 case AMDGPU_UCODE_ID_DMCU_ERAM:
1570 *type = GFX_FW_TYPE_DMCU_ERAM;
1572 case AMDGPU_UCODE_ID_DMCU_INTV:
1573 *type = GFX_FW_TYPE_DMCU_ISR;
1575 case AMDGPU_UCODE_ID_VCN0_RAM:
1576 *type = GFX_FW_TYPE_VCN0_RAM;
1578 case AMDGPU_UCODE_ID_VCN1_RAM:
1579 *type = GFX_FW_TYPE_VCN1_RAM;
1581 case AMDGPU_UCODE_ID_DMCUB:
1582 *type = GFX_FW_TYPE_DMUB;
1584 case AMDGPU_UCODE_ID_MAXIMUM:
1592 static void psp_print_fw_hdr(struct psp_context *psp,
1593 struct amdgpu_firmware_info *ucode)
1595 struct amdgpu_device *adev = psp->adev;
1596 struct common_firmware_header *hdr;
1598 switch (ucode->ucode_id) {
1599 case AMDGPU_UCODE_ID_SDMA0:
1600 case AMDGPU_UCODE_ID_SDMA1:
1601 case AMDGPU_UCODE_ID_SDMA2:
1602 case AMDGPU_UCODE_ID_SDMA3:
1603 case AMDGPU_UCODE_ID_SDMA4:
1604 case AMDGPU_UCODE_ID_SDMA5:
1605 case AMDGPU_UCODE_ID_SDMA6:
1606 case AMDGPU_UCODE_ID_SDMA7:
1607 hdr = (struct common_firmware_header *)
1608 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1609 amdgpu_ucode_print_sdma_hdr(hdr);
1611 case AMDGPU_UCODE_ID_CP_CE:
1612 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1613 amdgpu_ucode_print_gfx_hdr(hdr);
1615 case AMDGPU_UCODE_ID_CP_PFP:
1616 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1617 amdgpu_ucode_print_gfx_hdr(hdr);
1619 case AMDGPU_UCODE_ID_CP_ME:
1620 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1621 amdgpu_ucode_print_gfx_hdr(hdr);
1623 case AMDGPU_UCODE_ID_CP_MEC1:
1624 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1625 amdgpu_ucode_print_gfx_hdr(hdr);
1627 case AMDGPU_UCODE_ID_RLC_G:
1628 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1629 amdgpu_ucode_print_rlc_hdr(hdr);
1631 case AMDGPU_UCODE_ID_SMC:
1632 hdr = (struct common_firmware_header *)adev->pm.fw->data;
1633 amdgpu_ucode_print_smc_hdr(hdr);
1640 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1641 struct psp_gfx_cmd_resp *cmd)
1644 uint64_t fw_mem_mc_addr = ucode->mc_addr;
1646 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1648 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1649 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1650 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1651 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1653 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1655 DRM_ERROR("Unknown firmware type\n");
1660 static int psp_execute_np_fw_load(struct psp_context *psp,
1661 struct amdgpu_firmware_info *ucode)
1665 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1669 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1670 psp->fence_buf_mc_addr);
1675 static int psp_load_smu_fw(struct psp_context *psp)
1678 struct amdgpu_device* adev = psp->adev;
1679 struct amdgpu_firmware_info *ucode =
1680 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1681 struct amdgpu_ras *ras = psp->ras.ras;
1683 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
1687 if (adev->in_gpu_reset && ras && ras->supported) {
1688 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
1690 DRM_WARN("Failed to set MP1 state prepare for reload\n");
1694 ret = psp_execute_np_fw_load(psp, ucode);
1697 DRM_ERROR("PSP load smu failed!\n");
1702 static bool fw_load_skip_check(struct psp_context *psp,
1703 struct amdgpu_firmware_info *ucode)
1708 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1709 (psp_smu_reload_quirk(psp) ||
1710 psp->autoload_supported ||
1711 psp->pmfw_centralized_cstate_management))
1714 if (amdgpu_sriov_vf(psp->adev) &&
1715 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1716 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1717 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1718 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1719 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1720 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1721 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1722 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1723 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
1724 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
1725 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
1726 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
1727 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
1728 /*skip ucode loading in SRIOV VF */
1731 if (psp->autoload_supported &&
1732 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1733 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1734 /* skip mec JT when autoload is enabled */
1740 static int psp_np_fw_load(struct psp_context *psp)
1743 struct amdgpu_firmware_info *ucode;
1744 struct amdgpu_device* adev = psp->adev;
1746 if (psp->autoload_supported &&
1747 !psp->pmfw_centralized_cstate_management) {
1748 ret = psp_load_smu_fw(psp);
1753 for (i = 0; i < adev->firmware.max_ucodes; i++) {
1754 ucode = &adev->firmware.ucode[i];
1756 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1757 !fw_load_skip_check(psp, ucode)) {
1758 ret = psp_load_smu_fw(psp);
1764 if (fw_load_skip_check(psp, ucode))
1767 if (psp->autoload_supported &&
1768 (adev->asic_type == CHIP_SIENNA_CICHLID ||
1769 adev->asic_type == CHIP_NAVY_FLOUNDER) &&
1770 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
1771 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
1772 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
1773 /* PSP only receive one SDMA fw for sienna_cichlid,
1774 * as all four sdma fw are same */
1777 psp_print_fw_hdr(psp, ucode);
1779 ret = psp_execute_np_fw_load(psp, ucode);
1783 /* Start rlc autoload after psp recieved all the gfx firmware */
1784 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1785 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1786 ret = psp_rlc_autoload_start(psp);
1788 DRM_ERROR("Failed to start rlc autoload\n");
1797 static int psp_load_fw(struct amdgpu_device *adev)
1800 struct psp_context *psp = &adev->psp;
1802 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1803 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1807 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1811 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1812 AMDGPU_GEM_DOMAIN_GTT,
1814 &psp->fw_pri_mc_addr,
1819 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1820 AMDGPU_GEM_DOMAIN_VRAM,
1822 &psp->fence_buf_mc_addr,
1827 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1828 AMDGPU_GEM_DOMAIN_VRAM,
1829 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1830 (void **)&psp->cmd_buf_mem);
1834 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1836 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1838 DRM_ERROR("PSP ring init failed!\n");
1843 ret = psp_hw_start(psp);
1847 ret = psp_np_fw_load(psp);
1851 ret = psp_asd_load(psp);
1853 DRM_ERROR("PSP load asd failed!\n");
1857 if (psp->adev->psp.ta_fw) {
1858 ret = psp_ras_initialize(psp);
1860 dev_err(psp->adev->dev,
1861 "RAS: Failed to initialize RAS\n");
1863 ret = psp_hdcp_initialize(psp);
1865 dev_err(psp->adev->dev,
1866 "HDCP: Failed to initialize HDCP\n");
1868 ret = psp_dtm_initialize(psp);
1870 dev_err(psp->adev->dev,
1871 "DTM: Failed to initialize DTM\n");
1878 * all cleanup jobs (xgmi terminate, ras terminate,
1879 * ring destroy, cmd/fence/fw buffers destory,
1880 * psp->cmd destory) are delayed to psp_hw_fini
1885 static int psp_hw_init(void *handle)
1888 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1890 mutex_lock(&adev->firmware.mutex);
1892 * This sequence is just used on hw_init only once, no need on
1895 ret = amdgpu_ucode_init_bo(adev);
1899 ret = psp_load_fw(adev);
1901 DRM_ERROR("PSP firmware loading failed\n");
1905 mutex_unlock(&adev->firmware.mutex);
1909 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1910 mutex_unlock(&adev->firmware.mutex);
1914 static int psp_hw_fini(void *handle)
1916 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1917 struct psp_context *psp = &adev->psp;
1920 if (psp->adev->psp.ta_fw) {
1921 psp_ras_terminate(psp);
1922 psp_dtm_terminate(psp);
1923 psp_hdcp_terminate(psp);
1926 psp_asd_unload(psp);
1927 ret = psp_clear_vf_fw(psp);
1929 DRM_ERROR("PSP clear vf fw!\n");
1933 psp_tmr_terminate(psp);
1934 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1936 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1937 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1938 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1939 &psp->fence_buf_mc_addr, &psp->fence_buf);
1940 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1941 (void **)&psp->cmd_buf_mem);
1949 static int psp_suspend(void *handle)
1952 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1953 struct psp_context *psp = &adev->psp;
1955 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1956 psp->xgmi_context.initialized == 1) {
1957 ret = psp_xgmi_terminate(psp);
1959 DRM_ERROR("Failed to terminate xgmi ta\n");
1964 if (psp->adev->psp.ta_fw) {
1965 ret = psp_ras_terminate(psp);
1967 DRM_ERROR("Failed to terminate ras ta\n");
1970 ret = psp_hdcp_terminate(psp);
1972 DRM_ERROR("Failed to terminate hdcp ta\n");
1975 ret = psp_dtm_terminate(psp);
1977 DRM_ERROR("Failed to terminate dtm ta\n");
1982 ret = psp_asd_unload(psp);
1984 DRM_ERROR("Failed to unload asd\n");
1988 ret = psp_tmr_terminate(psp);
1990 DRM_ERROR("Falied to terminate tmr\n");
1994 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1996 DRM_ERROR("PSP ring stop failed\n");
2003 static int psp_resume(void *handle)
2006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2007 struct psp_context *psp = &adev->psp;
2009 DRM_INFO("PSP is resuming...\n");
2011 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2013 DRM_ERROR("Failed to process memory training!\n");
2017 mutex_lock(&adev->firmware.mutex);
2019 ret = psp_hw_start(psp);
2023 ret = psp_np_fw_load(psp);
2027 ret = psp_asd_load(psp);
2029 DRM_ERROR("PSP load asd failed!\n");
2033 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2034 ret = psp_xgmi_initialize(psp);
2035 /* Warning the XGMI seesion initialize failure
2036 * Instead of stop driver initialization
2039 dev_err(psp->adev->dev,
2040 "XGMI: Failed to initialize XGMI session\n");
2043 if (psp->adev->psp.ta_fw) {
2044 ret = psp_ras_initialize(psp);
2046 dev_err(psp->adev->dev,
2047 "RAS: Failed to initialize RAS\n");
2049 ret = psp_hdcp_initialize(psp);
2051 dev_err(psp->adev->dev,
2052 "HDCP: Failed to initialize HDCP\n");
2054 ret = psp_dtm_initialize(psp);
2056 dev_err(psp->adev->dev,
2057 "DTM: Failed to initialize DTM\n");
2060 mutex_unlock(&adev->firmware.mutex);
2065 DRM_ERROR("PSP resume failed\n");
2066 mutex_unlock(&adev->firmware.mutex);
2070 int psp_gpu_reset(struct amdgpu_device *adev)
2074 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2077 mutex_lock(&adev->psp.mutex);
2078 ret = psp_mode1_reset(&adev->psp);
2079 mutex_unlock(&adev->psp.mutex);
2084 int psp_rlc_autoload_start(struct psp_context *psp)
2087 struct psp_gfx_cmd_resp *cmd;
2089 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2093 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2095 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2096 psp->fence_buf_mc_addr);
2101 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2102 uint64_t cmd_gpu_addr, int cmd_size)
2104 struct amdgpu_firmware_info ucode = {0};
2106 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2107 AMDGPU_UCODE_ID_VCN0_RAM;
2108 ucode.mc_addr = cmd_gpu_addr;
2109 ucode.ucode_size = cmd_size;
2111 return psp_execute_np_fw_load(&adev->psp, &ucode);
2114 int psp_ring_cmd_submit(struct psp_context *psp,
2115 uint64_t cmd_buf_mc_addr,
2116 uint64_t fence_mc_addr,
2119 unsigned int psp_write_ptr_reg = 0;
2120 struct psp_gfx_rb_frame *write_frame;
2121 struct psp_ring *ring = &psp->km_ring;
2122 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2123 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2124 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2125 struct amdgpu_device *adev = psp->adev;
2126 uint32_t ring_size_dw = ring->ring_size / 4;
2127 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2129 /* KM (GPCOM) prepare write pointer */
2130 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2132 /* Update KM RB frame pointer to new frame */
2133 /* write_frame ptr increments by size of rb_frame in bytes */
2134 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2135 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2136 write_frame = ring_buffer_start;
2138 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2139 /* Check invalid write_frame ptr address */
2140 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2141 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2142 ring_buffer_start, ring_buffer_end, write_frame);
2143 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2147 /* Initialize KM RB frame */
2148 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2150 /* Update KM RB frame */
2151 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2152 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2153 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2154 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2155 write_frame->fence_value = index;
2156 amdgpu_asic_flush_hdp(adev, NULL);
2158 /* Update the write Pointer in DWORDs */
2159 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2160 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2164 int psp_init_asd_microcode(struct psp_context *psp,
2165 const char *chip_name)
2167 struct amdgpu_device *adev = psp->adev;
2169 const struct psp_firmware_header_v1_0 *asd_hdr;
2173 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2177 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2178 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2182 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2186 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2187 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2188 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
2189 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2190 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2191 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2194 dev_err(adev->dev, "fail to initialize asd microcode\n");
2195 release_firmware(adev->psp.asd_fw);
2196 adev->psp.asd_fw = NULL;
2200 int psp_init_sos_microcode(struct psp_context *psp,
2201 const char *chip_name)
2203 struct amdgpu_device *adev = psp->adev;
2205 const struct psp_firmware_header_v1_0 *sos_hdr;
2206 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2207 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2208 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2212 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2216 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2217 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2221 err = amdgpu_ucode_validate(adev->psp.sos_fw);
2225 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2226 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2228 switch (sos_hdr->header.header_version_major) {
2230 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2231 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
2232 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
2233 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
2234 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2235 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2236 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2237 le32_to_cpu(sos_hdr->sos_offset_bytes);
2238 if (sos_hdr->header.header_version_minor == 1) {
2239 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2240 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
2241 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2242 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
2243 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
2244 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2245 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
2247 if (sos_hdr->header.header_version_minor == 2) {
2248 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2249 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
2250 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2251 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
2253 if (sos_hdr->header.header_version_minor == 3) {
2254 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2255 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
2256 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2257 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
2258 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
2259 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2260 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
2261 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
2262 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2263 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
2268 "unsupported psp sos firmware\n");
2276 "failed to init sos firmware\n");
2277 release_firmware(adev->psp.sos_fw);
2278 adev->psp.sos_fw = NULL;
2283 int parse_ta_bin_descriptor(struct psp_context *psp,
2284 const struct ta_fw_bin_desc *desc,
2285 const struct ta_firmware_header_v2_0 *ta_hdr)
2287 uint8_t *ucode_start_addr = NULL;
2289 if (!psp || !desc || !ta_hdr)
2292 ucode_start_addr = (uint8_t *)ta_hdr +
2293 le32_to_cpu(desc->offset_bytes) +
2294 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2296 switch (desc->fw_type) {
2297 case TA_FW_TYPE_PSP_ASD:
2298 psp->asd_fw_version = le32_to_cpu(desc->fw_version);
2299 psp->asd_feature_version = le32_to_cpu(desc->fw_version);
2300 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes);
2301 psp->asd_start_addr = ucode_start_addr;
2303 case TA_FW_TYPE_PSP_XGMI:
2304 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
2305 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes);
2306 psp->ta_xgmi_start_addr = ucode_start_addr;
2308 case TA_FW_TYPE_PSP_RAS:
2309 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version);
2310 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes);
2311 psp->ta_ras_start_addr = ucode_start_addr;
2313 case TA_FW_TYPE_PSP_HDCP:
2314 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
2315 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes);
2316 psp->ta_hdcp_start_addr = ucode_start_addr;
2318 case TA_FW_TYPE_PSP_DTM:
2319 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version);
2320 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes);
2321 psp->ta_dtm_start_addr = ucode_start_addr;
2324 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
2331 int psp_init_ta_microcode(struct psp_context *psp,
2332 const char *chip_name)
2334 struct amdgpu_device *adev = psp->adev;
2336 const struct ta_firmware_header_v2_0 *ta_hdr;
2341 dev_err(adev->dev, "invalid chip name for ta microcode\n");
2345 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
2346 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
2350 err = amdgpu_ucode_validate(adev->psp.ta_fw);
2354 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
2356 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
2357 dev_err(adev->dev, "unsupported TA header version\n");
2362 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
2363 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
2368 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
2369 err = parse_ta_bin_descriptor(psp,
2370 &ta_hdr->ta_fw_bin[ta_index],
2378 dev_err(adev->dev, "fail to initialize ta microcode\n");
2379 release_firmware(adev->psp.ta_fw);
2380 adev->psp.ta_fw = NULL;
2384 static int psp_set_clockgating_state(void *handle,
2385 enum amd_clockgating_state state)
2390 static int psp_set_powergating_state(void *handle,
2391 enum amd_powergating_state state)
2396 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
2397 struct device_attribute *attr,
2400 struct drm_device *ddev = dev_get_drvdata(dev);
2401 struct amdgpu_device *adev = ddev->dev_private;
2405 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2406 DRM_INFO("PSP block is not ready yet.");
2410 mutex_lock(&adev->psp.mutex);
2411 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
2412 mutex_unlock(&adev->psp.mutex);
2415 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
2419 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver);
2422 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
2423 struct device_attribute *attr,
2427 struct drm_device *ddev = dev_get_drvdata(dev);
2428 struct amdgpu_device *adev = ddev->dev_private;
2430 dma_addr_t dma_addr;
2433 const struct firmware *usbc_pd_fw;
2435 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2436 DRM_INFO("PSP block is not ready yet.");
2440 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
2441 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
2445 /* We need contiguous physical mem to place the FW for psp to access */
2446 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
2448 ret = dma_mapping_error(adev->dev, dma_addr);
2452 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
2455 * x86 specific workaround.
2456 * Without it the buffer is invisible in PSP.
2458 * TODO Remove once PSP starts snooping CPU cache
2461 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
2464 mutex_lock(&adev->psp.mutex);
2465 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
2466 mutex_unlock(&adev->psp.mutex);
2469 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
2470 release_firmware(usbc_pd_fw);
2474 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
2481 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
2482 psp_usbc_pd_fw_sysfs_read,
2483 psp_usbc_pd_fw_sysfs_write);
2487 const struct amd_ip_funcs psp_ip_funcs = {
2489 .early_init = psp_early_init,
2491 .sw_init = psp_sw_init,
2492 .sw_fini = psp_sw_fini,
2493 .hw_init = psp_hw_init,
2494 .hw_fini = psp_hw_fini,
2495 .suspend = psp_suspend,
2496 .resume = psp_resume,
2498 .check_soft_reset = NULL,
2499 .wait_for_idle = NULL,
2501 .set_clockgating_state = psp_set_clockgating_state,
2502 .set_powergating_state = psp_set_powergating_state,
2505 static int psp_sysfs_init(struct amdgpu_device *adev)
2507 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
2510 DRM_ERROR("Failed to create USBC PD FW control file!");
2515 static void psp_sysfs_fini(struct amdgpu_device *adev)
2517 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
2520 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
2522 .type = AMD_IP_BLOCK_TYPE_PSP,
2526 .funcs = &psp_ip_funcs,
2529 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
2531 .type = AMD_IP_BLOCK_TYPE_PSP,
2535 .funcs = &psp_ip_funcs,
2538 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
2540 .type = AMD_IP_BLOCK_TYPE_PSP,
2544 .funcs = &psp_ip_funcs,
2547 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
2549 .type = AMD_IP_BLOCK_TYPE_PSP,
2553 .funcs = &psp_ip_funcs,