2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
33 #include "psp_v10_0.h"
34 #include "psp_v11_0.h"
36 static void psp_set_funcs(struct amdgpu_device *adev);
38 static int psp_early_init(void *handle)
40 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
41 struct psp_context *psp = &adev->psp;
45 switch (adev->asic_type) {
48 psp_v3_1_set_psp_funcs(psp);
49 psp->autoload_supported = false;
52 psp_v10_0_set_psp_funcs(psp);
53 psp->autoload_supported = false;
56 psp_v11_0_set_psp_funcs(psp);
57 psp->autoload_supported = false;
60 psp_v11_0_set_psp_funcs(psp);
61 psp->autoload_supported = true;
72 static int psp_sw_init(void *handle)
74 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
75 struct psp_context *psp = &adev->psp;
78 ret = psp_init_microcode(psp);
80 DRM_ERROR("Failed to load psp firmware!\n");
87 static int psp_sw_fini(void *handle)
89 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
91 release_firmware(adev->psp.sos_fw);
92 adev->psp.sos_fw = NULL;
93 release_firmware(adev->psp.asd_fw);
94 adev->psp.asd_fw = NULL;
95 if (adev->psp.ta_fw) {
96 release_firmware(adev->psp.ta_fw);
97 adev->psp.ta_fw = NULL;
102 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
103 uint32_t reg_val, uint32_t mask, bool check_changed)
107 struct amdgpu_device *adev = psp->adev;
109 for (i = 0; i < adev->usec_timeout; i++) {
110 val = RREG32(reg_index);
115 if ((val & mask) == reg_val)
125 psp_cmd_submit_buf(struct psp_context *psp,
126 struct amdgpu_firmware_info *ucode,
127 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
133 mutex_lock(&psp->mutex);
135 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
137 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
139 index = atomic_inc_return(&psp->fence_value);
140 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
141 fence_mc_addr, index);
143 atomic_dec(&psp->fence_value);
144 mutex_unlock(&psp->mutex);
148 while (*((unsigned int *)psp->fence_buf) != index) {
154 /* In some cases, psp response status is not 0 even there is no
155 * problem while the command is submitted. Some version of PSP FW
156 * doesn't write 0 to that field.
157 * So here we would like to only print a warning instead of an error
158 * during psp initialization to avoid breaking hw_init and it doesn't
161 if (psp->cmd_buf_mem->resp.status || !timeout) {
163 DRM_WARN("failed to load ucode id (%d) ",
165 DRM_WARN("psp command failed and response status is (%d)\n",
166 psp->cmd_buf_mem->resp.status);
168 mutex_unlock(&psp->mutex);
173 /* get xGMI session id from response buffer */
174 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
177 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
178 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
180 mutex_unlock(&psp->mutex);
185 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
186 struct psp_gfx_cmd_resp *cmd,
187 uint64_t tmr_mc, uint32_t size)
189 if (psp_support_vmr_ring(psp))
190 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
192 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
193 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
194 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
195 cmd->cmd.cmd_setup_tmr.buf_size = size;
198 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
199 uint64_t pri_buf_mc, uint32_t size)
201 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
202 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
203 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
204 cmd->cmd.cmd_load_toc.toc_size = size;
207 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
208 static int psp_load_toc(struct psp_context *psp,
212 struct psp_gfx_cmd_resp *cmd;
214 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
217 /* Copy toc to psp firmware private buffer */
218 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
219 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
221 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
223 ret = psp_cmd_submit_buf(psp, NULL, cmd,
224 psp->fence_buf_mc_addr);
226 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
231 /* Set up Trusted Memory Region */
232 static int psp_tmr_init(struct psp_context *psp)
238 * According to HW engineer, they prefer the TMR address be "naturally
239 * aligned" , e.g. the start address be an integer divide of TMR size.
241 * Note: this memory need be reserved till the driver
244 tmr_size = PSP_TMR_SIZE;
246 /* For ASICs support RLC autoload, psp will parse the toc
247 * and calculate the total size of TMR needed */
248 if (psp->toc_start_addr &&
251 ret = psp_load_toc(psp, &tmr_size);
253 DRM_ERROR("Failed to load toc\n");
258 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
259 AMDGPU_GEM_DOMAIN_VRAM,
260 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
265 static int psp_tmr_load(struct psp_context *psp)
268 struct psp_gfx_cmd_resp *cmd;
270 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
274 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
275 amdgpu_bo_size(psp->tmr_bo));
276 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
277 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
279 ret = psp_cmd_submit_buf(psp, NULL, cmd,
280 psp->fence_buf_mc_addr);
293 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
294 uint64_t asd_mc, uint64_t asd_mc_shared,
295 uint32_t size, uint32_t shared_size)
297 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
298 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
299 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
300 cmd->cmd.cmd_load_ta.app_len = size;
302 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
303 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
304 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
307 static int psp_asd_init(struct psp_context *psp)
312 * Allocate 16k memory aligned to 4k from Frame Buffer (local
313 * physical) for shared ASD <-> Driver
315 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
316 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
318 &psp->asd_shared_mc_addr,
319 &psp->asd_shared_buf);
324 static int psp_asd_load(struct psp_context *psp)
327 struct psp_gfx_cmd_resp *cmd;
329 /* If PSP version doesn't match ASD version, asd loading will be failed.
330 * add workaround to bypass it for sriov now.
331 * TODO: add version check to make it common
333 if (amdgpu_sriov_vf(psp->adev))
336 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
340 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
341 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
343 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
344 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
346 ret = psp_cmd_submit_buf(psp, NULL, cmd,
347 psp->fence_buf_mc_addr);
354 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
355 uint32_t id, uint32_t value)
357 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
358 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
359 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
362 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
365 struct psp_gfx_cmd_resp *cmd = NULL;
368 if (reg >= PSP_REG_LAST)
371 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
375 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
376 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
382 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
383 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
384 uint32_t xgmi_ta_size, uint32_t shared_size)
386 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
387 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
388 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
389 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
391 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
392 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
393 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
396 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
401 * Allocate 16k memory aligned to 4k from Frame Buffer (local
402 * physical) for xgmi ta <-> Driver
404 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
405 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
406 &psp->xgmi_context.xgmi_shared_bo,
407 &psp->xgmi_context.xgmi_shared_mc_addr,
408 &psp->xgmi_context.xgmi_shared_buf);
413 static int psp_xgmi_load(struct psp_context *psp)
416 struct psp_gfx_cmd_resp *cmd;
419 * TODO: bypass the loading in sriov for now
421 if (amdgpu_sriov_vf(psp->adev))
424 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
428 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
429 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
431 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
432 psp->xgmi_context.xgmi_shared_mc_addr,
433 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
435 ret = psp_cmd_submit_buf(psp, NULL, cmd,
436 psp->fence_buf_mc_addr);
439 psp->xgmi_context.initialized = 1;
440 psp->xgmi_context.session_id = cmd->resp.session_id;
448 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
449 uint32_t xgmi_session_id)
451 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
452 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
455 static int psp_xgmi_unload(struct psp_context *psp)
458 struct psp_gfx_cmd_resp *cmd;
461 * TODO: bypass the unloading in sriov for now
463 if (amdgpu_sriov_vf(psp->adev))
466 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
470 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
472 ret = psp_cmd_submit_buf(psp, NULL, cmd,
473 psp->fence_buf_mc_addr);
480 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
482 uint32_t xgmi_session_id)
484 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
485 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
486 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
487 /* Note: cmd_invoke_cmd.buf is not used for now */
490 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
493 struct psp_gfx_cmd_resp *cmd;
496 * TODO: bypass the loading in sriov for now
498 if (amdgpu_sriov_vf(psp->adev))
501 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
505 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
506 psp->xgmi_context.session_id);
508 ret = psp_cmd_submit_buf(psp, NULL, cmd,
509 psp->fence_buf_mc_addr);
516 static int psp_xgmi_terminate(struct psp_context *psp)
520 if (!psp->xgmi_context.initialized)
523 ret = psp_xgmi_unload(psp);
527 psp->xgmi_context.initialized = 0;
529 /* free xgmi shared memory */
530 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
531 &psp->xgmi_context.xgmi_shared_mc_addr,
532 &psp->xgmi_context.xgmi_shared_buf);
537 static int psp_xgmi_initialize(struct psp_context *psp)
539 struct ta_xgmi_shared_memory *xgmi_cmd;
542 if (!psp->adev->psp.ta_fw)
545 if (!psp->xgmi_context.initialized) {
546 ret = psp_xgmi_init_shared_buf(psp);
552 ret = psp_xgmi_load(psp);
556 /* Initialize XGMI session */
557 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
558 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
559 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
561 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
567 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
568 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
569 uint32_t ras_ta_size, uint32_t shared_size)
571 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
572 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
573 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
574 cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
576 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
577 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
578 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
581 static int psp_ras_init_shared_buf(struct psp_context *psp)
586 * Allocate 16k memory aligned to 4k from Frame Buffer (local
587 * physical) for ras ta <-> Driver
589 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
590 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
591 &psp->ras.ras_shared_bo,
592 &psp->ras.ras_shared_mc_addr,
593 &psp->ras.ras_shared_buf);
598 static int psp_ras_load(struct psp_context *psp)
601 struct psp_gfx_cmd_resp *cmd;
604 * TODO: bypass the loading in sriov for now
606 if (amdgpu_sriov_vf(psp->adev))
609 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
613 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
614 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
616 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
617 psp->ras.ras_shared_mc_addr,
618 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
620 ret = psp_cmd_submit_buf(psp, NULL, cmd,
621 psp->fence_buf_mc_addr);
624 psp->ras.ras_initialized = 1;
625 psp->ras.session_id = cmd->resp.session_id;
633 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
634 uint32_t ras_session_id)
636 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
637 cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
640 static int psp_ras_unload(struct psp_context *psp)
643 struct psp_gfx_cmd_resp *cmd;
646 * TODO: bypass the unloading in sriov for now
648 if (amdgpu_sriov_vf(psp->adev))
651 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
655 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
657 ret = psp_cmd_submit_buf(psp, NULL, cmd,
658 psp->fence_buf_mc_addr);
665 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
667 uint32_t ras_session_id)
669 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
670 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
671 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
672 /* Note: cmd_invoke_cmd.buf is not used for now */
675 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
678 struct psp_gfx_cmd_resp *cmd;
681 * TODO: bypass the loading in sriov for now
683 if (amdgpu_sriov_vf(psp->adev))
686 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
690 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
691 psp->ras.session_id);
693 ret = psp_cmd_submit_buf(psp, NULL, cmd,
694 psp->fence_buf_mc_addr);
701 int psp_ras_enable_features(struct psp_context *psp,
702 union ta_ras_cmd_input *info, bool enable)
704 struct ta_ras_shared_memory *ras_cmd;
707 if (!psp->ras.ras_initialized)
710 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
711 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
714 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
716 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
718 ras_cmd->ras_in_message = *info;
720 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
724 return ras_cmd->ras_status;
727 static int psp_ras_terminate(struct psp_context *psp)
731 if (!psp->ras.ras_initialized)
734 ret = psp_ras_unload(psp);
738 psp->ras.ras_initialized = 0;
740 /* free ras shared memory */
741 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
742 &psp->ras.ras_shared_mc_addr,
743 &psp->ras.ras_shared_buf);
748 static int psp_ras_initialize(struct psp_context *psp)
752 if (!psp->ras.ras_initialized) {
753 ret = psp_ras_init_shared_buf(psp);
758 ret = psp_ras_load(psp);
766 static int psp_hw_start(struct psp_context *psp)
768 struct amdgpu_device *adev = psp->adev;
771 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
772 if (psp->kdb_bin_size &&
773 (psp->funcs->bootloader_load_kdb != NULL)) {
774 ret = psp_bootloader_load_kdb(psp);
776 DRM_ERROR("PSP load kdb failed!\n");
781 ret = psp_bootloader_load_sysdrv(psp);
783 DRM_ERROR("PSP load sysdrv failed!\n");
787 ret = psp_bootloader_load_sos(psp);
789 DRM_ERROR("PSP load sos failed!\n");
794 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
796 DRM_ERROR("PSP create ring failed!\n");
800 ret = psp_tmr_init(psp);
802 DRM_ERROR("PSP tmr init failed!\n");
806 ret = psp_tmr_load(psp);
808 DRM_ERROR("PSP load tmr failed!\n");
812 ret = psp_asd_init(psp);
814 DRM_ERROR("PSP asd init failed!\n");
818 ret = psp_asd_load(psp);
820 DRM_ERROR("PSP load asd failed!\n");
824 if (adev->gmc.xgmi.num_physical_nodes > 1) {
825 ret = psp_xgmi_initialize(psp);
826 /* Warning the XGMI seesion initialize failure
827 * Instead of stop driver initialization
830 dev_err(psp->adev->dev,
831 "XGMI: Failed to initialize XGMI session\n");
835 if (psp->adev->psp.ta_fw) {
836 ret = psp_ras_initialize(psp);
838 dev_err(psp->adev->dev,
839 "RAS: Failed to initialize RAS\n");
845 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
846 enum psp_gfx_fw_type *type)
848 switch (ucode->ucode_id) {
849 case AMDGPU_UCODE_ID_SDMA0:
850 *type = GFX_FW_TYPE_SDMA0;
852 case AMDGPU_UCODE_ID_SDMA1:
853 *type = GFX_FW_TYPE_SDMA1;
855 case AMDGPU_UCODE_ID_CP_CE:
856 *type = GFX_FW_TYPE_CP_CE;
858 case AMDGPU_UCODE_ID_CP_PFP:
859 *type = GFX_FW_TYPE_CP_PFP;
861 case AMDGPU_UCODE_ID_CP_ME:
862 *type = GFX_FW_TYPE_CP_ME;
864 case AMDGPU_UCODE_ID_CP_MEC1:
865 *type = GFX_FW_TYPE_CP_MEC;
867 case AMDGPU_UCODE_ID_CP_MEC1_JT:
868 *type = GFX_FW_TYPE_CP_MEC_ME1;
870 case AMDGPU_UCODE_ID_CP_MEC2:
871 *type = GFX_FW_TYPE_CP_MEC;
873 case AMDGPU_UCODE_ID_CP_MEC2_JT:
874 *type = GFX_FW_TYPE_CP_MEC_ME2;
876 case AMDGPU_UCODE_ID_RLC_G:
877 *type = GFX_FW_TYPE_RLC_G;
879 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
880 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
882 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
883 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
885 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
886 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
888 case AMDGPU_UCODE_ID_SMC:
889 *type = GFX_FW_TYPE_SMU;
891 case AMDGPU_UCODE_ID_UVD:
892 *type = GFX_FW_TYPE_UVD;
894 case AMDGPU_UCODE_ID_UVD1:
895 *type = GFX_FW_TYPE_UVD1;
897 case AMDGPU_UCODE_ID_VCE:
898 *type = GFX_FW_TYPE_VCE;
900 case AMDGPU_UCODE_ID_VCN:
901 *type = GFX_FW_TYPE_VCN;
903 case AMDGPU_UCODE_ID_DMCU_ERAM:
904 *type = GFX_FW_TYPE_DMCU_ERAM;
906 case AMDGPU_UCODE_ID_DMCU_INTV:
907 *type = GFX_FW_TYPE_DMCU_ISR;
909 case AMDGPU_UCODE_ID_VCN0_RAM:
910 *type = GFX_FW_TYPE_VCN0_RAM;
912 case AMDGPU_UCODE_ID_VCN1_RAM:
913 *type = GFX_FW_TYPE_VCN1_RAM;
915 case AMDGPU_UCODE_ID_MAXIMUM:
923 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
924 struct psp_gfx_cmd_resp *cmd)
927 uint64_t fw_mem_mc_addr = ucode->mc_addr;
929 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
931 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
932 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
933 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
934 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
936 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
938 DRM_ERROR("Unknown firmware type\n");
943 static int psp_execute_np_fw_load(struct psp_context *psp,
944 struct amdgpu_firmware_info *ucode)
948 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
952 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
953 psp->fence_buf_mc_addr);
958 static int psp_np_fw_load(struct psp_context *psp)
961 struct amdgpu_firmware_info *ucode;
962 struct amdgpu_device* adev = psp->adev;
964 if (psp->autoload_supported) {
965 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
969 ret = psp_execute_np_fw_load(psp, ucode);
975 for (i = 0; i < adev->firmware.max_ucodes; i++) {
976 ucode = &adev->firmware.ucode[i];
980 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
981 (psp_smu_reload_quirk(psp) || psp->autoload_supported))
983 if (amdgpu_sriov_vf(adev) &&
984 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
985 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
986 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
987 /*skip ucode loading in SRIOV VF */
989 if (psp->autoload_supported &&
990 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
991 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
992 /* skip mec JT when autoload is enabled */
995 ret = psp_execute_np_fw_load(psp, ucode);
999 /* Start rlc autoload after psp recieved all the gfx firmware */
1000 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
1001 ret = psp_rlc_autoload(psp);
1003 DRM_ERROR("Failed to start rlc autoload\n");
1008 /* check if firmware loaded sucessfully */
1009 if (!amdgpu_psp_check_fw_loading_status(adev, i))
1017 static int psp_load_fw(struct amdgpu_device *adev)
1020 struct psp_context *psp = &adev->psp;
1022 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1023 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1027 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1031 /* this fw pri bo is not used under SRIOV */
1032 if (!amdgpu_sriov_vf(psp->adev)) {
1033 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1034 AMDGPU_GEM_DOMAIN_GTT,
1036 &psp->fw_pri_mc_addr,
1042 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1043 AMDGPU_GEM_DOMAIN_VRAM,
1045 &psp->fence_buf_mc_addr,
1050 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1051 AMDGPU_GEM_DOMAIN_VRAM,
1052 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1053 (void **)&psp->cmd_buf_mem);
1057 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1059 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1061 DRM_ERROR("PSP ring init failed!\n");
1066 ret = psp_hw_start(psp);
1070 ret = psp_np_fw_load(psp);
1078 * all cleanup jobs (xgmi terminate, ras terminate,
1079 * ring destroy, cmd/fence/fw buffers destory,
1080 * psp->cmd destory) are delayed to psp_hw_fini
1085 static int psp_hw_init(void *handle)
1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090 mutex_lock(&adev->firmware.mutex);
1092 * This sequence is just used on hw_init only once, no need on
1095 ret = amdgpu_ucode_init_bo(adev);
1099 ret = psp_load_fw(adev);
1101 DRM_ERROR("PSP firmware loading failed\n");
1105 mutex_unlock(&adev->firmware.mutex);
1109 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1110 mutex_unlock(&adev->firmware.mutex);
1114 static int psp_hw_fini(void *handle)
1116 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1117 struct psp_context *psp = &adev->psp;
1119 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1120 psp->xgmi_context.initialized == 1)
1121 psp_xgmi_terminate(psp);
1123 if (psp->adev->psp.ta_fw)
1124 psp_ras_terminate(psp);
1126 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1128 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
1129 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1130 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1131 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1132 &psp->fence_buf_mc_addr, &psp->fence_buf);
1133 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
1134 &psp->asd_shared_buf);
1135 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1136 (void **)&psp->cmd_buf_mem);
1144 static int psp_suspend(void *handle)
1147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148 struct psp_context *psp = &adev->psp;
1150 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1151 psp->xgmi_context.initialized == 1) {
1152 ret = psp_xgmi_terminate(psp);
1154 DRM_ERROR("Failed to terminate xgmi ta\n");
1159 if (psp->adev->psp.ta_fw) {
1160 ret = psp_ras_terminate(psp);
1162 DRM_ERROR("Failed to terminate ras ta\n");
1167 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1169 DRM_ERROR("PSP ring stop failed\n");
1176 static int psp_resume(void *handle)
1179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1180 struct psp_context *psp = &adev->psp;
1182 DRM_INFO("PSP is resuming...\n");
1184 mutex_lock(&adev->firmware.mutex);
1186 ret = psp_hw_start(psp);
1190 ret = psp_np_fw_load(psp);
1194 mutex_unlock(&adev->firmware.mutex);
1199 DRM_ERROR("PSP resume failed\n");
1200 mutex_unlock(&adev->firmware.mutex);
1204 int psp_gpu_reset(struct amdgpu_device *adev)
1208 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1211 mutex_lock(&adev->psp.mutex);
1212 ret = psp_mode1_reset(&adev->psp);
1213 mutex_unlock(&adev->psp.mutex);
1218 int psp_rlc_autoload_start(struct psp_context *psp)
1221 struct psp_gfx_cmd_resp *cmd;
1223 if (amdgpu_sriov_vf(psp->adev))
1226 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1230 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1232 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1233 psp->fence_buf_mc_addr);
1238 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1239 uint64_t cmd_gpu_addr, int cmd_size)
1241 struct amdgpu_firmware_info ucode = {0};
1243 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1244 AMDGPU_UCODE_ID_VCN0_RAM;
1245 ucode.mc_addr = cmd_gpu_addr;
1246 ucode.ucode_size = cmd_size;
1248 return psp_execute_np_fw_load(&adev->psp, &ucode);
1251 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1252 enum AMDGPU_UCODE_ID ucode_type)
1254 struct amdgpu_firmware_info *ucode = NULL;
1256 if (!adev->firmware.fw_size)
1259 ucode = &adev->firmware.ucode[ucode_type];
1260 if (!ucode->fw || !ucode->ucode_size)
1263 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1266 static int psp_set_clockgating_state(void *handle,
1267 enum amd_clockgating_state state)
1272 static int psp_set_powergating_state(void *handle,
1273 enum amd_powergating_state state)
1278 const struct amd_ip_funcs psp_ip_funcs = {
1280 .early_init = psp_early_init,
1282 .sw_init = psp_sw_init,
1283 .sw_fini = psp_sw_fini,
1284 .hw_init = psp_hw_init,
1285 .hw_fini = psp_hw_fini,
1286 .suspend = psp_suspend,
1287 .resume = psp_resume,
1289 .check_soft_reset = NULL,
1290 .wait_for_idle = NULL,
1292 .set_clockgating_state = psp_set_clockgating_state,
1293 .set_powergating_state = psp_set_powergating_state,
1296 static const struct amdgpu_psp_funcs psp_funcs = {
1297 .check_fw_loading_status = psp_check_fw_loading_status,
1300 static void psp_set_funcs(struct amdgpu_device *adev)
1302 if (NULL == adev->firmware.funcs)
1303 adev->firmware.funcs = &psp_funcs;
1306 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1308 .type = AMD_IP_BLOCK_TYPE_PSP,
1312 .funcs = &psp_ip_funcs,
1315 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1317 .type = AMD_IP_BLOCK_TYPE_PSP,
1321 .funcs = &psp_ip_funcs,
1324 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1326 .type = AMD_IP_BLOCK_TYPE_PSP,
1330 .funcs = &psp_ip_funcs,