drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <linux/dma-mapping.h>
  28 #include <drm/drm_drv.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_ucode.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v12_0.h"
  38 #include "psp_v13_0.h"
  39
  40 #include "amdgpu_ras.h"
  41 #include "amdgpu_securedisplay.h"
  42 #include "amdgpu_atomfirmware.h"
  43
  44 #include <drm/drm_drv.h>
  45
  46 static int psp_sysfs_init(struct amdgpu_device *adev);
  47 static void psp_sysfs_fini(struct amdgpu_device *adev);
  48
  49 static int psp_load_smu_fw(struct psp_context *psp);
  50
  51 /*
  52  * Due to DF Cstate management centralized to PMFW, the firmware
  53  * loading sequence will be updated as below:
  54  *   - Load KDB
  55  *   - Load SYS_DRV
  56  *   - Load tOS
  57  *   - Load PMFW
  58  *   - Setup TMR
  59  *   - Load other non-psp fw
  60  *   - Load ASD
  61  *   - Load XGMI/RAS/HDCP/DTM TA if any
  62  *
  63  * This new sequence is required for
  64  *   - Arcturus and onwards
  65  *   - Navi12 and onwards
  66  */
  67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  68 {
  69         struct amdgpu_device *adev = psp->adev;
  70
  71         psp->pmfw_centralized_cstate_management = false;
  72
  73         if (amdgpu_sriov_vf(adev))
  74                 return;
  75
  76         if (adev->flags & AMD_IS_APU)
  77                 return;
  78
  79         if ((adev->asic_type >= CHIP_ARCTURUS) ||
  80             (adev->asic_type >= CHIP_NAVI12))
  81                 psp->pmfw_centralized_cstate_management = true;
  82 }
  83
  84 static int psp_early_init(void *handle)
  85 {
  86         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  87         struct psp_context *psp = &adev->psp;
  88
  89         switch (adev->asic_type) {
  90         case CHIP_VEGA10:
  91         case CHIP_VEGA12:
  92                 psp_v3_1_set_psp_funcs(psp);
  93                 psp->autoload_supported = false;
  94                 break;
  95         case CHIP_RAVEN:
  96                 psp_v10_0_set_psp_funcs(psp);
  97                 psp->autoload_supported = false;
  98                 break;
  99         case CHIP_VEGA20:
 100         case CHIP_ARCTURUS:
 101                 psp_v11_0_set_psp_funcs(psp);
 102                 psp->autoload_supported = false;
 103                 break;
 104         case CHIP_NAVI10:
 105         case CHIP_NAVI14:
 106         case CHIP_NAVI12:
 107         case CHIP_SIENNA_CICHLID:
 108         case CHIP_NAVY_FLOUNDER:
 109         case CHIP_VANGOGH:
 110         case CHIP_DIMGREY_CAVEFISH:
 111         case CHIP_BEIGE_GOBY:
 112                 psp_v11_0_set_psp_funcs(psp);
 113                 psp->autoload_supported = true;
 114                 break;
 115         case CHIP_RENOIR:
 116                 psp_v12_0_set_psp_funcs(psp);
 117                 break;
 118         case CHIP_ALDEBARAN:
 119                 psp_v13_0_set_psp_funcs(psp);
 120                 break;
 121         case CHIP_YELLOW_CARP:
 122                 psp_v13_0_set_psp_funcs(psp);
 123                 psp->autoload_supported = true;
 124                 break;
 125         default:
 126                 return -EINVAL;
 127         }
 128
 129         psp->adev = adev;
 130
 131         psp_check_pmfw_centralized_cstate_management(psp);
 132
 133         return 0;
 134 }
 135
 136 static void psp_memory_training_fini(struct psp_context *psp)
 137 {
 138         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 139
 140         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 141         kfree(ctx->sys_cache);
 142         ctx->sys_cache = NULL;
 143 }
 144
 145 static int psp_memory_training_init(struct psp_context *psp)
 146 {
 147         int ret;
 148         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 149
 150         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 151                 DRM_DEBUG("memory training is not supported!\n");
 152                 return 0;
 153         }
 154
 155         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 156         if (ctx->sys_cache == NULL) {
 157                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 158                 ret = -ENOMEM;
 159                 goto Err_out;
 160         }
 161
 162         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 163                   ctx->train_data_size,
 164                   ctx->p2c_train_data_offset,
 165                   ctx->c2p_train_data_offset);
 166         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 167         return 0;
 168
 169 Err_out:
 170         psp_memory_training_fini(psp);
 171         return ret;
 172 }
 173
 174 static int psp_sw_init(void *handle)
 175 {
 176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 177         struct psp_context *psp = &adev->psp;
 178         int ret;
 179
 180         if (!amdgpu_sriov_vf(adev)) {
 181                 ret = psp_init_microcode(psp);
 182                 if (ret) {
 183                         DRM_ERROR("Failed to load psp firmware!\n");
 184                         return ret;
 185                 }
 186         } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
 187                 ret = psp_init_ta_microcode(psp, "aldebaran");
 188                 if (ret) {
 189                         DRM_ERROR("Failed to initialize ta microcode!\n");
 190                         return ret;
 191                 }
 192         }
 193
 194         ret = psp_memory_training_init(psp);
 195         if (ret) {
 196                 DRM_ERROR("Failed to initialize memory training!\n");
 197                 return ret;
 198         }
 199         ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 200         if (ret) {
 201                 DRM_ERROR("Failed to process memory training!\n");
 202                 return ret;
 203         }
 204
 205         if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
 206                 ret= psp_sysfs_init(adev);
 207                 if (ret) {
 208                         return ret;
 209                 }
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int psp_sw_fini(void *handle)
 216 {
 217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 218
 219         psp_memory_training_fini(&adev->psp);
 220         if (adev->psp.sos_fw) {
 221                 release_firmware(adev->psp.sos_fw);
 222                 adev->psp.sos_fw = NULL;
 223         }
 224         if (adev->psp.asd_fw) {
 225                 release_firmware(adev->psp.asd_fw);
 226                 adev->psp.asd_fw = NULL;
 227         }
 228         if (adev->psp.ta_fw) {
 229                 release_firmware(adev->psp.ta_fw);
 230                 adev->psp.ta_fw = NULL;
 231         }
 232
 233         if (adev->asic_type == CHIP_NAVI10 ||
 234             adev->asic_type == CHIP_SIENNA_CICHLID)
 235                 psp_sysfs_fini(adev);
 236
 237         return 0;
 238 }
 239
 240 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 241                  uint32_t reg_val, uint32_t mask, bool check_changed)
 242 {
 243         uint32_t val;
 244         int i;
 245         struct amdgpu_device *adev = psp->adev;
 246
 247         if (psp->adev->no_hw_access)
 248                 return 0;
 249
 250         for (i = 0; i < adev->usec_timeout; i++) {
 251                 val = RREG32(reg_index);
 252                 if (check_changed) {
 253                         if (val != reg_val)
 254                                 return 0;
 255                 } else {
 256                         if ((val & mask) == reg_val)
 257                                 return 0;
 258                 }
 259                 udelay(1);
 260         }
 261
 262         return -ETIME;
 263 }
 264
 265 static int
 266 psp_cmd_submit_buf(struct psp_context *psp,
 267                    struct amdgpu_firmware_info *ucode,
 268                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 269 {
 270         int ret;
 271         int index, idx;
 272         int timeout = 20000;
 273         bool ras_intr = false;
 274         bool skip_unsupport = false;
 275
 276         if (psp->adev->no_hw_access)
 277                 return 0;
 278
 279         if (!drm_dev_enter(&psp->adev->ddev, &idx))
 280                 return 0;
 281
 282         mutex_lock(&psp->mutex);
 283
 284         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 285
 286         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 287
 288         index = atomic_inc_return(&psp->fence_value);
 289         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 290         if (ret) {
 291                 atomic_dec(&psp->fence_value);
 292                 goto exit;
 293         }
 294
 295         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 296         while (*((unsigned int *)psp->fence_buf) != index) {
 297                 if (--timeout == 0)
 298                         break;
 299                 /*
 300                  * Shouldn't wait for timeout when err_event_athub occurs,
 301                  * because gpu reset thread triggered and lock resource should
 302                  * be released for psp resume sequence.
 303                  */
 304                 ras_intr = amdgpu_ras_intr_triggered();
 305                 if (ras_intr)
 306                         break;
 307                 usleep_range(10, 100);
 308                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 309         }
 310
 311         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 312         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 313                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 314
 315         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 316
 317         /* In some cases, psp response status is not 0 even there is no
 318          * problem while the command is submitted. Some version of PSP FW
 319          * doesn't write 0 to that field.
 320          * So here we would like to only print a warning instead of an error
 321          * during psp initialization to avoid breaking hw_init and it doesn't
 322          * return -EINVAL.
 323          */
 324         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 325                 if (ucode)
 326                         DRM_WARN("failed to load ucode id (%d) ",
 327                                   ucode->ucode_id);
 328                 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
 329                          psp->cmd_buf_mem->cmd_id,
 330                          psp->cmd_buf_mem->resp.status);
 331                 if (!timeout) {
 332                         ret = -EINVAL;
 333                         goto exit;
 334                 }
 335         }
 336
 337         if (ucode) {
 338                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 339                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 340         }
 341
 342 exit:
 343         mutex_unlock(&psp->mutex);
 344         drm_dev_exit(idx);
 345         return ret;
 346 }
 347
 348 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 349                                  struct psp_gfx_cmd_resp *cmd,
 350                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 351 {
 352         struct amdgpu_device *adev = psp->adev;
 353         uint32_t size = amdgpu_bo_size(tmr_bo);
 354         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 355
 356         if (amdgpu_sriov_vf(psp->adev))
 357                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 358         else
 359                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 360         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 361         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 362         cmd->cmd.cmd_setup_tmr.buf_size = size;
 363         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 364         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 365         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 366 }
 367
 368 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 369                                       uint64_t pri_buf_mc, uint32_t size)
 370 {
 371         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 372         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 373         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 374         cmd->cmd.cmd_load_toc.toc_size = size;
 375 }
 376
 377 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 378 static int psp_load_toc(struct psp_context *psp,
 379                         uint32_t *tmr_size)
 380 {
 381         int ret;
 382         struct psp_gfx_cmd_resp *cmd;
 383
 384         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 385         if (!cmd)
 386                 return -ENOMEM;
 387         /* Copy toc to psp firmware private buffer */
 388         psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size);
 389
 390         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 391
 392         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 393                                  psp->fence_buf_mc_addr);
 394         if (!ret)
 395                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 396         kfree(cmd);
 397         return ret;
 398 }
 399
 400 /* Set up Trusted Memory Region */
 401 static int psp_tmr_init(struct psp_context *psp)
 402 {
 403         int ret;
 404         int tmr_size;
 405         void *tmr_buf;
 406         void **pptr;
 407
 408         /*
 409          * According to HW engineer, they prefer the TMR address be "naturally
 410          * aligned" , e.g. the start address be an integer divide of TMR size.
 411          *
 412          * Note: this memory need be reserved till the driver
 413          * uninitializes.
 414          */
 415         tmr_size = PSP_TMR_SIZE(psp->adev);
 416
 417         /* For ASICs support RLC autoload, psp will parse the toc
 418          * and calculate the total size of TMR needed */
 419         if (!amdgpu_sriov_vf(psp->adev) &&
 420             psp->toc_start_addr &&
 421             psp->toc_bin_size &&
 422             psp->fw_pri_buf) {
 423                 ret = psp_load_toc(psp, &tmr_size);
 424                 if (ret) {
 425                         DRM_ERROR("Failed to load toc\n");
 426                         return ret;
 427                 }
 428         }
 429
 430         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 431         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
 432                                       AMDGPU_GEM_DOMAIN_VRAM,
 433                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 434
 435         return ret;
 436 }
 437
 438 static bool psp_skip_tmr(struct psp_context *psp)
 439 {
 440         switch (psp->adev->asic_type) {
 441         case CHIP_NAVI12:
 442         case CHIP_SIENNA_CICHLID:
 443         case CHIP_ALDEBARAN:
 444                 return true;
 445         default:
 446                 return false;
 447         }
 448 }
 449
 450 static int psp_tmr_load(struct psp_context *psp)
 451 {
 452         int ret;
 453         struct psp_gfx_cmd_resp *cmd;
 454
 455         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 456          * Already set up by host driver.
 457          */
 458         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 459                 return 0;
 460
 461         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 462         if (!cmd)
 463                 return -ENOMEM;
 464
 465         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 466         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 467                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 468
 469         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 470                                  psp->fence_buf_mc_addr);
 471
 472         kfree(cmd);
 473
 474         return ret;
 475 }
 476
 477 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 478                                         struct psp_gfx_cmd_resp *cmd)
 479 {
 480         if (amdgpu_sriov_vf(psp->adev))
 481                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 482         else
 483                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 484 }
 485
 486 static int psp_tmr_unload(struct psp_context *psp)
 487 {
 488         int ret;
 489         struct psp_gfx_cmd_resp *cmd;
 490
 491         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 492         if (!cmd)
 493                 return -ENOMEM;
 494
 495         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 496         DRM_INFO("free PSP TMR buffer\n");
 497
 498         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 499                                  psp->fence_buf_mc_addr);
 500
 501         kfree(cmd);
 502
 503         return ret;
 504 }
 505
 506 static int psp_tmr_terminate(struct psp_context *psp)
 507 {
 508         int ret;
 509         void *tmr_buf;
 510         void **pptr;
 511
 512         ret = psp_tmr_unload(psp);
 513         if (ret)
 514                 return ret;
 515
 516         /* free TMR memory buffer */
 517         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 518         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 519
 520         return 0;
 521 }
 522
 523 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 524                                         uint64_t *output_ptr)
 525 {
 526         int ret;
 527         struct psp_gfx_cmd_resp *cmd;
 528
 529         if (!output_ptr)
 530                 return -EINVAL;
 531
 532         if (amdgpu_sriov_vf(psp->adev))
 533                 return 0;
 534
 535         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 536         if (!cmd)
 537                 return -ENOMEM;
 538
 539         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 540
 541         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 542                                  psp->fence_buf_mc_addr);
 543
 544         if (!ret) {
 545                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 546                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 547         }
 548
 549         kfree(cmd);
 550
 551         return ret;
 552 }
 553
 554 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 555 {
 556         struct psp_context *psp = &adev->psp;
 557         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 558         int ret;
 559
 560         if (amdgpu_sriov_vf(adev))
 561                 return 0;
 562
 563         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 564
 565         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 566         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 567
 568         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 569         if (!ret) {
 570                 *boot_cfg =
 571                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 572         }
 573
 574         return ret;
 575 }
 576
 577 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 578 {
 579         struct psp_context *psp = &adev->psp;
 580         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 581
 582         if (amdgpu_sriov_vf(adev))
 583                 return 0;
 584
 585         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 586
 587         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 588         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 589         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 590         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 591
 592         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 593 }
 594
 595 static int psp_rl_load(struct amdgpu_device *adev)
 596 {
 597         struct psp_context *psp = &adev->psp;
 598         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 599
 600         if (psp->rl_bin_size == 0)
 601                 return 0;
 602
 603         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 604         memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size);
 605
 606         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 607
 608         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 609         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 610         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 611         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size;
 612         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 613
 614         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 615 }
 616
 617 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 618                                 uint64_t asd_mc, uint32_t size)
 619 {
 620         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 621         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 622         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 623         cmd->cmd.cmd_load_ta.app_len = size;
 624
 625         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
 626         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
 627         cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
 628 }
 629
 630 static int psp_asd_load(struct psp_context *psp)
 631 {
 632         int ret;
 633         struct psp_gfx_cmd_resp *cmd;
 634
 635         /* If PSP version doesn't match ASD version, asd loading will be failed.
 636          * add workaround to bypass it for sriov now.
 637          * TODO: add version check to make it common
 638          */
 639         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size)
 640                 return 0;
 641
 642         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 643         if (!cmd)
 644                 return -ENOMEM;
 645
 646         psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size);
 647
 648         psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 649                                   psp->asd_ucode_size);
 650
 651         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 652                                  psp->fence_buf_mc_addr);
 653         if (!ret) {
 654                 psp->asd_context.asd_initialized = true;
 655                 psp->asd_context.session_id = cmd->resp.session_id;
 656         }
 657
 658         kfree(cmd);
 659
 660         return ret;
 661 }
 662
 663 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 664                                        uint32_t session_id)
 665 {
 666         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 667         cmd->cmd.cmd_unload_ta.session_id = session_id;
 668 }
 669
 670 static int psp_asd_unload(struct psp_context *psp)
 671 {
 672         int ret;
 673         struct psp_gfx_cmd_resp *cmd;
 674
 675         if (amdgpu_sriov_vf(psp->adev))
 676                 return 0;
 677
 678         if (!psp->asd_context.asd_initialized)
 679                 return 0;
 680
 681         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 682         if (!cmd)
 683                 return -ENOMEM;
 684
 685         psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
 686
 687         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 688                                  psp->fence_buf_mc_addr);
 689         if (!ret)
 690                 psp->asd_context.asd_initialized = false;
 691
 692         kfree(cmd);
 693
 694         return ret;
 695 }
 696
 697 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 698                 uint32_t id, uint32_t value)
 699 {
 700         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 701         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 702         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 703 }
 704
 705 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 706                 uint32_t value)
 707 {
 708         struct psp_gfx_cmd_resp *cmd = NULL;
 709         int ret = 0;
 710
 711         if (reg >= PSP_REG_LAST)
 712                 return -EINVAL;
 713
 714         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 715         if (!cmd)
 716                 return -ENOMEM;
 717
 718         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 719         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 720         if (ret)
 721                 DRM_ERROR("PSP failed to program reg id %d", reg);
 722
 723         kfree(cmd);
 724         return ret;
 725 }
 726
 727 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 728                                      uint64_t ta_bin_mc,
 729                                      uint32_t ta_bin_size,
 730                                      uint64_t ta_shared_mc,
 731                                      uint32_t ta_shared_size)
 732 {
 733         cmd->cmd_id                             = GFX_CMD_ID_LOAD_TA;
 734         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 735         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 736         cmd->cmd.cmd_load_ta.app_len            = ta_bin_size;
 737
 738         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
 739         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
 740         cmd->cmd.cmd_load_ta.cmd_buf_len         = ta_shared_size;
 741 }
 742
 743 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 744 {
 745         int ret;
 746
 747         /*
 748          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 749          * physical) for xgmi ta <-> Driver
 750          */
 751         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 752                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 753                                       &psp->xgmi_context.xgmi_shared_bo,
 754                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 755                                       &psp->xgmi_context.xgmi_shared_buf);
 756
 757         return ret;
 758 }
 759
 760 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 761                                        uint32_t ta_cmd_id,
 762                                        uint32_t session_id)
 763 {
 764         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
 765         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
 766         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 767 }
 768
 769 static int psp_ta_invoke(struct psp_context *psp,
 770                   uint32_t ta_cmd_id,
 771                   uint32_t session_id)
 772 {
 773         int ret;
 774         struct psp_gfx_cmd_resp *cmd;
 775
 776         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 777         if (!cmd)
 778                 return -ENOMEM;
 779
 780         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
 781
 782         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 783                                  psp->fence_buf_mc_addr);
 784
 785         kfree(cmd);
 786
 787         return ret;
 788 }
 789
 790 static int psp_xgmi_load(struct psp_context *psp)
 791 {
 792         int ret;
 793         struct psp_gfx_cmd_resp *cmd;
 794
 795         /*
 796          * TODO: bypass the loading in sriov for now
 797          */
 798
 799         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 800         if (!cmd)
 801                 return -ENOMEM;
 802
 803         psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 804
 805         psp_prep_ta_load_cmd_buf(cmd,
 806                                  psp->fw_pri_mc_addr,
 807                                  psp->ta_xgmi_ucode_size,
 808                                  psp->xgmi_context.xgmi_shared_mc_addr,
 809                                  PSP_XGMI_SHARED_MEM_SIZE);
 810
 811         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 812                                  psp->fence_buf_mc_addr);
 813
 814         if (!ret) {
 815                 psp->xgmi_context.initialized = 1;
 816                 psp->xgmi_context.session_id = cmd->resp.session_id;
 817         }
 818
 819         kfree(cmd);
 820
 821         return ret;
 822 }
 823
 824 static int psp_xgmi_unload(struct psp_context *psp)
 825 {
 826         int ret;
 827         struct psp_gfx_cmd_resp *cmd;
 828         struct amdgpu_device *adev = psp->adev;
 829
 830         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
 831         if (adev->asic_type == CHIP_ARCTURUS ||
 832                 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
 833                 return 0;
 834
 835         /*
 836          * TODO: bypass the unloading in sriov for now
 837          */
 838
 839         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 840         if (!cmd)
 841                 return -ENOMEM;
 842
 843         psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 844
 845         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 846                                  psp->fence_buf_mc_addr);
 847
 848         kfree(cmd);
 849
 850         return ret;
 851 }
 852
 853 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 854 {
 855         return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
 856 }
 857
 858 int psp_xgmi_terminate(struct psp_context *psp)
 859 {
 860         int ret;
 861
 862         if (!psp->xgmi_context.initialized)
 863                 return 0;
 864
 865         ret = psp_xgmi_unload(psp);
 866         if (ret)
 867                 return ret;
 868
 869         psp->xgmi_context.initialized = 0;
 870
 871         /* free xgmi shared memory */
 872         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 873                         &psp->xgmi_context.xgmi_shared_mc_addr,
 874                         &psp->xgmi_context.xgmi_shared_buf);
 875
 876         return 0;
 877 }
 878
 879 int psp_xgmi_initialize(struct psp_context *psp)
 880 {
 881         struct ta_xgmi_shared_memory *xgmi_cmd;
 882         int ret;
 883
 884         if (!psp->adev->psp.ta_fw ||
 885             !psp->adev->psp.ta_xgmi_ucode_size ||
 886             !psp->adev->psp.ta_xgmi_start_addr)
 887                 return -ENOENT;
 888
 889         if (!psp->xgmi_context.initialized) {
 890                 ret = psp_xgmi_init_shared_buf(psp);
 891                 if (ret)
 892                         return ret;
 893         }
 894
 895         /* Load XGMI TA */
 896         ret = psp_xgmi_load(psp);
 897         if (ret)
 898                 return ret;
 899
 900         /* Initialize XGMI session */
 901         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 902         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 903         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 904
 905         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 906
 907         return ret;
 908 }
 909
 910 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 911 {
 912         struct ta_xgmi_shared_memory *xgmi_cmd;
 913         int ret;
 914
 915         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 916         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 917
 918         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 919
 920         /* Invoke xgmi ta to get hive id */
 921         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 922         if (ret)
 923                 return ret;
 924
 925         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 926
 927         return 0;
 928 }
 929
 930 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 931 {
 932         struct ta_xgmi_shared_memory *xgmi_cmd;
 933         int ret;
 934
 935         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 936         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 937
 938         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 939
 940         /* Invoke xgmi ta to get the node id */
 941         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 942         if (ret)
 943                 return ret;
 944
 945         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 946
 947         return 0;
 948 }
 949
 950 int psp_xgmi_get_topology_info(struct psp_context *psp,
 951                                int number_devices,
 952                                struct psp_xgmi_topology_info *topology)
 953 {
 954         struct ta_xgmi_shared_memory *xgmi_cmd;
 955         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 956         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 957         int i;
 958         int ret;
 959
 960         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 961                 return -EINVAL;
 962
 963         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 964         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 965
 966         /* Fill in the shared memory with topology information as input */
 967         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 968         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 969         topology_info_input->num_nodes = number_devices;
 970
 971         for (i = 0; i < topology_info_input->num_nodes; i++) {
 972                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 973                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 974                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 975                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 976         }
 977
 978         /* Invoke xgmi ta to get the topology information */
 979         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 980         if (ret)
 981                 return ret;
 982
 983         /* Read the output topology information from the shared memory */
 984         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 985         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 986         for (i = 0; i < topology->num_nodes; i++) {
 987                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 988                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 989                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 990                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 991         }
 992
 993         return 0;
 994 }
 995
 996 int psp_xgmi_set_topology_info(struct psp_context *psp,
 997                                int number_devices,
 998                                struct psp_xgmi_topology_info *topology)
 999 {
1000         struct ta_xgmi_shared_memory *xgmi_cmd;
1001         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1002         int i;
1003
1004         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1005                 return -EINVAL;
1006
1007         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
1008         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1009
1010         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1011         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1012         topology_info_input->num_nodes = number_devices;
1013
1014         for (i = 0; i < topology_info_input->num_nodes; i++) {
1015                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1016                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1017                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1018                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1019         }
1020
1021         /* Invoke xgmi ta to set topology information */
1022         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1023 }
1024
1025 // ras begin
1026 static int psp_ras_init_shared_buf(struct psp_context *psp)
1027 {
1028         int ret;
1029
1030         /*
1031          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1032          * physical) for ras ta <-> Driver
1033          */
1034         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
1035                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1036                         &psp->ras.ras_shared_bo,
1037                         &psp->ras.ras_shared_mc_addr,
1038                         &psp->ras.ras_shared_buf);
1039
1040         return ret;
1041 }
1042
1043 static int psp_ras_load(struct psp_context *psp)
1044 {
1045         int ret;
1046         struct psp_gfx_cmd_resp *cmd;
1047         struct ta_ras_shared_memory *ras_cmd;
1048
1049         /*
1050          * TODO: bypass the loading in sriov for now
1051          */
1052         if (amdgpu_sriov_vf(psp->adev))
1053                 return 0;
1054
1055         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1056         if (!cmd)
1057                 return -ENOMEM;
1058
1059         psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
1060
1061         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1062
1063         if (psp->adev->gmc.xgmi.connected_to_cpu)
1064                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1065         else
1066                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1067
1068         psp_prep_ta_load_cmd_buf(cmd,
1069                                  psp->fw_pri_mc_addr,
1070                                  psp->ta_ras_ucode_size,
1071                                  psp->ras.ras_shared_mc_addr,
1072                                  PSP_RAS_SHARED_MEM_SIZE);
1073
1074         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1075                         psp->fence_buf_mc_addr);
1076
1077         if (!ret) {
1078                 psp->ras.session_id = cmd->resp.session_id;
1079
1080                 if (!ras_cmd->ras_status)
1081                         psp->ras.ras_initialized = true;
1082                 else
1083                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1084         }
1085
1086         if (ret || ras_cmd->ras_status)
1087                 amdgpu_ras_fini(psp->adev);
1088
1089         kfree(cmd);
1090
1091         return ret;
1092 }
1093
1094 static int psp_ras_unload(struct psp_context *psp)
1095 {
1096         int ret;
1097         struct psp_gfx_cmd_resp *cmd;
1098
1099         /*
1100          * TODO: bypass the unloading in sriov for now
1101          */
1102         if (amdgpu_sriov_vf(psp->adev))
1103                 return 0;
1104
1105         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1106         if (!cmd)
1107                 return -ENOMEM;
1108
1109         psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
1110
1111         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1112                         psp->fence_buf_mc_addr);
1113
1114         kfree(cmd);
1115
1116         return ret;
1117 }
1118
1119 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1120 {
1121         struct ta_ras_shared_memory *ras_cmd;
1122         int ret;
1123
1124         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1125
1126         /*
1127          * TODO: bypass the loading in sriov for now
1128          */
1129         if (amdgpu_sriov_vf(psp->adev))
1130                 return 0;
1131
1132         ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1133
1134         if (amdgpu_ras_intr_triggered())
1135                 return ret;
1136
1137         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1138         {
1139                 DRM_WARN("RAS: Unsupported Interface");
1140                 return -EINVAL;
1141         }
1142
1143         if (!ret) {
1144                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1145                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1146
1147                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1148                 }
1149                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1150                         dev_warn(psp->adev->dev,
1151                                  "RAS internal register access blocked\n");
1152         }
1153
1154         return ret;
1155 }
1156
1157 static int psp_ras_status_to_errno(struct amdgpu_device *adev,
1158                                          enum ta_ras_status ras_status)
1159 {
1160         int ret = -EINVAL;
1161
1162         switch (ras_status) {
1163         case TA_RAS_STATUS__SUCCESS:
1164                 ret = 0;
1165                 break;
1166         case TA_RAS_STATUS__RESET_NEEDED:
1167                 ret = -EAGAIN;
1168                 break;
1169         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
1170                 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");
1171                 break;
1172         case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:
1173                 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");
1174                 break;
1175         default:
1176                 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);
1177         }
1178
1179         return ret;
1180 }
1181
1182 int psp_ras_enable_features(struct psp_context *psp,
1183                 union ta_ras_cmd_input *info, bool enable)
1184 {
1185         struct ta_ras_shared_memory *ras_cmd;
1186         int ret;
1187
1188         if (!psp->ras.ras_initialized)
1189                 return -EINVAL;
1190
1191         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1192         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1193
1194         if (enable)
1195                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1196         else
1197                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1198
1199         ras_cmd->ras_in_message = *info;
1200
1201         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1202         if (ret)
1203                 return -EINVAL;
1204
1205         return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1206 }
1207
1208 static int psp_ras_terminate(struct psp_context *psp)
1209 {
1210         int ret;
1211
1212         /*
1213          * TODO: bypass the terminate in sriov for now
1214          */
1215         if (amdgpu_sriov_vf(psp->adev))
1216                 return 0;
1217
1218         if (!psp->ras.ras_initialized)
1219                 return 0;
1220
1221         ret = psp_ras_unload(psp);
1222         if (ret)
1223                 return ret;
1224
1225         psp->ras.ras_initialized = false;
1226
1227         /* free ras shared memory */
1228         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1229                         &psp->ras.ras_shared_mc_addr,
1230                         &psp->ras.ras_shared_buf);
1231
1232         return 0;
1233 }
1234
1235 static int psp_ras_initialize(struct psp_context *psp)
1236 {
1237         int ret;
1238         uint32_t boot_cfg = 0xFF;
1239         struct amdgpu_device *adev = psp->adev;
1240
1241         /*
1242          * TODO: bypass the initialize in sriov for now
1243          */
1244         if (amdgpu_sriov_vf(adev))
1245                 return 0;
1246
1247         if (!adev->psp.ta_ras_ucode_size ||
1248             !adev->psp.ta_ras_start_addr) {
1249                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1250                 return 0;
1251         }
1252
1253         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1254                 /* query GECC enablement status from boot config
1255                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1256                  */
1257                 ret = psp_boot_config_get(adev, &boot_cfg);
1258                 if (ret)
1259                         dev_warn(adev->dev, "PSP get boot config failed\n");
1260
1261                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1262                         if (!boot_cfg) {
1263                                 dev_info(adev->dev, "GECC is disabled\n");
1264                         } else {
1265                                 /* disable GECC in next boot cycle if ras is
1266                                  * disabled by module parameter amdgpu_ras_enable
1267                                  * and/or amdgpu_ras_mask, or boot_config_get call
1268                                  * is failed
1269                                  */
1270                                 ret = psp_boot_config_set(adev, 0);
1271                                 if (ret)
1272                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1273                                 else
1274                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1275                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1276                         }
1277                 } else {
1278                         if (1 == boot_cfg) {
1279                                 dev_info(adev->dev, "GECC is enabled\n");
1280                         } else {
1281                                 /* enable GECC in next boot cycle if it is disabled
1282                                  * in boot config, or force enable GECC if failed to
1283                                  * get boot configuration
1284                                  */
1285                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1286                                 if (ret)
1287                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1288                                 else
1289                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1290                         }
1291                 }
1292         }
1293
1294         if (!psp->ras.ras_initialized) {
1295                 ret = psp_ras_init_shared_buf(psp);
1296                 if (ret)
1297                         return ret;
1298         }
1299
1300         ret = psp_ras_load(psp);
1301         if (ret)
1302                 return ret;
1303
1304         return 0;
1305 }
1306
1307 int psp_ras_trigger_error(struct psp_context *psp,
1308                           struct ta_ras_trigger_error_input *info)
1309 {
1310         struct ta_ras_shared_memory *ras_cmd;
1311         int ret;
1312
1313         if (!psp->ras.ras_initialized)
1314                 return -EINVAL;
1315
1316         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1317         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1318
1319         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1320         ras_cmd->ras_in_message.trigger_error = *info;
1321
1322         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1323         if (ret)
1324                 return -EINVAL;
1325
1326         /* If err_event_athub occurs error inject was successful, however
1327            return status from TA is no long reliable */
1328         if (amdgpu_ras_intr_triggered())
1329                 return 0;
1330
1331         return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1332 }
1333 // ras end
1334
1335 // HDCP start
1336 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1337 {
1338         int ret;
1339
1340         /*
1341          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1342          * physical) for hdcp ta <-> Driver
1343          */
1344         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1345                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1346                                       &psp->hdcp_context.hdcp_shared_bo,
1347                                       &psp->hdcp_context.hdcp_shared_mc_addr,
1348                                       &psp->hdcp_context.hdcp_shared_buf);
1349
1350         return ret;
1351 }
1352
1353 static int psp_hdcp_load(struct psp_context *psp)
1354 {
1355         int ret;
1356         struct psp_gfx_cmd_resp *cmd;
1357
1358         /*
1359          * TODO: bypass the loading in sriov for now
1360          */
1361         if (amdgpu_sriov_vf(psp->adev))
1362                 return 0;
1363
1364         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1365         if (!cmd)
1366                 return -ENOMEM;
1367
1368         psp_copy_fw(psp, psp->ta_hdcp_start_addr,
1369                     psp->ta_hdcp_ucode_size);
1370
1371         psp_prep_ta_load_cmd_buf(cmd,
1372                                  psp->fw_pri_mc_addr,
1373                                  psp->ta_hdcp_ucode_size,
1374                                  psp->hdcp_context.hdcp_shared_mc_addr,
1375                                  PSP_HDCP_SHARED_MEM_SIZE);
1376
1377         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1378
1379         if (!ret) {
1380                 psp->hdcp_context.hdcp_initialized = true;
1381                 psp->hdcp_context.session_id = cmd->resp.session_id;
1382                 mutex_init(&psp->hdcp_context.mutex);
1383         }
1384
1385         kfree(cmd);
1386
1387         return ret;
1388 }
1389 static int psp_hdcp_initialize(struct psp_context *psp)
1390 {
1391         int ret;
1392
1393         /*
1394          * TODO: bypass the initialize in sriov for now
1395          */
1396         if (amdgpu_sriov_vf(psp->adev))
1397                 return 0;
1398
1399         if (!psp->adev->psp.ta_hdcp_ucode_size ||
1400             !psp->adev->psp.ta_hdcp_start_addr) {
1401                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1402                 return 0;
1403         }
1404
1405         if (!psp->hdcp_context.hdcp_initialized) {
1406                 ret = psp_hdcp_init_shared_buf(psp);
1407                 if (ret)
1408                         return ret;
1409         }
1410
1411         ret = psp_hdcp_load(psp);
1412         if (ret)
1413                 return ret;
1414
1415         return 0;
1416 }
1417
1418 static int psp_hdcp_unload(struct psp_context *psp)
1419 {
1420         int ret;
1421         struct psp_gfx_cmd_resp *cmd;
1422
1423         /*
1424          * TODO: bypass the unloading in sriov for now
1425          */
1426         if (amdgpu_sriov_vf(psp->adev))
1427                 return 0;
1428
1429         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1430         if (!cmd)
1431                 return -ENOMEM;
1432
1433         psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1434
1435         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1436
1437         kfree(cmd);
1438
1439         return ret;
1440 }
1441
1442 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1443 {
1444         /*
1445          * TODO: bypass the loading in sriov for now
1446          */
1447         if (amdgpu_sriov_vf(psp->adev))
1448                 return 0;
1449
1450         return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1451 }
1452
1453 static int psp_hdcp_terminate(struct psp_context *psp)
1454 {
1455         int ret;
1456
1457         /*
1458          * TODO: bypass the terminate in sriov for now
1459          */
1460         if (amdgpu_sriov_vf(psp->adev))
1461                 return 0;
1462
1463         if (!psp->hdcp_context.hdcp_initialized) {
1464                 if (psp->hdcp_context.hdcp_shared_buf)
1465                         goto out;
1466                 else
1467                         return 0;
1468         }
1469
1470         ret = psp_hdcp_unload(psp);
1471         if (ret)
1472                 return ret;
1473
1474         psp->hdcp_context.hdcp_initialized = false;
1475
1476 out:
1477         /* free hdcp shared memory */
1478         amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1479                               &psp->hdcp_context.hdcp_shared_mc_addr,
1480                               &psp->hdcp_context.hdcp_shared_buf);
1481
1482         return 0;
1483 }
1484 // HDCP end
1485
1486 // DTM start
1487 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1488 {
1489         int ret;
1490
1491         /*
1492          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1493          * physical) for dtm ta <-> Driver
1494          */
1495         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1496                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1497                                       &psp->dtm_context.dtm_shared_bo,
1498                                       &psp->dtm_context.dtm_shared_mc_addr,
1499                                       &psp->dtm_context.dtm_shared_buf);
1500
1501         return ret;
1502 }
1503
1504 static int psp_dtm_load(struct psp_context *psp)
1505 {
1506         int ret;
1507         struct psp_gfx_cmd_resp *cmd;
1508
1509         /*
1510          * TODO: bypass the loading in sriov for now
1511          */
1512         if (amdgpu_sriov_vf(psp->adev))
1513                 return 0;
1514
1515         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1516         if (!cmd)
1517                 return -ENOMEM;
1518
1519         psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1520
1521         psp_prep_ta_load_cmd_buf(cmd,
1522                                  psp->fw_pri_mc_addr,
1523                                  psp->ta_dtm_ucode_size,
1524                                  psp->dtm_context.dtm_shared_mc_addr,
1525                                  PSP_DTM_SHARED_MEM_SIZE);
1526
1527         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1528
1529         if (!ret) {
1530                 psp->dtm_context.dtm_initialized = true;
1531                 psp->dtm_context.session_id = cmd->resp.session_id;
1532                 mutex_init(&psp->dtm_context.mutex);
1533         }
1534
1535         kfree(cmd);
1536
1537         return ret;
1538 }
1539
1540 static int psp_dtm_initialize(struct psp_context *psp)
1541 {
1542         int ret;
1543
1544         /*
1545          * TODO: bypass the initialize in sriov for now
1546          */
1547         if (amdgpu_sriov_vf(psp->adev))
1548                 return 0;
1549
1550         if (!psp->adev->psp.ta_dtm_ucode_size ||
1551             !psp->adev->psp.ta_dtm_start_addr) {
1552                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1553                 return 0;
1554         }
1555
1556         if (!psp->dtm_context.dtm_initialized) {
1557                 ret = psp_dtm_init_shared_buf(psp);
1558                 if (ret)
1559                         return ret;
1560         }
1561
1562         ret = psp_dtm_load(psp);
1563         if (ret)
1564                 return ret;
1565
1566         return 0;
1567 }
1568
1569 static int psp_dtm_unload(struct psp_context *psp)
1570 {
1571         int ret;
1572         struct psp_gfx_cmd_resp *cmd;
1573
1574         /*
1575          * TODO: bypass the unloading in sriov for now
1576          */
1577         if (amdgpu_sriov_vf(psp->adev))
1578                 return 0;
1579
1580         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1581         if (!cmd)
1582                 return -ENOMEM;
1583
1584         psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1585
1586         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1587
1588         kfree(cmd);
1589
1590         return ret;
1591 }
1592
1593 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1594 {
1595         /*
1596          * TODO: bypass the loading in sriov for now
1597          */
1598         if (amdgpu_sriov_vf(psp->adev))
1599                 return 0;
1600
1601         return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1602 }
1603
1604 static int psp_dtm_terminate(struct psp_context *psp)
1605 {
1606         int ret;
1607
1608         /*
1609          * TODO: bypass the terminate in sriov for now
1610          */
1611         if (amdgpu_sriov_vf(psp->adev))
1612                 return 0;
1613
1614         if (!psp->dtm_context.dtm_initialized) {
1615                 if (psp->dtm_context.dtm_shared_buf)
1616                         goto out;
1617                 else
1618                         return 0;
1619         }
1620
1621         ret = psp_dtm_unload(psp);
1622         if (ret)
1623                 return ret;
1624
1625         psp->dtm_context.dtm_initialized = false;
1626
1627 out:
1628         /* free hdcp shared memory */
1629         amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1630                               &psp->dtm_context.dtm_shared_mc_addr,
1631                               &psp->dtm_context.dtm_shared_buf);
1632
1633         return 0;
1634 }
1635 // DTM end
1636
1637 // RAP start
1638 static int psp_rap_init_shared_buf(struct psp_context *psp)
1639 {
1640         int ret;
1641
1642         /*
1643          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1644          * physical) for rap ta <-> Driver
1645          */
1646         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1647                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1648                                       &psp->rap_context.rap_shared_bo,
1649                                       &psp->rap_context.rap_shared_mc_addr,
1650                                       &psp->rap_context.rap_shared_buf);
1651
1652         return ret;
1653 }
1654
1655 static int psp_rap_load(struct psp_context *psp)
1656 {
1657         int ret;
1658         struct psp_gfx_cmd_resp *cmd;
1659
1660         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1661         if (!cmd)
1662                 return -ENOMEM;
1663
1664         psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1665
1666         psp_prep_ta_load_cmd_buf(cmd,
1667                                  psp->fw_pri_mc_addr,
1668                                  psp->ta_rap_ucode_size,
1669                                  psp->rap_context.rap_shared_mc_addr,
1670                                  PSP_RAP_SHARED_MEM_SIZE);
1671
1672         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1673
1674         if (!ret) {
1675                 psp->rap_context.rap_initialized = true;
1676                 psp->rap_context.session_id = cmd->resp.session_id;
1677                 mutex_init(&psp->rap_context.mutex);
1678         }
1679
1680         kfree(cmd);
1681
1682         return ret;
1683 }
1684
1685 static int psp_rap_unload(struct psp_context *psp)
1686 {
1687         int ret;
1688         struct psp_gfx_cmd_resp *cmd;
1689
1690         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1691         if (!cmd)
1692                 return -ENOMEM;
1693
1694         psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1695
1696         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1697
1698         kfree(cmd);
1699
1700         return ret;
1701 }
1702
1703 static int psp_rap_initialize(struct psp_context *psp)
1704 {
1705         int ret;
1706         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1707
1708         /*
1709          * TODO: bypass the initialize in sriov for now
1710          */
1711         if (amdgpu_sriov_vf(psp->adev))
1712                 return 0;
1713
1714         if (!psp->adev->psp.ta_rap_ucode_size ||
1715             !psp->adev->psp.ta_rap_start_addr) {
1716                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1717                 return 0;
1718         }
1719
1720         if (!psp->rap_context.rap_initialized) {
1721                 ret = psp_rap_init_shared_buf(psp);
1722                 if (ret)
1723                         return ret;
1724         }
1725
1726         ret = psp_rap_load(psp);
1727         if (ret)
1728                 return ret;
1729
1730         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1731         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1732                 psp_rap_unload(psp);
1733
1734                 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1735                               &psp->rap_context.rap_shared_mc_addr,
1736                               &psp->rap_context.rap_shared_buf);
1737
1738                 psp->rap_context.rap_initialized = false;
1739
1740                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1741                          ret, status);
1742
1743                 return ret;
1744         }
1745
1746         return 0;
1747 }
1748
1749 static int psp_rap_terminate(struct psp_context *psp)
1750 {
1751         int ret;
1752
1753         if (!psp->rap_context.rap_initialized)
1754                 return 0;
1755
1756         ret = psp_rap_unload(psp);
1757
1758         psp->rap_context.rap_initialized = false;
1759
1760         /* free rap shared memory */
1761         amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1762                               &psp->rap_context.rap_shared_mc_addr,
1763                               &psp->rap_context.rap_shared_buf);
1764
1765         return ret;
1766 }
1767
1768 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1769 {
1770         struct ta_rap_shared_memory *rap_cmd;
1771         int ret = 0;
1772
1773         if (!psp->rap_context.rap_initialized)
1774                 return 0;
1775
1776         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1777             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1778                 return -EINVAL;
1779
1780         mutex_lock(&psp->rap_context.mutex);
1781
1782         rap_cmd = (struct ta_rap_shared_memory *)
1783                   psp->rap_context.rap_shared_buf;
1784         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1785
1786         rap_cmd->cmd_id = ta_cmd_id;
1787         rap_cmd->validation_method_id = METHOD_A;
1788
1789         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1790         if (ret)
1791                 goto out_unlock;
1792
1793         if (status)
1794                 *status = rap_cmd->rap_status;
1795
1796 out_unlock:
1797         mutex_unlock(&psp->rap_context.mutex);
1798
1799         return ret;
1800 }
1801 // RAP end
1802
1803 /* securedisplay start */
1804 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1805 {
1806         int ret;
1807
1808         /*
1809          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1810          * physical) for sa ta <-> Driver
1811          */
1812         ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE,
1813                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1814                                       &psp->securedisplay_context.securedisplay_shared_bo,
1815                                       &psp->securedisplay_context.securedisplay_shared_mc_addr,
1816                                       &psp->securedisplay_context.securedisplay_shared_buf);
1817
1818         return ret;
1819 }
1820
1821 static int psp_securedisplay_load(struct psp_context *psp)
1822 {
1823         int ret;
1824         struct psp_gfx_cmd_resp *cmd;
1825
1826         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1827         if (!cmd)
1828                 return -ENOMEM;
1829
1830         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1831         memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size);
1832
1833         psp_prep_ta_load_cmd_buf(cmd,
1834                                  psp->fw_pri_mc_addr,
1835                                  psp->ta_securedisplay_ucode_size,
1836                                  psp->securedisplay_context.securedisplay_shared_mc_addr,
1837                                  PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
1838
1839         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1840
1841         if (ret)
1842                 goto failed;
1843
1844         psp->securedisplay_context.securedisplay_initialized = true;
1845         psp->securedisplay_context.session_id = cmd->resp.session_id;
1846         mutex_init(&psp->securedisplay_context.mutex);
1847
1848 failed:
1849         kfree(cmd);
1850         return ret;
1851 }
1852
1853 static int psp_securedisplay_unload(struct psp_context *psp)
1854 {
1855         int ret;
1856         struct psp_gfx_cmd_resp *cmd;
1857
1858         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1859         if (!cmd)
1860                 return -ENOMEM;
1861
1862         psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id);
1863
1864         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1865
1866         kfree(cmd);
1867
1868         return ret;
1869 }
1870
1871 static int psp_securedisplay_initialize(struct psp_context *psp)
1872 {
1873         int ret;
1874         struct securedisplay_cmd *securedisplay_cmd;
1875
1876         /*
1877          * TODO: bypass the initialize in sriov for now
1878          */
1879         if (amdgpu_sriov_vf(psp->adev))
1880                 return 0;
1881
1882         if (!psp->adev->psp.ta_securedisplay_ucode_size ||
1883             !psp->adev->psp.ta_securedisplay_start_addr) {
1884                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1885                 return 0;
1886         }
1887
1888         if (!psp->securedisplay_context.securedisplay_initialized) {
1889                 ret = psp_securedisplay_init_shared_buf(psp);
1890                 if (ret)
1891                         return ret;
1892         }
1893
1894         ret = psp_securedisplay_load(psp);
1895         if (ret)
1896                 return ret;
1897
1898         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1899                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1900
1901         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1902         if (ret) {
1903                 psp_securedisplay_unload(psp);
1904
1905                 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1906                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1907                               &psp->securedisplay_context.securedisplay_shared_buf);
1908
1909                 psp->securedisplay_context.securedisplay_initialized = false;
1910
1911                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1912                 return -EINVAL;
1913         }
1914
1915         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1916                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1917                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1918                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1919         }
1920
1921         return 0;
1922 }
1923
1924 static int psp_securedisplay_terminate(struct psp_context *psp)
1925 {
1926         int ret;
1927
1928         /*
1929          * TODO:bypass the terminate in sriov for now
1930          */
1931         if (amdgpu_sriov_vf(psp->adev))
1932                 return 0;
1933
1934         if (!psp->securedisplay_context.securedisplay_initialized)
1935                 return 0;
1936
1937         ret = psp_securedisplay_unload(psp);
1938         if (ret)
1939                 return ret;
1940
1941         psp->securedisplay_context.securedisplay_initialized = false;
1942
1943         /* free securedisplay shared memory */
1944         amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1945                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1946                               &psp->securedisplay_context.securedisplay_shared_buf);
1947
1948         return ret;
1949 }
1950
1951 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1952 {
1953         int ret;
1954
1955         if (!psp->securedisplay_context.securedisplay_initialized)
1956                 return -EINVAL;
1957
1958         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1959             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1960                 return -EINVAL;
1961
1962         mutex_lock(&psp->securedisplay_context.mutex);
1963
1964         ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id);
1965
1966         mutex_unlock(&psp->securedisplay_context.mutex);
1967
1968         return ret;
1969 }
1970 /* SECUREDISPLAY end */
1971
1972 static int psp_hw_start(struct psp_context *psp)
1973 {
1974         struct amdgpu_device *adev = psp->adev;
1975         int ret;
1976
1977         if (!amdgpu_sriov_vf(adev)) {
1978                 if (psp->kdb_bin_size &&
1979                     (psp->funcs->bootloader_load_kdb != NULL)) {
1980                         ret = psp_bootloader_load_kdb(psp);
1981                         if (ret) {
1982                                 DRM_ERROR("PSP load kdb failed!\n");
1983                                 return ret;
1984                         }
1985                 }
1986
1987                 if (psp->spl_bin_size) {
1988                         ret = psp_bootloader_load_spl(psp);
1989                         if (ret) {
1990                                 DRM_ERROR("PSP load spl failed!\n");
1991                                 return ret;
1992                         }
1993                 }
1994
1995                 ret = psp_bootloader_load_sysdrv(psp);
1996                 if (ret) {
1997                         DRM_ERROR("PSP load sysdrv failed!\n");
1998                         return ret;
1999                 }
2000
2001                 ret = psp_bootloader_load_sos(psp);
2002                 if (ret) {
2003                         DRM_ERROR("PSP load sos failed!\n");
2004                         return ret;
2005                 }
2006         }
2007
2008         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2009         if (ret) {
2010                 DRM_ERROR("PSP create ring failed!\n");
2011                 return ret;
2012         }
2013
2014         ret = psp_tmr_init(psp);
2015         if (ret) {
2016                 DRM_ERROR("PSP tmr init failed!\n");
2017                 return ret;
2018         }
2019
2020         /*
2021          * For ASICs with DF Cstate management centralized
2022          * to PMFW, TMR setup should be performed after PMFW
2023          * loaded and before other non-psp firmware loaded.
2024          */
2025         if (psp->pmfw_centralized_cstate_management) {
2026                 ret = psp_load_smu_fw(psp);
2027                 if (ret)
2028                         return ret;
2029         }
2030
2031         ret = psp_tmr_load(psp);
2032         if (ret) {
2033                 DRM_ERROR("PSP load tmr failed!\n");
2034                 return ret;
2035         }
2036
2037         return 0;
2038 }
2039
2040 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2041                            enum psp_gfx_fw_type *type)
2042 {
2043         switch (ucode->ucode_id) {
2044         case AMDGPU_UCODE_ID_SDMA0:
2045                 *type = GFX_FW_TYPE_SDMA0;
2046                 break;
2047         case AMDGPU_UCODE_ID_SDMA1:
2048                 *type = GFX_FW_TYPE_SDMA1;
2049                 break;
2050         case AMDGPU_UCODE_ID_SDMA2:
2051                 *type = GFX_FW_TYPE_SDMA2;
2052                 break;
2053         case AMDGPU_UCODE_ID_SDMA3:
2054                 *type = GFX_FW_TYPE_SDMA3;
2055                 break;
2056         case AMDGPU_UCODE_ID_SDMA4:
2057                 *type = GFX_FW_TYPE_SDMA4;
2058                 break;
2059         case AMDGPU_UCODE_ID_SDMA5:
2060                 *type = GFX_FW_TYPE_SDMA5;
2061                 break;
2062         case AMDGPU_UCODE_ID_SDMA6:
2063                 *type = GFX_FW_TYPE_SDMA6;
2064                 break;
2065         case AMDGPU_UCODE_ID_SDMA7:
2066                 *type = GFX_FW_TYPE_SDMA7;
2067                 break;
2068         case AMDGPU_UCODE_ID_CP_MES:
2069                 *type = GFX_FW_TYPE_CP_MES;
2070                 break;
2071         case AMDGPU_UCODE_ID_CP_MES_DATA:
2072                 *type = GFX_FW_TYPE_MES_STACK;
2073                 break;
2074         case AMDGPU_UCODE_ID_CP_CE:
2075                 *type = GFX_FW_TYPE_CP_CE;
2076                 break;
2077         case AMDGPU_UCODE_ID_CP_PFP:
2078                 *type = GFX_FW_TYPE_CP_PFP;
2079                 break;
2080         case AMDGPU_UCODE_ID_CP_ME:
2081                 *type = GFX_FW_TYPE_CP_ME;
2082                 break;
2083         case AMDGPU_UCODE_ID_CP_MEC1:
2084                 *type = GFX_FW_TYPE_CP_MEC;
2085                 break;
2086         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2087                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2088                 break;
2089         case AMDGPU_UCODE_ID_CP_MEC2:
2090                 *type = GFX_FW_TYPE_CP_MEC;
2091                 break;
2092         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2093                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2094                 break;
2095         case AMDGPU_UCODE_ID_RLC_G:
2096                 *type = GFX_FW_TYPE_RLC_G;
2097                 break;
2098         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2099                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2100                 break;
2101         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2102                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2103                 break;
2104         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2105                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2106                 break;
2107         case AMDGPU_UCODE_ID_RLC_IRAM:
2108                 *type = GFX_FW_TYPE_RLC_IRAM;
2109                 break;
2110         case AMDGPU_UCODE_ID_RLC_DRAM:
2111                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2112                 break;
2113         case AMDGPU_UCODE_ID_SMC:
2114                 *type = GFX_FW_TYPE_SMU;
2115                 break;
2116         case AMDGPU_UCODE_ID_UVD:
2117                 *type = GFX_FW_TYPE_UVD;
2118                 break;
2119         case AMDGPU_UCODE_ID_UVD1:
2120                 *type = GFX_FW_TYPE_UVD1;
2121                 break;
2122         case AMDGPU_UCODE_ID_VCE:
2123                 *type = GFX_FW_TYPE_VCE;
2124                 break;
2125         case AMDGPU_UCODE_ID_VCN:
2126                 *type = GFX_FW_TYPE_VCN;
2127                 break;
2128         case AMDGPU_UCODE_ID_VCN1:
2129                 *type = GFX_FW_TYPE_VCN1;
2130                 break;
2131         case AMDGPU_UCODE_ID_DMCU_ERAM:
2132                 *type = GFX_FW_TYPE_DMCU_ERAM;
2133                 break;
2134         case AMDGPU_UCODE_ID_DMCU_INTV:
2135                 *type = GFX_FW_TYPE_DMCU_ISR;
2136                 break;
2137         case AMDGPU_UCODE_ID_VCN0_RAM:
2138                 *type = GFX_FW_TYPE_VCN0_RAM;
2139                 break;
2140         case AMDGPU_UCODE_ID_VCN1_RAM:
2141                 *type = GFX_FW_TYPE_VCN1_RAM;
2142                 break;
2143         case AMDGPU_UCODE_ID_DMCUB:
2144                 *type = GFX_FW_TYPE_DMUB;
2145                 break;
2146         case AMDGPU_UCODE_ID_MAXIMUM:
2147         default:
2148                 return -EINVAL;
2149         }
2150
2151         return 0;
2152 }
2153
2154 static void psp_print_fw_hdr(struct psp_context *psp,
2155                              struct amdgpu_firmware_info *ucode)
2156 {
2157         struct amdgpu_device *adev = psp->adev;
2158         struct common_firmware_header *hdr;
2159
2160         switch (ucode->ucode_id) {
2161         case AMDGPU_UCODE_ID_SDMA0:
2162         case AMDGPU_UCODE_ID_SDMA1:
2163         case AMDGPU_UCODE_ID_SDMA2:
2164         case AMDGPU_UCODE_ID_SDMA3:
2165         case AMDGPU_UCODE_ID_SDMA4:
2166         case AMDGPU_UCODE_ID_SDMA5:
2167         case AMDGPU_UCODE_ID_SDMA6:
2168         case AMDGPU_UCODE_ID_SDMA7:
2169                 hdr = (struct common_firmware_header *)
2170                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2171                 amdgpu_ucode_print_sdma_hdr(hdr);
2172                 break;
2173         case AMDGPU_UCODE_ID_CP_CE:
2174                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2175                 amdgpu_ucode_print_gfx_hdr(hdr);
2176                 break;
2177         case AMDGPU_UCODE_ID_CP_PFP:
2178                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2179                 amdgpu_ucode_print_gfx_hdr(hdr);
2180                 break;
2181         case AMDGPU_UCODE_ID_CP_ME:
2182                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2183                 amdgpu_ucode_print_gfx_hdr(hdr);
2184                 break;
2185         case AMDGPU_UCODE_ID_CP_MEC1:
2186                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2187                 amdgpu_ucode_print_gfx_hdr(hdr);
2188                 break;
2189         case AMDGPU_UCODE_ID_RLC_G:
2190                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2191                 amdgpu_ucode_print_rlc_hdr(hdr);
2192                 break;
2193         case AMDGPU_UCODE_ID_SMC:
2194                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2195                 amdgpu_ucode_print_smc_hdr(hdr);
2196                 break;
2197         default:
2198                 break;
2199         }
2200 }
2201
2202 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2203                                        struct psp_gfx_cmd_resp *cmd)
2204 {
2205         int ret;
2206         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2207
2208         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
2209
2210         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2211         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2212         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2213         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2214
2215         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2216         if (ret)
2217                 DRM_ERROR("Unknown firmware type\n");
2218
2219         return ret;
2220 }
2221
2222 static int psp_execute_np_fw_load(struct psp_context *psp,
2223                                   struct amdgpu_firmware_info *ucode)
2224 {
2225         int ret = 0;
2226
2227         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
2228         if (ret)
2229                 return ret;
2230
2231         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
2232                                  psp->fence_buf_mc_addr);
2233
2234         return ret;
2235 }
2236
2237 static int psp_load_smu_fw(struct psp_context *psp)
2238 {
2239         int ret;
2240         struct amdgpu_device *adev = psp->adev;
2241         struct amdgpu_firmware_info *ucode =
2242                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2243         struct amdgpu_ras *ras = psp->ras.ras;
2244
2245         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2246                 return 0;
2247
2248         if ((amdgpu_in_reset(adev) &&
2249              ras && adev->ras_enabled &&
2250              (adev->asic_type == CHIP_ARCTURUS ||
2251               adev->asic_type == CHIP_VEGA20))) {
2252                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2253                 if (ret) {
2254                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2255                 }
2256         }
2257
2258         ret = psp_execute_np_fw_load(psp, ucode);
2259
2260         if (ret)
2261                 DRM_ERROR("PSP load smu failed!\n");
2262
2263         return ret;
2264 }
2265
2266 static bool fw_load_skip_check(struct psp_context *psp,
2267                                struct amdgpu_firmware_info *ucode)
2268 {
2269         if (!ucode->fw)
2270                 return true;
2271
2272         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2273             (psp_smu_reload_quirk(psp) ||
2274              psp->autoload_supported ||
2275              psp->pmfw_centralized_cstate_management))
2276                 return true;
2277
2278         if (amdgpu_sriov_vf(psp->adev) &&
2279            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2280             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2281             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2282             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2283             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2284             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2285             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2286             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2287             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2288             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2289             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2290             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2291             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2292                 /*skip ucode loading in SRIOV VF */
2293                 return true;
2294
2295         if (psp->autoload_supported &&
2296             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2297              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2298                 /* skip mec JT when autoload is enabled */
2299                 return true;
2300
2301         return false;
2302 }
2303
2304 int psp_load_fw_list(struct psp_context *psp,
2305                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2306 {
2307         int ret = 0, i;
2308         struct amdgpu_firmware_info *ucode;
2309
2310         for (i = 0; i < ucode_count; ++i) {
2311                 ucode = ucode_list[i];
2312                 psp_print_fw_hdr(psp, ucode);
2313                 ret = psp_execute_np_fw_load(psp, ucode);
2314                 if (ret)
2315                         return ret;
2316         }
2317         return ret;
2318 }
2319
2320 static int psp_np_fw_load(struct psp_context *psp)
2321 {
2322         int i, ret;
2323         struct amdgpu_firmware_info *ucode;
2324         struct amdgpu_device *adev = psp->adev;
2325
2326         if (psp->autoload_supported &&
2327             !psp->pmfw_centralized_cstate_management) {
2328                 ret = psp_load_smu_fw(psp);
2329                 if (ret)
2330                         return ret;
2331         }
2332
2333         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2334                 ucode = &adev->firmware.ucode[i];
2335
2336                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2337                     !fw_load_skip_check(psp, ucode)) {
2338                         ret = psp_load_smu_fw(psp);
2339                         if (ret)
2340                                 return ret;
2341                         continue;
2342                 }
2343
2344                 if (fw_load_skip_check(psp, ucode))
2345                         continue;
2346
2347                 if (psp->autoload_supported &&
2348                     (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2349                      adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2350                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2351                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2352                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2353                         /* PSP only receive one SDMA fw for sienna_cichlid,
2354                          * as all four sdma fw are same */
2355                         continue;
2356
2357                 psp_print_fw_hdr(psp, ucode);
2358
2359                 ret = psp_execute_np_fw_load(psp, ucode);
2360                 if (ret)
2361                         return ret;
2362
2363                 /* Start rlc autoload after psp recieved all the gfx firmware */
2364                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2365                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2366                         ret = psp_rlc_autoload_start(psp);
2367                         if (ret) {
2368                                 DRM_ERROR("Failed to start rlc autoload\n");
2369                                 return ret;
2370                         }
2371                 }
2372         }
2373
2374         return 0;
2375 }
2376
2377 static int psp_load_fw(struct amdgpu_device *adev)
2378 {
2379         int ret;
2380         struct psp_context *psp = &adev->psp;
2381
2382         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2383                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2384                 goto skip_memalloc;
2385         }
2386
2387         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2388         if (!psp->cmd)
2389                 return -ENOMEM;
2390
2391         if (amdgpu_sriov_vf(adev)) {
2392                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2393                                                 AMDGPU_GEM_DOMAIN_VRAM,
2394                                                 &psp->fw_pri_bo,
2395                                                 &psp->fw_pri_mc_addr,
2396                                                 &psp->fw_pri_buf);
2397         } else {
2398                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2399                                                 AMDGPU_GEM_DOMAIN_GTT,
2400                                                 &psp->fw_pri_bo,
2401                                                 &psp->fw_pri_mc_addr,
2402                                                 &psp->fw_pri_buf);
2403         }
2404
2405         if (ret)
2406                 goto failed;
2407
2408         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2409                                         AMDGPU_GEM_DOMAIN_VRAM,
2410                                         &psp->fence_buf_bo,
2411                                         &psp->fence_buf_mc_addr,
2412                                         &psp->fence_buf);
2413         if (ret)
2414                 goto failed;
2415
2416         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2417                                       AMDGPU_GEM_DOMAIN_VRAM,
2418                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2419                                       (void **)&psp->cmd_buf_mem);
2420         if (ret)
2421                 goto failed;
2422
2423         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2424
2425         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2426         if (ret) {
2427                 DRM_ERROR("PSP ring init failed!\n");
2428                 goto failed;
2429         }
2430
2431 skip_memalloc:
2432         ret = psp_hw_start(psp);
2433         if (ret)
2434                 goto failed;
2435
2436         ret = psp_np_fw_load(psp);
2437         if (ret)
2438                 goto failed;
2439
2440         ret = psp_asd_load(psp);
2441         if (ret) {
2442                 DRM_ERROR("PSP load asd failed!\n");
2443                 return ret;
2444         }
2445
2446         ret = psp_rl_load(adev);
2447         if (ret) {
2448                 DRM_ERROR("PSP load RL failed!\n");
2449                 return ret;
2450         }
2451
2452         if (psp->adev->psp.ta_fw) {
2453                 ret = psp_ras_initialize(psp);
2454                 if (ret)
2455                         dev_err(psp->adev->dev,
2456                                         "RAS: Failed to initialize RAS\n");
2457
2458                 ret = psp_hdcp_initialize(psp);
2459                 if (ret)
2460                         dev_err(psp->adev->dev,
2461                                 "HDCP: Failed to initialize HDCP\n");
2462
2463                 ret = psp_dtm_initialize(psp);
2464                 if (ret)
2465                         dev_err(psp->adev->dev,
2466                                 "DTM: Failed to initialize DTM\n");
2467
2468                 ret = psp_rap_initialize(psp);
2469                 if (ret)
2470                         dev_err(psp->adev->dev,
2471                                 "RAP: Failed to initialize RAP\n");
2472
2473                 ret = psp_securedisplay_initialize(psp);
2474                 if (ret)
2475                         dev_err(psp->adev->dev,
2476                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2477         }
2478
2479         return 0;
2480
2481 failed:
2482         /*
2483          * all cleanup jobs (xgmi terminate, ras terminate,
2484          * ring destroy, cmd/fence/fw buffers destory,
2485          * psp->cmd destory) are delayed to psp_hw_fini
2486          */
2487         return ret;
2488 }
2489
2490 static int psp_hw_init(void *handle)
2491 {
2492         int ret;
2493         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2494
2495         mutex_lock(&adev->firmware.mutex);
2496         /*
2497          * This sequence is just used on hw_init only once, no need on
2498          * resume.
2499          */
2500         ret = amdgpu_ucode_init_bo(adev);
2501         if (ret)
2502                 goto failed;
2503
2504         ret = psp_load_fw(adev);
2505         if (ret) {
2506                 DRM_ERROR("PSP firmware loading failed\n");
2507                 goto failed;
2508         }
2509
2510         mutex_unlock(&adev->firmware.mutex);
2511         return 0;
2512
2513 failed:
2514         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2515         mutex_unlock(&adev->firmware.mutex);
2516         return -EINVAL;
2517 }
2518
2519 static int psp_hw_fini(void *handle)
2520 {
2521         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2522         struct psp_context *psp = &adev->psp;
2523
2524         if (psp->adev->psp.ta_fw) {
2525                 psp_ras_terminate(psp);
2526                 psp_securedisplay_terminate(psp);
2527                 psp_rap_terminate(psp);
2528                 psp_dtm_terminate(psp);
2529                 psp_hdcp_terminate(psp);
2530         }
2531
2532         psp_asd_unload(psp);
2533
2534         psp_tmr_terminate(psp);
2535         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2536
2537         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2538                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2539         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2540                               &psp->fence_buf_mc_addr, &psp->fence_buf);
2541         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2542                               (void **)&psp->cmd_buf_mem);
2543
2544         kfree(psp->cmd);
2545         psp->cmd = NULL;
2546
2547         return 0;
2548 }
2549
2550 static int psp_suspend(void *handle)
2551 {
2552         int ret;
2553         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2554         struct psp_context *psp = &adev->psp;
2555
2556         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2557             psp->xgmi_context.initialized == 1) {
2558                 ret = psp_xgmi_terminate(psp);
2559                 if (ret) {
2560                         DRM_ERROR("Failed to terminate xgmi ta\n");
2561                         return ret;
2562                 }
2563         }
2564
2565         if (psp->adev->psp.ta_fw) {
2566                 ret = psp_ras_terminate(psp);
2567                 if (ret) {
2568                         DRM_ERROR("Failed to terminate ras ta\n");
2569                         return ret;
2570                 }
2571                 ret = psp_hdcp_terminate(psp);
2572                 if (ret) {
2573                         DRM_ERROR("Failed to terminate hdcp ta\n");
2574                         return ret;
2575                 }
2576                 ret = psp_dtm_terminate(psp);
2577                 if (ret) {
2578                         DRM_ERROR("Failed to terminate dtm ta\n");
2579                         return ret;
2580                 }
2581                 ret = psp_rap_terminate(psp);
2582                 if (ret) {
2583                         DRM_ERROR("Failed to terminate rap ta\n");
2584                         return ret;
2585                 }
2586                 ret = psp_securedisplay_terminate(psp);
2587                 if (ret) {
2588                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2589                         return ret;
2590                 }
2591         }
2592
2593         ret = psp_asd_unload(psp);
2594         if (ret) {
2595                 DRM_ERROR("Failed to unload asd\n");
2596                 return ret;
2597         }
2598
2599         ret = psp_tmr_terminate(psp);
2600         if (ret) {
2601                 DRM_ERROR("Failed to terminate tmr\n");
2602                 return ret;
2603         }
2604
2605         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2606         if (ret) {
2607                 DRM_ERROR("PSP ring stop failed\n");
2608                 return ret;
2609         }
2610
2611         return 0;
2612 }
2613
2614 static int psp_resume(void *handle)
2615 {
2616         int ret;
2617         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2618         struct psp_context *psp = &adev->psp;
2619
2620         DRM_INFO("PSP is resuming...\n");
2621
2622         ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2623         if (ret) {
2624                 DRM_ERROR("Failed to process memory training!\n");
2625                 return ret;
2626         }
2627
2628         mutex_lock(&adev->firmware.mutex);
2629
2630         ret = psp_hw_start(psp);
2631         if (ret)
2632                 goto failed;
2633
2634         ret = psp_np_fw_load(psp);
2635         if (ret)
2636                 goto failed;
2637
2638         ret = psp_asd_load(psp);
2639         if (ret) {
2640                 DRM_ERROR("PSP load asd failed!\n");
2641                 goto failed;
2642         }
2643
2644         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2645                 ret = psp_xgmi_initialize(psp);
2646                 /* Warning the XGMI seesion initialize failure
2647                  * Instead of stop driver initialization
2648                  */
2649                 if (ret)
2650                         dev_err(psp->adev->dev,
2651                                 "XGMI: Failed to initialize XGMI session\n");
2652         }
2653
2654         if (psp->adev->psp.ta_fw) {
2655                 ret = psp_ras_initialize(psp);
2656                 if (ret)
2657                         dev_err(psp->adev->dev,
2658                                         "RAS: Failed to initialize RAS\n");
2659
2660                 ret = psp_hdcp_initialize(psp);
2661                 if (ret)
2662                         dev_err(psp->adev->dev,
2663                                 "HDCP: Failed to initialize HDCP\n");
2664
2665                 ret = psp_dtm_initialize(psp);
2666                 if (ret)
2667                         dev_err(psp->adev->dev,
2668                                 "DTM: Failed to initialize DTM\n");
2669
2670                 ret = psp_rap_initialize(psp);
2671                 if (ret)
2672                         dev_err(psp->adev->dev,
2673                                 "RAP: Failed to initialize RAP\n");
2674
2675                 ret = psp_securedisplay_initialize(psp);
2676                 if (ret)
2677                         dev_err(psp->adev->dev,
2678                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2679         }
2680
2681         mutex_unlock(&adev->firmware.mutex);
2682
2683         return 0;
2684
2685 failed:
2686         DRM_ERROR("PSP resume failed\n");
2687         mutex_unlock(&adev->firmware.mutex);
2688         return ret;
2689 }
2690
2691 int psp_gpu_reset(struct amdgpu_device *adev)
2692 {
2693         int ret;
2694
2695         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2696                 return 0;
2697
2698         mutex_lock(&adev->psp.mutex);
2699         ret = psp_mode1_reset(&adev->psp);
2700         mutex_unlock(&adev->psp.mutex);
2701
2702         return ret;
2703 }
2704
2705 int psp_rlc_autoload_start(struct psp_context *psp)
2706 {
2707         int ret;
2708         struct psp_gfx_cmd_resp *cmd;
2709
2710         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2711         if (!cmd)
2712                 return -ENOMEM;
2713
2714         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2715
2716         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2717                                  psp->fence_buf_mc_addr);
2718         kfree(cmd);
2719         return ret;
2720 }
2721
2722 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2723                         uint64_t cmd_gpu_addr, int cmd_size)
2724 {
2725         struct amdgpu_firmware_info ucode = {0};
2726
2727         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2728                 AMDGPU_UCODE_ID_VCN0_RAM;
2729         ucode.mc_addr = cmd_gpu_addr;
2730         ucode.ucode_size = cmd_size;
2731
2732         return psp_execute_np_fw_load(&adev->psp, &ucode);
2733 }
2734
2735 int psp_ring_cmd_submit(struct psp_context *psp,
2736                         uint64_t cmd_buf_mc_addr,
2737                         uint64_t fence_mc_addr,
2738                         int index)
2739 {
2740         unsigned int psp_write_ptr_reg = 0;
2741         struct psp_gfx_rb_frame *write_frame;
2742         struct psp_ring *ring = &psp->km_ring;
2743         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2744         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2745                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2746         struct amdgpu_device *adev = psp->adev;
2747         uint32_t ring_size_dw = ring->ring_size / 4;
2748         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2749
2750         /* KM (GPCOM) prepare write pointer */
2751         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2752
2753         /* Update KM RB frame pointer to new frame */
2754         /* write_frame ptr increments by size of rb_frame in bytes */
2755         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2756         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2757                 write_frame = ring_buffer_start;
2758         else
2759                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2760         /* Check invalid write_frame ptr address */
2761         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2762                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2763                           ring_buffer_start, ring_buffer_end, write_frame);
2764                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2765                 return -EINVAL;
2766         }
2767
2768         /* Initialize KM RB frame */
2769         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2770
2771         /* Update KM RB frame */
2772         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2773         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2774         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2775         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2776         write_frame->fence_value = index;
2777         amdgpu_device_flush_hdp(adev, NULL);
2778
2779         /* Update the write Pointer in DWORDs */
2780         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2781         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2782         return 0;
2783 }
2784
2785 int psp_init_asd_microcode(struct psp_context *psp,
2786                            const char *chip_name)
2787 {
2788         struct amdgpu_device *adev = psp->adev;
2789         char fw_name[PSP_FW_NAME_LEN];
2790         const struct psp_firmware_header_v1_0 *asd_hdr;
2791         int err = 0;
2792
2793         if (!chip_name) {
2794                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2795                 return -EINVAL;
2796         }
2797
2798         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2799         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2800         if (err)
2801                 goto out;
2802
2803         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2804         if (err)
2805                 goto out;
2806
2807         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2808         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2809         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2810         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2811         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2812                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2813         return 0;
2814 out:
2815         dev_err(adev->dev, "fail to initialize asd microcode\n");
2816         release_firmware(adev->psp.asd_fw);
2817         adev->psp.asd_fw = NULL;
2818         return err;
2819 }
2820
2821 int psp_init_toc_microcode(struct psp_context *psp,
2822                            const char *chip_name)
2823 {
2824         struct amdgpu_device *adev = psp->adev;
2825         char fw_name[30];
2826         const struct psp_firmware_header_v1_0 *toc_hdr;
2827         int err = 0;
2828
2829         if (!chip_name) {
2830                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2831                 return -EINVAL;
2832         }
2833
2834         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2835         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2836         if (err)
2837                 goto out;
2838
2839         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2840         if (err)
2841                 goto out;
2842
2843         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2844         adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2845         adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2846         adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2847         adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2848                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2849         return 0;
2850 out:
2851         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2852         release_firmware(adev->psp.toc_fw);
2853         adev->psp.toc_fw = NULL;
2854         return err;
2855 }
2856
2857 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
2858 {
2859         const struct psp_firmware_header_v1_0 *sos_hdr;
2860         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2861
2862         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2863
2864         if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) {
2865                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2866                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
2867
2868                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos.offset_bytes);
2869                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2870                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2871
2872                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos.size_bytes);
2873                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2874                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
2875         } else {
2876                 /* Load alternate PSP SOS FW */
2877                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2878
2879                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2880                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2881
2882                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
2883                 adev->psp.sys_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2884                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
2885
2886                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
2887                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2888                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
2889         }
2890
2891         if ((adev->psp.sys_bin_size == 0) || (adev->psp.sos_bin_size == 0)) {
2892                 dev_warn(adev->dev, "PSP SOS FW not available");
2893                 return -EINVAL;
2894         }
2895
2896         return 0;
2897 }
2898
2899 int psp_init_sos_microcode(struct psp_context *psp,
2900                            const char *chip_name)
2901 {
2902         struct amdgpu_device *adev = psp->adev;
2903         char fw_name[PSP_FW_NAME_LEN];
2904         const struct psp_firmware_header_v1_0 *sos_hdr;
2905         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2906         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2907         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2908         int err = 0;
2909
2910         if (!chip_name) {
2911                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2912                 return -EINVAL;
2913         }
2914
2915         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2916         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2917         if (err)
2918                 goto out;
2919
2920         err = amdgpu_ucode_validate(adev->psp.sos_fw);
2921         if (err)
2922                 goto out;
2923
2924         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2925         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2926
2927         switch (sos_hdr->header.header_version_major) {
2928         case 1:
2929                 err = psp_init_sos_base_fw(adev);
2930                 if (err)
2931                         goto out;
2932
2933                 if (sos_hdr->header.header_version_minor == 1) {
2934                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2935                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
2936                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2937                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
2938                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
2939                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2940                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
2941                 }
2942                 if (sos_hdr->header.header_version_minor == 2) {
2943                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2944                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
2945                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2946                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
2947                 }
2948                 if (sos_hdr->header.header_version_minor == 3) {
2949                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2950                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
2951                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2952                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
2953                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
2954                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2955                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
2956                         adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
2957                         adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2958                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
2959                         adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
2960                         adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2961                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
2962                 }
2963                 break;
2964         default:
2965                 dev_err(adev->dev,
2966                         "unsupported psp sos firmware\n");
2967                 err = -EINVAL;
2968                 goto out;
2969         }
2970
2971         return 0;
2972 out:
2973         dev_err(adev->dev,
2974                 "failed to init sos firmware\n");
2975         release_firmware(adev->psp.sos_fw);
2976         adev->psp.sos_fw = NULL;
2977
2978         return err;
2979 }
2980
2981 static int parse_ta_bin_descriptor(struct psp_context *psp,
2982                                    const struct ta_fw_bin_desc *desc,
2983                                    const struct ta_firmware_header_v2_0 *ta_hdr)
2984 {
2985         uint8_t *ucode_start_addr  = NULL;
2986
2987         if (!psp || !desc || !ta_hdr)
2988                 return -EINVAL;
2989
2990         ucode_start_addr  = (uint8_t *)ta_hdr +
2991                             le32_to_cpu(desc->offset_bytes) +
2992                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2993
2994         switch (desc->fw_type) {
2995         case TA_FW_TYPE_PSP_ASD:
2996                 psp->asd_fw_version        = le32_to_cpu(desc->fw_version);
2997                 psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
2998                 psp->asd_ucode_size        = le32_to_cpu(desc->size_bytes);
2999                 psp->asd_start_addr        = ucode_start_addr;
3000                 break;
3001         case TA_FW_TYPE_PSP_XGMI:
3002                 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
3003                 psp->ta_xgmi_ucode_size    = le32_to_cpu(desc->size_bytes);
3004                 psp->ta_xgmi_start_addr    = ucode_start_addr;
3005                 break;
3006         case TA_FW_TYPE_PSP_RAS:
3007                 psp->ta_ras_ucode_version  = le32_to_cpu(desc->fw_version);
3008                 psp->ta_ras_ucode_size     = le32_to_cpu(desc->size_bytes);
3009                 psp->ta_ras_start_addr     = ucode_start_addr;
3010                 break;
3011         case TA_FW_TYPE_PSP_HDCP:
3012                 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
3013                 psp->ta_hdcp_ucode_size    = le32_to_cpu(desc->size_bytes);
3014                 psp->ta_hdcp_start_addr    = ucode_start_addr;
3015                 break;
3016         case TA_FW_TYPE_PSP_DTM:
3017                 psp->ta_dtm_ucode_version  = le32_to_cpu(desc->fw_version);
3018                 psp->ta_dtm_ucode_size     = le32_to_cpu(desc->size_bytes);
3019                 psp->ta_dtm_start_addr     = ucode_start_addr;
3020                 break;
3021         case TA_FW_TYPE_PSP_RAP:
3022                 psp->ta_rap_ucode_version  = le32_to_cpu(desc->fw_version);
3023                 psp->ta_rap_ucode_size     = le32_to_cpu(desc->size_bytes);
3024                 psp->ta_rap_start_addr     = ucode_start_addr;
3025                 break;
3026         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3027                 psp->ta_securedisplay_ucode_version  = le32_to_cpu(desc->fw_version);
3028                 psp->ta_securedisplay_ucode_size     = le32_to_cpu(desc->size_bytes);
3029                 psp->ta_securedisplay_start_addr     = ucode_start_addr;
3030                 break;
3031         default:
3032                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3033                 break;
3034         }
3035
3036         return 0;
3037 }
3038
3039 int psp_init_ta_microcode(struct psp_context *psp,
3040                           const char *chip_name)
3041 {
3042         struct amdgpu_device *adev = psp->adev;
3043         char fw_name[PSP_FW_NAME_LEN];
3044         const struct ta_firmware_header_v2_0 *ta_hdr;
3045         int err = 0;
3046         int ta_index = 0;
3047
3048         if (!chip_name) {
3049                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3050                 return -EINVAL;
3051         }
3052
3053         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3054         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3055         if (err)
3056                 goto out;
3057
3058         err = amdgpu_ucode_validate(adev->psp.ta_fw);
3059         if (err)
3060                 goto out;
3061
3062         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3063
3064         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3065                 dev_err(adev->dev, "unsupported TA header version\n");
3066                 err = -EINVAL;
3067                 goto out;
3068         }
3069
3070         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
3071                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3072                 err = -EINVAL;
3073                 goto out;
3074         }
3075
3076         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3077                 err = parse_ta_bin_descriptor(psp,
3078                                               &ta_hdr->ta_fw_bin[ta_index],
3079                                               ta_hdr);
3080                 if (err)
3081                         goto out;
3082         }
3083
3084         return 0;
3085 out:
3086         dev_err(adev->dev, "fail to initialize ta microcode\n");
3087         release_firmware(adev->psp.ta_fw);
3088         adev->psp.ta_fw = NULL;
3089         return err;
3090 }
3091
3092 static int psp_set_clockgating_state(void *handle,
3093                                      enum amd_clockgating_state state)
3094 {
3095         return 0;
3096 }
3097
3098 static int psp_set_powergating_state(void *handle,
3099                                      enum amd_powergating_state state)
3100 {
3101         return 0;
3102 }
3103
3104 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3105                                          struct device_attribute *attr,
3106                                          char *buf)
3107 {
3108         struct drm_device *ddev = dev_get_drvdata(dev);
3109         struct amdgpu_device *adev = drm_to_adev(ddev);
3110         uint32_t fw_ver;
3111         int ret;
3112
3113         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3114                 DRM_INFO("PSP block is not ready yet.");
3115                 return -EBUSY;
3116         }
3117
3118         mutex_lock(&adev->psp.mutex);
3119         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3120         mutex_unlock(&adev->psp.mutex);
3121
3122         if (ret) {
3123                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3124                 return ret;
3125         }
3126
3127         return sysfs_emit(buf, "%x\n", fw_ver);
3128 }
3129
3130 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3131                                                        struct device_attribute *attr,
3132                                                        const char *buf,
3133                                                        size_t count)
3134 {
3135         struct drm_device *ddev = dev_get_drvdata(dev);
3136         struct amdgpu_device *adev = drm_to_adev(ddev);
3137         void *cpu_addr;
3138         dma_addr_t dma_addr;
3139         int ret, idx;
3140         char fw_name[100];
3141         const struct firmware *usbc_pd_fw;
3142
3143         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3144                 DRM_INFO("PSP block is not ready yet.");
3145                 return -EBUSY;
3146         }
3147
3148         if (!drm_dev_enter(ddev, &idx))
3149                 return -ENODEV;
3150
3151         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3152         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3153         if (ret)
3154                 goto fail;
3155
3156         /* We need contiguous physical mem to place the FW  for psp to access */
3157         cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
3158
3159         ret = dma_mapping_error(adev->dev, dma_addr);
3160         if (ret)
3161                 goto rel_buf;
3162
3163         memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3164
3165         /*
3166          * x86 specific workaround.
3167          * Without it the buffer is invisible in PSP.
3168          *
3169          * TODO Remove once PSP starts snooping CPU cache
3170          */
3171 #ifdef CONFIG_X86
3172         clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
3173 #endif
3174
3175         mutex_lock(&adev->psp.mutex);
3176         ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
3177         mutex_unlock(&adev->psp.mutex);
3178
3179 rel_buf:
3180         dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
3181         release_firmware(usbc_pd_fw);
3182 fail:
3183         if (ret) {
3184                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3185                 count = ret;
3186         }
3187
3188         drm_dev_exit(idx);
3189         return count;
3190 }
3191
3192 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3193 {
3194         int idx;
3195
3196         if (!drm_dev_enter(&psp->adev->ddev, &idx))
3197                 return;
3198
3199         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3200         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3201
3202         drm_dev_exit(idx);
3203 }
3204
3205 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3206                    psp_usbc_pd_fw_sysfs_read,
3207                    psp_usbc_pd_fw_sysfs_write);
3208
3209
3210
3211 const struct amd_ip_funcs psp_ip_funcs = {
3212         .name = "psp",
3213         .early_init = psp_early_init,
3214         .late_init = NULL,
3215         .sw_init = psp_sw_init,
3216         .sw_fini = psp_sw_fini,
3217         .hw_init = psp_hw_init,
3218         .hw_fini = psp_hw_fini,
3219         .suspend = psp_suspend,
3220         .resume = psp_resume,
3221         .is_idle = NULL,
3222         .check_soft_reset = NULL,
3223         .wait_for_idle = NULL,
3224         .soft_reset = NULL,
3225         .set_clockgating_state = psp_set_clockgating_state,
3226         .set_powergating_state = psp_set_powergating_state,
3227 };
3228
3229 static int psp_sysfs_init(struct amdgpu_device *adev)
3230 {
3231         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3232
3233         if (ret)
3234                 DRM_ERROR("Failed to create USBC PD FW control file!");
3235
3236         return ret;
3237 }
3238
3239 static void psp_sysfs_fini(struct amdgpu_device *adev)
3240 {
3241         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3242 }
3243
3244 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3245 {
3246         .type = AMD_IP_BLOCK_TYPE_PSP,
3247         .major = 3,
3248         .minor = 1,
3249         .rev = 0,
3250         .funcs = &psp_ip_funcs,
3251 };
3252
3253 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3254 {
3255         .type = AMD_IP_BLOCK_TYPE_PSP,
3256         .major = 10,
3257         .minor = 0,
3258         .rev = 0,
3259         .funcs = &psp_ip_funcs,
3260 };
3261
3262 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3263 {
3264         .type = AMD_IP_BLOCK_TYPE_PSP,
3265         .major = 11,
3266         .minor = 0,
3267         .rev = 0,
3268         .funcs = &psp_ip_funcs,
3269 };
3270
3271 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3272 {
3273         .type = AMD_IP_BLOCK_TYPE_PSP,
3274         .major = 12,
3275         .minor = 0,
3276         .rev = 0,
3277         .funcs = &psp_ip_funcs,
3278 };
3279
3280 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3281         .type = AMD_IP_BLOCK_TYPE_PSP,
3282         .major = 13,
3283         .minor = 0,
3284         .rev = 0,
3285         .funcs = &psp_ip_funcs,
3286 };