drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "soc15_common.h"
  33 #include "psp_v3_1.h"
  34 #include "psp_v10_0.h"
  35 #include "psp_v11_0.h"
  36 #include "psp_v12_0.h"
  37
  38 #include "amdgpu_ras.h"
  39
  40 static int psp_sysfs_init(struct amdgpu_device *adev);
  41 static void psp_sysfs_fini(struct amdgpu_device *adev);
  42
  43 static int psp_load_smu_fw(struct psp_context *psp);
  44
  45 /*
  46  * Due to DF Cstate management centralized to PMFW, the firmware
  47  * loading sequence will be updated as below:
  48  *   - Load KDB
  49  *   - Load SYS_DRV
  50  *   - Load tOS
  51  *   - Load PMFW
  52  *   - Setup TMR
  53  *   - Load other non-psp fw
  54  *   - Load ASD
  55  *   - Load XGMI/RAS/HDCP/DTM TA if any
  56  *
  57  * This new sequence is required for
  58  *   - Arcturus
  59  *   - Navi12 and onwards
  60  */
  61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  62 {
  63         struct amdgpu_device *adev = psp->adev;
  64
  65         psp->pmfw_centralized_cstate_management = false;
  66
  67         if (amdgpu_sriov_vf(adev))
  68                 return;
  69
  70         if (adev->flags & AMD_IS_APU)
  71                 return;
  72
  73         if ((adev->asic_type == CHIP_ARCTURUS) ||
  74             (adev->asic_type >= CHIP_NAVI12))
  75                 psp->pmfw_centralized_cstate_management = true;
  76 }
  77
  78 static int psp_early_init(void *handle)
  79 {
  80         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  81         struct psp_context *psp = &adev->psp;
  82
  83         switch (adev->asic_type) {
  84         case CHIP_VEGA10:
  85         case CHIP_VEGA12:
  86                 psp_v3_1_set_psp_funcs(psp);
  87                 psp->autoload_supported = false;
  88                 break;
  89         case CHIP_RAVEN:
  90                 psp_v10_0_set_psp_funcs(psp);
  91                 psp->autoload_supported = false;
  92                 break;
  93         case CHIP_VEGA20:
  94         case CHIP_ARCTURUS:
  95                 psp_v11_0_set_psp_funcs(psp);
  96                 psp->autoload_supported = false;
  97                 break;
  98         case CHIP_NAVI10:
  99         case CHIP_NAVI14:
 100         case CHIP_NAVI12:
 101         case CHIP_SIENNA_CICHLID:
 102         case CHIP_NAVY_FLOUNDER:
 103         case CHIP_VANGOGH:
 104         case CHIP_DIMGREY_CAVEFISH:
 105                 psp_v11_0_set_psp_funcs(psp);
 106                 psp->autoload_supported = true;
 107                 break;
 108         case CHIP_RENOIR:
 109                 psp_v12_0_set_psp_funcs(psp);
 110                 break;
 111         default:
 112                 return -EINVAL;
 113         }
 114
 115         psp->adev = adev;
 116
 117         psp_check_pmfw_centralized_cstate_management(psp);
 118
 119         return 0;
 120 }
 121
 122 static void psp_memory_training_fini(struct psp_context *psp)
 123 {
 124         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 125
 126         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 127         kfree(ctx->sys_cache);
 128         ctx->sys_cache = NULL;
 129 }
 130
 131 static int psp_memory_training_init(struct psp_context *psp)
 132 {
 133         int ret;
 134         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 135
 136         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 137                 DRM_DEBUG("memory training is not supported!\n");
 138                 return 0;
 139         }
 140
 141         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 142         if (ctx->sys_cache == NULL) {
 143                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 144                 ret = -ENOMEM;
 145                 goto Err_out;
 146         }
 147
 148         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 149                   ctx->train_data_size,
 150                   ctx->p2c_train_data_offset,
 151                   ctx->c2p_train_data_offset);
 152         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 153         return 0;
 154
 155 Err_out:
 156         psp_memory_training_fini(psp);
 157         return ret;
 158 }
 159
 160 static int psp_sw_init(void *handle)
 161 {
 162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 163         struct psp_context *psp = &adev->psp;
 164         int ret;
 165
 166         if (!amdgpu_sriov_vf(adev)) {
 167                 ret = psp_init_microcode(psp);
 168                 if (ret) {
 169                         DRM_ERROR("Failed to load psp firmware!\n");
 170                         return ret;
 171                 }
 172         }
 173
 174         ret = psp_memory_training_init(psp);
 175         if (ret) {
 176                 DRM_ERROR("Failed to initialize memory training!\n");
 177                 return ret;
 178         }
 179         ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 180         if (ret) {
 181                 DRM_ERROR("Failed to process memory training!\n");
 182                 return ret;
 183         }
 184
 185         if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
 186                 ret= psp_sysfs_init(adev);
 187                 if (ret) {
 188                         return ret;
 189                 }
 190         }
 191
 192         return 0;
 193 }
 194
 195 static int psp_sw_fini(void *handle)
 196 {
 197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 198
 199         psp_memory_training_fini(&adev->psp);
 200         if (adev->psp.sos_fw) {
 201                 release_firmware(adev->psp.sos_fw);
 202                 adev->psp.sos_fw = NULL;
 203         }
 204         if (adev->psp.asd_fw) {
 205                 release_firmware(adev->psp.asd_fw);
 206                 adev->psp.asd_fw = NULL;
 207         }
 208         if (adev->psp.ta_fw) {
 209                 release_firmware(adev->psp.ta_fw);
 210                 adev->psp.ta_fw = NULL;
 211         }
 212
 213         if (adev->asic_type == CHIP_NAVI10 ||
 214             adev->asic_type == CHIP_SIENNA_CICHLID)
 215                 psp_sysfs_fini(adev);
 216
 217         return 0;
 218 }
 219
 220 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 221                  uint32_t reg_val, uint32_t mask, bool check_changed)
 222 {
 223         uint32_t val;
 224         int i;
 225         struct amdgpu_device *adev = psp->adev;
 226
 227         if (psp->adev->in_pci_err_recovery)
 228                 return 0;
 229
 230         for (i = 0; i < adev->usec_timeout; i++) {
 231                 val = RREG32(reg_index);
 232                 if (check_changed) {
 233                         if (val != reg_val)
 234                                 return 0;
 235                 } else {
 236                         if ((val & mask) == reg_val)
 237                                 return 0;
 238                 }
 239                 udelay(1);
 240         }
 241
 242         return -ETIME;
 243 }
 244
 245 static int
 246 psp_cmd_submit_buf(struct psp_context *psp,
 247                    struct amdgpu_firmware_info *ucode,
 248                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 249 {
 250         int ret;
 251         int index;
 252         int timeout = 2000;
 253         bool ras_intr = false;
 254         bool skip_unsupport = false;
 255
 256         if (psp->adev->in_pci_err_recovery)
 257                 return 0;
 258
 259         mutex_lock(&psp->mutex);
 260
 261         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 262
 263         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 264
 265         index = atomic_inc_return(&psp->fence_value);
 266         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 267         if (ret) {
 268                 atomic_dec(&psp->fence_value);
 269                 mutex_unlock(&psp->mutex);
 270                 return ret;
 271         }
 272
 273         amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 274         while (*((unsigned int *)psp->fence_buf) != index) {
 275                 if (--timeout == 0)
 276                         break;
 277                 /*
 278                  * Shouldn't wait for timeout when err_event_athub occurs,
 279                  * because gpu reset thread triggered and lock resource should
 280                  * be released for psp resume sequence.
 281                  */
 282                 ras_intr = amdgpu_ras_intr_triggered();
 283                 if (ras_intr)
 284                         break;
 285                 msleep(1);
 286                 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 287         }
 288
 289         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 290         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 291                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 292
 293         /* In some cases, psp response status is not 0 even there is no
 294          * problem while the command is submitted. Some version of PSP FW
 295          * doesn't write 0 to that field.
 296          * So here we would like to only print a warning instead of an error
 297          * during psp initialization to avoid breaking hw_init and it doesn't
 298          * return -EINVAL.
 299          */
 300         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 301                 if (ucode)
 302                         DRM_WARN("failed to load ucode id (%d) ",
 303                                   ucode->ucode_id);
 304                 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
 305                          psp->cmd_buf_mem->cmd_id,
 306                          psp->cmd_buf_mem->resp.status);
 307                 if (!timeout) {
 308                         mutex_unlock(&psp->mutex);
 309                         return -EINVAL;
 310                 }
 311         }
 312
 313         /* get xGMI session id from response buffer */
 314         cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
 315
 316         if (ucode) {
 317                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 318                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 319         }
 320         mutex_unlock(&psp->mutex);
 321
 322         return ret;
 323 }
 324
 325 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 326                                  struct psp_gfx_cmd_resp *cmd,
 327                                  uint64_t tmr_mc, uint32_t size)
 328 {
 329         if (amdgpu_sriov_vf(psp->adev))
 330                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 331         else
 332                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 333         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 334         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 335         cmd->cmd.cmd_setup_tmr.buf_size = size;
 336 }
 337
 338 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 339                                       uint64_t pri_buf_mc, uint32_t size)
 340 {
 341         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 342         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 343         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 344         cmd->cmd.cmd_load_toc.toc_size = size;
 345 }
 346
 347 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 348 static int psp_load_toc(struct psp_context *psp,
 349                         uint32_t *tmr_size)
 350 {
 351         int ret;
 352         struct psp_gfx_cmd_resp *cmd;
 353
 354         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 355         if (!cmd)
 356                 return -ENOMEM;
 357         /* Copy toc to psp firmware private buffer */
 358         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 359         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 360
 361         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 362
 363         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 364                                  psp->fence_buf_mc_addr);
 365         if (!ret)
 366                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 367         kfree(cmd);
 368         return ret;
 369 }
 370
 371 /* Set up Trusted Memory Region */
 372 static int psp_tmr_init(struct psp_context *psp)
 373 {
 374         int ret;
 375         int tmr_size;
 376         void *tmr_buf;
 377         void **pptr;
 378
 379         /*
 380          * According to HW engineer, they prefer the TMR address be "naturally
 381          * aligned" , e.g. the start address be an integer divide of TMR size.
 382          *
 383          * Note: this memory need be reserved till the driver
 384          * uninitializes.
 385          */
 386         tmr_size = PSP_TMR_SIZE;
 387
 388         /* For ASICs support RLC autoload, psp will parse the toc
 389          * and calculate the total size of TMR needed */
 390         if (!amdgpu_sriov_vf(psp->adev) &&
 391             psp->toc_start_addr &&
 392             psp->toc_bin_size &&
 393             psp->fw_pri_buf) {
 394                 ret = psp_load_toc(psp, &tmr_size);
 395                 if (ret) {
 396                         DRM_ERROR("Failed to load toc\n");
 397                         return ret;
 398                 }
 399         }
 400
 401         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 402         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
 403                                       AMDGPU_GEM_DOMAIN_VRAM,
 404                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 405
 406         return ret;
 407 }
 408
 409 static int psp_clear_vf_fw(struct psp_context *psp)
 410 {
 411         int ret;
 412         struct psp_gfx_cmd_resp *cmd;
 413
 414         if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12)
 415                 return 0;
 416
 417         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 418         if (!cmd)
 419                 return -ENOMEM;
 420
 421         cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW;
 422
 423         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 424         kfree(cmd);
 425
 426         return ret;
 427 }
 428
 429 static bool psp_skip_tmr(struct psp_context *psp)
 430 {
 431         switch (psp->adev->asic_type) {
 432         case CHIP_NAVI12:
 433         case CHIP_SIENNA_CICHLID:
 434                 return true;
 435         default:
 436                 return false;
 437         }
 438 }
 439
 440 static int psp_tmr_load(struct psp_context *psp)
 441 {
 442         int ret;
 443         struct psp_gfx_cmd_resp *cmd;
 444
 445         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 446          * Already set up by host driver.
 447          */
 448         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 449                 return 0;
 450
 451         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 452         if (!cmd)
 453                 return -ENOMEM;
 454
 455         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
 456                              amdgpu_bo_size(psp->tmr_bo));
 457         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 458                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 459
 460         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 461                                  psp->fence_buf_mc_addr);
 462
 463         kfree(cmd);
 464
 465         return ret;
 466 }
 467
 468 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 469                                         struct psp_gfx_cmd_resp *cmd)
 470 {
 471         if (amdgpu_sriov_vf(psp->adev))
 472                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 473         else
 474                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 475 }
 476
 477 static int psp_tmr_unload(struct psp_context *psp)
 478 {
 479         int ret;
 480         struct psp_gfx_cmd_resp *cmd;
 481
 482         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 483         if (!cmd)
 484                 return -ENOMEM;
 485
 486         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 487         DRM_INFO("free PSP TMR buffer\n");
 488
 489         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 490                                  psp->fence_buf_mc_addr);
 491
 492         kfree(cmd);
 493
 494         return ret;
 495 }
 496
 497 static int psp_tmr_terminate(struct psp_context *psp)
 498 {
 499         int ret;
 500         void *tmr_buf;
 501         void **pptr;
 502
 503         ret = psp_tmr_unload(psp);
 504         if (ret)
 505                 return ret;
 506
 507         /* free TMR memory buffer */
 508         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 509         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 510
 511         return 0;
 512 }
 513
 514 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 515                                 uint64_t asd_mc, uint32_t size)
 516 {
 517         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 518         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 519         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 520         cmd->cmd.cmd_load_ta.app_len = size;
 521
 522         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
 523         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
 524         cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
 525 }
 526
 527 static int psp_asd_load(struct psp_context *psp)
 528 {
 529         int ret;
 530         struct psp_gfx_cmd_resp *cmd;
 531
 532         /* If PSP version doesn't match ASD version, asd loading will be failed.
 533          * add workaround to bypass it for sriov now.
 534          * TODO: add version check to make it common
 535          */
 536         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)
 537                 return 0;
 538
 539         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 540         if (!cmd)
 541                 return -ENOMEM;
 542
 543         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 544         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 545
 546         psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 547                                   psp->asd_ucode_size);
 548
 549         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 550                                  psp->fence_buf_mc_addr);
 551         if (!ret) {
 552                 psp->asd_context.asd_initialized = true;
 553                 psp->asd_context.session_id = cmd->resp.session_id;
 554         }
 555
 556         kfree(cmd);
 557
 558         return ret;
 559 }
 560
 561 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 562                                        uint32_t session_id)
 563 {
 564         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 565         cmd->cmd.cmd_unload_ta.session_id = session_id;
 566 }
 567
 568 static int psp_asd_unload(struct psp_context *psp)
 569 {
 570         int ret;
 571         struct psp_gfx_cmd_resp *cmd;
 572
 573         if (amdgpu_sriov_vf(psp->adev))
 574                 return 0;
 575
 576         if (!psp->asd_context.asd_initialized)
 577                 return 0;
 578
 579         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 580         if (!cmd)
 581                 return -ENOMEM;
 582
 583         psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
 584
 585         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 586                                  psp->fence_buf_mc_addr);
 587         if (!ret)
 588                 psp->asd_context.asd_initialized = false;
 589
 590         kfree(cmd);
 591
 592         return ret;
 593 }
 594
 595 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 596                 uint32_t id, uint32_t value)
 597 {
 598         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 599         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 600         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 601 }
 602
 603 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 604                 uint32_t value)
 605 {
 606         struct psp_gfx_cmd_resp *cmd = NULL;
 607         int ret = 0;
 608
 609         if (reg >= PSP_REG_LAST)
 610                 return -EINVAL;
 611
 612         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 613         if (!cmd)
 614                 return -ENOMEM;
 615
 616         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 617         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 618
 619         kfree(cmd);
 620         return ret;
 621 }
 622
 623 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 624                                      uint64_t ta_bin_mc,
 625                                      uint32_t ta_bin_size,
 626                                      uint64_t ta_shared_mc,
 627                                      uint32_t ta_shared_size)
 628 {
 629         cmd->cmd_id                             = GFX_CMD_ID_LOAD_TA;
 630         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 631         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 632         cmd->cmd.cmd_load_ta.app_len            = ta_bin_size;
 633
 634         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
 635         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
 636         cmd->cmd.cmd_load_ta.cmd_buf_len         = ta_shared_size;
 637 }
 638
 639 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 640 {
 641         int ret;
 642
 643         /*
 644          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 645          * physical) for xgmi ta <-> Driver
 646          */
 647         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 648                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 649                                       &psp->xgmi_context.xgmi_shared_bo,
 650                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 651                                       &psp->xgmi_context.xgmi_shared_buf);
 652
 653         return ret;
 654 }
 655
 656 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 657                                        uint32_t ta_cmd_id,
 658                                        uint32_t session_id)
 659 {
 660         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
 661         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
 662         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 663 }
 664
 665 static int psp_ta_invoke(struct psp_context *psp,
 666                   uint32_t ta_cmd_id,
 667                   uint32_t session_id)
 668 {
 669         int ret;
 670         struct psp_gfx_cmd_resp *cmd;
 671
 672         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 673         if (!cmd)
 674                 return -ENOMEM;
 675
 676         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
 677
 678         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 679                                  psp->fence_buf_mc_addr);
 680
 681         kfree(cmd);
 682
 683         return ret;
 684 }
 685
 686 static int psp_xgmi_load(struct psp_context *psp)
 687 {
 688         int ret;
 689         struct psp_gfx_cmd_resp *cmd;
 690
 691         /*
 692          * TODO: bypass the loading in sriov for now
 693          */
 694
 695         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 696         if (!cmd)
 697                 return -ENOMEM;
 698
 699         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 700         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 701
 702         psp_prep_ta_load_cmd_buf(cmd,
 703                                  psp->fw_pri_mc_addr,
 704                                  psp->ta_xgmi_ucode_size,
 705                                  psp->xgmi_context.xgmi_shared_mc_addr,
 706                                  PSP_XGMI_SHARED_MEM_SIZE);
 707
 708         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 709                                  psp->fence_buf_mc_addr);
 710
 711         if (!ret) {
 712                 psp->xgmi_context.initialized = 1;
 713                 psp->xgmi_context.session_id = cmd->resp.session_id;
 714         }
 715
 716         kfree(cmd);
 717
 718         return ret;
 719 }
 720
 721 static int psp_xgmi_unload(struct psp_context *psp)
 722 {
 723         int ret;
 724         struct psp_gfx_cmd_resp *cmd;
 725         struct amdgpu_device *adev = psp->adev;
 726
 727         /* XGMI TA unload currently is not supported on Arcturus */
 728         if (adev->asic_type == CHIP_ARCTURUS)
 729                 return 0;
 730
 731         /*
 732          * TODO: bypass the unloading in sriov for now
 733          */
 734
 735         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 736         if (!cmd)
 737                 return -ENOMEM;
 738
 739         psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 740
 741         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 742                                  psp->fence_buf_mc_addr);
 743
 744         kfree(cmd);
 745
 746         return ret;
 747 }
 748
 749 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 750 {
 751         return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
 752 }
 753
 754 int psp_xgmi_terminate(struct psp_context *psp)
 755 {
 756         int ret;
 757
 758         if (!psp->xgmi_context.initialized)
 759                 return 0;
 760
 761         ret = psp_xgmi_unload(psp);
 762         if (ret)
 763                 return ret;
 764
 765         psp->xgmi_context.initialized = 0;
 766
 767         /* free xgmi shared memory */
 768         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 769                         &psp->xgmi_context.xgmi_shared_mc_addr,
 770                         &psp->xgmi_context.xgmi_shared_buf);
 771
 772         return 0;
 773 }
 774
 775 int psp_xgmi_initialize(struct psp_context *psp)
 776 {
 777         struct ta_xgmi_shared_memory *xgmi_cmd;
 778         int ret;
 779
 780         if (!psp->adev->psp.ta_fw ||
 781             !psp->adev->psp.ta_xgmi_ucode_size ||
 782             !psp->adev->psp.ta_xgmi_start_addr)
 783                 return -ENOENT;
 784
 785         if (!psp->xgmi_context.initialized) {
 786                 ret = psp_xgmi_init_shared_buf(psp);
 787                 if (ret)
 788                         return ret;
 789         }
 790
 791         /* Load XGMI TA */
 792         ret = psp_xgmi_load(psp);
 793         if (ret)
 794                 return ret;
 795
 796         /* Initialize XGMI session */
 797         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 798         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 799         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 800
 801         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 802
 803         return ret;
 804 }
 805
 806 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 807 {
 808         struct ta_xgmi_shared_memory *xgmi_cmd;
 809         int ret;
 810
 811         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 812         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 813
 814         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 815
 816         /* Invoke xgmi ta to get hive id */
 817         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 818         if (ret)
 819                 return ret;
 820
 821         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 822
 823         return 0;
 824 }
 825
 826 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 827 {
 828         struct ta_xgmi_shared_memory *xgmi_cmd;
 829         int ret;
 830
 831         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 832         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 833
 834         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 835
 836         /* Invoke xgmi ta to get the node id */
 837         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 838         if (ret)
 839                 return ret;
 840
 841         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 842
 843         return 0;
 844 }
 845
 846 int psp_xgmi_get_topology_info(struct psp_context *psp,
 847                                int number_devices,
 848                                struct psp_xgmi_topology_info *topology)
 849 {
 850         struct ta_xgmi_shared_memory *xgmi_cmd;
 851         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 852         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 853         int i;
 854         int ret;
 855
 856         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 857                 return -EINVAL;
 858
 859         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 860         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 861
 862         /* Fill in the shared memory with topology information as input */
 863         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 864         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 865         topology_info_input->num_nodes = number_devices;
 866
 867         for (i = 0; i < topology_info_input->num_nodes; i++) {
 868                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 869                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 870                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 871                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 872         }
 873
 874         /* Invoke xgmi ta to get the topology information */
 875         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 876         if (ret)
 877                 return ret;
 878
 879         /* Read the output topology information from the shared memory */
 880         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 881         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 882         for (i = 0; i < topology->num_nodes; i++) {
 883                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 884                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 885                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 886                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 887         }
 888
 889         return 0;
 890 }
 891
 892 int psp_xgmi_set_topology_info(struct psp_context *psp,
 893                                int number_devices,
 894                                struct psp_xgmi_topology_info *topology)
 895 {
 896         struct ta_xgmi_shared_memory *xgmi_cmd;
 897         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 898         int i;
 899
 900         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 901                 return -EINVAL;
 902
 903         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 904         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 905
 906         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 907         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 908         topology_info_input->num_nodes = number_devices;
 909
 910         for (i = 0; i < topology_info_input->num_nodes; i++) {
 911                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 912                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 913                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 914                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 915         }
 916
 917         /* Invoke xgmi ta to set topology information */
 918         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 919 }
 920
 921 // ras begin
 922 static int psp_ras_init_shared_buf(struct psp_context *psp)
 923 {
 924         int ret;
 925
 926         /*
 927          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 928          * physical) for ras ta <-> Driver
 929          */
 930         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 931                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 932                         &psp->ras.ras_shared_bo,
 933                         &psp->ras.ras_shared_mc_addr,
 934                         &psp->ras.ras_shared_buf);
 935
 936         return ret;
 937 }
 938
 939 static int psp_ras_load(struct psp_context *psp)
 940 {
 941         int ret;
 942         struct psp_gfx_cmd_resp *cmd;
 943         struct ta_ras_shared_memory *ras_cmd;
 944
 945         /*
 946          * TODO: bypass the loading in sriov for now
 947          */
 948         if (amdgpu_sriov_vf(psp->adev))
 949                 return 0;
 950
 951         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 952         if (!cmd)
 953                 return -ENOMEM;
 954
 955         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 956         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
 957
 958         psp_prep_ta_load_cmd_buf(cmd,
 959                                  psp->fw_pri_mc_addr,
 960                                  psp->ta_ras_ucode_size,
 961                                  psp->ras.ras_shared_mc_addr,
 962                                  PSP_RAS_SHARED_MEM_SIZE);
 963
 964         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 965                         psp->fence_buf_mc_addr);
 966
 967         ras_cmd = (struct ta_ras_shared_memory*)psp->ras.ras_shared_buf;
 968
 969         if (!ret) {
 970                 psp->ras.session_id = cmd->resp.session_id;
 971
 972                 if (!ras_cmd->ras_status)
 973                         psp->ras.ras_initialized = true;
 974                 else
 975                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
 976         }
 977
 978         if (ret || ras_cmd->ras_status)
 979                 amdgpu_ras_fini(psp->adev);
 980
 981         kfree(cmd);
 982
 983         return ret;
 984 }
 985
 986 static int psp_ras_unload(struct psp_context *psp)
 987 {
 988         int ret;
 989         struct psp_gfx_cmd_resp *cmd;
 990
 991         /*
 992          * TODO: bypass the unloading in sriov for now
 993          */
 994         if (amdgpu_sriov_vf(psp->adev))
 995                 return 0;
 996
 997         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 998         if (!cmd)
 999                 return -ENOMEM;
1000
1001         psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
1002
1003         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1004                         psp->fence_buf_mc_addr);
1005
1006         kfree(cmd);
1007
1008         return ret;
1009 }
1010
1011 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1012 {
1013         struct ta_ras_shared_memory *ras_cmd;
1014         int ret;
1015
1016         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1017
1018         /*
1019          * TODO: bypass the loading in sriov for now
1020          */
1021         if (amdgpu_sriov_vf(psp->adev))
1022                 return 0;
1023
1024         ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1025
1026         if (amdgpu_ras_intr_triggered())
1027                 return ret;
1028
1029         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1030         {
1031                 DRM_WARN("RAS: Unsupported Interface");
1032                 return -EINVAL;
1033         }
1034
1035         if (!ret) {
1036                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1037                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1038
1039                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1040                 }
1041                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1042                         dev_warn(psp->adev->dev,
1043                                  "RAS internal register access blocked\n");
1044         }
1045
1046         return ret;
1047 }
1048
1049 int psp_ras_enable_features(struct psp_context *psp,
1050                 union ta_ras_cmd_input *info, bool enable)
1051 {
1052         struct ta_ras_shared_memory *ras_cmd;
1053         int ret;
1054
1055         if (!psp->ras.ras_initialized)
1056                 return -EINVAL;
1057
1058         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1059         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1060
1061         if (enable)
1062                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1063         else
1064                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1065
1066         ras_cmd->ras_in_message = *info;
1067
1068         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1069         if (ret)
1070                 return -EINVAL;
1071
1072         return ras_cmd->ras_status;
1073 }
1074
1075 static int psp_ras_terminate(struct psp_context *psp)
1076 {
1077         int ret;
1078
1079         /*
1080          * TODO: bypass the terminate in sriov for now
1081          */
1082         if (amdgpu_sriov_vf(psp->adev))
1083                 return 0;
1084
1085         if (!psp->ras.ras_initialized)
1086                 return 0;
1087
1088         ret = psp_ras_unload(psp);
1089         if (ret)
1090                 return ret;
1091
1092         psp->ras.ras_initialized = false;
1093
1094         /* free ras shared memory */
1095         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1096                         &psp->ras.ras_shared_mc_addr,
1097                         &psp->ras.ras_shared_buf);
1098
1099         return 0;
1100 }
1101
1102 static int psp_ras_initialize(struct psp_context *psp)
1103 {
1104         int ret;
1105
1106         /*
1107          * TODO: bypass the initialize in sriov for now
1108          */
1109         if (amdgpu_sriov_vf(psp->adev))
1110                 return 0;
1111
1112         if (!psp->adev->psp.ta_ras_ucode_size ||
1113             !psp->adev->psp.ta_ras_start_addr) {
1114                 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
1115                 return 0;
1116         }
1117
1118         if (!psp->ras.ras_initialized) {
1119                 ret = psp_ras_init_shared_buf(psp);
1120                 if (ret)
1121                         return ret;
1122         }
1123
1124         ret = psp_ras_load(psp);
1125         if (ret)
1126                 return ret;
1127
1128         return 0;
1129 }
1130
1131 int psp_ras_trigger_error(struct psp_context *psp,
1132                           struct ta_ras_trigger_error_input *info)
1133 {
1134         struct ta_ras_shared_memory *ras_cmd;
1135         int ret;
1136
1137         if (!psp->ras.ras_initialized)
1138                 return -EINVAL;
1139
1140         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1141         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1142
1143         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1144         ras_cmd->ras_in_message.trigger_error = *info;
1145
1146         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1147         if (ret)
1148                 return -EINVAL;
1149
1150         /* If err_event_athub occurs error inject was successful, however
1151            return status from TA is no long reliable */
1152         if (amdgpu_ras_intr_triggered())
1153                 return 0;
1154
1155         return ras_cmd->ras_status;
1156 }
1157 // ras end
1158
1159 // HDCP start
1160 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1161 {
1162         int ret;
1163
1164         /*
1165          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1166          * physical) for hdcp ta <-> Driver
1167          */
1168         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1169                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1170                                       &psp->hdcp_context.hdcp_shared_bo,
1171                                       &psp->hdcp_context.hdcp_shared_mc_addr,
1172                                       &psp->hdcp_context.hdcp_shared_buf);
1173
1174         return ret;
1175 }
1176
1177 static int psp_hdcp_load(struct psp_context *psp)
1178 {
1179         int ret;
1180         struct psp_gfx_cmd_resp *cmd;
1181
1182         /*
1183          * TODO: bypass the loading in sriov for now
1184          */
1185         if (amdgpu_sriov_vf(psp->adev))
1186                 return 0;
1187
1188         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1189         if (!cmd)
1190                 return -ENOMEM;
1191
1192         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1193         memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
1194                psp->ta_hdcp_ucode_size);
1195
1196         psp_prep_ta_load_cmd_buf(cmd,
1197                                  psp->fw_pri_mc_addr,
1198                                  psp->ta_hdcp_ucode_size,
1199                                  psp->hdcp_context.hdcp_shared_mc_addr,
1200                                  PSP_HDCP_SHARED_MEM_SIZE);
1201
1202         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1203
1204         if (!ret) {
1205                 psp->hdcp_context.hdcp_initialized = true;
1206                 psp->hdcp_context.session_id = cmd->resp.session_id;
1207                 mutex_init(&psp->hdcp_context.mutex);
1208         }
1209
1210         kfree(cmd);
1211
1212         return ret;
1213 }
1214 static int psp_hdcp_initialize(struct psp_context *psp)
1215 {
1216         int ret;
1217
1218         /*
1219          * TODO: bypass the initialize in sriov for now
1220          */
1221         if (amdgpu_sriov_vf(psp->adev))
1222                 return 0;
1223
1224         if (!psp->adev->psp.ta_hdcp_ucode_size ||
1225             !psp->adev->psp.ta_hdcp_start_addr) {
1226                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1227                 return 0;
1228         }
1229
1230         if (!psp->hdcp_context.hdcp_initialized) {
1231                 ret = psp_hdcp_init_shared_buf(psp);
1232                 if (ret)
1233                         return ret;
1234         }
1235
1236         ret = psp_hdcp_load(psp);
1237         if (ret)
1238                 return ret;
1239
1240         return 0;
1241 }
1242
1243 static int psp_hdcp_unload(struct psp_context *psp)
1244 {
1245         int ret;
1246         struct psp_gfx_cmd_resp *cmd;
1247
1248         /*
1249          * TODO: bypass the unloading in sriov for now
1250          */
1251         if (amdgpu_sriov_vf(psp->adev))
1252                 return 0;
1253
1254         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1255         if (!cmd)
1256                 return -ENOMEM;
1257
1258         psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1259
1260         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1261
1262         kfree(cmd);
1263
1264         return ret;
1265 }
1266
1267 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1268 {
1269         /*
1270          * TODO: bypass the loading in sriov for now
1271          */
1272         if (amdgpu_sriov_vf(psp->adev))
1273                 return 0;
1274
1275         return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1276 }
1277
1278 static int psp_hdcp_terminate(struct psp_context *psp)
1279 {
1280         int ret;
1281
1282         /*
1283          * TODO: bypass the terminate in sriov for now
1284          */
1285         if (amdgpu_sriov_vf(psp->adev))
1286                 return 0;
1287
1288         if (!psp->hdcp_context.hdcp_initialized)
1289                 return 0;
1290
1291         ret = psp_hdcp_unload(psp);
1292         if (ret)
1293                 return ret;
1294
1295         psp->hdcp_context.hdcp_initialized = false;
1296
1297         /* free hdcp shared memory */
1298         amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1299                               &psp->hdcp_context.hdcp_shared_mc_addr,
1300                               &psp->hdcp_context.hdcp_shared_buf);
1301
1302         return 0;
1303 }
1304 // HDCP end
1305
1306 // DTM start
1307 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1308 {
1309         int ret;
1310
1311         /*
1312          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1313          * physical) for dtm ta <-> Driver
1314          */
1315         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1316                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1317                                       &psp->dtm_context.dtm_shared_bo,
1318                                       &psp->dtm_context.dtm_shared_mc_addr,
1319                                       &psp->dtm_context.dtm_shared_buf);
1320
1321         return ret;
1322 }
1323
1324 static int psp_dtm_load(struct psp_context *psp)
1325 {
1326         int ret;
1327         struct psp_gfx_cmd_resp *cmd;
1328
1329         /*
1330          * TODO: bypass the loading in sriov for now
1331          */
1332         if (amdgpu_sriov_vf(psp->adev))
1333                 return 0;
1334
1335         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1336         if (!cmd)
1337                 return -ENOMEM;
1338
1339         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1340         memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1341
1342         psp_prep_ta_load_cmd_buf(cmd,
1343                                  psp->fw_pri_mc_addr,
1344                                  psp->ta_dtm_ucode_size,
1345                                  psp->dtm_context.dtm_shared_mc_addr,
1346                                  PSP_DTM_SHARED_MEM_SIZE);
1347
1348         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1349
1350         if (!ret) {
1351                 psp->dtm_context.dtm_initialized = true;
1352                 psp->dtm_context.session_id = cmd->resp.session_id;
1353                 mutex_init(&psp->dtm_context.mutex);
1354         }
1355
1356         kfree(cmd);
1357
1358         return ret;
1359 }
1360
1361 static int psp_dtm_initialize(struct psp_context *psp)
1362 {
1363         int ret;
1364
1365         /*
1366          * TODO: bypass the initialize in sriov for now
1367          */
1368         if (amdgpu_sriov_vf(psp->adev))
1369                 return 0;
1370
1371         if (!psp->adev->psp.ta_dtm_ucode_size ||
1372             !psp->adev->psp.ta_dtm_start_addr) {
1373                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1374                 return 0;
1375         }
1376
1377         if (!psp->dtm_context.dtm_initialized) {
1378                 ret = psp_dtm_init_shared_buf(psp);
1379                 if (ret)
1380                         return ret;
1381         }
1382
1383         ret = psp_dtm_load(psp);
1384         if (ret)
1385                 return ret;
1386
1387         return 0;
1388 }
1389
1390 static int psp_dtm_unload(struct psp_context *psp)
1391 {
1392         int ret;
1393         struct psp_gfx_cmd_resp *cmd;
1394
1395         /*
1396          * TODO: bypass the unloading in sriov for now
1397          */
1398         if (amdgpu_sriov_vf(psp->adev))
1399                 return 0;
1400
1401         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1402         if (!cmd)
1403                 return -ENOMEM;
1404
1405         psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1406
1407         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1408
1409         kfree(cmd);
1410
1411         return ret;
1412 }
1413
1414 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1415 {
1416         /*
1417          * TODO: bypass the loading in sriov for now
1418          */
1419         if (amdgpu_sriov_vf(psp->adev))
1420                 return 0;
1421
1422         return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1423 }
1424
1425 static int psp_dtm_terminate(struct psp_context *psp)
1426 {
1427         int ret;
1428
1429         /*
1430          * TODO: bypass the terminate in sriov for now
1431          */
1432         if (amdgpu_sriov_vf(psp->adev))
1433                 return 0;
1434
1435         if (!psp->dtm_context.dtm_initialized)
1436                 return 0;
1437
1438         ret = psp_dtm_unload(psp);
1439         if (ret)
1440                 return ret;
1441
1442         psp->dtm_context.dtm_initialized = false;
1443
1444         /* free hdcp shared memory */
1445         amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1446                               &psp->dtm_context.dtm_shared_mc_addr,
1447                               &psp->dtm_context.dtm_shared_buf);
1448
1449         return 0;
1450 }
1451 // DTM end
1452
1453 // RAP start
1454 static int psp_rap_init_shared_buf(struct psp_context *psp)
1455 {
1456         int ret;
1457
1458         /*
1459          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1460          * physical) for rap ta <-> Driver
1461          */
1462         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1463                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1464                                       &psp->rap_context.rap_shared_bo,
1465                                       &psp->rap_context.rap_shared_mc_addr,
1466                                       &psp->rap_context.rap_shared_buf);
1467
1468         return ret;
1469 }
1470
1471 static int psp_rap_load(struct psp_context *psp)
1472 {
1473         int ret;
1474         struct psp_gfx_cmd_resp *cmd;
1475
1476         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1477         if (!cmd)
1478                 return -ENOMEM;
1479
1480         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1481         memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1482
1483         psp_prep_ta_load_cmd_buf(cmd,
1484                                  psp->fw_pri_mc_addr,
1485                                  psp->ta_rap_ucode_size,
1486                                  psp->rap_context.rap_shared_mc_addr,
1487                                  PSP_RAP_SHARED_MEM_SIZE);
1488
1489         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1490
1491         if (!ret) {
1492                 psp->rap_context.rap_initialized = true;
1493                 psp->rap_context.session_id = cmd->resp.session_id;
1494                 mutex_init(&psp->rap_context.mutex);
1495         }
1496
1497         kfree(cmd);
1498
1499         return ret;
1500 }
1501
1502 static int psp_rap_unload(struct psp_context *psp)
1503 {
1504         int ret;
1505         struct psp_gfx_cmd_resp *cmd;
1506
1507         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1508         if (!cmd)
1509                 return -ENOMEM;
1510
1511         psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1512
1513         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1514
1515         kfree(cmd);
1516
1517         return ret;
1518 }
1519
1520 static int psp_rap_initialize(struct psp_context *psp)
1521 {
1522         int ret;
1523
1524         /*
1525          * TODO: bypass the initialize in sriov for now
1526          */
1527         if (amdgpu_sriov_vf(psp->adev))
1528                 return 0;
1529
1530         if (!psp->adev->psp.ta_rap_ucode_size ||
1531             !psp->adev->psp.ta_rap_start_addr) {
1532                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1533                 return 0;
1534         }
1535
1536         if (!psp->rap_context.rap_initialized) {
1537                 ret = psp_rap_init_shared_buf(psp);
1538                 if (ret)
1539                         return ret;
1540         }
1541
1542         ret = psp_rap_load(psp);
1543         if (ret)
1544                 return ret;
1545
1546         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE);
1547         if (ret != TA_RAP_STATUS__SUCCESS) {
1548                 psp_rap_unload(psp);
1549
1550                 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1551                               &psp->rap_context.rap_shared_mc_addr,
1552                               &psp->rap_context.rap_shared_buf);
1553
1554                 psp->rap_context.rap_initialized = false;
1555
1556                 dev_warn(psp->adev->dev, "RAP TA initialize fail.\n");
1557                 return -EINVAL;
1558         }
1559
1560         return 0;
1561 }
1562
1563 static int psp_rap_terminate(struct psp_context *psp)
1564 {
1565         int ret;
1566
1567         if (!psp->rap_context.rap_initialized)
1568                 return 0;
1569
1570         ret = psp_rap_unload(psp);
1571
1572         psp->rap_context.rap_initialized = false;
1573
1574         /* free rap shared memory */
1575         amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1576                               &psp->rap_context.rap_shared_mc_addr,
1577                               &psp->rap_context.rap_shared_buf);
1578
1579         return ret;
1580 }
1581
1582 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1583 {
1584         struct ta_rap_shared_memory *rap_cmd;
1585         int ret;
1586
1587         if (!psp->rap_context.rap_initialized)
1588                 return -EINVAL;
1589
1590         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1591             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1592                 return -EINVAL;
1593
1594         mutex_lock(&psp->rap_context.mutex);
1595
1596         rap_cmd = (struct ta_rap_shared_memory *)
1597                   psp->rap_context.rap_shared_buf;
1598         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1599
1600         rap_cmd->cmd_id = ta_cmd_id;
1601         rap_cmd->validation_method_id = METHOD_A;
1602
1603         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1604         if (ret) {
1605                 mutex_unlock(&psp->rap_context.mutex);
1606                 return ret;
1607         }
1608
1609         mutex_unlock(&psp->rap_context.mutex);
1610
1611         return rap_cmd->rap_status;
1612 }
1613 // RAP end
1614
1615 static int psp_hw_start(struct psp_context *psp)
1616 {
1617         struct amdgpu_device *adev = psp->adev;
1618         int ret;
1619
1620         if (!amdgpu_sriov_vf(adev)) {
1621                 if (psp->kdb_bin_size &&
1622                     (psp->funcs->bootloader_load_kdb != NULL)) {
1623                         ret = psp_bootloader_load_kdb(psp);
1624                         if (ret) {
1625                                 DRM_ERROR("PSP load kdb failed!\n");
1626                                 return ret;
1627                         }
1628                 }
1629
1630                 if (psp->spl_bin_size) {
1631                         ret = psp_bootloader_load_spl(psp);
1632                         if (ret) {
1633                                 DRM_ERROR("PSP load spl failed!\n");
1634                                 return ret;
1635                         }
1636                 }
1637
1638                 ret = psp_bootloader_load_sysdrv(psp);
1639                 if (ret) {
1640                         DRM_ERROR("PSP load sysdrv failed!\n");
1641                         return ret;
1642                 }
1643
1644                 ret = psp_bootloader_load_sos(psp);
1645                 if (ret) {
1646                         DRM_ERROR("PSP load sos failed!\n");
1647                         return ret;
1648                 }
1649         }
1650
1651         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1652         if (ret) {
1653                 DRM_ERROR("PSP create ring failed!\n");
1654                 return ret;
1655         }
1656
1657         ret = psp_clear_vf_fw(psp);
1658         if (ret) {
1659                 DRM_ERROR("PSP clear vf fw!\n");
1660                 return ret;
1661         }
1662
1663         ret = psp_tmr_init(psp);
1664         if (ret) {
1665                 DRM_ERROR("PSP tmr init failed!\n");
1666                 return ret;
1667         }
1668
1669         /*
1670          * For ASICs with DF Cstate management centralized
1671          * to PMFW, TMR setup should be performed after PMFW
1672          * loaded and before other non-psp firmware loaded.
1673          */
1674         if (psp->pmfw_centralized_cstate_management) {
1675                 ret = psp_load_smu_fw(psp);
1676                 if (ret)
1677                         return ret;
1678         }
1679
1680         ret = psp_tmr_load(psp);
1681         if (ret) {
1682                 DRM_ERROR("PSP load tmr failed!\n");
1683                 return ret;
1684         }
1685
1686         return 0;
1687 }
1688
1689 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1690                            enum psp_gfx_fw_type *type)
1691 {
1692         switch (ucode->ucode_id) {
1693         case AMDGPU_UCODE_ID_SDMA0:
1694                 *type = GFX_FW_TYPE_SDMA0;
1695                 break;
1696         case AMDGPU_UCODE_ID_SDMA1:
1697                 *type = GFX_FW_TYPE_SDMA1;
1698                 break;
1699         case AMDGPU_UCODE_ID_SDMA2:
1700                 *type = GFX_FW_TYPE_SDMA2;
1701                 break;
1702         case AMDGPU_UCODE_ID_SDMA3:
1703                 *type = GFX_FW_TYPE_SDMA3;
1704                 break;
1705         case AMDGPU_UCODE_ID_SDMA4:
1706                 *type = GFX_FW_TYPE_SDMA4;
1707                 break;
1708         case AMDGPU_UCODE_ID_SDMA5:
1709                 *type = GFX_FW_TYPE_SDMA5;
1710                 break;
1711         case AMDGPU_UCODE_ID_SDMA6:
1712                 *type = GFX_FW_TYPE_SDMA6;
1713                 break;
1714         case AMDGPU_UCODE_ID_SDMA7:
1715                 *type = GFX_FW_TYPE_SDMA7;
1716                 break;
1717         case AMDGPU_UCODE_ID_CP_MES:
1718                 *type = GFX_FW_TYPE_CP_MES;
1719                 break;
1720         case AMDGPU_UCODE_ID_CP_MES_DATA:
1721                 *type = GFX_FW_TYPE_MES_STACK;
1722                 break;
1723         case AMDGPU_UCODE_ID_CP_CE:
1724                 *type = GFX_FW_TYPE_CP_CE;
1725                 break;
1726         case AMDGPU_UCODE_ID_CP_PFP:
1727                 *type = GFX_FW_TYPE_CP_PFP;
1728                 break;
1729         case AMDGPU_UCODE_ID_CP_ME:
1730                 *type = GFX_FW_TYPE_CP_ME;
1731                 break;
1732         case AMDGPU_UCODE_ID_CP_MEC1:
1733                 *type = GFX_FW_TYPE_CP_MEC;
1734                 break;
1735         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1736                 *type = GFX_FW_TYPE_CP_MEC_ME1;
1737                 break;
1738         case AMDGPU_UCODE_ID_CP_MEC2:
1739                 *type = GFX_FW_TYPE_CP_MEC;
1740                 break;
1741         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1742                 *type = GFX_FW_TYPE_CP_MEC_ME2;
1743                 break;
1744         case AMDGPU_UCODE_ID_RLC_G:
1745                 *type = GFX_FW_TYPE_RLC_G;
1746                 break;
1747         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1748                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
1749                 break;
1750         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
1751                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
1752                 break;
1753         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
1754                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
1755                 break;
1756         case AMDGPU_UCODE_ID_RLC_IRAM:
1757                 *type = GFX_FW_TYPE_RLC_IRAM;
1758                 break;
1759         case AMDGPU_UCODE_ID_RLC_DRAM:
1760                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
1761                 break;
1762         case AMDGPU_UCODE_ID_SMC:
1763                 *type = GFX_FW_TYPE_SMU;
1764                 break;
1765         case AMDGPU_UCODE_ID_UVD:
1766                 *type = GFX_FW_TYPE_UVD;
1767                 break;
1768         case AMDGPU_UCODE_ID_UVD1:
1769                 *type = GFX_FW_TYPE_UVD1;
1770                 break;
1771         case AMDGPU_UCODE_ID_VCE:
1772                 *type = GFX_FW_TYPE_VCE;
1773                 break;
1774         case AMDGPU_UCODE_ID_VCN:
1775                 *type = GFX_FW_TYPE_VCN;
1776                 break;
1777         case AMDGPU_UCODE_ID_VCN1:
1778                 *type = GFX_FW_TYPE_VCN1;
1779                 break;
1780         case AMDGPU_UCODE_ID_DMCU_ERAM:
1781                 *type = GFX_FW_TYPE_DMCU_ERAM;
1782                 break;
1783         case AMDGPU_UCODE_ID_DMCU_INTV:
1784                 *type = GFX_FW_TYPE_DMCU_ISR;
1785                 break;
1786         case AMDGPU_UCODE_ID_VCN0_RAM:
1787                 *type = GFX_FW_TYPE_VCN0_RAM;
1788                 break;
1789         case AMDGPU_UCODE_ID_VCN1_RAM:
1790                 *type = GFX_FW_TYPE_VCN1_RAM;
1791                 break;
1792         case AMDGPU_UCODE_ID_DMCUB:
1793                 *type = GFX_FW_TYPE_DMUB;
1794                 break;
1795         case AMDGPU_UCODE_ID_MAXIMUM:
1796         default:
1797                 return -EINVAL;
1798         }
1799
1800         return 0;
1801 }
1802
1803 static void psp_print_fw_hdr(struct psp_context *psp,
1804                              struct amdgpu_firmware_info *ucode)
1805 {
1806         struct amdgpu_device *adev = psp->adev;
1807         struct common_firmware_header *hdr;
1808
1809         switch (ucode->ucode_id) {
1810         case AMDGPU_UCODE_ID_SDMA0:
1811         case AMDGPU_UCODE_ID_SDMA1:
1812         case AMDGPU_UCODE_ID_SDMA2:
1813         case AMDGPU_UCODE_ID_SDMA3:
1814         case AMDGPU_UCODE_ID_SDMA4:
1815         case AMDGPU_UCODE_ID_SDMA5:
1816         case AMDGPU_UCODE_ID_SDMA6:
1817         case AMDGPU_UCODE_ID_SDMA7:
1818                 hdr = (struct common_firmware_header *)
1819                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1820                 amdgpu_ucode_print_sdma_hdr(hdr);
1821                 break;
1822         case AMDGPU_UCODE_ID_CP_CE:
1823                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1824                 amdgpu_ucode_print_gfx_hdr(hdr);
1825                 break;
1826         case AMDGPU_UCODE_ID_CP_PFP:
1827                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1828                 amdgpu_ucode_print_gfx_hdr(hdr);
1829                 break;
1830         case AMDGPU_UCODE_ID_CP_ME:
1831                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1832                 amdgpu_ucode_print_gfx_hdr(hdr);
1833                 break;
1834         case AMDGPU_UCODE_ID_CP_MEC1:
1835                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1836                 amdgpu_ucode_print_gfx_hdr(hdr);
1837                 break;
1838         case AMDGPU_UCODE_ID_RLC_G:
1839                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1840                 amdgpu_ucode_print_rlc_hdr(hdr);
1841                 break;
1842         case AMDGPU_UCODE_ID_SMC:
1843                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
1844                 amdgpu_ucode_print_smc_hdr(hdr);
1845                 break;
1846         default:
1847                 break;
1848         }
1849 }
1850
1851 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1852                                        struct psp_gfx_cmd_resp *cmd)
1853 {
1854         int ret;
1855         uint64_t fw_mem_mc_addr = ucode->mc_addr;
1856
1857         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1858
1859         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1860         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1861         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1862         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1863
1864         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1865         if (ret)
1866                 DRM_ERROR("Unknown firmware type\n");
1867
1868         return ret;
1869 }
1870
1871 static int psp_execute_np_fw_load(struct psp_context *psp,
1872                                   struct amdgpu_firmware_info *ucode)
1873 {
1874         int ret = 0;
1875
1876         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1877         if (ret)
1878                 return ret;
1879
1880         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1881                                  psp->fence_buf_mc_addr);
1882
1883         return ret;
1884 }
1885
1886 static int psp_load_smu_fw(struct psp_context *psp)
1887 {
1888         int ret;
1889         struct amdgpu_device* adev = psp->adev;
1890         struct amdgpu_firmware_info *ucode =
1891                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1892         struct amdgpu_ras *ras = psp->ras.ras;
1893
1894         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
1895                 return 0;
1896
1897
1898         if (amdgpu_in_reset(adev) && ras && ras->supported) {
1899                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
1900                 if (ret) {
1901                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
1902                 }
1903         }
1904
1905         ret = psp_execute_np_fw_load(psp, ucode);
1906
1907         if (ret)
1908                 DRM_ERROR("PSP load smu failed!\n");
1909
1910         return ret;
1911 }
1912
1913 static bool fw_load_skip_check(struct psp_context *psp,
1914                                struct amdgpu_firmware_info *ucode)
1915 {
1916         if (!ucode->fw)
1917                 return true;
1918
1919         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1920             (psp_smu_reload_quirk(psp) ||
1921              psp->autoload_supported ||
1922              psp->pmfw_centralized_cstate_management))
1923                 return true;
1924
1925         if (amdgpu_sriov_vf(psp->adev) &&
1926            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1927             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1928             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1929             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1930             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1931             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1932             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1933             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1934             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
1935             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
1936             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
1937             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
1938             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
1939                 /*skip ucode loading in SRIOV VF */
1940                 return true;
1941
1942         if (psp->autoload_supported &&
1943             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1944              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1945                 /* skip mec JT when autoload is enabled */
1946                 return true;
1947
1948         return false;
1949 }
1950
1951 static int psp_np_fw_load(struct psp_context *psp)
1952 {
1953         int i, ret;
1954         struct amdgpu_firmware_info *ucode;
1955         struct amdgpu_device* adev = psp->adev;
1956
1957         if (psp->autoload_supported &&
1958             !psp->pmfw_centralized_cstate_management) {
1959                 ret = psp_load_smu_fw(psp);
1960                 if (ret)
1961                         return ret;
1962         }
1963
1964         for (i = 0; i < adev->firmware.max_ucodes; i++) {
1965                 ucode = &adev->firmware.ucode[i];
1966
1967                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1968                     !fw_load_skip_check(psp, ucode)) {
1969                         ret = psp_load_smu_fw(psp);
1970                         if (ret)
1971                                 return ret;
1972                         continue;
1973                 }
1974
1975                 if (fw_load_skip_check(psp, ucode))
1976                         continue;
1977
1978                 if (psp->autoload_supported &&
1979                     (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1980                      adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
1981                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
1982                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
1983                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
1984                         /* PSP only receive one SDMA fw for sienna_cichlid,
1985                          * as all four sdma fw are same */
1986                         continue;
1987
1988                 psp_print_fw_hdr(psp, ucode);
1989
1990                 ret = psp_execute_np_fw_load(psp, ucode);
1991                 if (ret)
1992                         return ret;
1993
1994                 /* Start rlc autoload after psp recieved all the gfx firmware */
1995                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1996                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1997                         ret = psp_rlc_autoload_start(psp);
1998                         if (ret) {
1999                                 DRM_ERROR("Failed to start rlc autoload\n");
2000                                 return ret;
2001                         }
2002                 }
2003         }
2004
2005         return 0;
2006 }
2007
2008 static int psp_load_fw(struct amdgpu_device *adev)
2009 {
2010         int ret;
2011         struct psp_context *psp = &adev->psp;
2012
2013         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2014                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2015                 goto skip_memalloc;
2016         }
2017
2018         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2019         if (!psp->cmd)
2020                 return -ENOMEM;
2021
2022         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2023                                         AMDGPU_GEM_DOMAIN_GTT,
2024                                         &psp->fw_pri_bo,
2025                                         &psp->fw_pri_mc_addr,
2026                                         &psp->fw_pri_buf);
2027         if (ret)
2028                 goto failed;
2029
2030         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2031                                         AMDGPU_GEM_DOMAIN_VRAM,
2032                                         &psp->fence_buf_bo,
2033                                         &psp->fence_buf_mc_addr,
2034                                         &psp->fence_buf);
2035         if (ret)
2036                 goto failed;
2037
2038         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2039                                       AMDGPU_GEM_DOMAIN_VRAM,
2040                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2041                                       (void **)&psp->cmd_buf_mem);
2042         if (ret)
2043                 goto failed;
2044
2045         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2046
2047         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2048         if (ret) {
2049                 DRM_ERROR("PSP ring init failed!\n");
2050                 goto failed;
2051         }
2052
2053 skip_memalloc:
2054         ret = psp_hw_start(psp);
2055         if (ret)
2056                 goto failed;
2057
2058         ret = psp_np_fw_load(psp);
2059         if (ret)
2060                 goto failed;
2061
2062         ret = psp_asd_load(psp);
2063         if (ret) {
2064                 DRM_ERROR("PSP load asd failed!\n");
2065                 return ret;
2066         }
2067
2068         if (psp->adev->psp.ta_fw) {
2069                 ret = psp_ras_initialize(psp);
2070                 if (ret)
2071                         dev_err(psp->adev->dev,
2072                                         "RAS: Failed to initialize RAS\n");
2073
2074                 ret = psp_hdcp_initialize(psp);
2075                 if (ret)
2076                         dev_err(psp->adev->dev,
2077                                 "HDCP: Failed to initialize HDCP\n");
2078
2079                 ret = psp_dtm_initialize(psp);
2080                 if (ret)
2081                         dev_err(psp->adev->dev,
2082                                 "DTM: Failed to initialize DTM\n");
2083
2084                 ret = psp_rap_initialize(psp);
2085                 if (ret)
2086                         dev_err(psp->adev->dev,
2087                                 "RAP: Failed to initialize RAP\n");
2088         }
2089
2090         return 0;
2091
2092 failed:
2093         /*
2094          * all cleanup jobs (xgmi terminate, ras terminate,
2095          * ring destroy, cmd/fence/fw buffers destory,
2096          * psp->cmd destory) are delayed to psp_hw_fini
2097          */
2098         return ret;
2099 }
2100
2101 static int psp_hw_init(void *handle)
2102 {
2103         int ret;
2104         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2105
2106         mutex_lock(&adev->firmware.mutex);
2107         /*
2108          * This sequence is just used on hw_init only once, no need on
2109          * resume.
2110          */
2111         ret = amdgpu_ucode_init_bo(adev);
2112         if (ret)
2113                 goto failed;
2114
2115         ret = psp_load_fw(adev);
2116         if (ret) {
2117                 DRM_ERROR("PSP firmware loading failed\n");
2118                 goto failed;
2119         }
2120
2121         mutex_unlock(&adev->firmware.mutex);
2122         return 0;
2123
2124 failed:
2125         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2126         mutex_unlock(&adev->firmware.mutex);
2127         return -EINVAL;
2128 }
2129
2130 static int psp_hw_fini(void *handle)
2131 {
2132         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2133         struct psp_context *psp = &adev->psp;
2134         int ret;
2135
2136         if (psp->adev->psp.ta_fw) {
2137                 psp_ras_terminate(psp);
2138                 psp_rap_terminate(psp);
2139                 psp_dtm_terminate(psp);
2140                 psp_hdcp_terminate(psp);
2141         }
2142
2143         psp_asd_unload(psp);
2144         ret = psp_clear_vf_fw(psp);
2145         if (ret) {
2146                 DRM_ERROR("PSP clear vf fw!\n");
2147                 return ret;
2148         }
2149
2150         psp_tmr_terminate(psp);
2151         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2152
2153         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2154                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2155         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2156                               &psp->fence_buf_mc_addr, &psp->fence_buf);
2157         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2158                               (void **)&psp->cmd_buf_mem);
2159
2160         kfree(psp->cmd);
2161         psp->cmd = NULL;
2162
2163         return 0;
2164 }
2165
2166 static int psp_suspend(void *handle)
2167 {
2168         int ret;
2169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2170         struct psp_context *psp = &adev->psp;
2171
2172         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2173             psp->xgmi_context.initialized == 1) {
2174                 ret = psp_xgmi_terminate(psp);
2175                 if (ret) {
2176                         DRM_ERROR("Failed to terminate xgmi ta\n");
2177                         return ret;
2178                 }
2179         }
2180
2181         if (psp->adev->psp.ta_fw) {
2182                 ret = psp_ras_terminate(psp);
2183                 if (ret) {
2184                         DRM_ERROR("Failed to terminate ras ta\n");
2185                         return ret;
2186                 }
2187                 ret = psp_hdcp_terminate(psp);
2188                 if (ret) {
2189                         DRM_ERROR("Failed to terminate hdcp ta\n");
2190                         return ret;
2191                 }
2192                 ret = psp_dtm_terminate(psp);
2193                 if (ret) {
2194                         DRM_ERROR("Failed to terminate dtm ta\n");
2195                         return ret;
2196                 }
2197                 ret = psp_rap_terminate(psp);
2198                 if (ret) {
2199                         DRM_ERROR("Failed to terminate rap ta\n");
2200                         return ret;
2201                 }
2202         }
2203
2204         ret = psp_asd_unload(psp);
2205         if (ret) {
2206                 DRM_ERROR("Failed to unload asd\n");
2207                 return ret;
2208         }
2209
2210         ret = psp_tmr_terminate(psp);
2211         if (ret) {
2212                 DRM_ERROR("Failed to terminate tmr\n");
2213                 return ret;
2214         }
2215
2216         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2217         if (ret) {
2218                 DRM_ERROR("PSP ring stop failed\n");
2219                 return ret;
2220         }
2221
2222         return 0;
2223 }
2224
2225 static int psp_resume(void *handle)
2226 {
2227         int ret;
2228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2229         struct psp_context *psp = &adev->psp;
2230
2231         DRM_INFO("PSP is resuming...\n");
2232
2233         ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2234         if (ret) {
2235                 DRM_ERROR("Failed to process memory training!\n");
2236                 return ret;
2237         }
2238
2239         mutex_lock(&adev->firmware.mutex);
2240
2241         ret = psp_hw_start(psp);
2242         if (ret)
2243                 goto failed;
2244
2245         ret = psp_np_fw_load(psp);
2246         if (ret)
2247                 goto failed;
2248
2249         ret = psp_asd_load(psp);
2250         if (ret) {
2251                 DRM_ERROR("PSP load asd failed!\n");
2252                 goto failed;
2253         }
2254
2255         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2256                 ret = psp_xgmi_initialize(psp);
2257                 /* Warning the XGMI seesion initialize failure
2258                  * Instead of stop driver initialization
2259                  */
2260                 if (ret)
2261                         dev_err(psp->adev->dev,
2262                                 "XGMI: Failed to initialize XGMI session\n");
2263         }
2264
2265         if (psp->adev->psp.ta_fw) {
2266                 ret = psp_ras_initialize(psp);
2267                 if (ret)
2268                         dev_err(psp->adev->dev,
2269                                         "RAS: Failed to initialize RAS\n");
2270
2271                 ret = psp_hdcp_initialize(psp);
2272                 if (ret)
2273                         dev_err(psp->adev->dev,
2274                                 "HDCP: Failed to initialize HDCP\n");
2275
2276                 ret = psp_dtm_initialize(psp);
2277                 if (ret)
2278                         dev_err(psp->adev->dev,
2279                                 "DTM: Failed to initialize DTM\n");
2280
2281                 ret = psp_rap_initialize(psp);
2282                 if (ret)
2283                         dev_err(psp->adev->dev,
2284                                 "RAP: Failed to initialize RAP\n");
2285         }
2286
2287         mutex_unlock(&adev->firmware.mutex);
2288
2289         return 0;
2290
2291 failed:
2292         DRM_ERROR("PSP resume failed\n");
2293         mutex_unlock(&adev->firmware.mutex);
2294         return ret;
2295 }
2296
2297 int psp_gpu_reset(struct amdgpu_device *adev)
2298 {
2299         int ret;
2300
2301         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2302                 return 0;
2303
2304         mutex_lock(&adev->psp.mutex);
2305         ret = psp_mode1_reset(&adev->psp);
2306         mutex_unlock(&adev->psp.mutex);
2307
2308         return ret;
2309 }
2310
2311 int psp_rlc_autoload_start(struct psp_context *psp)
2312 {
2313         int ret;
2314         struct psp_gfx_cmd_resp *cmd;
2315
2316         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2317         if (!cmd)
2318                 return -ENOMEM;
2319
2320         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2321
2322         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2323                                  psp->fence_buf_mc_addr);
2324         kfree(cmd);
2325         return ret;
2326 }
2327
2328 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2329                         uint64_t cmd_gpu_addr, int cmd_size)
2330 {
2331         struct amdgpu_firmware_info ucode = {0};
2332
2333         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2334                 AMDGPU_UCODE_ID_VCN0_RAM;
2335         ucode.mc_addr = cmd_gpu_addr;
2336         ucode.ucode_size = cmd_size;
2337
2338         return psp_execute_np_fw_load(&adev->psp, &ucode);
2339 }
2340
2341 int psp_ring_cmd_submit(struct psp_context *psp,
2342                         uint64_t cmd_buf_mc_addr,
2343                         uint64_t fence_mc_addr,
2344                         int index)
2345 {
2346         unsigned int psp_write_ptr_reg = 0;
2347         struct psp_gfx_rb_frame *write_frame;
2348         struct psp_ring *ring = &psp->km_ring;
2349         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2350         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2351                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2352         struct amdgpu_device *adev = psp->adev;
2353         uint32_t ring_size_dw = ring->ring_size / 4;
2354         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2355
2356         /* KM (GPCOM) prepare write pointer */
2357         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2358
2359         /* Update KM RB frame pointer to new frame */
2360         /* write_frame ptr increments by size of rb_frame in bytes */
2361         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2362         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2363                 write_frame = ring_buffer_start;
2364         else
2365                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2366         /* Check invalid write_frame ptr address */
2367         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2368                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2369                           ring_buffer_start, ring_buffer_end, write_frame);
2370                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2371                 return -EINVAL;
2372         }
2373
2374         /* Initialize KM RB frame */
2375         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2376
2377         /* Update KM RB frame */
2378         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2379         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2380         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2381         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2382         write_frame->fence_value = index;
2383         amdgpu_asic_flush_hdp(adev, NULL);
2384
2385         /* Update the write Pointer in DWORDs */
2386         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2387         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2388         return 0;
2389 }
2390
2391 int psp_init_asd_microcode(struct psp_context *psp,
2392                            const char *chip_name)
2393 {
2394         struct amdgpu_device *adev = psp->adev;
2395         char fw_name[PSP_FW_NAME_LEN];
2396         const struct psp_firmware_header_v1_0 *asd_hdr;
2397         int err = 0;
2398
2399         if (!chip_name) {
2400                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2401                 return -EINVAL;
2402         }
2403
2404         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2405         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2406         if (err)
2407                 goto out;
2408
2409         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2410         if (err)
2411                 goto out;
2412
2413         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2414         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2415         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
2416         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2417         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2418                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2419         return 0;
2420 out:
2421         dev_err(adev->dev, "fail to initialize asd microcode\n");
2422         release_firmware(adev->psp.asd_fw);
2423         adev->psp.asd_fw = NULL;
2424         return err;
2425 }
2426
2427 int psp_init_toc_microcode(struct psp_context *psp,
2428                            const char *chip_name)
2429 {
2430         struct amdgpu_device *adev = psp->adev;
2431         char fw_name[30];
2432         const struct psp_firmware_header_v1_0 *toc_hdr;
2433         int err = 0;
2434
2435         if (!chip_name) {
2436                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2437                 return -EINVAL;
2438         }
2439
2440         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2441         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2442         if (err)
2443                 goto out;
2444
2445         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2446         if (err)
2447                 goto out;
2448
2449         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2450         adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2451         adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
2452         adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2453         adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2454                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2455         return 0;
2456 out:
2457         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2458         release_firmware(adev->psp.toc_fw);
2459         adev->psp.toc_fw = NULL;
2460         return err;
2461 }
2462
2463 int psp_init_sos_microcode(struct psp_context *psp,
2464                            const char *chip_name)
2465 {
2466         struct amdgpu_device *adev = psp->adev;
2467         char fw_name[PSP_FW_NAME_LEN];
2468         const struct psp_firmware_header_v1_0 *sos_hdr;
2469         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2470         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2471         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2472         int err = 0;
2473
2474         if (!chip_name) {
2475                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2476                 return -EINVAL;
2477         }
2478
2479         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2480         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2481         if (err)
2482                 goto out;
2483
2484         err = amdgpu_ucode_validate(adev->psp.sos_fw);
2485         if (err)
2486                 goto out;
2487
2488         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2489         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2490
2491         switch (sos_hdr->header.header_version_major) {
2492         case 1:
2493                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2494                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
2495                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
2496                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
2497                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2498                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2499                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2500                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
2501                 if (sos_hdr->header.header_version_minor == 1) {
2502                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2503                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
2504                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2505                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
2506                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
2507                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2508                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
2509                 }
2510                 if (sos_hdr->header.header_version_minor == 2) {
2511                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2512                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
2513                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2514                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
2515                 }
2516                 if (sos_hdr->header.header_version_minor == 3) {
2517                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2518                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
2519                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2520                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
2521                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
2522                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2523                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
2524                         adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
2525                         adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2526                                 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
2527                 }
2528                 break;
2529         default:
2530                 dev_err(adev->dev,
2531                         "unsupported psp sos firmware\n");
2532                 err = -EINVAL;
2533                 goto out;
2534         }
2535
2536         return 0;
2537 out:
2538         dev_err(adev->dev,
2539                 "failed to init sos firmware\n");
2540         release_firmware(adev->psp.sos_fw);
2541         adev->psp.sos_fw = NULL;
2542
2543         return err;
2544 }
2545
2546 int parse_ta_bin_descriptor(struct psp_context *psp,
2547                             const struct ta_fw_bin_desc *desc,
2548                             const struct ta_firmware_header_v2_0 *ta_hdr)
2549 {
2550         uint8_t *ucode_start_addr  = NULL;
2551
2552         if (!psp || !desc || !ta_hdr)
2553                 return -EINVAL;
2554
2555         ucode_start_addr  = (uint8_t *)ta_hdr +
2556                             le32_to_cpu(desc->offset_bytes) +
2557                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2558
2559         switch (desc->fw_type) {
2560         case TA_FW_TYPE_PSP_ASD:
2561                 psp->asd_fw_version        = le32_to_cpu(desc->fw_version);
2562                 psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
2563                 psp->asd_ucode_size        = le32_to_cpu(desc->size_bytes);
2564                 psp->asd_start_addr        = ucode_start_addr;
2565                 break;
2566         case TA_FW_TYPE_PSP_XGMI:
2567                 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
2568                 psp->ta_xgmi_ucode_size    = le32_to_cpu(desc->size_bytes);
2569                 psp->ta_xgmi_start_addr    = ucode_start_addr;
2570                 break;
2571         case TA_FW_TYPE_PSP_RAS:
2572                 psp->ta_ras_ucode_version  = le32_to_cpu(desc->fw_version);
2573                 psp->ta_ras_ucode_size     = le32_to_cpu(desc->size_bytes);
2574                 psp->ta_ras_start_addr     = ucode_start_addr;
2575                 break;
2576         case TA_FW_TYPE_PSP_HDCP:
2577                 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
2578                 psp->ta_hdcp_ucode_size    = le32_to_cpu(desc->size_bytes);
2579                 psp->ta_hdcp_start_addr    = ucode_start_addr;
2580                 break;
2581         case TA_FW_TYPE_PSP_DTM:
2582                 psp->ta_dtm_ucode_version  = le32_to_cpu(desc->fw_version);
2583                 psp->ta_dtm_ucode_size     = le32_to_cpu(desc->size_bytes);
2584                 psp->ta_dtm_start_addr     = ucode_start_addr;
2585                 break;
2586         case TA_FW_TYPE_PSP_RAP:
2587                 psp->ta_rap_ucode_version  = le32_to_cpu(desc->fw_version);
2588                 psp->ta_rap_ucode_size     = le32_to_cpu(desc->size_bytes);
2589                 psp->ta_rap_start_addr     = ucode_start_addr;
2590                 break;
2591         default:
2592                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
2593                 break;
2594         }
2595
2596         return 0;
2597 }
2598
2599 int psp_init_ta_microcode(struct psp_context *psp,
2600                           const char *chip_name)
2601 {
2602         struct amdgpu_device *adev = psp->adev;
2603         char fw_name[30];
2604         const struct ta_firmware_header_v2_0 *ta_hdr;
2605         int err = 0;
2606         int ta_index = 0;
2607
2608         if (!chip_name) {
2609                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
2610                 return -EINVAL;
2611         }
2612
2613         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
2614         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
2615         if (err)
2616                 goto out;
2617
2618         err = amdgpu_ucode_validate(adev->psp.ta_fw);
2619         if (err)
2620                 goto out;
2621
2622         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
2623
2624         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
2625                 dev_err(adev->dev, "unsupported TA header version\n");
2626                 err = -EINVAL;
2627                 goto out;
2628         }
2629
2630         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
2631                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
2632                 err = -EINVAL;
2633                 goto out;
2634         }
2635
2636         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
2637                 err = parse_ta_bin_descriptor(psp,
2638                                               &ta_hdr->ta_fw_bin[ta_index],
2639                                               ta_hdr);
2640                 if (err)
2641                         goto out;
2642         }
2643
2644         return 0;
2645 out:
2646         dev_err(adev->dev, "fail to initialize ta microcode\n");
2647         release_firmware(adev->psp.ta_fw);
2648         adev->psp.ta_fw = NULL;
2649         return err;
2650 }
2651
2652 static int psp_set_clockgating_state(void *handle,
2653                                      enum amd_clockgating_state state)
2654 {
2655         return 0;
2656 }
2657
2658 static int psp_set_powergating_state(void *handle,
2659                                      enum amd_powergating_state state)
2660 {
2661         return 0;
2662 }
2663
2664 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
2665                                          struct device_attribute *attr,
2666                                          char *buf)
2667 {
2668         struct drm_device *ddev = dev_get_drvdata(dev);
2669         struct amdgpu_device *adev = drm_to_adev(ddev);
2670         uint32_t fw_ver;
2671         int ret;
2672
2673         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2674                 DRM_INFO("PSP block is not ready yet.");
2675                 return -EBUSY;
2676         }
2677
2678         mutex_lock(&adev->psp.mutex);
2679         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
2680         mutex_unlock(&adev->psp.mutex);
2681
2682         if (ret) {
2683                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
2684                 return ret;
2685         }
2686
2687         return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver);
2688 }
2689
2690 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
2691                                                        struct device_attribute *attr,
2692                                                        const char *buf,
2693                                                        size_t count)
2694 {
2695         struct drm_device *ddev = dev_get_drvdata(dev);
2696         struct amdgpu_device *adev = drm_to_adev(ddev);
2697         void *cpu_addr;
2698         dma_addr_t dma_addr;
2699         int ret;
2700         char fw_name[100];
2701         const struct firmware *usbc_pd_fw;
2702
2703         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2704                 DRM_INFO("PSP block is not ready yet.");
2705                 return -EBUSY;
2706         }
2707
2708         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
2709         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
2710         if (ret)
2711                 goto fail;
2712
2713         /* We need contiguous physical mem to place the FW  for psp to access */
2714         cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
2715
2716         ret = dma_mapping_error(adev->dev, dma_addr);
2717         if (ret)
2718                 goto rel_buf;
2719
2720         memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
2721
2722         /*
2723          * x86 specific workaround.
2724          * Without it the buffer is invisible in PSP.
2725          *
2726          * TODO Remove once PSP starts snooping CPU cache
2727          */
2728 #ifdef CONFIG_X86
2729         clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
2730 #endif
2731
2732         mutex_lock(&adev->psp.mutex);
2733         ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
2734         mutex_unlock(&adev->psp.mutex);
2735
2736 rel_buf:
2737         dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
2738         release_firmware(usbc_pd_fw);
2739
2740 fail:
2741         if (ret) {
2742                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
2743                 return ret;
2744         }
2745
2746         return count;
2747 }
2748
2749 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
2750                    psp_usbc_pd_fw_sysfs_read,
2751                    psp_usbc_pd_fw_sysfs_write);
2752
2753
2754
2755 const struct amd_ip_funcs psp_ip_funcs = {
2756         .name = "psp",
2757         .early_init = psp_early_init,
2758         .late_init = NULL,
2759         .sw_init = psp_sw_init,
2760         .sw_fini = psp_sw_fini,
2761         .hw_init = psp_hw_init,
2762         .hw_fini = psp_hw_fini,
2763         .suspend = psp_suspend,
2764         .resume = psp_resume,
2765         .is_idle = NULL,
2766         .check_soft_reset = NULL,
2767         .wait_for_idle = NULL,
2768         .soft_reset = NULL,
2769         .set_clockgating_state = psp_set_clockgating_state,
2770         .set_powergating_state = psp_set_powergating_state,
2771 };
2772
2773 static int psp_sysfs_init(struct amdgpu_device *adev)
2774 {
2775         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
2776
2777         if (ret)
2778                 DRM_ERROR("Failed to create USBC PD FW control file!");
2779
2780         return ret;
2781 }
2782
2783 static void psp_sysfs_fini(struct amdgpu_device *adev)
2784 {
2785         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
2786 }
2787
2788 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
2789 {
2790         .type = AMD_IP_BLOCK_TYPE_PSP,
2791         .major = 3,
2792         .minor = 1,
2793         .rev = 0,
2794         .funcs = &psp_ip_funcs,
2795 };
2796
2797 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
2798 {
2799         .type = AMD_IP_BLOCK_TYPE_PSP,
2800         .major = 10,
2801         .minor = 0,
2802         .rev = 0,
2803         .funcs = &psp_ip_funcs,
2804 };
2805
2806 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
2807 {
2808         .type = AMD_IP_BLOCK_TYPE_PSP,
2809         .major = 11,
2810         .minor = 0,
2811         .rev = 0,
2812         .funcs = &psp_ip_funcs,
2813 };
2814
2815 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
2816 {
2817         .type = AMD_IP_BLOCK_TYPE_PSP,
2818         .major = 12,
2819         .minor = 0,
2820         .rev = 0,
2821         .funcs = &psp_ip_funcs,
2822 };