2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <linux/dma-mapping.h>
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "soc15_common.h"
34 #include "psp_v10_0.h"
35 #include "psp_v11_0.h"
36 #include "psp_v12_0.h"
38 #include "amdgpu_ras.h"
40 static int psp_sysfs_init(struct amdgpu_device *adev);
41 static void psp_sysfs_fini(struct amdgpu_device *adev);
43 static int psp_load_smu_fw(struct psp_context *psp);
46 * Due to DF Cstate management centralized to PMFW, the firmware
47 * loading sequence will be updated as below:
53 * - Load other non-psp fw
55 * - Load XGMI/RAS/HDCP/DTM TA if any
57 * This new sequence is required for
59 * - Navi12 and onwards
61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
63 struct amdgpu_device *adev = psp->adev;
65 psp->pmfw_centralized_cstate_management = false;
67 if (amdgpu_sriov_vf(adev))
70 if (adev->flags & AMD_IS_APU)
73 if ((adev->asic_type == CHIP_ARCTURUS) ||
74 (adev->asic_type >= CHIP_NAVI12))
75 psp->pmfw_centralized_cstate_management = true;
78 static int psp_early_init(void *handle)
80 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
81 struct psp_context *psp = &adev->psp;
83 switch (adev->asic_type) {
86 psp_v3_1_set_psp_funcs(psp);
87 psp->autoload_supported = false;
90 psp_v10_0_set_psp_funcs(psp);
91 psp->autoload_supported = false;
95 psp_v11_0_set_psp_funcs(psp);
96 psp->autoload_supported = false;
101 case CHIP_SIENNA_CICHLID:
102 case CHIP_NAVY_FLOUNDER:
104 case CHIP_DIMGREY_CAVEFISH:
105 psp_v11_0_set_psp_funcs(psp);
106 psp->autoload_supported = true;
109 psp_v12_0_set_psp_funcs(psp);
117 psp_check_pmfw_centralized_cstate_management(psp);
122 static void psp_memory_training_fini(struct psp_context *psp)
124 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
126 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
127 kfree(ctx->sys_cache);
128 ctx->sys_cache = NULL;
131 static int psp_memory_training_init(struct psp_context *psp)
134 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
136 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
137 DRM_DEBUG("memory training is not supported!\n");
141 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
142 if (ctx->sys_cache == NULL) {
143 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
148 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
149 ctx->train_data_size,
150 ctx->p2c_train_data_offset,
151 ctx->c2p_train_data_offset);
152 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
156 psp_memory_training_fini(psp);
160 static int psp_sw_init(void *handle)
162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
163 struct psp_context *psp = &adev->psp;
166 if (!amdgpu_sriov_vf(adev)) {
167 ret = psp_init_microcode(psp);
169 DRM_ERROR("Failed to load psp firmware!\n");
174 ret = psp_memory_training_init(psp);
176 DRM_ERROR("Failed to initialize memory training!\n");
179 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
181 DRM_ERROR("Failed to process memory training!\n");
185 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
186 ret= psp_sysfs_init(adev);
195 static int psp_sw_fini(void *handle)
197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
199 psp_memory_training_fini(&adev->psp);
200 if (adev->psp.sos_fw) {
201 release_firmware(adev->psp.sos_fw);
202 adev->psp.sos_fw = NULL;
204 if (adev->psp.asd_fw) {
205 release_firmware(adev->psp.asd_fw);
206 adev->psp.asd_fw = NULL;
208 if (adev->psp.ta_fw) {
209 release_firmware(adev->psp.ta_fw);
210 adev->psp.ta_fw = NULL;
213 if (adev->asic_type == CHIP_NAVI10 ||
214 adev->asic_type == CHIP_SIENNA_CICHLID)
215 psp_sysfs_fini(adev);
220 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
221 uint32_t reg_val, uint32_t mask, bool check_changed)
225 struct amdgpu_device *adev = psp->adev;
227 if (psp->adev->in_pci_err_recovery)
230 for (i = 0; i < adev->usec_timeout; i++) {
231 val = RREG32(reg_index);
236 if ((val & mask) == reg_val)
246 psp_cmd_submit_buf(struct psp_context *psp,
247 struct amdgpu_firmware_info *ucode,
248 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
253 bool ras_intr = false;
254 bool skip_unsupport = false;
256 if (psp->adev->in_pci_err_recovery)
259 mutex_lock(&psp->mutex);
261 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
263 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
265 index = atomic_inc_return(&psp->fence_value);
266 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
268 atomic_dec(&psp->fence_value);
269 mutex_unlock(&psp->mutex);
273 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
274 while (*((unsigned int *)psp->fence_buf) != index) {
278 * Shouldn't wait for timeout when err_event_athub occurs,
279 * because gpu reset thread triggered and lock resource should
280 * be released for psp resume sequence.
282 ras_intr = amdgpu_ras_intr_triggered();
286 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
289 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
290 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
291 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
293 /* In some cases, psp response status is not 0 even there is no
294 * problem while the command is submitted. Some version of PSP FW
295 * doesn't write 0 to that field.
296 * So here we would like to only print a warning instead of an error
297 * during psp initialization to avoid breaking hw_init and it doesn't
300 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
302 DRM_WARN("failed to load ucode id (%d) ",
304 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
305 psp->cmd_buf_mem->cmd_id,
306 psp->cmd_buf_mem->resp.status);
308 mutex_unlock(&psp->mutex);
313 /* get xGMI session id from response buffer */
314 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
317 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
318 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
320 mutex_unlock(&psp->mutex);
325 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
326 struct psp_gfx_cmd_resp *cmd,
327 uint64_t tmr_mc, uint32_t size)
329 if (amdgpu_sriov_vf(psp->adev))
330 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
332 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
333 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
334 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
335 cmd->cmd.cmd_setup_tmr.buf_size = size;
338 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
339 uint64_t pri_buf_mc, uint32_t size)
341 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
342 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
343 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
344 cmd->cmd.cmd_load_toc.toc_size = size;
347 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
348 static int psp_load_toc(struct psp_context *psp,
352 struct psp_gfx_cmd_resp *cmd;
354 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
357 /* Copy toc to psp firmware private buffer */
358 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
359 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
361 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
363 ret = psp_cmd_submit_buf(psp, NULL, cmd,
364 psp->fence_buf_mc_addr);
366 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
371 /* Set up Trusted Memory Region */
372 static int psp_tmr_init(struct psp_context *psp)
380 * According to HW engineer, they prefer the TMR address be "naturally
381 * aligned" , e.g. the start address be an integer divide of TMR size.
383 * Note: this memory need be reserved till the driver
386 tmr_size = PSP_TMR_SIZE;
388 /* For ASICs support RLC autoload, psp will parse the toc
389 * and calculate the total size of TMR needed */
390 if (!amdgpu_sriov_vf(psp->adev) &&
391 psp->toc_start_addr &&
394 ret = psp_load_toc(psp, &tmr_size);
396 DRM_ERROR("Failed to load toc\n");
401 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
402 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
403 AMDGPU_GEM_DOMAIN_VRAM,
404 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
409 static int psp_clear_vf_fw(struct psp_context *psp)
412 struct psp_gfx_cmd_resp *cmd;
414 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12)
417 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
421 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW;
423 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
429 static bool psp_skip_tmr(struct psp_context *psp)
431 switch (psp->adev->asic_type) {
433 case CHIP_SIENNA_CICHLID:
440 static int psp_tmr_load(struct psp_context *psp)
443 struct psp_gfx_cmd_resp *cmd;
445 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
446 * Already set up by host driver.
448 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
451 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
455 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
456 amdgpu_bo_size(psp->tmr_bo));
457 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
458 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
460 ret = psp_cmd_submit_buf(psp, NULL, cmd,
461 psp->fence_buf_mc_addr);
468 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
469 struct psp_gfx_cmd_resp *cmd)
471 if (amdgpu_sriov_vf(psp->adev))
472 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
474 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
477 static int psp_tmr_unload(struct psp_context *psp)
480 struct psp_gfx_cmd_resp *cmd;
482 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
486 psp_prep_tmr_unload_cmd_buf(psp, cmd);
487 DRM_INFO("free PSP TMR buffer\n");
489 ret = psp_cmd_submit_buf(psp, NULL, cmd,
490 psp->fence_buf_mc_addr);
497 static int psp_tmr_terminate(struct psp_context *psp)
503 ret = psp_tmr_unload(psp);
507 /* free TMR memory buffer */
508 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
509 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
514 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
515 uint64_t asd_mc, uint32_t size)
517 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
518 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
519 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
520 cmd->cmd.cmd_load_ta.app_len = size;
522 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
523 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
524 cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
527 static int psp_asd_load(struct psp_context *psp)
530 struct psp_gfx_cmd_resp *cmd;
532 /* If PSP version doesn't match ASD version, asd loading will be failed.
533 * add workaround to bypass it for sriov now.
534 * TODO: add version check to make it common
536 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)
539 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
543 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
544 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
546 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
547 psp->asd_ucode_size);
549 ret = psp_cmd_submit_buf(psp, NULL, cmd,
550 psp->fence_buf_mc_addr);
552 psp->asd_context.asd_initialized = true;
553 psp->asd_context.session_id = cmd->resp.session_id;
561 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
564 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
565 cmd->cmd.cmd_unload_ta.session_id = session_id;
568 static int psp_asd_unload(struct psp_context *psp)
571 struct psp_gfx_cmd_resp *cmd;
573 if (amdgpu_sriov_vf(psp->adev))
576 if (!psp->asd_context.asd_initialized)
579 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
583 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
585 ret = psp_cmd_submit_buf(psp, NULL, cmd,
586 psp->fence_buf_mc_addr);
588 psp->asd_context.asd_initialized = false;
595 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
596 uint32_t id, uint32_t value)
598 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
599 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
600 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
603 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
606 struct psp_gfx_cmd_resp *cmd = NULL;
609 if (reg >= PSP_REG_LAST)
612 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
616 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
617 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
623 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
625 uint32_t ta_bin_size,
626 uint64_t ta_shared_mc,
627 uint32_t ta_shared_size)
629 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
630 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
631 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
632 cmd->cmd.cmd_load_ta.app_len = ta_bin_size;
634 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
635 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
636 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size;
639 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
644 * Allocate 16k memory aligned to 4k from Frame Buffer (local
645 * physical) for xgmi ta <-> Driver
647 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
648 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
649 &psp->xgmi_context.xgmi_shared_bo,
650 &psp->xgmi_context.xgmi_shared_mc_addr,
651 &psp->xgmi_context.xgmi_shared_buf);
656 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
660 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
661 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
662 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
665 static int psp_ta_invoke(struct psp_context *psp,
670 struct psp_gfx_cmd_resp *cmd;
672 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
676 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
678 ret = psp_cmd_submit_buf(psp, NULL, cmd,
679 psp->fence_buf_mc_addr);
686 static int psp_xgmi_load(struct psp_context *psp)
689 struct psp_gfx_cmd_resp *cmd;
692 * TODO: bypass the loading in sriov for now
695 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
699 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
700 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
702 psp_prep_ta_load_cmd_buf(cmd,
704 psp->ta_xgmi_ucode_size,
705 psp->xgmi_context.xgmi_shared_mc_addr,
706 PSP_XGMI_SHARED_MEM_SIZE);
708 ret = psp_cmd_submit_buf(psp, NULL, cmd,
709 psp->fence_buf_mc_addr);
712 psp->xgmi_context.initialized = 1;
713 psp->xgmi_context.session_id = cmd->resp.session_id;
721 static int psp_xgmi_unload(struct psp_context *psp)
724 struct psp_gfx_cmd_resp *cmd;
725 struct amdgpu_device *adev = psp->adev;
727 /* XGMI TA unload currently is not supported on Arcturus */
728 if (adev->asic_type == CHIP_ARCTURUS)
732 * TODO: bypass the unloading in sriov for now
735 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
739 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
741 ret = psp_cmd_submit_buf(psp, NULL, cmd,
742 psp->fence_buf_mc_addr);
749 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
751 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
754 int psp_xgmi_terminate(struct psp_context *psp)
758 if (!psp->xgmi_context.initialized)
761 ret = psp_xgmi_unload(psp);
765 psp->xgmi_context.initialized = 0;
767 /* free xgmi shared memory */
768 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
769 &psp->xgmi_context.xgmi_shared_mc_addr,
770 &psp->xgmi_context.xgmi_shared_buf);
775 int psp_xgmi_initialize(struct psp_context *psp)
777 struct ta_xgmi_shared_memory *xgmi_cmd;
780 if (!psp->adev->psp.ta_fw ||
781 !psp->adev->psp.ta_xgmi_ucode_size ||
782 !psp->adev->psp.ta_xgmi_start_addr)
785 if (!psp->xgmi_context.initialized) {
786 ret = psp_xgmi_init_shared_buf(psp);
792 ret = psp_xgmi_load(psp);
796 /* Initialize XGMI session */
797 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
798 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
799 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
801 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
806 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
808 struct ta_xgmi_shared_memory *xgmi_cmd;
811 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
812 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
814 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
816 /* Invoke xgmi ta to get hive id */
817 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
821 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
826 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
828 struct ta_xgmi_shared_memory *xgmi_cmd;
831 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
832 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
834 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
836 /* Invoke xgmi ta to get the node id */
837 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
841 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
846 int psp_xgmi_get_topology_info(struct psp_context *psp,
848 struct psp_xgmi_topology_info *topology)
850 struct ta_xgmi_shared_memory *xgmi_cmd;
851 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
852 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
856 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
859 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
860 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
862 /* Fill in the shared memory with topology information as input */
863 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
864 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
865 topology_info_input->num_nodes = number_devices;
867 for (i = 0; i < topology_info_input->num_nodes; i++) {
868 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
869 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
870 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
871 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
874 /* Invoke xgmi ta to get the topology information */
875 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
879 /* Read the output topology information from the shared memory */
880 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
881 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
882 for (i = 0; i < topology->num_nodes; i++) {
883 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
884 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
885 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
886 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
892 int psp_xgmi_set_topology_info(struct psp_context *psp,
894 struct psp_xgmi_topology_info *topology)
896 struct ta_xgmi_shared_memory *xgmi_cmd;
897 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
900 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
903 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
904 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
906 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
907 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
908 topology_info_input->num_nodes = number_devices;
910 for (i = 0; i < topology_info_input->num_nodes; i++) {
911 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
912 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
913 topology_info_input->nodes[i].is_sharing_enabled = 1;
914 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
917 /* Invoke xgmi ta to set topology information */
918 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
922 static int psp_ras_init_shared_buf(struct psp_context *psp)
927 * Allocate 16k memory aligned to 4k from Frame Buffer (local
928 * physical) for ras ta <-> Driver
930 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
931 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
932 &psp->ras.ras_shared_bo,
933 &psp->ras.ras_shared_mc_addr,
934 &psp->ras.ras_shared_buf);
939 static int psp_ras_load(struct psp_context *psp)
942 struct psp_gfx_cmd_resp *cmd;
943 struct ta_ras_shared_memory *ras_cmd;
946 * TODO: bypass the loading in sriov for now
948 if (amdgpu_sriov_vf(psp->adev))
951 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
955 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
956 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
958 psp_prep_ta_load_cmd_buf(cmd,
960 psp->ta_ras_ucode_size,
961 psp->ras.ras_shared_mc_addr,
962 PSP_RAS_SHARED_MEM_SIZE);
964 ret = psp_cmd_submit_buf(psp, NULL, cmd,
965 psp->fence_buf_mc_addr);
967 ras_cmd = (struct ta_ras_shared_memory*)psp->ras.ras_shared_buf;
970 psp->ras.session_id = cmd->resp.session_id;
972 if (!ras_cmd->ras_status)
973 psp->ras.ras_initialized = true;
975 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
978 if (ret || ras_cmd->ras_status)
979 amdgpu_ras_fini(psp->adev);
986 static int psp_ras_unload(struct psp_context *psp)
989 struct psp_gfx_cmd_resp *cmd;
992 * TODO: bypass the unloading in sriov for now
994 if (amdgpu_sriov_vf(psp->adev))
997 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1001 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
1003 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1004 psp->fence_buf_mc_addr);
1011 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1013 struct ta_ras_shared_memory *ras_cmd;
1016 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1019 * TODO: bypass the loading in sriov for now
1021 if (amdgpu_sriov_vf(psp->adev))
1024 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1026 if (amdgpu_ras_intr_triggered())
1029 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1031 DRM_WARN("RAS: Unsupported Interface");
1036 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1037 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1039 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1041 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1042 dev_warn(psp->adev->dev,
1043 "RAS internal register access blocked\n");
1049 int psp_ras_enable_features(struct psp_context *psp,
1050 union ta_ras_cmd_input *info, bool enable)
1052 struct ta_ras_shared_memory *ras_cmd;
1055 if (!psp->ras.ras_initialized)
1058 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1059 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1062 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1064 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1066 ras_cmd->ras_in_message = *info;
1068 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1072 return ras_cmd->ras_status;
1075 static int psp_ras_terminate(struct psp_context *psp)
1080 * TODO: bypass the terminate in sriov for now
1082 if (amdgpu_sriov_vf(psp->adev))
1085 if (!psp->ras.ras_initialized)
1088 ret = psp_ras_unload(psp);
1092 psp->ras.ras_initialized = false;
1094 /* free ras shared memory */
1095 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1096 &psp->ras.ras_shared_mc_addr,
1097 &psp->ras.ras_shared_buf);
1102 static int psp_ras_initialize(struct psp_context *psp)
1107 * TODO: bypass the initialize in sriov for now
1109 if (amdgpu_sriov_vf(psp->adev))
1112 if (!psp->adev->psp.ta_ras_ucode_size ||
1113 !psp->adev->psp.ta_ras_start_addr) {
1114 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
1118 if (!psp->ras.ras_initialized) {
1119 ret = psp_ras_init_shared_buf(psp);
1124 ret = psp_ras_load(psp);
1131 int psp_ras_trigger_error(struct psp_context *psp,
1132 struct ta_ras_trigger_error_input *info)
1134 struct ta_ras_shared_memory *ras_cmd;
1137 if (!psp->ras.ras_initialized)
1140 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1141 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1143 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1144 ras_cmd->ras_in_message.trigger_error = *info;
1146 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1150 /* If err_event_athub occurs error inject was successful, however
1151 return status from TA is no long reliable */
1152 if (amdgpu_ras_intr_triggered())
1155 return ras_cmd->ras_status;
1160 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1165 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1166 * physical) for hdcp ta <-> Driver
1168 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1169 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1170 &psp->hdcp_context.hdcp_shared_bo,
1171 &psp->hdcp_context.hdcp_shared_mc_addr,
1172 &psp->hdcp_context.hdcp_shared_buf);
1177 static int psp_hdcp_load(struct psp_context *psp)
1180 struct psp_gfx_cmd_resp *cmd;
1183 * TODO: bypass the loading in sriov for now
1185 if (amdgpu_sriov_vf(psp->adev))
1188 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1192 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1193 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
1194 psp->ta_hdcp_ucode_size);
1196 psp_prep_ta_load_cmd_buf(cmd,
1197 psp->fw_pri_mc_addr,
1198 psp->ta_hdcp_ucode_size,
1199 psp->hdcp_context.hdcp_shared_mc_addr,
1200 PSP_HDCP_SHARED_MEM_SIZE);
1202 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1205 psp->hdcp_context.hdcp_initialized = true;
1206 psp->hdcp_context.session_id = cmd->resp.session_id;
1207 mutex_init(&psp->hdcp_context.mutex);
1214 static int psp_hdcp_initialize(struct psp_context *psp)
1219 * TODO: bypass the initialize in sriov for now
1221 if (amdgpu_sriov_vf(psp->adev))
1224 if (!psp->adev->psp.ta_hdcp_ucode_size ||
1225 !psp->adev->psp.ta_hdcp_start_addr) {
1226 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1230 if (!psp->hdcp_context.hdcp_initialized) {
1231 ret = psp_hdcp_init_shared_buf(psp);
1236 ret = psp_hdcp_load(psp);
1243 static int psp_hdcp_unload(struct psp_context *psp)
1246 struct psp_gfx_cmd_resp *cmd;
1249 * TODO: bypass the unloading in sriov for now
1251 if (amdgpu_sriov_vf(psp->adev))
1254 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1258 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1260 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1267 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1270 * TODO: bypass the loading in sriov for now
1272 if (amdgpu_sriov_vf(psp->adev))
1275 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1278 static int psp_hdcp_terminate(struct psp_context *psp)
1283 * TODO: bypass the terminate in sriov for now
1285 if (amdgpu_sriov_vf(psp->adev))
1288 if (!psp->hdcp_context.hdcp_initialized)
1291 ret = psp_hdcp_unload(psp);
1295 psp->hdcp_context.hdcp_initialized = false;
1297 /* free hdcp shared memory */
1298 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1299 &psp->hdcp_context.hdcp_shared_mc_addr,
1300 &psp->hdcp_context.hdcp_shared_buf);
1307 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1312 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1313 * physical) for dtm ta <-> Driver
1315 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1316 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1317 &psp->dtm_context.dtm_shared_bo,
1318 &psp->dtm_context.dtm_shared_mc_addr,
1319 &psp->dtm_context.dtm_shared_buf);
1324 static int psp_dtm_load(struct psp_context *psp)
1327 struct psp_gfx_cmd_resp *cmd;
1330 * TODO: bypass the loading in sriov for now
1332 if (amdgpu_sriov_vf(psp->adev))
1335 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1339 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1340 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1342 psp_prep_ta_load_cmd_buf(cmd,
1343 psp->fw_pri_mc_addr,
1344 psp->ta_dtm_ucode_size,
1345 psp->dtm_context.dtm_shared_mc_addr,
1346 PSP_DTM_SHARED_MEM_SIZE);
1348 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1351 psp->dtm_context.dtm_initialized = true;
1352 psp->dtm_context.session_id = cmd->resp.session_id;
1353 mutex_init(&psp->dtm_context.mutex);
1361 static int psp_dtm_initialize(struct psp_context *psp)
1366 * TODO: bypass the initialize in sriov for now
1368 if (amdgpu_sriov_vf(psp->adev))
1371 if (!psp->adev->psp.ta_dtm_ucode_size ||
1372 !psp->adev->psp.ta_dtm_start_addr) {
1373 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1377 if (!psp->dtm_context.dtm_initialized) {
1378 ret = psp_dtm_init_shared_buf(psp);
1383 ret = psp_dtm_load(psp);
1390 static int psp_dtm_unload(struct psp_context *psp)
1393 struct psp_gfx_cmd_resp *cmd;
1396 * TODO: bypass the unloading in sriov for now
1398 if (amdgpu_sriov_vf(psp->adev))
1401 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1405 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1407 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1414 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1417 * TODO: bypass the loading in sriov for now
1419 if (amdgpu_sriov_vf(psp->adev))
1422 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1425 static int psp_dtm_terminate(struct psp_context *psp)
1430 * TODO: bypass the terminate in sriov for now
1432 if (amdgpu_sriov_vf(psp->adev))
1435 if (!psp->dtm_context.dtm_initialized)
1438 ret = psp_dtm_unload(psp);
1442 psp->dtm_context.dtm_initialized = false;
1444 /* free hdcp shared memory */
1445 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1446 &psp->dtm_context.dtm_shared_mc_addr,
1447 &psp->dtm_context.dtm_shared_buf);
1454 static int psp_rap_init_shared_buf(struct psp_context *psp)
1459 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1460 * physical) for rap ta <-> Driver
1462 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1463 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1464 &psp->rap_context.rap_shared_bo,
1465 &psp->rap_context.rap_shared_mc_addr,
1466 &psp->rap_context.rap_shared_buf);
1471 static int psp_rap_load(struct psp_context *psp)
1474 struct psp_gfx_cmd_resp *cmd;
1476 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1480 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1481 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1483 psp_prep_ta_load_cmd_buf(cmd,
1484 psp->fw_pri_mc_addr,
1485 psp->ta_rap_ucode_size,
1486 psp->rap_context.rap_shared_mc_addr,
1487 PSP_RAP_SHARED_MEM_SIZE);
1489 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1492 psp->rap_context.rap_initialized = true;
1493 psp->rap_context.session_id = cmd->resp.session_id;
1494 mutex_init(&psp->rap_context.mutex);
1502 static int psp_rap_unload(struct psp_context *psp)
1505 struct psp_gfx_cmd_resp *cmd;
1507 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1511 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1513 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1520 static int psp_rap_initialize(struct psp_context *psp)
1525 * TODO: bypass the initialize in sriov for now
1527 if (amdgpu_sriov_vf(psp->adev))
1530 if (!psp->adev->psp.ta_rap_ucode_size ||
1531 !psp->adev->psp.ta_rap_start_addr) {
1532 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1536 if (!psp->rap_context.rap_initialized) {
1537 ret = psp_rap_init_shared_buf(psp);
1542 ret = psp_rap_load(psp);
1546 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE);
1547 if (ret != TA_RAP_STATUS__SUCCESS) {
1548 psp_rap_unload(psp);
1550 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1551 &psp->rap_context.rap_shared_mc_addr,
1552 &psp->rap_context.rap_shared_buf);
1554 psp->rap_context.rap_initialized = false;
1556 dev_warn(psp->adev->dev, "RAP TA initialize fail.\n");
1563 static int psp_rap_terminate(struct psp_context *psp)
1567 if (!psp->rap_context.rap_initialized)
1570 ret = psp_rap_unload(psp);
1572 psp->rap_context.rap_initialized = false;
1574 /* free rap shared memory */
1575 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1576 &psp->rap_context.rap_shared_mc_addr,
1577 &psp->rap_context.rap_shared_buf);
1582 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1584 struct ta_rap_shared_memory *rap_cmd;
1587 if (!psp->rap_context.rap_initialized)
1590 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1591 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1594 mutex_lock(&psp->rap_context.mutex);
1596 rap_cmd = (struct ta_rap_shared_memory *)
1597 psp->rap_context.rap_shared_buf;
1598 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1600 rap_cmd->cmd_id = ta_cmd_id;
1601 rap_cmd->validation_method_id = METHOD_A;
1603 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1605 mutex_unlock(&psp->rap_context.mutex);
1609 mutex_unlock(&psp->rap_context.mutex);
1611 return rap_cmd->rap_status;
1615 static int psp_hw_start(struct psp_context *psp)
1617 struct amdgpu_device *adev = psp->adev;
1620 if (!amdgpu_sriov_vf(adev)) {
1621 if (psp->kdb_bin_size &&
1622 (psp->funcs->bootloader_load_kdb != NULL)) {
1623 ret = psp_bootloader_load_kdb(psp);
1625 DRM_ERROR("PSP load kdb failed!\n");
1630 if (psp->spl_bin_size) {
1631 ret = psp_bootloader_load_spl(psp);
1633 DRM_ERROR("PSP load spl failed!\n");
1638 ret = psp_bootloader_load_sysdrv(psp);
1640 DRM_ERROR("PSP load sysdrv failed!\n");
1644 ret = psp_bootloader_load_sos(psp);
1646 DRM_ERROR("PSP load sos failed!\n");
1651 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1653 DRM_ERROR("PSP create ring failed!\n");
1657 ret = psp_clear_vf_fw(psp);
1659 DRM_ERROR("PSP clear vf fw!\n");
1663 ret = psp_tmr_init(psp);
1665 DRM_ERROR("PSP tmr init failed!\n");
1670 * For ASICs with DF Cstate management centralized
1671 * to PMFW, TMR setup should be performed after PMFW
1672 * loaded and before other non-psp firmware loaded.
1674 if (psp->pmfw_centralized_cstate_management) {
1675 ret = psp_load_smu_fw(psp);
1680 ret = psp_tmr_load(psp);
1682 DRM_ERROR("PSP load tmr failed!\n");
1689 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1690 enum psp_gfx_fw_type *type)
1692 switch (ucode->ucode_id) {
1693 case AMDGPU_UCODE_ID_SDMA0:
1694 *type = GFX_FW_TYPE_SDMA0;
1696 case AMDGPU_UCODE_ID_SDMA1:
1697 *type = GFX_FW_TYPE_SDMA1;
1699 case AMDGPU_UCODE_ID_SDMA2:
1700 *type = GFX_FW_TYPE_SDMA2;
1702 case AMDGPU_UCODE_ID_SDMA3:
1703 *type = GFX_FW_TYPE_SDMA3;
1705 case AMDGPU_UCODE_ID_SDMA4:
1706 *type = GFX_FW_TYPE_SDMA4;
1708 case AMDGPU_UCODE_ID_SDMA5:
1709 *type = GFX_FW_TYPE_SDMA5;
1711 case AMDGPU_UCODE_ID_SDMA6:
1712 *type = GFX_FW_TYPE_SDMA6;
1714 case AMDGPU_UCODE_ID_SDMA7:
1715 *type = GFX_FW_TYPE_SDMA7;
1717 case AMDGPU_UCODE_ID_CP_MES:
1718 *type = GFX_FW_TYPE_CP_MES;
1720 case AMDGPU_UCODE_ID_CP_MES_DATA:
1721 *type = GFX_FW_TYPE_MES_STACK;
1723 case AMDGPU_UCODE_ID_CP_CE:
1724 *type = GFX_FW_TYPE_CP_CE;
1726 case AMDGPU_UCODE_ID_CP_PFP:
1727 *type = GFX_FW_TYPE_CP_PFP;
1729 case AMDGPU_UCODE_ID_CP_ME:
1730 *type = GFX_FW_TYPE_CP_ME;
1732 case AMDGPU_UCODE_ID_CP_MEC1:
1733 *type = GFX_FW_TYPE_CP_MEC;
1735 case AMDGPU_UCODE_ID_CP_MEC1_JT:
1736 *type = GFX_FW_TYPE_CP_MEC_ME1;
1738 case AMDGPU_UCODE_ID_CP_MEC2:
1739 *type = GFX_FW_TYPE_CP_MEC;
1741 case AMDGPU_UCODE_ID_CP_MEC2_JT:
1742 *type = GFX_FW_TYPE_CP_MEC_ME2;
1744 case AMDGPU_UCODE_ID_RLC_G:
1745 *type = GFX_FW_TYPE_RLC_G;
1747 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1748 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
1750 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
1751 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
1753 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
1754 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
1756 case AMDGPU_UCODE_ID_RLC_IRAM:
1757 *type = GFX_FW_TYPE_RLC_IRAM;
1759 case AMDGPU_UCODE_ID_RLC_DRAM:
1760 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
1762 case AMDGPU_UCODE_ID_SMC:
1763 *type = GFX_FW_TYPE_SMU;
1765 case AMDGPU_UCODE_ID_UVD:
1766 *type = GFX_FW_TYPE_UVD;
1768 case AMDGPU_UCODE_ID_UVD1:
1769 *type = GFX_FW_TYPE_UVD1;
1771 case AMDGPU_UCODE_ID_VCE:
1772 *type = GFX_FW_TYPE_VCE;
1774 case AMDGPU_UCODE_ID_VCN:
1775 *type = GFX_FW_TYPE_VCN;
1777 case AMDGPU_UCODE_ID_VCN1:
1778 *type = GFX_FW_TYPE_VCN1;
1780 case AMDGPU_UCODE_ID_DMCU_ERAM:
1781 *type = GFX_FW_TYPE_DMCU_ERAM;
1783 case AMDGPU_UCODE_ID_DMCU_INTV:
1784 *type = GFX_FW_TYPE_DMCU_ISR;
1786 case AMDGPU_UCODE_ID_VCN0_RAM:
1787 *type = GFX_FW_TYPE_VCN0_RAM;
1789 case AMDGPU_UCODE_ID_VCN1_RAM:
1790 *type = GFX_FW_TYPE_VCN1_RAM;
1792 case AMDGPU_UCODE_ID_DMCUB:
1793 *type = GFX_FW_TYPE_DMUB;
1795 case AMDGPU_UCODE_ID_MAXIMUM:
1803 static void psp_print_fw_hdr(struct psp_context *psp,
1804 struct amdgpu_firmware_info *ucode)
1806 struct amdgpu_device *adev = psp->adev;
1807 struct common_firmware_header *hdr;
1809 switch (ucode->ucode_id) {
1810 case AMDGPU_UCODE_ID_SDMA0:
1811 case AMDGPU_UCODE_ID_SDMA1:
1812 case AMDGPU_UCODE_ID_SDMA2:
1813 case AMDGPU_UCODE_ID_SDMA3:
1814 case AMDGPU_UCODE_ID_SDMA4:
1815 case AMDGPU_UCODE_ID_SDMA5:
1816 case AMDGPU_UCODE_ID_SDMA6:
1817 case AMDGPU_UCODE_ID_SDMA7:
1818 hdr = (struct common_firmware_header *)
1819 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1820 amdgpu_ucode_print_sdma_hdr(hdr);
1822 case AMDGPU_UCODE_ID_CP_CE:
1823 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1824 amdgpu_ucode_print_gfx_hdr(hdr);
1826 case AMDGPU_UCODE_ID_CP_PFP:
1827 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1828 amdgpu_ucode_print_gfx_hdr(hdr);
1830 case AMDGPU_UCODE_ID_CP_ME:
1831 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1832 amdgpu_ucode_print_gfx_hdr(hdr);
1834 case AMDGPU_UCODE_ID_CP_MEC1:
1835 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1836 amdgpu_ucode_print_gfx_hdr(hdr);
1838 case AMDGPU_UCODE_ID_RLC_G:
1839 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1840 amdgpu_ucode_print_rlc_hdr(hdr);
1842 case AMDGPU_UCODE_ID_SMC:
1843 hdr = (struct common_firmware_header *)adev->pm.fw->data;
1844 amdgpu_ucode_print_smc_hdr(hdr);
1851 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1852 struct psp_gfx_cmd_resp *cmd)
1855 uint64_t fw_mem_mc_addr = ucode->mc_addr;
1857 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1859 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1860 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1861 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1862 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1864 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1866 DRM_ERROR("Unknown firmware type\n");
1871 static int psp_execute_np_fw_load(struct psp_context *psp,
1872 struct amdgpu_firmware_info *ucode)
1876 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1880 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1881 psp->fence_buf_mc_addr);
1886 static int psp_load_smu_fw(struct psp_context *psp)
1889 struct amdgpu_device* adev = psp->adev;
1890 struct amdgpu_firmware_info *ucode =
1891 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1892 struct amdgpu_ras *ras = psp->ras.ras;
1894 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
1898 if (amdgpu_in_reset(adev) && ras && ras->supported) {
1899 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
1901 DRM_WARN("Failed to set MP1 state prepare for reload\n");
1905 ret = psp_execute_np_fw_load(psp, ucode);
1908 DRM_ERROR("PSP load smu failed!\n");
1913 static bool fw_load_skip_check(struct psp_context *psp,
1914 struct amdgpu_firmware_info *ucode)
1919 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1920 (psp_smu_reload_quirk(psp) ||
1921 psp->autoload_supported ||
1922 psp->pmfw_centralized_cstate_management))
1925 if (amdgpu_sriov_vf(psp->adev) &&
1926 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1927 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1928 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1929 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1930 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1931 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1932 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1933 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1934 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
1935 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
1936 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
1937 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
1938 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
1939 /*skip ucode loading in SRIOV VF */
1942 if (psp->autoload_supported &&
1943 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1944 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1945 /* skip mec JT when autoload is enabled */
1951 static int psp_np_fw_load(struct psp_context *psp)
1954 struct amdgpu_firmware_info *ucode;
1955 struct amdgpu_device* adev = psp->adev;
1957 if (psp->autoload_supported &&
1958 !psp->pmfw_centralized_cstate_management) {
1959 ret = psp_load_smu_fw(psp);
1964 for (i = 0; i < adev->firmware.max_ucodes; i++) {
1965 ucode = &adev->firmware.ucode[i];
1967 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1968 !fw_load_skip_check(psp, ucode)) {
1969 ret = psp_load_smu_fw(psp);
1975 if (fw_load_skip_check(psp, ucode))
1978 if (psp->autoload_supported &&
1979 (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1980 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
1981 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
1982 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
1983 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
1984 /* PSP only receive one SDMA fw for sienna_cichlid,
1985 * as all four sdma fw are same */
1988 psp_print_fw_hdr(psp, ucode);
1990 ret = psp_execute_np_fw_load(psp, ucode);
1994 /* Start rlc autoload after psp recieved all the gfx firmware */
1995 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1996 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1997 ret = psp_rlc_autoload_start(psp);
1999 DRM_ERROR("Failed to start rlc autoload\n");
2008 static int psp_load_fw(struct amdgpu_device *adev)
2011 struct psp_context *psp = &adev->psp;
2013 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2014 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2018 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2022 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2023 AMDGPU_GEM_DOMAIN_GTT,
2025 &psp->fw_pri_mc_addr,
2030 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2031 AMDGPU_GEM_DOMAIN_VRAM,
2033 &psp->fence_buf_mc_addr,
2038 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2039 AMDGPU_GEM_DOMAIN_VRAM,
2040 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2041 (void **)&psp->cmd_buf_mem);
2045 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2047 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2049 DRM_ERROR("PSP ring init failed!\n");
2054 ret = psp_hw_start(psp);
2058 ret = psp_np_fw_load(psp);
2062 ret = psp_asd_load(psp);
2064 DRM_ERROR("PSP load asd failed!\n");
2068 if (psp->adev->psp.ta_fw) {
2069 ret = psp_ras_initialize(psp);
2071 dev_err(psp->adev->dev,
2072 "RAS: Failed to initialize RAS\n");
2074 ret = psp_hdcp_initialize(psp);
2076 dev_err(psp->adev->dev,
2077 "HDCP: Failed to initialize HDCP\n");
2079 ret = psp_dtm_initialize(psp);
2081 dev_err(psp->adev->dev,
2082 "DTM: Failed to initialize DTM\n");
2084 ret = psp_rap_initialize(psp);
2086 dev_err(psp->adev->dev,
2087 "RAP: Failed to initialize RAP\n");
2094 * all cleanup jobs (xgmi terminate, ras terminate,
2095 * ring destroy, cmd/fence/fw buffers destory,
2096 * psp->cmd destory) are delayed to psp_hw_fini
2101 static int psp_hw_init(void *handle)
2104 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2106 mutex_lock(&adev->firmware.mutex);
2108 * This sequence is just used on hw_init only once, no need on
2111 ret = amdgpu_ucode_init_bo(adev);
2115 ret = psp_load_fw(adev);
2117 DRM_ERROR("PSP firmware loading failed\n");
2121 mutex_unlock(&adev->firmware.mutex);
2125 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2126 mutex_unlock(&adev->firmware.mutex);
2130 static int psp_hw_fini(void *handle)
2132 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2133 struct psp_context *psp = &adev->psp;
2136 if (psp->adev->psp.ta_fw) {
2137 psp_ras_terminate(psp);
2138 psp_rap_terminate(psp);
2139 psp_dtm_terminate(psp);
2140 psp_hdcp_terminate(psp);
2143 psp_asd_unload(psp);
2144 ret = psp_clear_vf_fw(psp);
2146 DRM_ERROR("PSP clear vf fw!\n");
2150 psp_tmr_terminate(psp);
2151 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2153 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2154 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2155 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2156 &psp->fence_buf_mc_addr, &psp->fence_buf);
2157 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2158 (void **)&psp->cmd_buf_mem);
2166 static int psp_suspend(void *handle)
2169 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2170 struct psp_context *psp = &adev->psp;
2172 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2173 psp->xgmi_context.initialized == 1) {
2174 ret = psp_xgmi_terminate(psp);
2176 DRM_ERROR("Failed to terminate xgmi ta\n");
2181 if (psp->adev->psp.ta_fw) {
2182 ret = psp_ras_terminate(psp);
2184 DRM_ERROR("Failed to terminate ras ta\n");
2187 ret = psp_hdcp_terminate(psp);
2189 DRM_ERROR("Failed to terminate hdcp ta\n");
2192 ret = psp_dtm_terminate(psp);
2194 DRM_ERROR("Failed to terminate dtm ta\n");
2197 ret = psp_rap_terminate(psp);
2199 DRM_ERROR("Failed to terminate rap ta\n");
2204 ret = psp_asd_unload(psp);
2206 DRM_ERROR("Failed to unload asd\n");
2210 ret = psp_tmr_terminate(psp);
2212 DRM_ERROR("Failed to terminate tmr\n");
2216 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2218 DRM_ERROR("PSP ring stop failed\n");
2225 static int psp_resume(void *handle)
2228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2229 struct psp_context *psp = &adev->psp;
2231 DRM_INFO("PSP is resuming...\n");
2233 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2235 DRM_ERROR("Failed to process memory training!\n");
2239 mutex_lock(&adev->firmware.mutex);
2241 ret = psp_hw_start(psp);
2245 ret = psp_np_fw_load(psp);
2249 ret = psp_asd_load(psp);
2251 DRM_ERROR("PSP load asd failed!\n");
2255 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2256 ret = psp_xgmi_initialize(psp);
2257 /* Warning the XGMI seesion initialize failure
2258 * Instead of stop driver initialization
2261 dev_err(psp->adev->dev,
2262 "XGMI: Failed to initialize XGMI session\n");
2265 if (psp->adev->psp.ta_fw) {
2266 ret = psp_ras_initialize(psp);
2268 dev_err(psp->adev->dev,
2269 "RAS: Failed to initialize RAS\n");
2271 ret = psp_hdcp_initialize(psp);
2273 dev_err(psp->adev->dev,
2274 "HDCP: Failed to initialize HDCP\n");
2276 ret = psp_dtm_initialize(psp);
2278 dev_err(psp->adev->dev,
2279 "DTM: Failed to initialize DTM\n");
2281 ret = psp_rap_initialize(psp);
2283 dev_err(psp->adev->dev,
2284 "RAP: Failed to initialize RAP\n");
2287 mutex_unlock(&adev->firmware.mutex);
2292 DRM_ERROR("PSP resume failed\n");
2293 mutex_unlock(&adev->firmware.mutex);
2297 int psp_gpu_reset(struct amdgpu_device *adev)
2301 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2304 mutex_lock(&adev->psp.mutex);
2305 ret = psp_mode1_reset(&adev->psp);
2306 mutex_unlock(&adev->psp.mutex);
2311 int psp_rlc_autoload_start(struct psp_context *psp)
2314 struct psp_gfx_cmd_resp *cmd;
2316 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2320 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2322 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2323 psp->fence_buf_mc_addr);
2328 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2329 uint64_t cmd_gpu_addr, int cmd_size)
2331 struct amdgpu_firmware_info ucode = {0};
2333 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2334 AMDGPU_UCODE_ID_VCN0_RAM;
2335 ucode.mc_addr = cmd_gpu_addr;
2336 ucode.ucode_size = cmd_size;
2338 return psp_execute_np_fw_load(&adev->psp, &ucode);
2341 int psp_ring_cmd_submit(struct psp_context *psp,
2342 uint64_t cmd_buf_mc_addr,
2343 uint64_t fence_mc_addr,
2346 unsigned int psp_write_ptr_reg = 0;
2347 struct psp_gfx_rb_frame *write_frame;
2348 struct psp_ring *ring = &psp->km_ring;
2349 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2350 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2351 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2352 struct amdgpu_device *adev = psp->adev;
2353 uint32_t ring_size_dw = ring->ring_size / 4;
2354 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2356 /* KM (GPCOM) prepare write pointer */
2357 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2359 /* Update KM RB frame pointer to new frame */
2360 /* write_frame ptr increments by size of rb_frame in bytes */
2361 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2362 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2363 write_frame = ring_buffer_start;
2365 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2366 /* Check invalid write_frame ptr address */
2367 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2368 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2369 ring_buffer_start, ring_buffer_end, write_frame);
2370 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2374 /* Initialize KM RB frame */
2375 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2377 /* Update KM RB frame */
2378 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2379 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2380 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2381 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2382 write_frame->fence_value = index;
2383 amdgpu_asic_flush_hdp(adev, NULL);
2385 /* Update the write Pointer in DWORDs */
2386 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2387 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2391 int psp_init_asd_microcode(struct psp_context *psp,
2392 const char *chip_name)
2394 struct amdgpu_device *adev = psp->adev;
2395 char fw_name[PSP_FW_NAME_LEN];
2396 const struct psp_firmware_header_v1_0 *asd_hdr;
2400 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2404 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2405 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2409 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2413 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2414 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2415 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
2416 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2417 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2418 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2421 dev_err(adev->dev, "fail to initialize asd microcode\n");
2422 release_firmware(adev->psp.asd_fw);
2423 adev->psp.asd_fw = NULL;
2427 int psp_init_toc_microcode(struct psp_context *psp,
2428 const char *chip_name)
2430 struct amdgpu_device *adev = psp->adev;
2432 const struct psp_firmware_header_v1_0 *toc_hdr;
2436 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2440 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2441 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2445 err = amdgpu_ucode_validate(adev->psp.toc_fw);
2449 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2450 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2451 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
2452 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2453 adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2454 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2457 dev_err(adev->dev, "fail to request/validate toc microcode\n");
2458 release_firmware(adev->psp.toc_fw);
2459 adev->psp.toc_fw = NULL;
2463 int psp_init_sos_microcode(struct psp_context *psp,
2464 const char *chip_name)
2466 struct amdgpu_device *adev = psp->adev;
2467 char fw_name[PSP_FW_NAME_LEN];
2468 const struct psp_firmware_header_v1_0 *sos_hdr;
2469 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2470 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2471 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2475 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2479 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2480 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2484 err = amdgpu_ucode_validate(adev->psp.sos_fw);
2488 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2489 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2491 switch (sos_hdr->header.header_version_major) {
2493 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2494 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
2495 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
2496 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
2497 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2498 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2499 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2500 le32_to_cpu(sos_hdr->sos_offset_bytes);
2501 if (sos_hdr->header.header_version_minor == 1) {
2502 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2503 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
2504 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2505 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
2506 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
2507 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2508 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
2510 if (sos_hdr->header.header_version_minor == 2) {
2511 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2512 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
2513 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2514 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
2516 if (sos_hdr->header.header_version_minor == 3) {
2517 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2518 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
2519 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2520 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
2521 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
2522 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2523 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
2524 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
2525 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2526 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
2531 "unsupported psp sos firmware\n");
2539 "failed to init sos firmware\n");
2540 release_firmware(adev->psp.sos_fw);
2541 adev->psp.sos_fw = NULL;
2546 int parse_ta_bin_descriptor(struct psp_context *psp,
2547 const struct ta_fw_bin_desc *desc,
2548 const struct ta_firmware_header_v2_0 *ta_hdr)
2550 uint8_t *ucode_start_addr = NULL;
2552 if (!psp || !desc || !ta_hdr)
2555 ucode_start_addr = (uint8_t *)ta_hdr +
2556 le32_to_cpu(desc->offset_bytes) +
2557 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2559 switch (desc->fw_type) {
2560 case TA_FW_TYPE_PSP_ASD:
2561 psp->asd_fw_version = le32_to_cpu(desc->fw_version);
2562 psp->asd_feature_version = le32_to_cpu(desc->fw_version);
2563 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes);
2564 psp->asd_start_addr = ucode_start_addr;
2566 case TA_FW_TYPE_PSP_XGMI:
2567 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
2568 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes);
2569 psp->ta_xgmi_start_addr = ucode_start_addr;
2571 case TA_FW_TYPE_PSP_RAS:
2572 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version);
2573 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes);
2574 psp->ta_ras_start_addr = ucode_start_addr;
2576 case TA_FW_TYPE_PSP_HDCP:
2577 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
2578 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes);
2579 psp->ta_hdcp_start_addr = ucode_start_addr;
2581 case TA_FW_TYPE_PSP_DTM:
2582 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version);
2583 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes);
2584 psp->ta_dtm_start_addr = ucode_start_addr;
2586 case TA_FW_TYPE_PSP_RAP:
2587 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version);
2588 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes);
2589 psp->ta_rap_start_addr = ucode_start_addr;
2592 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
2599 int psp_init_ta_microcode(struct psp_context *psp,
2600 const char *chip_name)
2602 struct amdgpu_device *adev = psp->adev;
2604 const struct ta_firmware_header_v2_0 *ta_hdr;
2609 dev_err(adev->dev, "invalid chip name for ta microcode\n");
2613 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
2614 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
2618 err = amdgpu_ucode_validate(adev->psp.ta_fw);
2622 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
2624 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
2625 dev_err(adev->dev, "unsupported TA header version\n");
2630 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
2631 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
2636 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
2637 err = parse_ta_bin_descriptor(psp,
2638 &ta_hdr->ta_fw_bin[ta_index],
2646 dev_err(adev->dev, "fail to initialize ta microcode\n");
2647 release_firmware(adev->psp.ta_fw);
2648 adev->psp.ta_fw = NULL;
2652 static int psp_set_clockgating_state(void *handle,
2653 enum amd_clockgating_state state)
2658 static int psp_set_powergating_state(void *handle,
2659 enum amd_powergating_state state)
2664 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
2665 struct device_attribute *attr,
2668 struct drm_device *ddev = dev_get_drvdata(dev);
2669 struct amdgpu_device *adev = drm_to_adev(ddev);
2673 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2674 DRM_INFO("PSP block is not ready yet.");
2678 mutex_lock(&adev->psp.mutex);
2679 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
2680 mutex_unlock(&adev->psp.mutex);
2683 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
2687 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver);
2690 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
2691 struct device_attribute *attr,
2695 struct drm_device *ddev = dev_get_drvdata(dev);
2696 struct amdgpu_device *adev = drm_to_adev(ddev);
2698 dma_addr_t dma_addr;
2701 const struct firmware *usbc_pd_fw;
2703 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2704 DRM_INFO("PSP block is not ready yet.");
2708 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
2709 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
2713 /* We need contiguous physical mem to place the FW for psp to access */
2714 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
2716 ret = dma_mapping_error(adev->dev, dma_addr);
2720 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
2723 * x86 specific workaround.
2724 * Without it the buffer is invisible in PSP.
2726 * TODO Remove once PSP starts snooping CPU cache
2729 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
2732 mutex_lock(&adev->psp.mutex);
2733 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
2734 mutex_unlock(&adev->psp.mutex);
2737 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
2738 release_firmware(usbc_pd_fw);
2742 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
2749 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
2750 psp_usbc_pd_fw_sysfs_read,
2751 psp_usbc_pd_fw_sysfs_write);
2755 const struct amd_ip_funcs psp_ip_funcs = {
2757 .early_init = psp_early_init,
2759 .sw_init = psp_sw_init,
2760 .sw_fini = psp_sw_fini,
2761 .hw_init = psp_hw_init,
2762 .hw_fini = psp_hw_fini,
2763 .suspend = psp_suspend,
2764 .resume = psp_resume,
2766 .check_soft_reset = NULL,
2767 .wait_for_idle = NULL,
2769 .set_clockgating_state = psp_set_clockgating_state,
2770 .set_powergating_state = psp_set_powergating_state,
2773 static int psp_sysfs_init(struct amdgpu_device *adev)
2775 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
2778 DRM_ERROR("Failed to create USBC PD FW control file!");
2783 static void psp_sysfs_fini(struct amdgpu_device *adev)
2785 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
2788 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
2790 .type = AMD_IP_BLOCK_TYPE_PSP,
2794 .funcs = &psp_ip_funcs,
2797 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
2799 .type = AMD_IP_BLOCK_TYPE_PSP,
2803 .funcs = &psp_ip_funcs,
2806 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
2808 .type = AMD_IP_BLOCK_TYPE_PSP,
2812 .funcs = &psp_ip_funcs,
2815 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
2817 .type = AMD_IP_BLOCK_TYPE_PSP,
2821 .funcs = &psp_ip_funcs,