drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34
  35 static void psp_set_funcs(struct amdgpu_device *adev);
  36
  37 static int psp_early_init(void *handle)
  38 {
  39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  40
  41         psp_set_funcs(adev);
  42
  43         return 0;
  44 }
  45
  46 static int psp_sw_init(void *handle)
  47 {
  48         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  49         struct psp_context *psp = &adev->psp;
  50         int ret;
  51
  52         switch (adev->asic_type) {
  53         case CHIP_VEGA10:
  54                 psp->init_microcode = psp_v3_1_init_microcode;
  55                 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  56                 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  57                 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  58                 psp->ring_init = psp_v3_1_ring_init;
  59                 psp->ring_create = psp_v3_1_ring_create;
  60                 psp->ring_destroy = psp_v3_1_ring_destroy;
  61                 psp->cmd_submit = psp_v3_1_cmd_submit;
  62                 psp->compare_sram_data = psp_v3_1_compare_sram_data;
  63                 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  64                 break;
  65         case CHIP_RAVEN:
  66                 psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
  67                 psp->ring_init = psp_v10_0_ring_init;
  68                 psp->cmd_submit = psp_v10_0_cmd_submit;
  69                 psp->compare_sram_data = psp_v10_0_compare_sram_data;
  70                 break;
  71         default:
  72                 return -EINVAL;
  73         }
  74
  75         psp->adev = adev;
  76
  77         ret = psp_init_microcode(psp);
  78         if (ret) {
  79                 DRM_ERROR("Failed to load psp firmware!\n");
  80                 return ret;
  81         }
  82
  83         return 0;
  84 }
  85
  86 static int psp_sw_fini(void *handle)
  87 {
  88         return 0;
  89 }
  90
  91 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  92                  uint32_t reg_val, uint32_t mask, bool check_changed)
  93 {
  94         uint32_t val;
  95         int i;
  96         struct amdgpu_device *adev = psp->adev;
  97
  98         val = RREG32(reg_index);
  99
 100         for (i = 0; i < adev->usec_timeout; i++) {
 101                 if (check_changed) {
 102                         if (val != reg_val)
 103                                 return 0;
 104                 } else {
 105                         if ((val & mask) == reg_val)
 106                                 return 0;
 107                 }
 108                 udelay(1);
 109         }
 110
 111         return -ETIME;
 112 }
 113
 114 static int
 115 psp_cmd_submit_buf(struct psp_context *psp,
 116                    struct amdgpu_firmware_info *ucode,
 117                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 118                    int index)
 119 {
 120         int ret;
 121
 122         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 123
 124         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 125
 126         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 127                              fence_mc_addr, index);
 128
 129         while (*((unsigned int *)psp->fence_buf) != index) {
 130                 msleep(1);
 131         }
 132
 133         return ret;
 134 }
 135
 136 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 137                                  uint64_t tmr_mc, uint32_t size)
 138 {
 139         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 140         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 141         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 142         cmd->cmd.cmd_setup_tmr.buf_size = size;
 143 }
 144
 145 /* Set up Trusted Memory Region */
 146 static int psp_tmr_init(struct psp_context *psp)
 147 {
 148         int ret;
 149
 150         /*
 151          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 152          * physical).
 153          *
 154          * Note: this memory need be reserved till the driver
 155          * uninitializes.
 156          */
 157         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 158                                       AMDGPU_GEM_DOMAIN_VRAM,
 159                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 160
 161         return ret;
 162 }
 163
 164 static int psp_tmr_load(struct psp_context *psp)
 165 {
 166         int ret;
 167         struct psp_gfx_cmd_resp *cmd;
 168
 169         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 170         if (!cmd)
 171                 return -ENOMEM;
 172
 173         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 174
 175         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 176                                  psp->fence_buf_mc_addr, 1);
 177         if (ret)
 178                 goto failed;
 179
 180         kfree(cmd);
 181
 182         return 0;
 183
 184 failed:
 185         kfree(cmd);
 186         return ret;
 187 }
 188
 189 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 190                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 191                                  uint32_t size, uint32_t shared_size)
 192 {
 193         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 194         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 195         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 196         cmd->cmd.cmd_load_ta.app_len = size;
 197
 198         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 199         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 200         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 201 }
 202
 203 static int psp_asd_init(struct psp_context *psp)
 204 {
 205         int ret;
 206
 207         /*
 208          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 209          * physical) for shared ASD <-> Driver
 210          */
 211         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 212                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 213                                       &psp->asd_shared_bo,
 214                                       &psp->asd_shared_mc_addr,
 215                                       &psp->asd_shared_buf);
 216
 217         return ret;
 218 }
 219
 220 static int psp_asd_load(struct psp_context *psp)
 221 {
 222         int ret;
 223         struct psp_gfx_cmd_resp *cmd;
 224
 225         /* If PSP version doesn't match ASD version, asd loading will be failed.
 226          * add workaround to bypass it for sriov now.
 227          * TODO: add version check to make it common
 228          */
 229         if (amdgpu_sriov_vf(psp->adev))
 230                 return 0;
 231
 232         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 233         if (!cmd)
 234                 return -ENOMEM;
 235
 236         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 237         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 238
 239         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 240                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 241
 242         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 243                                  psp->fence_buf_mc_addr, 2);
 244
 245         kfree(cmd);
 246
 247         return ret;
 248 }
 249
 250 static int psp_hw_start(struct psp_context *psp)
 251 {
 252         int ret;
 253
 254         ret = psp_bootloader_load_sysdrv(psp);
 255         if (ret)
 256                 return ret;
 257
 258         ret = psp_bootloader_load_sos(psp);
 259         if (ret)
 260                 return ret;
 261
 262         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 263         if (ret)
 264                 return ret;
 265
 266         ret = psp_tmr_load(psp);
 267         if (ret)
 268                 return ret;
 269
 270         ret = psp_asd_load(psp);
 271         if (ret)
 272                 return ret;
 273
 274         return 0;
 275 }
 276
 277 static int psp_np_fw_load(struct psp_context *psp)
 278 {
 279         int i, ret;
 280         struct amdgpu_firmware_info *ucode;
 281         struct amdgpu_device* adev = psp->adev;
 282
 283         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 284                 ucode = &adev->firmware.ucode[i];
 285                 if (!ucode->fw)
 286                         continue;
 287
 288                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 289                     psp_smu_reload_quirk(psp))
 290                         continue;
 291                 if (amdgpu_sriov_vf(adev) &&
 292                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 293                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 294                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 295                         /*skip ucode loading in SRIOV VF */
 296                         continue;
 297
 298                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 299                 if (ret)
 300                         return ret;
 301
 302                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 303                                          psp->fence_buf_mc_addr, i + 3);
 304                 if (ret)
 305                         return ret;
 306
 307 #if 0
 308                 /* check if firmware loaded sucessfully */
 309                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 310                         return -EINVAL;
 311 #endif
 312         }
 313
 314         return 0;
 315 }
 316
 317 static int psp_load_fw(struct amdgpu_device *adev)
 318 {
 319         int ret;
 320         struct psp_context *psp = &adev->psp;
 321
 322         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 323         if (!psp->cmd)
 324                 return -ENOMEM;
 325
 326         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 327                                       AMDGPU_GEM_DOMAIN_GTT,
 328                                       &psp->fw_pri_bo,
 329                                       &psp->fw_pri_mc_addr,
 330                                       &psp->fw_pri_buf);
 331         if (ret)
 332                 goto failed;
 333
 334         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 335                                       AMDGPU_GEM_DOMAIN_VRAM,
 336                                       &psp->fence_buf_bo,
 337                                       &psp->fence_buf_mc_addr,
 338                                       &psp->fence_buf);
 339         if (ret)
 340                 goto failed_mem2;
 341
 342         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 343                                       AMDGPU_GEM_DOMAIN_VRAM,
 344                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 345                                       (void **)&psp->cmd_buf_mem);
 346         if (ret)
 347                 goto failed_mem1;
 348
 349         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 350
 351         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 352         if (ret)
 353                 goto failed_mem;
 354
 355         ret = psp_tmr_init(psp);
 356         if (ret)
 357                 goto failed_mem;
 358
 359         ret = psp_asd_init(psp);
 360         if (ret)
 361                 goto failed_mem;
 362
 363         ret = psp_hw_start(psp);
 364         if (ret)
 365                 goto failed_mem;
 366
 367         ret = psp_np_fw_load(psp);
 368         if (ret)
 369                 goto failed_mem;
 370
 371         return 0;
 372
 373 failed_mem:
 374         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 375                               &psp->cmd_buf_mc_addr,
 376                               (void **)&psp->cmd_buf_mem);
 377 failed_mem1:
 378         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 379                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 380 failed_mem2:
 381         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 382                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 383 failed:
 384         kfree(psp->cmd);
 385         psp->cmd = NULL;
 386         return ret;
 387 }
 388
 389 static int psp_hw_init(void *handle)
 390 {
 391         int ret;
 392         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 393
 394
 395         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 396                 return 0;
 397
 398         mutex_lock(&adev->firmware.mutex);
 399         /*
 400          * This sequence is just used on hw_init only once, no need on
 401          * resume.
 402          */
 403         ret = amdgpu_ucode_init_bo(adev);
 404         if (ret)
 405                 goto failed;
 406
 407         ret = psp_load_fw(adev);
 408         if (ret) {
 409                 DRM_ERROR("PSP firmware loading failed\n");
 410                 goto failed;
 411         }
 412
 413         mutex_unlock(&adev->firmware.mutex);
 414         return 0;
 415
 416 failed:
 417         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 418         mutex_unlock(&adev->firmware.mutex);
 419         return -EINVAL;
 420 }
 421
 422 static int psp_hw_fini(void *handle)
 423 {
 424         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 425         struct psp_context *psp = &adev->psp;
 426
 427         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 428                 return 0;
 429
 430         amdgpu_ucode_fini_bo(adev);
 431
 432         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 433
 434         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 435         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 436                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 437         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 438                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 439         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 440                               &psp->asd_shared_buf);
 441         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 442                               (void **)&psp->cmd_buf_mem);
 443
 444         kfree(psp->cmd);
 445         psp->cmd = NULL;
 446
 447         return 0;
 448 }
 449
 450 static int psp_suspend(void *handle)
 451 {
 452         return 0;
 453 }
 454
 455 static int psp_resume(void *handle)
 456 {
 457         int ret;
 458         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 459         struct psp_context *psp = &adev->psp;
 460
 461         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 462                 return 0;
 463
 464         DRM_INFO("PSP is resuming...\n");
 465
 466         mutex_lock(&adev->firmware.mutex);
 467
 468         ret = psp_hw_start(psp);
 469         if (ret)
 470                 goto failed;
 471
 472         ret = psp_np_fw_load(psp);
 473         if (ret)
 474                 goto failed;
 475
 476         mutex_unlock(&adev->firmware.mutex);
 477
 478         return 0;
 479
 480 failed:
 481         DRM_ERROR("PSP resume failed\n");
 482         mutex_unlock(&adev->firmware.mutex);
 483         return ret;
 484 }
 485
 486 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 487                                         enum AMDGPU_UCODE_ID ucode_type)
 488 {
 489         struct amdgpu_firmware_info *ucode = NULL;
 490
 491         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 492                 DRM_INFO("firmware is not loaded by PSP\n");
 493                 return true;
 494         }
 495
 496         if (!adev->firmware.fw_size)
 497                 return false;
 498
 499         ucode = &adev->firmware.ucode[ucode_type];
 500         if (!ucode->fw || !ucode->ucode_size)
 501                 return false;
 502
 503         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 504 }
 505
 506 static int psp_set_clockgating_state(void *handle,
 507                                      enum amd_clockgating_state state)
 508 {
 509         return 0;
 510 }
 511
 512 static int psp_set_powergating_state(void *handle,
 513                                      enum amd_powergating_state state)
 514 {
 515         return 0;
 516 }
 517
 518 const struct amd_ip_funcs psp_ip_funcs = {
 519         .name = "psp",
 520         .early_init = psp_early_init,
 521         .late_init = NULL,
 522         .sw_init = psp_sw_init,
 523         .sw_fini = psp_sw_fini,
 524         .hw_init = psp_hw_init,
 525         .hw_fini = psp_hw_fini,
 526         .suspend = psp_suspend,
 527         .resume = psp_resume,
 528         .is_idle = NULL,
 529         .wait_for_idle = NULL,
 530         .soft_reset = NULL,
 531         .set_clockgating_state = psp_set_clockgating_state,
 532         .set_powergating_state = psp_set_powergating_state,
 533 };
 534
 535 static const struct amdgpu_psp_funcs psp_funcs = {
 536         .check_fw_loading_status = psp_check_fw_loading_status,
 537 };
 538
 539 static void psp_set_funcs(struct amdgpu_device *adev)
 540 {
 541         if (NULL == adev->firmware.funcs)
 542                 adev->firmware.funcs = &psp_funcs;
 543 }
 544
 545 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 546 {
 547         .type = AMD_IP_BLOCK_TYPE_PSP,
 548         .major = 3,
 549         .minor = 1,
 550         .rev = 0,
 551         .funcs = &psp_ip_funcs,
 552 };
 553
 554 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 555 {
 556         .type = AMD_IP_BLOCK_TYPE_PSP,
 557         .major = 10,
 558         .minor = 0,
 559         .rev = 0,
 560         .funcs = &psp_ip_funcs,
 561 };