drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "soc15_common.h"
  33 #include "psp_v3_1.h"
  34 #include "psp_v10_0.h"
  35 #include "psp_v11_0.h"
  36 #include "psp_v12_0.h"
  37 #include "psp_v13_0.h"
  38
  39 #include "amdgpu_ras.h"
  40 #include "amdgpu_securedisplay.h"
  41
  42 static int psp_sysfs_init(struct amdgpu_device *adev);
  43 static void psp_sysfs_fini(struct amdgpu_device *adev);
  44
  45 static int psp_load_smu_fw(struct psp_context *psp);
  46
  47 /*
  48  * Due to DF Cstate management centralized to PMFW, the firmware
  49  * loading sequence will be updated as below:
  50  *   - Load KDB
  51  *   - Load SYS_DRV
  52  *   - Load tOS
  53  *   - Load PMFW
  54  *   - Setup TMR
  55  *   - Load other non-psp fw
  56  *   - Load ASD
  57  *   - Load XGMI/RAS/HDCP/DTM TA if any
  58  *
  59  * This new sequence is required for
  60  *   - Arcturus and onwards
  61  *   - Navi12 and onwards
  62  */
  63 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  64 {
  65         struct amdgpu_device *adev = psp->adev;
  66
  67         psp->pmfw_centralized_cstate_management = false;
  68
  69         if (amdgpu_sriov_vf(adev))
  70                 return;
  71
  72         if (adev->flags & AMD_IS_APU)
  73                 return;
  74
  75         if ((adev->asic_type >= CHIP_ARCTURUS) ||
  76             (adev->asic_type >= CHIP_NAVI12))
  77                 psp->pmfw_centralized_cstate_management = true;
  78 }
  79
  80 static int psp_early_init(void *handle)
  81 {
  82         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  83         struct psp_context *psp = &adev->psp;
  84
  85         switch (adev->asic_type) {
  86         case CHIP_VEGA10:
  87         case CHIP_VEGA12:
  88                 psp_v3_1_set_psp_funcs(psp);
  89                 psp->autoload_supported = false;
  90                 break;
  91         case CHIP_RAVEN:
  92                 psp_v10_0_set_psp_funcs(psp);
  93                 psp->autoload_supported = false;
  94                 break;
  95         case CHIP_VEGA20:
  96         case CHIP_ARCTURUS:
  97                 psp_v11_0_set_psp_funcs(psp);
  98                 psp->autoload_supported = false;
  99                 break;
 100         case CHIP_NAVI10:
 101         case CHIP_NAVI14:
 102         case CHIP_NAVI12:
 103         case CHIP_SIENNA_CICHLID:
 104         case CHIP_NAVY_FLOUNDER:
 105         case CHIP_VANGOGH:
 106         case CHIP_DIMGREY_CAVEFISH:
 107                 psp_v11_0_set_psp_funcs(psp);
 108                 psp->autoload_supported = true;
 109                 break;
 110         case CHIP_RENOIR:
 111                 psp_v12_0_set_psp_funcs(psp);
 112                 break;
 113         case CHIP_ALDEBARAN:
 114                 psp_v13_0_set_psp_funcs(psp);
 115                 break;
 116         default:
 117                 return -EINVAL;
 118         }
 119
 120         psp->adev = adev;
 121
 122         psp_check_pmfw_centralized_cstate_management(psp);
 123
 124         return 0;
 125 }
 126
 127 static void psp_memory_training_fini(struct psp_context *psp)
 128 {
 129         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 130
 131         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 132         kfree(ctx->sys_cache);
 133         ctx->sys_cache = NULL;
 134 }
 135
 136 static int psp_memory_training_init(struct psp_context *psp)
 137 {
 138         int ret;
 139         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 140
 141         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 142                 DRM_DEBUG("memory training is not supported!\n");
 143                 return 0;
 144         }
 145
 146         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 147         if (ctx->sys_cache == NULL) {
 148                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 149                 ret = -ENOMEM;
 150                 goto Err_out;
 151         }
 152
 153         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 154                   ctx->train_data_size,
 155                   ctx->p2c_train_data_offset,
 156                   ctx->c2p_train_data_offset);
 157         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 158         return 0;
 159
 160 Err_out:
 161         psp_memory_training_fini(psp);
 162         return ret;
 163 }
 164
 165 static int psp_sw_init(void *handle)
 166 {
 167         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 168         struct psp_context *psp = &adev->psp;
 169         int ret;
 170
 171         if (!amdgpu_sriov_vf(adev)) {
 172                 ret = psp_init_microcode(psp);
 173                 if (ret) {
 174                         DRM_ERROR("Failed to load psp firmware!\n");
 175                         return ret;
 176                 }
 177         }
 178
 179         ret = psp_memory_training_init(psp);
 180         if (ret) {
 181                 DRM_ERROR("Failed to initialize memory training!\n");
 182                 return ret;
 183         }
 184         ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 185         if (ret) {
 186                 DRM_ERROR("Failed to process memory training!\n");
 187                 return ret;
 188         }
 189
 190         if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
 191                 ret= psp_sysfs_init(adev);
 192                 if (ret) {
 193                         return ret;
 194                 }
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int psp_sw_fini(void *handle)
 201 {
 202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 203
 204         psp_memory_training_fini(&adev->psp);
 205         if (adev->psp.sos_fw) {
 206                 release_firmware(adev->psp.sos_fw);
 207                 adev->psp.sos_fw = NULL;
 208         }
 209         if (adev->psp.asd_fw) {
 210                 release_firmware(adev->psp.asd_fw);
 211                 adev->psp.asd_fw = NULL;
 212         }
 213         if (adev->psp.ta_fw) {
 214                 release_firmware(adev->psp.ta_fw);
 215                 adev->psp.ta_fw = NULL;
 216         }
 217
 218         if (adev->asic_type == CHIP_NAVI10 ||
 219             adev->asic_type == CHIP_SIENNA_CICHLID)
 220                 psp_sysfs_fini(adev);
 221
 222         return 0;
 223 }
 224
 225 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 226                  uint32_t reg_val, uint32_t mask, bool check_changed)
 227 {
 228         uint32_t val;
 229         int i;
 230         struct amdgpu_device *adev = psp->adev;
 231
 232         if (psp->adev->in_pci_err_recovery)
 233                 return 0;
 234
 235         for (i = 0; i < adev->usec_timeout; i++) {
 236                 val = RREG32(reg_index);
 237                 if (check_changed) {
 238                         if (val != reg_val)
 239                                 return 0;
 240                 } else {
 241                         if ((val & mask) == reg_val)
 242                                 return 0;
 243                 }
 244                 udelay(1);
 245         }
 246
 247         return -ETIME;
 248 }
 249
 250 static int
 251 psp_cmd_submit_buf(struct psp_context *psp,
 252                    struct amdgpu_firmware_info *ucode,
 253                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 254 {
 255         int ret;
 256         int index;
 257         int timeout = 20000;
 258         bool ras_intr = false;
 259         bool skip_unsupport = false;
 260
 261         if (psp->adev->in_pci_err_recovery)
 262                 return 0;
 263
 264         mutex_lock(&psp->mutex);
 265
 266         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 267
 268         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 269
 270         index = atomic_inc_return(&psp->fence_value);
 271         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 272         if (ret) {
 273                 atomic_dec(&psp->fence_value);
 274                 mutex_unlock(&psp->mutex);
 275                 return ret;
 276         }
 277
 278         amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 279         while (*((unsigned int *)psp->fence_buf) != index) {
 280                 if (--timeout == 0)
 281                         break;
 282                 /*
 283                  * Shouldn't wait for timeout when err_event_athub occurs,
 284                  * because gpu reset thread triggered and lock resource should
 285                  * be released for psp resume sequence.
 286                  */
 287                 ras_intr = amdgpu_ras_intr_triggered();
 288                 if (ras_intr)
 289                         break;
 290                 usleep_range(10, 100);
 291                 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 292         }
 293
 294         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 295         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 296                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 297
 298         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 299
 300         /* In some cases, psp response status is not 0 even there is no
 301          * problem while the command is submitted. Some version of PSP FW
 302          * doesn't write 0 to that field.
 303          * So here we would like to only print a warning instead of an error
 304          * during psp initialization to avoid breaking hw_init and it doesn't
 305          * return -EINVAL.
 306          */
 307         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 308                 if (ucode)
 309                         DRM_WARN("failed to load ucode id (%d) ",
 310                                   ucode->ucode_id);
 311                 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
 312                          psp->cmd_buf_mem->cmd_id,
 313                          psp->cmd_buf_mem->resp.status);
 314                 if (!timeout) {
 315                         mutex_unlock(&psp->mutex);
 316                         return -EINVAL;
 317                 }
 318         }
 319
 320         if (ucode) {
 321                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 322                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 323         }
 324         mutex_unlock(&psp->mutex);
 325
 326         return ret;
 327 }
 328
 329 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 330                                  struct psp_gfx_cmd_resp *cmd,
 331                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 332 {
 333         struct amdgpu_device *adev = psp->adev;
 334         uint32_t size = amdgpu_bo_size(tmr_bo);
 335         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 336
 337         if (amdgpu_sriov_vf(psp->adev))
 338                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 339         else
 340                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 341         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 342         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 343         cmd->cmd.cmd_setup_tmr.buf_size = size;
 344         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 345         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 346         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 347 }
 348
 349 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 350                                       uint64_t pri_buf_mc, uint32_t size)
 351 {
 352         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 353         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 354         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 355         cmd->cmd.cmd_load_toc.toc_size = size;
 356 }
 357
 358 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 359 static int psp_load_toc(struct psp_context *psp,
 360                         uint32_t *tmr_size)
 361 {
 362         int ret;
 363         struct psp_gfx_cmd_resp *cmd;
 364
 365         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 366         if (!cmd)
 367                 return -ENOMEM;
 368         /* Copy toc to psp firmware private buffer */
 369         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 370         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 371
 372         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 373
 374         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 375                                  psp->fence_buf_mc_addr);
 376         if (!ret)
 377                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 378         kfree(cmd);
 379         return ret;
 380 }
 381
 382 /* Set up Trusted Memory Region */
 383 static int psp_tmr_init(struct psp_context *psp)
 384 {
 385         int ret;
 386         int tmr_size;
 387         void *tmr_buf;
 388         void **pptr;
 389
 390         /*
 391          * According to HW engineer, they prefer the TMR address be "naturally
 392          * aligned" , e.g. the start address be an integer divide of TMR size.
 393          *
 394          * Note: this memory need be reserved till the driver
 395          * uninitializes.
 396          */
 397         tmr_size = PSP_TMR_SIZE(psp->adev);
 398
 399         /* For ASICs support RLC autoload, psp will parse the toc
 400          * and calculate the total size of TMR needed */
 401         if (!amdgpu_sriov_vf(psp->adev) &&
 402             psp->toc_start_addr &&
 403             psp->toc_bin_size &&
 404             psp->fw_pri_buf) {
 405                 ret = psp_load_toc(psp, &tmr_size);
 406                 if (ret) {
 407                         DRM_ERROR("Failed to load toc\n");
 408                         return ret;
 409                 }
 410         }
 411
 412         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 413         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
 414                                       AMDGPU_GEM_DOMAIN_VRAM,
 415                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 416
 417         return ret;
 418 }
 419
 420 static bool psp_skip_tmr(struct psp_context *psp)
 421 {
 422         switch (psp->adev->asic_type) {
 423         case CHIP_NAVI12:
 424         case CHIP_SIENNA_CICHLID:
 425         case CHIP_ALDEBARAN:
 426                 return true;
 427         default:
 428                 return false;
 429         }
 430 }
 431
 432 static int psp_tmr_load(struct psp_context *psp)
 433 {
 434         int ret;
 435         struct psp_gfx_cmd_resp *cmd;
 436
 437         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 438          * Already set up by host driver.
 439          */
 440         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 441                 return 0;
 442
 443         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 444         if (!cmd)
 445                 return -ENOMEM;
 446
 447         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 448         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 449                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 450
 451         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 452                                  psp->fence_buf_mc_addr);
 453
 454         kfree(cmd);
 455
 456         return ret;
 457 }
 458
 459 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 460                                         struct psp_gfx_cmd_resp *cmd)
 461 {
 462         if (amdgpu_sriov_vf(psp->adev))
 463                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 464         else
 465                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 466 }
 467
 468 static int psp_tmr_unload(struct psp_context *psp)
 469 {
 470         int ret;
 471         struct psp_gfx_cmd_resp *cmd;
 472
 473         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 474         if (!cmd)
 475                 return -ENOMEM;
 476
 477         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 478         DRM_INFO("free PSP TMR buffer\n");
 479
 480         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 481                                  psp->fence_buf_mc_addr);
 482
 483         kfree(cmd);
 484
 485         return ret;
 486 }
 487
 488 static int psp_tmr_terminate(struct psp_context *psp)
 489 {
 490         int ret;
 491         void *tmr_buf;
 492         void **pptr;
 493
 494         ret = psp_tmr_unload(psp);
 495         if (ret)
 496                 return ret;
 497
 498         /* free TMR memory buffer */
 499         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 500         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 501
 502         return 0;
 503 }
 504
 505 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 506                                         uint64_t *output_ptr)
 507 {
 508         int ret;
 509         struct psp_gfx_cmd_resp *cmd;
 510
 511         if (!output_ptr)
 512                 return -EINVAL;
 513
 514         if (amdgpu_sriov_vf(psp->adev))
 515                 return 0;
 516
 517         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 518         if (!cmd)
 519                 return -ENOMEM;
 520
 521         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 522
 523         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 524                                  psp->fence_buf_mc_addr);
 525
 526         if (!ret) {
 527                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 528                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 529         }
 530
 531         kfree(cmd);
 532
 533         return ret;
 534 }
 535
 536 static int psp_boot_config_set(struct amdgpu_device *adev)
 537 {
 538         struct psp_context *psp = &adev->psp;
 539         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 540
 541         if (adev->asic_type != CHIP_SIENNA_CICHLID || amdgpu_sriov_vf(adev))
 542                 return 0;
 543
 544         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 545
 546         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 547         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 548         cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC;
 549         cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC;
 550
 551         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 552 }
 553
 554 static int psp_rl_load(struct amdgpu_device *adev)
 555 {
 556         struct psp_context *psp = &adev->psp;
 557         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 558
 559         if (psp->rl_bin_size == 0)
 560                 return 0;
 561
 562         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 563         memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size);
 564
 565         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 566
 567         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 568         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 569         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 570         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size;
 571         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 572
 573         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 574 }
 575
 576 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 577                                 uint64_t asd_mc, uint32_t size)
 578 {
 579         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 580         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 581         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 582         cmd->cmd.cmd_load_ta.app_len = size;
 583
 584         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
 585         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
 586         cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
 587 }
 588
 589 static int psp_asd_load(struct psp_context *psp)
 590 {
 591         int ret;
 592         struct psp_gfx_cmd_resp *cmd;
 593
 594         /* If PSP version doesn't match ASD version, asd loading will be failed.
 595          * add workaround to bypass it for sriov now.
 596          * TODO: add version check to make it common
 597          */
 598         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size)
 599                 return 0;
 600
 601         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 602         if (!cmd)
 603                 return -ENOMEM;
 604
 605         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 606         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 607
 608         psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 609                                   psp->asd_ucode_size);
 610
 611         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 612                                  psp->fence_buf_mc_addr);
 613         if (!ret) {
 614                 psp->asd_context.asd_initialized = true;
 615                 psp->asd_context.session_id = cmd->resp.session_id;
 616         }
 617
 618         kfree(cmd);
 619
 620         return ret;
 621 }
 622
 623 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 624                                        uint32_t session_id)
 625 {
 626         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 627         cmd->cmd.cmd_unload_ta.session_id = session_id;
 628 }
 629
 630 static int psp_asd_unload(struct psp_context *psp)
 631 {
 632         int ret;
 633         struct psp_gfx_cmd_resp *cmd;
 634
 635         if (amdgpu_sriov_vf(psp->adev))
 636                 return 0;
 637
 638         if (!psp->asd_context.asd_initialized)
 639                 return 0;
 640
 641         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 642         if (!cmd)
 643                 return -ENOMEM;
 644
 645         psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
 646
 647         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 648                                  psp->fence_buf_mc_addr);
 649         if (!ret)
 650                 psp->asd_context.asd_initialized = false;
 651
 652         kfree(cmd);
 653
 654         return ret;
 655 }
 656
 657 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 658                 uint32_t id, uint32_t value)
 659 {
 660         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 661         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 662         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 663 }
 664
 665 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 666                 uint32_t value)
 667 {
 668         struct psp_gfx_cmd_resp *cmd = NULL;
 669         int ret = 0;
 670
 671         if (reg >= PSP_REG_LAST)
 672                 return -EINVAL;
 673
 674         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 675         if (!cmd)
 676                 return -ENOMEM;
 677
 678         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 679         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 680
 681         kfree(cmd);
 682         return ret;
 683 }
 684
 685 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 686                                      uint64_t ta_bin_mc,
 687                                      uint32_t ta_bin_size,
 688                                      uint64_t ta_shared_mc,
 689                                      uint32_t ta_shared_size)
 690 {
 691         cmd->cmd_id                             = GFX_CMD_ID_LOAD_TA;
 692         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 693         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 694         cmd->cmd.cmd_load_ta.app_len            = ta_bin_size;
 695
 696         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
 697         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
 698         cmd->cmd.cmd_load_ta.cmd_buf_len         = ta_shared_size;
 699 }
 700
 701 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 702 {
 703         int ret;
 704
 705         /*
 706          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 707          * physical) for xgmi ta <-> Driver
 708          */
 709         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 710                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 711                                       &psp->xgmi_context.xgmi_shared_bo,
 712                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 713                                       &psp->xgmi_context.xgmi_shared_buf);
 714
 715         return ret;
 716 }
 717
 718 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 719                                        uint32_t ta_cmd_id,
 720                                        uint32_t session_id)
 721 {
 722         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
 723         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
 724         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 725 }
 726
 727 static int psp_ta_invoke(struct psp_context *psp,
 728                   uint32_t ta_cmd_id,
 729                   uint32_t session_id)
 730 {
 731         int ret;
 732         struct psp_gfx_cmd_resp *cmd;
 733
 734         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 735         if (!cmd)
 736                 return -ENOMEM;
 737
 738         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
 739
 740         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 741                                  psp->fence_buf_mc_addr);
 742
 743         kfree(cmd);
 744
 745         return ret;
 746 }
 747
 748 static int psp_xgmi_load(struct psp_context *psp)
 749 {
 750         int ret;
 751         struct psp_gfx_cmd_resp *cmd;
 752
 753         /*
 754          * TODO: bypass the loading in sriov for now
 755          */
 756
 757         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 758         if (!cmd)
 759                 return -ENOMEM;
 760
 761         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 762         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 763
 764         psp_prep_ta_load_cmd_buf(cmd,
 765                                  psp->fw_pri_mc_addr,
 766                                  psp->ta_xgmi_ucode_size,
 767                                  psp->xgmi_context.xgmi_shared_mc_addr,
 768                                  PSP_XGMI_SHARED_MEM_SIZE);
 769
 770         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 771                                  psp->fence_buf_mc_addr);
 772
 773         if (!ret) {
 774                 psp->xgmi_context.initialized = 1;
 775                 psp->xgmi_context.session_id = cmd->resp.session_id;
 776         }
 777
 778         kfree(cmd);
 779
 780         return ret;
 781 }
 782
 783 static int psp_xgmi_unload(struct psp_context *psp)
 784 {
 785         int ret;
 786         struct psp_gfx_cmd_resp *cmd;
 787         struct amdgpu_device *adev = psp->adev;
 788
 789         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
 790         if (adev->asic_type == CHIP_ARCTURUS ||
 791                 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
 792                 return 0;
 793
 794         /*
 795          * TODO: bypass the unloading in sriov for now
 796          */
 797
 798         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 799         if (!cmd)
 800                 return -ENOMEM;
 801
 802         psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 803
 804         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 805                                  psp->fence_buf_mc_addr);
 806
 807         kfree(cmd);
 808
 809         return ret;
 810 }
 811
 812 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 813 {
 814         return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
 815 }
 816
 817 int psp_xgmi_terminate(struct psp_context *psp)
 818 {
 819         int ret;
 820
 821         if (!psp->xgmi_context.initialized)
 822                 return 0;
 823
 824         ret = psp_xgmi_unload(psp);
 825         if (ret)
 826                 return ret;
 827
 828         psp->xgmi_context.initialized = 0;
 829
 830         /* free xgmi shared memory */
 831         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 832                         &psp->xgmi_context.xgmi_shared_mc_addr,
 833                         &psp->xgmi_context.xgmi_shared_buf);
 834
 835         return 0;
 836 }
 837
 838 int psp_xgmi_initialize(struct psp_context *psp)
 839 {
 840         struct ta_xgmi_shared_memory *xgmi_cmd;
 841         int ret;
 842
 843         if (!psp->adev->psp.ta_fw ||
 844             !psp->adev->psp.ta_xgmi_ucode_size ||
 845             !psp->adev->psp.ta_xgmi_start_addr)
 846                 return -ENOENT;
 847
 848         if (!psp->xgmi_context.initialized) {
 849                 ret = psp_xgmi_init_shared_buf(psp);
 850                 if (ret)
 851                         return ret;
 852         }
 853
 854         /* Load XGMI TA */
 855         ret = psp_xgmi_load(psp);
 856         if (ret)
 857                 return ret;
 858
 859         /* Initialize XGMI session */
 860         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 861         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 862         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 863
 864         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 865
 866         return ret;
 867 }
 868
 869 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 870 {
 871         struct ta_xgmi_shared_memory *xgmi_cmd;
 872         int ret;
 873
 874         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 875         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 876
 877         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 878
 879         /* Invoke xgmi ta to get hive id */
 880         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 881         if (ret)
 882                 return ret;
 883
 884         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 885
 886         return 0;
 887 }
 888
 889 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 890 {
 891         struct ta_xgmi_shared_memory *xgmi_cmd;
 892         int ret;
 893
 894         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 895         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 896
 897         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 898
 899         /* Invoke xgmi ta to get the node id */
 900         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 901         if (ret)
 902                 return ret;
 903
 904         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 905
 906         return 0;
 907 }
 908
 909 int psp_xgmi_get_topology_info(struct psp_context *psp,
 910                                int number_devices,
 911                                struct psp_xgmi_topology_info *topology)
 912 {
 913         struct ta_xgmi_shared_memory *xgmi_cmd;
 914         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 915         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 916         int i;
 917         int ret;
 918
 919         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 920                 return -EINVAL;
 921
 922         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 923         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 924
 925         /* Fill in the shared memory with topology information as input */
 926         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 927         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 928         topology_info_input->num_nodes = number_devices;
 929
 930         for (i = 0; i < topology_info_input->num_nodes; i++) {
 931                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 932                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 933                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 934                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 935         }
 936
 937         /* Invoke xgmi ta to get the topology information */
 938         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 939         if (ret)
 940                 return ret;
 941
 942         /* Read the output topology information from the shared memory */
 943         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 944         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 945         for (i = 0; i < topology->num_nodes; i++) {
 946                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 947                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 948                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 949                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 950         }
 951
 952         return 0;
 953 }
 954
 955 int psp_xgmi_set_topology_info(struct psp_context *psp,
 956                                int number_devices,
 957                                struct psp_xgmi_topology_info *topology)
 958 {
 959         struct ta_xgmi_shared_memory *xgmi_cmd;
 960         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 961         int i;
 962
 963         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 964                 return -EINVAL;
 965
 966         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 967         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 968
 969         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 970         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 971         topology_info_input->num_nodes = number_devices;
 972
 973         for (i = 0; i < topology_info_input->num_nodes; i++) {
 974                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 975                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 976                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 977                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 978         }
 979
 980         /* Invoke xgmi ta to set topology information */
 981         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 982 }
 983
 984 // ras begin
 985 static int psp_ras_init_shared_buf(struct psp_context *psp)
 986 {
 987         int ret;
 988
 989         /*
 990          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 991          * physical) for ras ta <-> Driver
 992          */
 993         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 994                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 995                         &psp->ras.ras_shared_bo,
 996                         &psp->ras.ras_shared_mc_addr,
 997                         &psp->ras.ras_shared_buf);
 998
 999         return ret;
1000 }
1001
1002 static int psp_ras_load(struct psp_context *psp)
1003 {
1004         int ret;
1005         struct psp_gfx_cmd_resp *cmd;
1006         struct ta_ras_shared_memory *ras_cmd;
1007
1008         /*
1009          * TODO: bypass the loading in sriov for now
1010          */
1011         if (amdgpu_sriov_vf(psp->adev))
1012                 return 0;
1013
1014         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1015         if (!cmd)
1016                 return -ENOMEM;
1017
1018         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1019         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
1020
1021         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1022
1023         if (psp->adev->gmc.xgmi.connected_to_cpu)
1024                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1025         else
1026                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1027
1028         psp_prep_ta_load_cmd_buf(cmd,
1029                                  psp->fw_pri_mc_addr,
1030                                  psp->ta_ras_ucode_size,
1031                                  psp->ras.ras_shared_mc_addr,
1032                                  PSP_RAS_SHARED_MEM_SIZE);
1033
1034         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1035                         psp->fence_buf_mc_addr);
1036
1037         if (!ret) {
1038                 psp->ras.session_id = cmd->resp.session_id;
1039
1040                 if (!ras_cmd->ras_status)
1041                         psp->ras.ras_initialized = true;
1042                 else
1043                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1044         }
1045
1046         if (ret || ras_cmd->ras_status)
1047                 amdgpu_ras_fini(psp->adev);
1048
1049         kfree(cmd);
1050
1051         return ret;
1052 }
1053
1054 static int psp_ras_unload(struct psp_context *psp)
1055 {
1056         int ret;
1057         struct psp_gfx_cmd_resp *cmd;
1058
1059         /*
1060          * TODO: bypass the unloading in sriov for now
1061          */
1062         if (amdgpu_sriov_vf(psp->adev))
1063                 return 0;
1064
1065         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1066         if (!cmd)
1067                 return -ENOMEM;
1068
1069         psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
1070
1071         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1072                         psp->fence_buf_mc_addr);
1073
1074         kfree(cmd);
1075
1076         return ret;
1077 }
1078
1079 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1080 {
1081         struct ta_ras_shared_memory *ras_cmd;
1082         int ret;
1083
1084         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1085
1086         /*
1087          * TODO: bypass the loading in sriov for now
1088          */
1089         if (amdgpu_sriov_vf(psp->adev))
1090                 return 0;
1091
1092         ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1093
1094         if (amdgpu_ras_intr_triggered())
1095                 return ret;
1096
1097         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1098         {
1099                 DRM_WARN("RAS: Unsupported Interface");
1100                 return -EINVAL;
1101         }
1102
1103         if (!ret) {
1104                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1105                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1106
1107                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1108                 }
1109                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1110                         dev_warn(psp->adev->dev,
1111                                  "RAS internal register access blocked\n");
1112         }
1113
1114         return ret;
1115 }
1116
1117 int psp_ras_enable_features(struct psp_context *psp,
1118                 union ta_ras_cmd_input *info, bool enable)
1119 {
1120         struct ta_ras_shared_memory *ras_cmd;
1121         int ret;
1122
1123         if (!psp->ras.ras_initialized)
1124                 return -EINVAL;
1125
1126         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1127         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1128
1129         if (enable)
1130                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1131         else
1132                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1133
1134         ras_cmd->ras_in_message = *info;
1135
1136         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1137         if (ret)
1138                 return -EINVAL;
1139
1140         return ras_cmd->ras_status;
1141 }
1142
1143 static int psp_ras_terminate(struct psp_context *psp)
1144 {
1145         int ret;
1146
1147         /*
1148          * TODO: bypass the terminate in sriov for now
1149          */
1150         if (amdgpu_sriov_vf(psp->adev))
1151                 return 0;
1152
1153         if (!psp->ras.ras_initialized)
1154                 return 0;
1155
1156         ret = psp_ras_unload(psp);
1157         if (ret)
1158                 return ret;
1159
1160         psp->ras.ras_initialized = false;
1161
1162         /* free ras shared memory */
1163         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1164                         &psp->ras.ras_shared_mc_addr,
1165                         &psp->ras.ras_shared_buf);
1166
1167         return 0;
1168 }
1169
1170 static int psp_ras_initialize(struct psp_context *psp)
1171 {
1172         int ret;
1173
1174         /*
1175          * TODO: bypass the initialize in sriov for now
1176          */
1177         if (amdgpu_sriov_vf(psp->adev))
1178                 return 0;
1179
1180         if (!psp->adev->psp.ta_ras_ucode_size ||
1181             !psp->adev->psp.ta_ras_start_addr) {
1182                 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
1183                 return 0;
1184         }
1185
1186         if (!psp->ras.ras_initialized) {
1187                 ret = psp_ras_init_shared_buf(psp);
1188                 if (ret)
1189                         return ret;
1190         }
1191
1192         ret = psp_ras_load(psp);
1193         if (ret)
1194                 return ret;
1195
1196         return 0;
1197 }
1198
1199 int psp_ras_trigger_error(struct psp_context *psp,
1200                           struct ta_ras_trigger_error_input *info)
1201 {
1202         struct ta_ras_shared_memory *ras_cmd;
1203         int ret;
1204
1205         if (!psp->ras.ras_initialized)
1206                 return -EINVAL;
1207
1208         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1209         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1210
1211         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1212         ras_cmd->ras_in_message.trigger_error = *info;
1213
1214         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1215         if (ret)
1216                 return -EINVAL;
1217
1218         /* If err_event_athub occurs error inject was successful, however
1219            return status from TA is no long reliable */
1220         if (amdgpu_ras_intr_triggered())
1221                 return 0;
1222
1223         return ras_cmd->ras_status;
1224 }
1225 // ras end
1226
1227 // HDCP start
1228 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1229 {
1230         int ret;
1231
1232         /*
1233          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1234          * physical) for hdcp ta <-> Driver
1235          */
1236         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1237                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1238                                       &psp->hdcp_context.hdcp_shared_bo,
1239                                       &psp->hdcp_context.hdcp_shared_mc_addr,
1240                                       &psp->hdcp_context.hdcp_shared_buf);
1241
1242         return ret;
1243 }
1244
1245 static int psp_hdcp_load(struct psp_context *psp)
1246 {
1247         int ret;
1248         struct psp_gfx_cmd_resp *cmd;
1249
1250         /*
1251          * TODO: bypass the loading in sriov for now
1252          */
1253         if (amdgpu_sriov_vf(psp->adev))
1254                 return 0;
1255
1256         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1257         if (!cmd)
1258                 return -ENOMEM;
1259
1260         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1261         memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
1262                psp->ta_hdcp_ucode_size);
1263
1264         psp_prep_ta_load_cmd_buf(cmd,
1265                                  psp->fw_pri_mc_addr,
1266                                  psp->ta_hdcp_ucode_size,
1267                                  psp->hdcp_context.hdcp_shared_mc_addr,
1268                                  PSP_HDCP_SHARED_MEM_SIZE);
1269
1270         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1271
1272         if (!ret) {
1273                 psp->hdcp_context.hdcp_initialized = true;
1274                 psp->hdcp_context.session_id = cmd->resp.session_id;
1275                 mutex_init(&psp->hdcp_context.mutex);
1276         }
1277
1278         kfree(cmd);
1279
1280         return ret;
1281 }
1282 static int psp_hdcp_initialize(struct psp_context *psp)
1283 {
1284         int ret;
1285
1286         /*
1287          * TODO: bypass the initialize in sriov for now
1288          */
1289         if (amdgpu_sriov_vf(psp->adev))
1290                 return 0;
1291
1292         if (!psp->adev->psp.ta_hdcp_ucode_size ||
1293             !psp->adev->psp.ta_hdcp_start_addr) {
1294                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1295                 return 0;
1296         }
1297
1298         if (!psp->hdcp_context.hdcp_initialized) {
1299                 ret = psp_hdcp_init_shared_buf(psp);
1300                 if (ret)
1301                         return ret;
1302         }
1303
1304         ret = psp_hdcp_load(psp);
1305         if (ret)
1306                 return ret;
1307
1308         return 0;
1309 }
1310
1311 static int psp_hdcp_unload(struct psp_context *psp)
1312 {
1313         int ret;
1314         struct psp_gfx_cmd_resp *cmd;
1315
1316         /*
1317          * TODO: bypass the unloading in sriov for now
1318          */
1319         if (amdgpu_sriov_vf(psp->adev))
1320                 return 0;
1321
1322         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1323         if (!cmd)
1324                 return -ENOMEM;
1325
1326         psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1327
1328         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1329
1330         kfree(cmd);
1331
1332         return ret;
1333 }
1334
1335 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1336 {
1337         /*
1338          * TODO: bypass the loading in sriov for now
1339          */
1340         if (amdgpu_sriov_vf(psp->adev))
1341                 return 0;
1342
1343         return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1344 }
1345
1346 static int psp_hdcp_terminate(struct psp_context *psp)
1347 {
1348         int ret;
1349
1350         /*
1351          * TODO: bypass the terminate in sriov for now
1352          */
1353         if (amdgpu_sriov_vf(psp->adev))
1354                 return 0;
1355
1356         if (!psp->hdcp_context.hdcp_initialized) {
1357                 if (psp->hdcp_context.hdcp_shared_buf)
1358                         goto out;
1359                 else
1360                         return 0;
1361         }
1362
1363         ret = psp_hdcp_unload(psp);
1364         if (ret)
1365                 return ret;
1366
1367         psp->hdcp_context.hdcp_initialized = false;
1368
1369 out:
1370         /* free hdcp shared memory */
1371         amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1372                               &psp->hdcp_context.hdcp_shared_mc_addr,
1373                               &psp->hdcp_context.hdcp_shared_buf);
1374
1375         return 0;
1376 }
1377 // HDCP end
1378
1379 // DTM start
1380 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1381 {
1382         int ret;
1383
1384         /*
1385          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1386          * physical) for dtm ta <-> Driver
1387          */
1388         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1389                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1390                                       &psp->dtm_context.dtm_shared_bo,
1391                                       &psp->dtm_context.dtm_shared_mc_addr,
1392                                       &psp->dtm_context.dtm_shared_buf);
1393
1394         return ret;
1395 }
1396
1397 static int psp_dtm_load(struct psp_context *psp)
1398 {
1399         int ret;
1400         struct psp_gfx_cmd_resp *cmd;
1401
1402         /*
1403          * TODO: bypass the loading in sriov for now
1404          */
1405         if (amdgpu_sriov_vf(psp->adev))
1406                 return 0;
1407
1408         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1409         if (!cmd)
1410                 return -ENOMEM;
1411
1412         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1413         memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1414
1415         psp_prep_ta_load_cmd_buf(cmd,
1416                                  psp->fw_pri_mc_addr,
1417                                  psp->ta_dtm_ucode_size,
1418                                  psp->dtm_context.dtm_shared_mc_addr,
1419                                  PSP_DTM_SHARED_MEM_SIZE);
1420
1421         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1422
1423         if (!ret) {
1424                 psp->dtm_context.dtm_initialized = true;
1425                 psp->dtm_context.session_id = cmd->resp.session_id;
1426                 mutex_init(&psp->dtm_context.mutex);
1427         }
1428
1429         kfree(cmd);
1430
1431         return ret;
1432 }
1433
1434 static int psp_dtm_initialize(struct psp_context *psp)
1435 {
1436         int ret;
1437
1438         /*
1439          * TODO: bypass the initialize in sriov for now
1440          */
1441         if (amdgpu_sriov_vf(psp->adev))
1442                 return 0;
1443
1444         if (!psp->adev->psp.ta_dtm_ucode_size ||
1445             !psp->adev->psp.ta_dtm_start_addr) {
1446                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1447                 return 0;
1448         }
1449
1450         if (!psp->dtm_context.dtm_initialized) {
1451                 ret = psp_dtm_init_shared_buf(psp);
1452                 if (ret)
1453                         return ret;
1454         }
1455
1456         ret = psp_dtm_load(psp);
1457         if (ret)
1458                 return ret;
1459
1460         return 0;
1461 }
1462
1463 static int psp_dtm_unload(struct psp_context *psp)
1464 {
1465         int ret;
1466         struct psp_gfx_cmd_resp *cmd;
1467
1468         /*
1469          * TODO: bypass the unloading in sriov for now
1470          */
1471         if (amdgpu_sriov_vf(psp->adev))
1472                 return 0;
1473
1474         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1475         if (!cmd)
1476                 return -ENOMEM;
1477
1478         psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1479
1480         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1481
1482         kfree(cmd);
1483
1484         return ret;
1485 }
1486
1487 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1488 {
1489         /*
1490          * TODO: bypass the loading in sriov for now
1491          */
1492         if (amdgpu_sriov_vf(psp->adev))
1493                 return 0;
1494
1495         return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1496 }
1497
1498 static int psp_dtm_terminate(struct psp_context *psp)
1499 {
1500         int ret;
1501
1502         /*
1503          * TODO: bypass the terminate in sriov for now
1504          */
1505         if (amdgpu_sriov_vf(psp->adev))
1506                 return 0;
1507
1508         if (!psp->dtm_context.dtm_initialized) {
1509                 if (psp->dtm_context.dtm_shared_buf)
1510                         goto out;
1511                 else
1512                         return 0;
1513         }
1514
1515         ret = psp_dtm_unload(psp);
1516         if (ret)
1517                 return ret;
1518
1519         psp->dtm_context.dtm_initialized = false;
1520
1521 out:
1522         /* free hdcp shared memory */
1523         amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1524                               &psp->dtm_context.dtm_shared_mc_addr,
1525                               &psp->dtm_context.dtm_shared_buf);
1526
1527         return 0;
1528 }
1529 // DTM end
1530
1531 // RAP start
1532 static int psp_rap_init_shared_buf(struct psp_context *psp)
1533 {
1534         int ret;
1535
1536         /*
1537          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1538          * physical) for rap ta <-> Driver
1539          */
1540         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1541                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1542                                       &psp->rap_context.rap_shared_bo,
1543                                       &psp->rap_context.rap_shared_mc_addr,
1544                                       &psp->rap_context.rap_shared_buf);
1545
1546         return ret;
1547 }
1548
1549 static int psp_rap_load(struct psp_context *psp)
1550 {
1551         int ret;
1552         struct psp_gfx_cmd_resp *cmd;
1553
1554         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1555         if (!cmd)
1556                 return -ENOMEM;
1557
1558         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1559         memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1560
1561         psp_prep_ta_load_cmd_buf(cmd,
1562                                  psp->fw_pri_mc_addr,
1563                                  psp->ta_rap_ucode_size,
1564                                  psp->rap_context.rap_shared_mc_addr,
1565                                  PSP_RAP_SHARED_MEM_SIZE);
1566
1567         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1568
1569         if (!ret) {
1570                 psp->rap_context.rap_initialized = true;
1571                 psp->rap_context.session_id = cmd->resp.session_id;
1572                 mutex_init(&psp->rap_context.mutex);
1573         }
1574
1575         kfree(cmd);
1576
1577         return ret;
1578 }
1579
1580 static int psp_rap_unload(struct psp_context *psp)
1581 {
1582         int ret;
1583         struct psp_gfx_cmd_resp *cmd;
1584
1585         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1586         if (!cmd)
1587                 return -ENOMEM;
1588
1589         psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1590
1591         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1592
1593         kfree(cmd);
1594
1595         return ret;
1596 }
1597
1598 static int psp_rap_initialize(struct psp_context *psp)
1599 {
1600         int ret;
1601         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1602
1603         /*
1604          * TODO: bypass the initialize in sriov for now
1605          */
1606         if (amdgpu_sriov_vf(psp->adev))
1607                 return 0;
1608
1609         if (!psp->adev->psp.ta_rap_ucode_size ||
1610             !psp->adev->psp.ta_rap_start_addr) {
1611                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1612                 return 0;
1613         }
1614
1615         if (!psp->rap_context.rap_initialized) {
1616                 ret = psp_rap_init_shared_buf(psp);
1617                 if (ret)
1618                         return ret;
1619         }
1620
1621         ret = psp_rap_load(psp);
1622         if (ret)
1623                 return ret;
1624
1625         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1626         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1627                 psp_rap_unload(psp);
1628
1629                 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1630                               &psp->rap_context.rap_shared_mc_addr,
1631                               &psp->rap_context.rap_shared_buf);
1632
1633                 psp->rap_context.rap_initialized = false;
1634
1635                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1636                          ret, status);
1637
1638                 return ret;
1639         }
1640
1641         return 0;
1642 }
1643
1644 static int psp_rap_terminate(struct psp_context *psp)
1645 {
1646         int ret;
1647
1648         if (!psp->rap_context.rap_initialized)
1649                 return 0;
1650
1651         ret = psp_rap_unload(psp);
1652
1653         psp->rap_context.rap_initialized = false;
1654
1655         /* free rap shared memory */
1656         amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1657                               &psp->rap_context.rap_shared_mc_addr,
1658                               &psp->rap_context.rap_shared_buf);
1659
1660         return ret;
1661 }
1662
1663 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1664 {
1665         struct ta_rap_shared_memory *rap_cmd;
1666         int ret = 0;
1667
1668         if (!psp->rap_context.rap_initialized)
1669                 return 0;
1670
1671         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1672             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1673                 return -EINVAL;
1674
1675         mutex_lock(&psp->rap_context.mutex);
1676
1677         rap_cmd = (struct ta_rap_shared_memory *)
1678                   psp->rap_context.rap_shared_buf;
1679         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1680
1681         rap_cmd->cmd_id = ta_cmd_id;
1682         rap_cmd->validation_method_id = METHOD_A;
1683
1684         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1685         if (ret)
1686                 goto out_unlock;
1687
1688         if (status)
1689                 *status = rap_cmd->rap_status;
1690
1691 out_unlock:
1692         mutex_unlock(&psp->rap_context.mutex);
1693
1694         return ret;
1695 }
1696 // RAP end
1697
1698 /* securedisplay start */
1699 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1700 {
1701         int ret;
1702
1703         /*
1704          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1705          * physical) for sa ta <-> Driver
1706          */
1707         ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE,
1708                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1709                                       &psp->securedisplay_context.securedisplay_shared_bo,
1710                                       &psp->securedisplay_context.securedisplay_shared_mc_addr,
1711                                       &psp->securedisplay_context.securedisplay_shared_buf);
1712
1713         return ret;
1714 }
1715
1716 static int psp_securedisplay_load(struct psp_context *psp)
1717 {
1718         int ret;
1719         struct psp_gfx_cmd_resp *cmd;
1720
1721         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1722         if (!cmd)
1723                 return -ENOMEM;
1724
1725         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1726         memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size);
1727
1728         psp_prep_ta_load_cmd_buf(cmd,
1729                                  psp->fw_pri_mc_addr,
1730                                  psp->ta_securedisplay_ucode_size,
1731                                  psp->securedisplay_context.securedisplay_shared_mc_addr,
1732                                  PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
1733
1734         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1735
1736         if (ret)
1737                 goto failed;
1738
1739         psp->securedisplay_context.securedisplay_initialized = true;
1740         psp->securedisplay_context.session_id = cmd->resp.session_id;
1741         mutex_init(&psp->securedisplay_context.mutex);
1742
1743 failed:
1744         kfree(cmd);
1745         return ret;
1746 }
1747
1748 static int psp_securedisplay_unload(struct psp_context *psp)
1749 {
1750         int ret;
1751         struct psp_gfx_cmd_resp *cmd;
1752
1753         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1754         if (!cmd)
1755                 return -ENOMEM;
1756
1757         psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id);
1758
1759         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1760
1761         kfree(cmd);
1762
1763         return ret;
1764 }
1765
1766 static int psp_securedisplay_initialize(struct psp_context *psp)
1767 {
1768         int ret;
1769         struct securedisplay_cmd *securedisplay_cmd;
1770
1771         /*
1772          * TODO: bypass the initialize in sriov for now
1773          */
1774         if (amdgpu_sriov_vf(psp->adev))
1775                 return 0;
1776
1777         if (!psp->adev->psp.ta_securedisplay_ucode_size ||
1778             !psp->adev->psp.ta_securedisplay_start_addr) {
1779                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1780                 return 0;
1781         }
1782
1783         if (!psp->securedisplay_context.securedisplay_initialized) {
1784                 ret = psp_securedisplay_init_shared_buf(psp);
1785                 if (ret)
1786                         return ret;
1787         }
1788
1789         ret = psp_securedisplay_load(psp);
1790         if (ret)
1791                 return ret;
1792
1793         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1794                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1795
1796         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1797         if (ret) {
1798                 psp_securedisplay_unload(psp);
1799
1800                 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1801                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1802                               &psp->securedisplay_context.securedisplay_shared_buf);
1803
1804                 psp->securedisplay_context.securedisplay_initialized = false;
1805
1806                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1807                 return -EINVAL;
1808         }
1809
1810         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1811                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1812                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1813                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1814         }
1815
1816         return 0;
1817 }
1818
1819 static int psp_securedisplay_terminate(struct psp_context *psp)
1820 {
1821         int ret;
1822
1823         /*
1824          * TODO:bypass the terminate in sriov for now
1825          */
1826         if (amdgpu_sriov_vf(psp->adev))
1827                 return 0;
1828
1829         if (!psp->securedisplay_context.securedisplay_initialized)
1830                 return 0;
1831
1832         ret = psp_securedisplay_unload(psp);
1833         if (ret)
1834                 return ret;
1835
1836         psp->securedisplay_context.securedisplay_initialized = false;
1837
1838         /* free securedisplay shared memory */
1839         amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1840                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1841                               &psp->securedisplay_context.securedisplay_shared_buf);
1842
1843         return ret;
1844 }
1845
1846 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1847 {
1848         int ret;
1849
1850         if (!psp->securedisplay_context.securedisplay_initialized)
1851                 return -EINVAL;
1852
1853         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1854             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1855                 return -EINVAL;
1856
1857         mutex_lock(&psp->securedisplay_context.mutex);
1858
1859         ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id);
1860
1861         mutex_unlock(&psp->securedisplay_context.mutex);
1862
1863         return ret;
1864 }
1865 /* SECUREDISPLAY end */
1866
1867 static int psp_hw_start(struct psp_context *psp)
1868 {
1869         struct amdgpu_device *adev = psp->adev;
1870         int ret;
1871
1872         if (!amdgpu_sriov_vf(adev)) {
1873                 if (psp->kdb_bin_size &&
1874                     (psp->funcs->bootloader_load_kdb != NULL)) {
1875                         ret = psp_bootloader_load_kdb(psp);
1876                         if (ret) {
1877                                 DRM_ERROR("PSP load kdb failed!\n");
1878                                 return ret;
1879                         }
1880                 }
1881
1882                 if (psp->spl_bin_size) {
1883                         ret = psp_bootloader_load_spl(psp);
1884                         if (ret) {
1885                                 DRM_ERROR("PSP load spl failed!\n");
1886                                 return ret;
1887                         }
1888                 }
1889
1890                 ret = psp_bootloader_load_sysdrv(psp);
1891                 if (ret) {
1892                         DRM_ERROR("PSP load sysdrv failed!\n");
1893                         return ret;
1894                 }
1895
1896                 ret = psp_bootloader_load_sos(psp);
1897                 if (ret) {
1898                         DRM_ERROR("PSP load sos failed!\n");
1899                         return ret;
1900                 }
1901         }
1902
1903         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1904         if (ret) {
1905                 DRM_ERROR("PSP create ring failed!\n");
1906                 return ret;
1907         }
1908
1909         ret = psp_boot_config_set(adev);
1910         if (ret) {
1911                 DRM_WARN("PSP set boot config@\n");
1912         }
1913
1914         ret = psp_tmr_init(psp);
1915         if (ret) {
1916                 DRM_ERROR("PSP tmr init failed!\n");
1917                 return ret;
1918         }
1919
1920         /*
1921          * For ASICs with DF Cstate management centralized
1922          * to PMFW, TMR setup should be performed after PMFW
1923          * loaded and before other non-psp firmware loaded.
1924          */
1925         if (psp->pmfw_centralized_cstate_management) {
1926                 ret = psp_load_smu_fw(psp);
1927                 if (ret)
1928                         return ret;
1929         }
1930
1931         ret = psp_tmr_load(psp);
1932         if (ret) {
1933                 DRM_ERROR("PSP load tmr failed!\n");
1934                 return ret;
1935         }
1936
1937         return 0;
1938 }
1939
1940 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1941                            enum psp_gfx_fw_type *type)
1942 {
1943         switch (ucode->ucode_id) {
1944         case AMDGPU_UCODE_ID_SDMA0:
1945                 *type = GFX_FW_TYPE_SDMA0;
1946                 break;
1947         case AMDGPU_UCODE_ID_SDMA1:
1948                 *type = GFX_FW_TYPE_SDMA1;
1949                 break;
1950         case AMDGPU_UCODE_ID_SDMA2:
1951                 *type = GFX_FW_TYPE_SDMA2;
1952                 break;
1953         case AMDGPU_UCODE_ID_SDMA3:
1954                 *type = GFX_FW_TYPE_SDMA3;
1955                 break;
1956         case AMDGPU_UCODE_ID_SDMA4:
1957                 *type = GFX_FW_TYPE_SDMA4;
1958                 break;
1959         case AMDGPU_UCODE_ID_SDMA5:
1960                 *type = GFX_FW_TYPE_SDMA5;
1961                 break;
1962         case AMDGPU_UCODE_ID_SDMA6:
1963                 *type = GFX_FW_TYPE_SDMA6;
1964                 break;
1965         case AMDGPU_UCODE_ID_SDMA7:
1966                 *type = GFX_FW_TYPE_SDMA7;
1967                 break;
1968         case AMDGPU_UCODE_ID_CP_MES:
1969                 *type = GFX_FW_TYPE_CP_MES;
1970                 break;
1971         case AMDGPU_UCODE_ID_CP_MES_DATA:
1972                 *type = GFX_FW_TYPE_MES_STACK;
1973                 break;
1974         case AMDGPU_UCODE_ID_CP_CE:
1975                 *type = GFX_FW_TYPE_CP_CE;
1976                 break;
1977         case AMDGPU_UCODE_ID_CP_PFP:
1978                 *type = GFX_FW_TYPE_CP_PFP;
1979                 break;
1980         case AMDGPU_UCODE_ID_CP_ME:
1981                 *type = GFX_FW_TYPE_CP_ME;
1982                 break;
1983         case AMDGPU_UCODE_ID_CP_MEC1:
1984                 *type = GFX_FW_TYPE_CP_MEC;
1985                 break;
1986         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1987                 *type = GFX_FW_TYPE_CP_MEC_ME1;
1988                 break;
1989         case AMDGPU_UCODE_ID_CP_MEC2:
1990                 *type = GFX_FW_TYPE_CP_MEC;
1991                 break;
1992         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1993                 *type = GFX_FW_TYPE_CP_MEC_ME2;
1994                 break;
1995         case AMDGPU_UCODE_ID_RLC_G:
1996                 *type = GFX_FW_TYPE_RLC_G;
1997                 break;
1998         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1999                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2000                 break;
2001         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2002                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2003                 break;
2004         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2005                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2006                 break;
2007         case AMDGPU_UCODE_ID_RLC_IRAM:
2008                 *type = GFX_FW_TYPE_RLC_IRAM;
2009                 break;
2010         case AMDGPU_UCODE_ID_RLC_DRAM:
2011                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2012                 break;
2013         case AMDGPU_UCODE_ID_SMC:
2014                 *type = GFX_FW_TYPE_SMU;
2015                 break;
2016         case AMDGPU_UCODE_ID_UVD:
2017                 *type = GFX_FW_TYPE_UVD;
2018                 break;
2019         case AMDGPU_UCODE_ID_UVD1:
2020                 *type = GFX_FW_TYPE_UVD1;
2021                 break;
2022         case AMDGPU_UCODE_ID_VCE:
2023                 *type = GFX_FW_TYPE_VCE;
2024                 break;
2025         case AMDGPU_UCODE_ID_VCN:
2026                 *type = GFX_FW_TYPE_VCN;
2027                 break;
2028         case AMDGPU_UCODE_ID_VCN1:
2029                 *type = GFX_FW_TYPE_VCN1;
2030                 break;
2031         case AMDGPU_UCODE_ID_DMCU_ERAM:
2032                 *type = GFX_FW_TYPE_DMCU_ERAM;
2033                 break;
2034         case AMDGPU_UCODE_ID_DMCU_INTV:
2035                 *type = GFX_FW_TYPE_DMCU_ISR;
2036                 break;
2037         case AMDGPU_UCODE_ID_VCN0_RAM:
2038                 *type = GFX_FW_TYPE_VCN0_RAM;
2039                 break;
2040         case AMDGPU_UCODE_ID_VCN1_RAM:
2041                 *type = GFX_FW_TYPE_VCN1_RAM;
2042                 break;
2043         case AMDGPU_UCODE_ID_DMCUB:
2044                 *type = GFX_FW_TYPE_DMUB;
2045                 break;
2046         case AMDGPU_UCODE_ID_MAXIMUM:
2047         default:
2048                 return -EINVAL;
2049         }
2050
2051         return 0;
2052 }
2053
2054 static void psp_print_fw_hdr(struct psp_context *psp,
2055                              struct amdgpu_firmware_info *ucode)
2056 {
2057         struct amdgpu_device *adev = psp->adev;
2058         struct common_firmware_header *hdr;
2059
2060         switch (ucode->ucode_id) {
2061         case AMDGPU_UCODE_ID_SDMA0:
2062         case AMDGPU_UCODE_ID_SDMA1:
2063         case AMDGPU_UCODE_ID_SDMA2:
2064         case AMDGPU_UCODE_ID_SDMA3:
2065         case AMDGPU_UCODE_ID_SDMA4:
2066         case AMDGPU_UCODE_ID_SDMA5:
2067         case AMDGPU_UCODE_ID_SDMA6:
2068         case AMDGPU_UCODE_ID_SDMA7:
2069                 hdr = (struct common_firmware_header *)
2070                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2071                 amdgpu_ucode_print_sdma_hdr(hdr);
2072                 break;
2073         case AMDGPU_UCODE_ID_CP_CE:
2074                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2075                 amdgpu_ucode_print_gfx_hdr(hdr);
2076                 break;
2077         case AMDGPU_UCODE_ID_CP_PFP:
2078                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2079                 amdgpu_ucode_print_gfx_hdr(hdr);
2080                 break;
2081         case AMDGPU_UCODE_ID_CP_ME:
2082                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2083                 amdgpu_ucode_print_gfx_hdr(hdr);
2084                 break;
2085         case AMDGPU_UCODE_ID_CP_MEC1:
2086                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2087                 amdgpu_ucode_print_gfx_hdr(hdr);
2088                 break;
2089         case AMDGPU_UCODE_ID_RLC_G:
2090                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2091                 amdgpu_ucode_print_rlc_hdr(hdr);
2092                 break;
2093         case AMDGPU_UCODE_ID_SMC:
2094                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2095                 amdgpu_ucode_print_smc_hdr(hdr);
2096                 break;
2097         default:
2098                 break;
2099         }
2100 }
2101
2102 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2103                                        struct psp_gfx_cmd_resp *cmd)
2104 {
2105         int ret;
2106         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2107
2108         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
2109
2110         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2111         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2112         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2113         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2114
2115         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2116         if (ret)
2117                 DRM_ERROR("Unknown firmware type\n");
2118
2119         return ret;
2120 }
2121
2122 static int psp_execute_np_fw_load(struct psp_context *psp,
2123                                   struct amdgpu_firmware_info *ucode)
2124 {
2125         int ret = 0;
2126
2127         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
2128         if (ret)
2129                 return ret;
2130
2131         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
2132                                  psp->fence_buf_mc_addr);
2133
2134         return ret;
2135 }
2136
2137 static int psp_load_smu_fw(struct psp_context *psp)
2138 {
2139         int ret;
2140         struct amdgpu_device *adev = psp->adev;
2141         struct amdgpu_firmware_info *ucode =
2142                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2143         struct amdgpu_ras *ras = psp->ras.ras;
2144
2145         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2146                 return 0;
2147
2148         if ((amdgpu_in_reset(adev) &&
2149              ras && adev->ras_features &&
2150              (adev->asic_type == CHIP_ARCTURUS ||
2151               adev->asic_type == CHIP_VEGA20)) ||
2152              (adev->in_runpm &&
2153               adev->asic_type >= CHIP_NAVI10 &&
2154               adev->asic_type <= CHIP_NAVI12)) {
2155                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2156                 if (ret) {
2157                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2158                 }
2159         }
2160
2161         ret = psp_execute_np_fw_load(psp, ucode);
2162
2163         if (ret)
2164                 DRM_ERROR("PSP load smu failed!\n");
2165
2166         return ret;
2167 }
2168
2169 static bool fw_load_skip_check(struct psp_context *psp,
2170                                struct amdgpu_firmware_info *ucode)
2171 {
2172         if (!ucode->fw)
2173                 return true;
2174
2175         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2176             (psp_smu_reload_quirk(psp) ||
2177              psp->autoload_supported ||
2178              psp->pmfw_centralized_cstate_management))
2179                 return true;
2180
2181         if (amdgpu_sriov_vf(psp->adev) &&
2182            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2183             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2184             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2185             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2186             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2187             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2188             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2189             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2190             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2191             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2192             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2193             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2194             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2195                 /*skip ucode loading in SRIOV VF */
2196                 return true;
2197
2198         if (psp->autoload_supported &&
2199             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2200              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2201                 /* skip mec JT when autoload is enabled */
2202                 return true;
2203
2204         return false;
2205 }
2206
2207 int psp_load_fw_list(struct psp_context *psp,
2208                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2209 {
2210         int ret = 0, i;
2211         struct amdgpu_firmware_info *ucode;
2212
2213         for (i = 0; i < ucode_count; ++i) {
2214                 ucode = ucode_list[i];
2215                 psp_print_fw_hdr(psp, ucode);
2216                 ret = psp_execute_np_fw_load(psp, ucode);
2217                 if (ret)
2218                         return ret;
2219         }
2220         return ret;
2221 }
2222
2223 static int psp_np_fw_load(struct psp_context *psp)
2224 {
2225         int i, ret;
2226         struct amdgpu_firmware_info *ucode;
2227         struct amdgpu_device *adev = psp->adev;
2228
2229         if (psp->autoload_supported &&
2230             !psp->pmfw_centralized_cstate_management) {
2231                 ret = psp_load_smu_fw(psp);
2232                 if (ret)
2233                         return ret;
2234         }
2235
2236         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2237                 ucode = &adev->firmware.ucode[i];
2238
2239                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2240                     !fw_load_skip_check(psp, ucode)) {
2241                         ret = psp_load_smu_fw(psp);
2242                         if (ret)
2243                                 return ret;
2244                         continue;
2245                 }
2246
2247                 if (fw_load_skip_check(psp, ucode))
2248                         continue;
2249
2250                 if (psp->autoload_supported &&
2251                     (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2252                      adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2253                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2254                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2255                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2256                         /* PSP only receive one SDMA fw for sienna_cichlid,
2257                          * as all four sdma fw are same */
2258                         continue;
2259
2260                 psp_print_fw_hdr(psp, ucode);
2261
2262                 ret = psp_execute_np_fw_load(psp, ucode);
2263                 if (ret)
2264                         return ret;
2265
2266                 /* Start rlc autoload after psp recieved all the gfx firmware */
2267                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2268                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2269                         ret = psp_rlc_autoload_start(psp);
2270                         if (ret) {
2271                                 DRM_ERROR("Failed to start rlc autoload\n");
2272                                 return ret;
2273                         }
2274                 }
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int psp_load_fw(struct amdgpu_device *adev)
2281 {
2282         int ret;
2283         struct psp_context *psp = &adev->psp;
2284
2285         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2286                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2287                 goto skip_memalloc;
2288         }
2289
2290         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2291         if (!psp->cmd)
2292                 return -ENOMEM;
2293
2294         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2295                                         AMDGPU_GEM_DOMAIN_GTT,
2296                                         &psp->fw_pri_bo,
2297                                         &psp->fw_pri_mc_addr,
2298                                         &psp->fw_pri_buf);
2299         if (ret)
2300                 goto failed;
2301
2302         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2303                                         AMDGPU_GEM_DOMAIN_VRAM,
2304                                         &psp->fence_buf_bo,
2305                                         &psp->fence_buf_mc_addr,
2306                                         &psp->fence_buf);
2307         if (ret)
2308                 goto failed;
2309
2310         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2311                                       AMDGPU_GEM_DOMAIN_VRAM,
2312                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2313                                       (void **)&psp->cmd_buf_mem);
2314         if (ret)
2315                 goto failed;
2316
2317         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2318
2319         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2320         if (ret) {
2321                 DRM_ERROR("PSP ring init failed!\n");
2322                 goto failed;
2323         }
2324
2325 skip_memalloc:
2326         ret = psp_hw_start(psp);
2327         if (ret)
2328                 goto failed;
2329
2330         ret = psp_np_fw_load(psp);
2331         if (ret)
2332                 goto failed;
2333
2334         ret = psp_asd_load(psp);
2335         if (ret) {
2336                 DRM_ERROR("PSP load asd failed!\n");
2337                 return ret;
2338         }
2339
2340         ret = psp_rl_load(adev);
2341         if (ret) {
2342                 DRM_ERROR("PSP load RL failed!\n");
2343                 return ret;
2344         }
2345
2346         if (psp->adev->psp.ta_fw) {
2347                 ret = psp_ras_initialize(psp);
2348                 if (ret)
2349                         dev_err(psp->adev->dev,
2350                                         "RAS: Failed to initialize RAS\n");
2351
2352                 ret = psp_hdcp_initialize(psp);
2353                 if (ret)
2354                         dev_err(psp->adev->dev,
2355                                 "HDCP: Failed to initialize HDCP\n");
2356
2357                 ret = psp_dtm_initialize(psp);
2358                 if (ret)
2359                         dev_err(psp->adev->dev,
2360                                 "DTM: Failed to initialize DTM\n");
2361
2362                 ret = psp_rap_initialize(psp);
2363                 if (ret)
2364                         dev_err(psp->adev->dev,
2365                                 "RAP: Failed to initialize RAP\n");
2366
2367                 ret = psp_securedisplay_initialize(psp);
2368                 if (ret)
2369                         dev_err(psp->adev->dev,
2370                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2371         }
2372
2373         return 0;
2374
2375 failed:
2376         /*
2377          * all cleanup jobs (xgmi terminate, ras terminate,
2378          * ring destroy, cmd/fence/fw buffers destory,
2379          * psp->cmd destory) are delayed to psp_hw_fini
2380          */
2381         return ret;
2382 }
2383
2384 static int psp_hw_init(void *handle)
2385 {
2386         int ret;
2387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2388
2389         mutex_lock(&adev->firmware.mutex);
2390         /*
2391          * This sequence is just used on hw_init only once, no need on
2392          * resume.
2393          */
2394         ret = amdgpu_ucode_init_bo(adev);
2395         if (ret)
2396                 goto failed;
2397
2398         ret = psp_load_fw(adev);
2399         if (ret) {
2400                 DRM_ERROR("PSP firmware loading failed\n");
2401                 goto failed;
2402         }
2403
2404         mutex_unlock(&adev->firmware.mutex);
2405         return 0;
2406
2407 failed:
2408         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2409         mutex_unlock(&adev->firmware.mutex);
2410         return -EINVAL;
2411 }
2412
2413 static int psp_hw_fini(void *handle)
2414 {
2415         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2416         struct psp_context *psp = &adev->psp;
2417
2418         if (psp->adev->psp.ta_fw) {
2419                 psp_ras_terminate(psp);
2420                 psp_securedisplay_terminate(psp);
2421                 psp_rap_terminate(psp);
2422                 psp_dtm_terminate(psp);
2423                 psp_hdcp_terminate(psp);
2424         }
2425
2426         psp_asd_unload(psp);
2427
2428         psp_tmr_terminate(psp);
2429         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2430
2431         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2432                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2433         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2434                               &psp->fence_buf_mc_addr, &psp->fence_buf);
2435         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2436                               (void **)&psp->cmd_buf_mem);
2437
2438         kfree(psp->cmd);
2439         psp->cmd = NULL;
2440
2441         return 0;
2442 }
2443
2444 static int psp_suspend(void *handle)
2445 {
2446         int ret;
2447         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2448         struct psp_context *psp = &adev->psp;
2449
2450         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2451             psp->xgmi_context.initialized == 1) {
2452                 ret = psp_xgmi_terminate(psp);
2453                 if (ret) {
2454                         DRM_ERROR("Failed to terminate xgmi ta\n");
2455                         return ret;
2456                 }
2457         }
2458
2459         if (psp->adev->psp.ta_fw) {
2460                 ret = psp_ras_terminate(psp);
2461                 if (ret) {
2462                         DRM_ERROR("Failed to terminate ras ta\n");
2463                         return ret;
2464                 }
2465                 ret = psp_hdcp_terminate(psp);
2466                 if (ret) {
2467                         DRM_ERROR("Failed to terminate hdcp ta\n");
2468                         return ret;
2469                 }
2470                 ret = psp_dtm_terminate(psp);
2471                 if (ret) {
2472                         DRM_ERROR("Failed to terminate dtm ta\n");
2473                         return ret;
2474                 }
2475                 ret = psp_rap_terminate(psp);
2476                 if (ret) {
2477                         DRM_ERROR("Failed to terminate rap ta\n");
2478                         return ret;
2479                 }
2480                 ret = psp_securedisplay_terminate(psp);
2481                 if (ret) {
2482                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2483                         return ret;
2484                 }
2485         }
2486
2487         ret = psp_asd_unload(psp);
2488         if (ret) {
2489                 DRM_ERROR("Failed to unload asd\n");
2490                 return ret;
2491         }
2492
2493         ret = psp_tmr_terminate(psp);
2494         if (ret) {
2495                 DRM_ERROR("Failed to terminate tmr\n");
2496                 return ret;
2497         }
2498
2499         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2500         if (ret) {
2501                 DRM_ERROR("PSP ring stop failed\n");
2502                 return ret;
2503         }
2504
2505         return 0;
2506 }
2507
2508 static int psp_resume(void *handle)
2509 {
2510         int ret;
2511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2512         struct psp_context *psp = &adev->psp;
2513
2514         DRM_INFO("PSP is resuming...\n");
2515
2516         ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2517         if (ret) {
2518                 DRM_ERROR("Failed to process memory training!\n");
2519                 return ret;
2520         }
2521
2522         mutex_lock(&adev->firmware.mutex);
2523
2524         ret = psp_hw_start(psp);
2525         if (ret)
2526                 goto failed;
2527
2528         ret = psp_np_fw_load(psp);
2529         if (ret)
2530                 goto failed;
2531
2532         ret = psp_asd_load(psp);
2533         if (ret) {
2534                 DRM_ERROR("PSP load asd failed!\n");
2535                 goto failed;
2536         }
2537
2538         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2539                 ret = psp_xgmi_initialize(psp);
2540                 /* Warning the XGMI seesion initialize failure
2541                  * Instead of stop driver initialization
2542                  */
2543                 if (ret)
2544                         dev_err(psp->adev->dev,
2545                                 "XGMI: Failed to initialize XGMI session\n");
2546         }
2547
2548         if (psp->adev->psp.ta_fw) {
2549                 ret = psp_ras_initialize(psp);
2550                 if (ret)
2551                         dev_err(psp->adev->dev,
2552                                         "RAS: Failed to initialize RAS\n");
2553
2554                 ret = psp_hdcp_initialize(psp);
2555                 if (ret)
2556                         dev_err(psp->adev->dev,
2557                                 "HDCP: Failed to initialize HDCP\n");
2558
2559                 ret = psp_dtm_initialize(psp);
2560                 if (ret)
2561                         dev_err(psp->adev->dev,
2562                                 "DTM: Failed to initialize DTM\n");
2563
2564                 ret = psp_rap_initialize(psp);
2565                 if (ret)
2566                         dev_err(psp->adev->dev,
2567                                 "RAP: Failed to initialize RAP\n");
2568
2569                 ret = psp_securedisplay_initialize(psp);
2570                 if (ret)
2571                         dev_err(psp->adev->dev,
2572                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2573         }
2574
2575         mutex_unlock(&adev->firmware.mutex);
2576
2577         return 0;
2578
2579 failed:
2580         DRM_ERROR("PSP resume failed\n");
2581         mutex_unlock(&adev->firmware.mutex);
2582         return ret;
2583 }
2584
2585 int psp_gpu_reset(struct amdgpu_device *adev)
2586 {
2587         int ret;
2588
2589         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2590                 return 0;
2591
2592         mutex_lock(&adev->psp.mutex);
2593         ret = psp_mode1_reset(&adev->psp);
2594         mutex_unlock(&adev->psp.mutex);
2595
2596         return ret;
2597 }
2598
2599 int psp_rlc_autoload_start(struct psp_context *psp)
2600 {
2601         int ret;
2602         struct psp_gfx_cmd_resp *cmd;
2603
2604         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2605         if (!cmd)
2606                 return -ENOMEM;
2607
2608         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2609
2610         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2611                                  psp->fence_buf_mc_addr);
2612         kfree(cmd);
2613         return ret;
2614 }
2615
2616 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2617                         uint64_t cmd_gpu_addr, int cmd_size)
2618 {
2619         struct amdgpu_firmware_info ucode = {0};
2620
2621         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2622                 AMDGPU_UCODE_ID_VCN0_RAM;
2623         ucode.mc_addr = cmd_gpu_addr;
2624         ucode.ucode_size = cmd_size;
2625
2626         return psp_execute_np_fw_load(&adev->psp, &ucode);
2627 }
2628
2629 int psp_ring_cmd_submit(struct psp_context *psp,
2630                         uint64_t cmd_buf_mc_addr,
2631                         uint64_t fence_mc_addr,
2632                         int index)
2633 {
2634         unsigned int psp_write_ptr_reg = 0;
2635         struct psp_gfx_rb_frame *write_frame;
2636         struct psp_ring *ring = &psp->km_ring;
2637         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2638         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2639                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2640         struct amdgpu_device *adev = psp->adev;
2641         uint32_t ring_size_dw = ring->ring_size / 4;
2642         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2643
2644         /* KM (GPCOM) prepare write pointer */
2645         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2646
2647         /* Update KM RB frame pointer to new frame */
2648         /* write_frame ptr increments by size of rb_frame in bytes */
2649         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2650         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2651                 write_frame = ring_buffer_start;
2652         else
2653                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2654         /* Check invalid write_frame ptr address */
2655         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2656                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2657                           ring_buffer_start, ring_buffer_end, write_frame);
2658                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2659                 return -EINVAL;
2660         }
2661
2662         /* Initialize KM RB frame */
2663         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2664
2665         /* Update KM RB frame */
2666         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2667         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2668         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2669         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2670         write_frame->fence_value = index;
2671         amdgpu_asic_flush_hdp(adev, NULL);
2672
2673         /* Update the write Pointer in DWORDs */
2674         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2675         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2676         return 0;
2677 }
2678
2679 int psp_init_asd_microcode(struct psp_context *psp,
2680                            const char *chip_name)
2681 {
2682         struct amdgpu_device *adev = psp->adev;
2683         char fw_name[PSP_FW_NAME_LEN];
2684         const struct psp_firmware_header_v1_0 *asd_hdr;
2685         int err = 0;
2686
2687         if (!chip_name) {
2688                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2689                 return -EINVAL;
2690         }
2691
2692         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2693         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2694         if (err)
2695                 goto out;
2696
2697         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2698         if (err)
2699                 goto out;
2700
2701         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2702         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2703         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
2704         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2705         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2706                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2707         return 0;
2708 out:
2709         dev_err(adev->dev, "fail to initialize asd microcode\n");
2710         release_firmware(adev->psp.asd_fw);
2711         adev->psp.asd_fw = NULL;
2712         return err;
2713 }
2714
2715 int psp_init_toc_microcode(struct psp_context *psp,
2716                            const char *chip_name)
2717 {
2718         struct amdgpu_device *adev = psp->adev;
2719         char fw_name[30];
2720         const struct psp_firmware_header_v1_0 *toc_hdr;
2721         int err = 0;
2722
2723         if (!chip_name) {
2724                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2725                 return -EINVAL;
2726         }
2727
2728         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2729         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2730         if (err)
2731                 goto out;
2732
2733         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2734         if (err)
2735                 goto out;
2736
2737         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2738         adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2739         adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
2740         adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2741         adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2742                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2743         return 0;
2744 out:
2745         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2746         release_firmware(adev->psp.toc_fw);
2747         adev->psp.toc_fw = NULL;
2748         return err;
2749 }
2750
2751 int psp_init_sos_microcode(struct psp_context *psp,
2752                            const char *chip_name)
2753 {
2754         struct amdgpu_device *adev = psp->adev;
2755         char fw_name[PSP_FW_NAME_LEN];
2756         const struct psp_firmware_header_v1_0 *sos_hdr;
2757         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2758         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2759         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2760         int err = 0;
2761
2762         if (!chip_name) {
2763                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2764                 return -EINVAL;
2765         }
2766
2767         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2768         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2769         if (err)
2770                 goto out;
2771
2772         err = amdgpu_ucode_validate(adev->psp.sos_fw);
2773         if (err)
2774                 goto out;
2775
2776         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2777         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2778
2779         switch (sos_hdr->header.header_version_major) {
2780         case 1:
2781                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2782                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
2783                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
2784                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
2785                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2786                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2787                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2788                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
2789                 if (sos_hdr->header.header_version_minor == 1) {
2790                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2791                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
2792                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2793                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
2794                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
2795                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2796                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
2797                 }
2798                 if (sos_hdr->header.header_version_minor == 2) {
2799                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2800                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
2801                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2802                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
2803                 }
2804                 if (sos_hdr->header.header_version_minor == 3) {
2805                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2806                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
2807                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2808                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
2809                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
2810                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2811                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
2812                         adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
2813                         adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2814                                 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
2815                         adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes);
2816                         adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2817                                 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes);
2818                 }
2819                 break;
2820         default:
2821                 dev_err(adev->dev,
2822                         "unsupported psp sos firmware\n");
2823                 err = -EINVAL;
2824                 goto out;
2825         }
2826
2827         return 0;
2828 out:
2829         dev_err(adev->dev,
2830                 "failed to init sos firmware\n");
2831         release_firmware(adev->psp.sos_fw);
2832         adev->psp.sos_fw = NULL;
2833
2834         return err;
2835 }
2836
2837 static int parse_ta_bin_descriptor(struct psp_context *psp,
2838                                    const struct ta_fw_bin_desc *desc,
2839                                    const struct ta_firmware_header_v2_0 *ta_hdr)
2840 {
2841         uint8_t *ucode_start_addr  = NULL;
2842
2843         if (!psp || !desc || !ta_hdr)
2844                 return -EINVAL;
2845
2846         ucode_start_addr  = (uint8_t *)ta_hdr +
2847                             le32_to_cpu(desc->offset_bytes) +
2848                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2849
2850         switch (desc->fw_type) {
2851         case TA_FW_TYPE_PSP_ASD:
2852                 psp->asd_fw_version        = le32_to_cpu(desc->fw_version);
2853                 psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
2854                 psp->asd_ucode_size        = le32_to_cpu(desc->size_bytes);
2855                 psp->asd_start_addr        = ucode_start_addr;
2856                 break;
2857         case TA_FW_TYPE_PSP_XGMI:
2858                 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
2859                 psp->ta_xgmi_ucode_size    = le32_to_cpu(desc->size_bytes);
2860                 psp->ta_xgmi_start_addr    = ucode_start_addr;
2861                 break;
2862         case TA_FW_TYPE_PSP_RAS:
2863                 psp->ta_ras_ucode_version  = le32_to_cpu(desc->fw_version);
2864                 psp->ta_ras_ucode_size     = le32_to_cpu(desc->size_bytes);
2865                 psp->ta_ras_start_addr     = ucode_start_addr;
2866                 break;
2867         case TA_FW_TYPE_PSP_HDCP:
2868                 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
2869                 psp->ta_hdcp_ucode_size    = le32_to_cpu(desc->size_bytes);
2870                 psp->ta_hdcp_start_addr    = ucode_start_addr;
2871                 break;
2872         case TA_FW_TYPE_PSP_DTM:
2873                 psp->ta_dtm_ucode_version  = le32_to_cpu(desc->fw_version);
2874                 psp->ta_dtm_ucode_size     = le32_to_cpu(desc->size_bytes);
2875                 psp->ta_dtm_start_addr     = ucode_start_addr;
2876                 break;
2877         case TA_FW_TYPE_PSP_RAP:
2878                 psp->ta_rap_ucode_version  = le32_to_cpu(desc->fw_version);
2879                 psp->ta_rap_ucode_size     = le32_to_cpu(desc->size_bytes);
2880                 psp->ta_rap_start_addr     = ucode_start_addr;
2881                 break;
2882         case TA_FW_TYPE_PSP_SECUREDISPLAY:
2883                 psp->ta_securedisplay_ucode_version  = le32_to_cpu(desc->fw_version);
2884                 psp->ta_securedisplay_ucode_size     = le32_to_cpu(desc->size_bytes);
2885                 psp->ta_securedisplay_start_addr     = ucode_start_addr;
2886                 break;
2887         default:
2888                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
2889                 break;
2890         }
2891
2892         return 0;
2893 }
2894
2895 int psp_init_ta_microcode(struct psp_context *psp,
2896                           const char *chip_name)
2897 {
2898         struct amdgpu_device *adev = psp->adev;
2899         char fw_name[PSP_FW_NAME_LEN];
2900         const struct ta_firmware_header_v2_0 *ta_hdr;
2901         int err = 0;
2902         int ta_index = 0;
2903
2904         if (!chip_name) {
2905                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
2906                 return -EINVAL;
2907         }
2908
2909         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
2910         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
2911         if (err)
2912                 goto out;
2913
2914         err = amdgpu_ucode_validate(adev->psp.ta_fw);
2915         if (err)
2916                 goto out;
2917
2918         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
2919
2920         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
2921                 dev_err(adev->dev, "unsupported TA header version\n");
2922                 err = -EINVAL;
2923                 goto out;
2924         }
2925
2926         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
2927                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
2928                 err = -EINVAL;
2929                 goto out;
2930         }
2931
2932         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
2933                 err = parse_ta_bin_descriptor(psp,
2934                                               &ta_hdr->ta_fw_bin[ta_index],
2935                                               ta_hdr);
2936                 if (err)
2937                         goto out;
2938         }
2939
2940         return 0;
2941 out:
2942         dev_err(adev->dev, "fail to initialize ta microcode\n");
2943         release_firmware(adev->psp.ta_fw);
2944         adev->psp.ta_fw = NULL;
2945         return err;
2946 }
2947
2948 static int psp_set_clockgating_state(void *handle,
2949                                      enum amd_clockgating_state state)
2950 {
2951         return 0;
2952 }
2953
2954 static int psp_set_powergating_state(void *handle,
2955                                      enum amd_powergating_state state)
2956 {
2957         return 0;
2958 }
2959
2960 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
2961                                          struct device_attribute *attr,
2962                                          char *buf)
2963 {
2964         struct drm_device *ddev = dev_get_drvdata(dev);
2965         struct amdgpu_device *adev = drm_to_adev(ddev);
2966         uint32_t fw_ver;
2967         int ret;
2968
2969         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2970                 DRM_INFO("PSP block is not ready yet.");
2971                 return -EBUSY;
2972         }
2973
2974         mutex_lock(&adev->psp.mutex);
2975         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
2976         mutex_unlock(&adev->psp.mutex);
2977
2978         if (ret) {
2979                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
2980                 return ret;
2981         }
2982
2983         return sysfs_emit(buf, "%x\n", fw_ver);
2984 }
2985
2986 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
2987                                                        struct device_attribute *attr,
2988                                                        const char *buf,
2989                                                        size_t count)
2990 {
2991         struct drm_device *ddev = dev_get_drvdata(dev);
2992         struct amdgpu_device *adev = drm_to_adev(ddev);
2993         void *cpu_addr;
2994         dma_addr_t dma_addr;
2995         int ret;
2996         char fw_name[100];
2997         const struct firmware *usbc_pd_fw;
2998
2999         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3000                 DRM_INFO("PSP block is not ready yet.");
3001                 return -EBUSY;
3002         }
3003
3004         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3005         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3006         if (ret)
3007                 goto fail;
3008
3009         /* We need contiguous physical mem to place the FW  for psp to access */
3010         cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
3011
3012         ret = dma_mapping_error(adev->dev, dma_addr);
3013         if (ret)
3014                 goto rel_buf;
3015
3016         memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3017
3018         /*
3019          * x86 specific workaround.
3020          * Without it the buffer is invisible in PSP.
3021          *
3022          * TODO Remove once PSP starts snooping CPU cache
3023          */
3024 #ifdef CONFIG_X86
3025         clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
3026 #endif
3027
3028         mutex_lock(&adev->psp.mutex);
3029         ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
3030         mutex_unlock(&adev->psp.mutex);
3031
3032 rel_buf:
3033         dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
3034         release_firmware(usbc_pd_fw);
3035
3036 fail:
3037         if (ret) {
3038                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3039                 return ret;
3040         }
3041
3042         return count;
3043 }
3044
3045 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3046                    psp_usbc_pd_fw_sysfs_read,
3047                    psp_usbc_pd_fw_sysfs_write);
3048
3049
3050
3051 const struct amd_ip_funcs psp_ip_funcs = {
3052         .name = "psp",
3053         .early_init = psp_early_init,
3054         .late_init = NULL,
3055         .sw_init = psp_sw_init,
3056         .sw_fini = psp_sw_fini,
3057         .hw_init = psp_hw_init,
3058         .hw_fini = psp_hw_fini,
3059         .suspend = psp_suspend,
3060         .resume = psp_resume,
3061         .is_idle = NULL,
3062         .check_soft_reset = NULL,
3063         .wait_for_idle = NULL,
3064         .soft_reset = NULL,
3065         .set_clockgating_state = psp_set_clockgating_state,
3066         .set_powergating_state = psp_set_powergating_state,
3067 };
3068
3069 static int psp_sysfs_init(struct amdgpu_device *adev)
3070 {
3071         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3072
3073         if (ret)
3074                 DRM_ERROR("Failed to create USBC PD FW control file!");
3075
3076         return ret;
3077 }
3078
3079 static void psp_sysfs_fini(struct amdgpu_device *adev)
3080 {
3081         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3082 }
3083
3084 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3085 {
3086         .type = AMD_IP_BLOCK_TYPE_PSP,
3087         .major = 3,
3088         .minor = 1,
3089         .rev = 0,
3090         .funcs = &psp_ip_funcs,
3091 };
3092
3093 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3094 {
3095         .type = AMD_IP_BLOCK_TYPE_PSP,
3096         .major = 10,
3097         .minor = 0,
3098         .rev = 0,
3099         .funcs = &psp_ip_funcs,
3100 };
3101
3102 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3103 {
3104         .type = AMD_IP_BLOCK_TYPE_PSP,
3105         .major = 11,
3106         .minor = 0,
3107         .rev = 0,
3108         .funcs = &psp_ip_funcs,
3109 };
3110
3111 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3112 {
3113         .type = AMD_IP_BLOCK_TYPE_PSP,
3114         .major = 12,
3115         .minor = 0,
3116         .rev = 0,
3117         .funcs = &psp_ip_funcs,
3118 };
3119
3120 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3121         .type = AMD_IP_BLOCK_TYPE_PSP,
3122         .major = 13,
3123         .minor = 0,
3124         .rev = 0,
3125         .funcs = &psp_ip_funcs,
3126 };