2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
33 #include "psp_v10_0.h"
35 static void psp_set_funcs(struct amdgpu_device *adev);
37 static int psp_early_init(void *handle)
39 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
46 static int psp_sw_init(void *handle)
48 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
49 struct psp_context *psp = &adev->psp;
52 switch (adev->asic_type) {
54 psp->init_microcode = psp_v3_1_init_microcode;
55 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
56 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
57 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
58 psp->ring_init = psp_v3_1_ring_init;
59 psp->ring_create = psp_v3_1_ring_create;
60 psp->ring_destroy = psp_v3_1_ring_destroy;
61 psp->cmd_submit = psp_v3_1_cmd_submit;
62 psp->compare_sram_data = psp_v3_1_compare_sram_data;
63 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
66 psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
67 psp->ring_init = psp_v10_0_ring_init;
68 psp->cmd_submit = psp_v10_0_cmd_submit;
69 psp->compare_sram_data = psp_v10_0_compare_sram_data;
77 ret = psp_init_microcode(psp);
79 DRM_ERROR("Failed to load psp firmware!\n");
86 static int psp_sw_fini(void *handle)
91 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
92 uint32_t reg_val, uint32_t mask, bool check_changed)
96 struct amdgpu_device *adev = psp->adev;
98 val = RREG32(reg_index);
100 for (i = 0; i < adev->usec_timeout; i++) {
105 if ((val & mask) == reg_val)
115 psp_cmd_submit_buf(struct psp_context *psp,
116 struct amdgpu_firmware_info *ucode,
117 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
121 struct amdgpu_bo *cmd_buf_bo;
122 uint64_t cmd_buf_mc_addr;
123 struct psp_gfx_cmd_resp *cmd_buf_mem;
124 struct amdgpu_device *adev = psp->adev;
126 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
127 AMDGPU_GEM_DOMAIN_VRAM,
128 &cmd_buf_bo, &cmd_buf_mc_addr,
129 (void **)&cmd_buf_mem);
133 memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
135 memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
137 ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
138 fence_mc_addr, index);
140 while (*((unsigned int *)psp->fence_buf) != index) {
144 amdgpu_bo_free_kernel(&cmd_buf_bo,
146 (void **)&cmd_buf_mem);
151 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
152 uint64_t tmr_mc, uint32_t size)
154 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
155 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
156 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
157 cmd->cmd.cmd_setup_tmr.buf_size = size;
160 /* Set up Trusted Memory Region */
161 static int psp_tmr_init(struct psp_context *psp)
166 * Allocate 3M memory aligned to 1M from Frame Buffer (local
169 * Note: this memory need be reserved till the driver
172 ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
173 AMDGPU_GEM_DOMAIN_VRAM,
174 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
179 static int psp_tmr_load(struct psp_context *psp)
182 struct psp_gfx_cmd_resp *cmd;
184 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
188 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
190 ret = psp_cmd_submit_buf(psp, NULL, cmd,
191 psp->fence_buf_mc_addr, 1);
204 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
205 uint64_t asd_mc, uint64_t asd_mc_shared,
206 uint32_t size, uint32_t shared_size)
208 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
209 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
210 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
211 cmd->cmd.cmd_load_ta.app_len = size;
213 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
214 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
215 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
218 static int psp_asd_init(struct psp_context *psp)
223 * Allocate 16k memory aligned to 4k from Frame Buffer (local
224 * physical) for shared ASD <-> Driver
226 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
227 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
229 &psp->asd_shared_mc_addr,
230 &psp->asd_shared_buf);
235 static int psp_asd_load(struct psp_context *psp)
238 struct psp_gfx_cmd_resp *cmd;
240 /* If PSP version doesn't match ASD version, asd loading will be failed.
241 * add workaround to bypass it for sriov now.
242 * TODO: add version check to make it common
244 if (amdgpu_sriov_vf(psp->adev))
247 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
251 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
252 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
254 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
255 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
257 ret = psp_cmd_submit_buf(psp, NULL, cmd,
258 psp->fence_buf_mc_addr, 2);
265 static int psp_hw_start(struct psp_context *psp)
269 ret = psp_bootloader_load_sysdrv(psp);
273 ret = psp_bootloader_load_sos(psp);
277 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
281 ret = psp_tmr_load(psp);
285 ret = psp_asd_load(psp);
292 static int psp_np_fw_load(struct psp_context *psp)
295 struct amdgpu_firmware_info *ucode;
296 struct amdgpu_device* adev = psp->adev;
298 for (i = 0; i < adev->firmware.max_ucodes; i++) {
299 ucode = &adev->firmware.ucode[i];
303 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
304 psp_smu_reload_quirk(psp))
306 if (amdgpu_sriov_vf(adev) &&
307 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
308 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
309 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
310 /*skip ucode loading in SRIOV VF */
313 ret = psp_prep_cmd_buf(ucode, psp->cmd);
317 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
318 psp->fence_buf_mc_addr, i + 3);
323 /* check if firmware loaded sucessfully */
324 if (!amdgpu_psp_check_fw_loading_status(adev, i))
332 static int psp_load_fw(struct amdgpu_device *adev)
335 struct psp_context *psp = &adev->psp;
337 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
341 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
342 AMDGPU_GEM_DOMAIN_GTT,
344 &psp->fw_pri_mc_addr,
349 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
350 AMDGPU_GEM_DOMAIN_VRAM,
352 &psp->fence_buf_mc_addr,
357 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
359 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
363 ret = psp_tmr_init(psp);
367 ret = psp_asd_init(psp);
371 ret = psp_hw_start(psp);
375 ret = psp_np_fw_load(psp);
382 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
383 &psp->fence_buf_mc_addr, &psp->fence_buf);
385 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
386 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
393 static int psp_hw_init(void *handle)
396 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
399 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
402 mutex_lock(&adev->firmware.mutex);
404 * This sequence is just used on hw_init only once, no need on
407 ret = amdgpu_ucode_init_bo(adev);
411 ret = psp_load_fw(adev);
413 DRM_ERROR("PSP firmware loading failed\n");
417 mutex_unlock(&adev->firmware.mutex);
421 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
422 mutex_unlock(&adev->firmware.mutex);
426 static int psp_hw_fini(void *handle)
428 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
429 struct psp_context *psp = &adev->psp;
431 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
434 amdgpu_ucode_fini_bo(adev);
436 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
439 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
442 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
443 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
445 if (psp->fence_buf_bo)
446 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
447 &psp->fence_buf_mc_addr, &psp->fence_buf);
455 static int psp_suspend(void *handle)
460 static int psp_resume(void *handle)
463 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
464 struct psp_context *psp = &adev->psp;
466 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
469 DRM_INFO("PSP is resuming...\n");
471 mutex_lock(&adev->firmware.mutex);
473 ret = psp_hw_start(psp);
477 ret = psp_np_fw_load(psp);
481 mutex_unlock(&adev->firmware.mutex);
486 DRM_ERROR("PSP resume failed\n");
487 mutex_unlock(&adev->firmware.mutex);
491 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
492 enum AMDGPU_UCODE_ID ucode_type)
494 struct amdgpu_firmware_info *ucode = NULL;
496 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
497 DRM_INFO("firmware is not loaded by PSP\n");
501 if (!adev->firmware.fw_size)
504 ucode = &adev->firmware.ucode[ucode_type];
505 if (!ucode->fw || !ucode->ucode_size)
508 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
511 static int psp_set_clockgating_state(void *handle,
512 enum amd_clockgating_state state)
517 static int psp_set_powergating_state(void *handle,
518 enum amd_powergating_state state)
523 const struct amd_ip_funcs psp_ip_funcs = {
525 .early_init = psp_early_init,
527 .sw_init = psp_sw_init,
528 .sw_fini = psp_sw_fini,
529 .hw_init = psp_hw_init,
530 .hw_fini = psp_hw_fini,
531 .suspend = psp_suspend,
532 .resume = psp_resume,
534 .wait_for_idle = NULL,
536 .set_clockgating_state = psp_set_clockgating_state,
537 .set_powergating_state = psp_set_powergating_state,
540 static const struct amdgpu_psp_funcs psp_funcs = {
541 .check_fw_loading_status = psp_check_fw_loading_status,
544 static void psp_set_funcs(struct amdgpu_device *adev)
546 if (NULL == adev->firmware.funcs)
547 adev->firmware.funcs = &psp_funcs;
550 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
552 .type = AMD_IP_BLOCK_TYPE_PSP,
556 .funcs = &psp_ip_funcs,
559 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
561 .type = AMD_IP_BLOCK_TYPE_PSP,
565 .funcs = &psp_ip_funcs,