drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40
  41 #include "amdgpu_ras.h"
  42 #include "amdgpu_securedisplay.h"
  43 #include "amdgpu_atomfirmware.h"
  44
  45 static int psp_sysfs_init(struct amdgpu_device *adev);
  46 static void psp_sysfs_fini(struct amdgpu_device *adev);
  47
  48 static int psp_load_smu_fw(struct psp_context *psp);
  49 static int psp_rap_terminate(struct psp_context *psp);
  50 static int psp_securedisplay_terminate(struct psp_context *psp);
  51
  52 /*
  53  * Due to DF Cstate management centralized to PMFW, the firmware
  54  * loading sequence will be updated as below:
  55  *   - Load KDB
  56  *   - Load SYS_DRV
  57  *   - Load tOS
  58  *   - Load PMFW
  59  *   - Setup TMR
  60  *   - Load other non-psp fw
  61  *   - Load ASD
  62  *   - Load XGMI/RAS/HDCP/DTM TA if any
  63  *
  64  * This new sequence is required for
  65  *   - Arcturus and onwards
  66  */
  67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  68 {
  69         struct amdgpu_device *adev = psp->adev;
  70
  71         if (amdgpu_sriov_vf(adev)) {
  72                 psp->pmfw_centralized_cstate_management = false;
  73                 return;
  74         }
  75
  76         switch (adev->ip_versions[MP0_HWIP][0]) {
  77         case IP_VERSION(11, 0, 0):
  78         case IP_VERSION(11, 0, 4):
  79         case IP_VERSION(11, 0, 5):
  80         case IP_VERSION(11, 0, 7):
  81         case IP_VERSION(11, 0, 9):
  82         case IP_VERSION(11, 0, 11):
  83         case IP_VERSION(11, 0, 12):
  84         case IP_VERSION(11, 0, 13):
  85         case IP_VERSION(13, 0, 2):
  86                 psp->pmfw_centralized_cstate_management = true;
  87                 break;
  88         default:
  89                 psp->pmfw_centralized_cstate_management = false;
  90                 break;
  91         }
  92 }
  93
  94 static int psp_early_init(void *handle)
  95 {
  96         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  97         struct psp_context *psp = &adev->psp;
  98
  99         switch (adev->ip_versions[MP0_HWIP][0]) {
 100         case IP_VERSION(9, 0, 0):
 101                 psp_v3_1_set_psp_funcs(psp);
 102                 psp->autoload_supported = false;
 103                 break;
 104         case IP_VERSION(10, 0, 0):
 105         case IP_VERSION(10, 0, 1):
 106                 psp_v10_0_set_psp_funcs(psp);
 107                 psp->autoload_supported = false;
 108                 break;
 109         case IP_VERSION(11, 0, 2):
 110         case IP_VERSION(11, 0, 4):
 111                 psp_v11_0_set_psp_funcs(psp);
 112                 psp->autoload_supported = false;
 113                 break;
 114         case IP_VERSION(11, 0, 0):
 115         case IP_VERSION(11, 0, 5):
 116         case IP_VERSION(11, 0, 9):
 117         case IP_VERSION(11, 0, 7):
 118         case IP_VERSION(11, 0, 11):
 119         case IP_VERSION(11, 5, 0):
 120         case IP_VERSION(11, 0, 12):
 121         case IP_VERSION(11, 0, 13):
 122                 psp_v11_0_set_psp_funcs(psp);
 123                 psp->autoload_supported = true;
 124                 break;
 125         case IP_VERSION(11, 0, 3):
 126         case IP_VERSION(12, 0, 1):
 127                 psp_v12_0_set_psp_funcs(psp);
 128                 break;
 129         case IP_VERSION(13, 0, 2):
 130                 psp_v13_0_set_psp_funcs(psp);
 131                 break;
 132         case IP_VERSION(13, 0, 1):
 133         case IP_VERSION(13, 0, 3):
 134         case IP_VERSION(13, 0, 5):
 135         case IP_VERSION(13, 0, 8):
 136                 psp_v13_0_set_psp_funcs(psp);
 137                 psp->autoload_supported = true;
 138                 break;
 139         case IP_VERSION(11, 0, 8):
 140                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 141                         psp_v11_0_8_set_psp_funcs(psp);
 142                         psp->autoload_supported = false;
 143                 }
 144                 break;
 145         default:
 146                 return -EINVAL;
 147         }
 148
 149         psp->adev = adev;
 150
 151         psp_check_pmfw_centralized_cstate_management(psp);
 152
 153         return 0;
 154 }
 155
 156 static void psp_memory_training_fini(struct psp_context *psp)
 157 {
 158         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 159
 160         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 161         kfree(ctx->sys_cache);
 162         ctx->sys_cache = NULL;
 163 }
 164
 165 static int psp_memory_training_init(struct psp_context *psp)
 166 {
 167         int ret;
 168         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 169
 170         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 171                 DRM_DEBUG("memory training is not supported!\n");
 172                 return 0;
 173         }
 174
 175         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 176         if (ctx->sys_cache == NULL) {
 177                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 178                 ret = -ENOMEM;
 179                 goto Err_out;
 180         }
 181
 182         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 183                   ctx->train_data_size,
 184                   ctx->p2c_train_data_offset,
 185                   ctx->c2p_train_data_offset);
 186         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 187         return 0;
 188
 189 Err_out:
 190         psp_memory_training_fini(psp);
 191         return ret;
 192 }
 193
 194 /*
 195  * Helper funciton to query psp runtime database entry
 196  *
 197  * @adev: amdgpu_device pointer
 198  * @entry_type: the type of psp runtime database entry
 199  * @db_entry: runtime database entry pointer
 200  *
 201  * Return false if runtime database doesn't exit or entry is invalid
 202  * or true if the specific database entry is found, and copy to @db_entry
 203  */
 204 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 205                                      enum psp_runtime_entry_type entry_type,
 206                                      void *db_entry)
 207 {
 208         uint64_t db_header_pos, db_dir_pos;
 209         struct psp_runtime_data_header db_header = {0};
 210         struct psp_runtime_data_directory db_dir = {0};
 211         bool ret = false;
 212         int i;
 213
 214         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 215         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 216
 217         /* read runtime db header from vram */
 218         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 219                         sizeof(struct psp_runtime_data_header), false);
 220
 221         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 222                 /* runtime db doesn't exist, exit */
 223                 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
 224                 return false;
 225         }
 226
 227         /* read runtime database entry from vram */
 228         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 229                         sizeof(struct psp_runtime_data_directory), false);
 230
 231         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 232                 /* invalid db entry count, exit */
 233                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 234                 return false;
 235         }
 236
 237         /* look up for requested entry type */
 238         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 239                 if (db_dir.entry_list[i].entry_type == entry_type) {
 240                         switch (entry_type) {
 241                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 242                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 243                                         /* invalid db entry size */
 244                                         dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
 245                                         return false;
 246                                 }
 247                                 /* read runtime database entry */
 248                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 249                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 250                                 ret = true;
 251                                 break;
 252                         default:
 253                                 ret = false;
 254                                 break;
 255                         }
 256                 }
 257         }
 258
 259         return ret;
 260 }
 261
 262 static int psp_init_sriov_microcode(struct psp_context *psp)
 263 {
 264         struct amdgpu_device *adev = psp->adev;
 265         int ret = 0;
 266
 267         switch (adev->ip_versions[MP0_HWIP][0]) {
 268         case IP_VERSION(9, 0, 0):
 269                 ret = psp_init_cap_microcode(psp, "vega10");
 270                 break;
 271         case IP_VERSION(11, 0, 9):
 272                 ret = psp_init_cap_microcode(psp, "navi12");
 273                 break;
 274         case IP_VERSION(11, 0, 7):
 275                 ret = psp_init_cap_microcode(psp, "sienna_cichlid");
 276                 break;
 277         case IP_VERSION(13, 0, 2):
 278                 ret = psp_init_cap_microcode(psp, "aldebaran");
 279                 ret &= psp_init_ta_microcode(psp, "aldebaran");
 280                 break;
 281         default:
 282                 BUG();
 283                 break;
 284         }
 285
 286         return ret;
 287 }
 288
 289 static int psp_sw_init(void *handle)
 290 {
 291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 292         struct psp_context *psp = &adev->psp;
 293         int ret;
 294         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 295         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 296
 297         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 298         if (!psp->cmd) {
 299                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 300                 ret = -ENOMEM;
 301         }
 302
 303         if (amdgpu_sriov_vf(adev))
 304                 ret = psp_init_sriov_microcode(psp);
 305         else
 306                 ret = psp_init_microcode(psp);
 307         if (ret) {
 308                 DRM_ERROR("Failed to load psp firmware!\n");
 309                 return ret;
 310         }
 311
 312         adev->psp.xgmi_context.supports_extended_data =
 313                 !adev->gmc.xgmi.connected_to_cpu &&
 314                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 315
 316         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 317         if (psp_get_runtime_db_entry(adev,
 318                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 319                                 &boot_cfg_entry)) {
 320                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 321                 if ((psp->boot_cfg_bitmask) &
 322                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 323                         /* If psp runtime database exists, then
 324                          * only enable two stage memory training
 325                          * when TWO_STAGE_DRAM_TRAINING bit is set
 326                          * in runtime database */
 327                         mem_training_ctx->enable_mem_training = true;
 328                 }
 329
 330         } else {
 331                 /* If psp runtime database doesn't exist or
 332                  * is invalid, force enable two stage memory
 333                  * training */
 334                 mem_training_ctx->enable_mem_training = true;
 335         }
 336
 337         if (mem_training_ctx->enable_mem_training) {
 338                 ret = psp_memory_training_init(psp);
 339                 if (ret) {
 340                         DRM_ERROR("Failed to initialize memory training!\n");
 341                         return ret;
 342                 }
 343
 344                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 345                 if (ret) {
 346                         DRM_ERROR("Failed to process memory training!\n");
 347                         return ret;
 348                 }
 349         }
 350
 351         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 352             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 353                 ret= psp_sysfs_init(adev);
 354                 if (ret) {
 355                         return ret;
 356                 }
 357         }
 358
 359         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 360                                       amdgpu_sriov_vf(adev) ?
 361                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 362                                       &psp->fw_pri_bo,
 363                                       &psp->fw_pri_mc_addr,
 364                                       &psp->fw_pri_buf);
 365         if (ret)
 366                 return ret;
 367
 368         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 369                                       AMDGPU_GEM_DOMAIN_VRAM,
 370                                       &psp->fence_buf_bo,
 371                                       &psp->fence_buf_mc_addr,
 372                                       &psp->fence_buf);
 373         if (ret)
 374                 goto failed1;
 375
 376         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 377                                       AMDGPU_GEM_DOMAIN_VRAM,
 378                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 379                                       (void **)&psp->cmd_buf_mem);
 380         if (ret)
 381                 goto failed2;
 382
 383         return 0;
 384
 385 failed2:
 386         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 387                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 388 failed1:
 389         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 390                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 391         return ret;
 392 }
 393
 394 static int psp_sw_fini(void *handle)
 395 {
 396         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 397         struct psp_context *psp = &adev->psp;
 398         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 399
 400         psp_memory_training_fini(psp);
 401         if (psp->sos_fw) {
 402                 release_firmware(psp->sos_fw);
 403                 psp->sos_fw = NULL;
 404         }
 405         if (psp->asd_fw) {
 406                 release_firmware(psp->asd_fw);
 407                 psp->asd_fw = NULL;
 408         }
 409         if (psp->ta_fw) {
 410                 release_firmware(psp->ta_fw);
 411                 psp->ta_fw = NULL;
 412         }
 413         if (adev->psp.cap_fw) {
 414                 release_firmware(psp->cap_fw);
 415                 psp->cap_fw = NULL;
 416         }
 417
 418         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 419             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 420                 psp_sysfs_fini(adev);
 421
 422         kfree(cmd);
 423         cmd = NULL;
 424
 425         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 426                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 427         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 428                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 429         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 430                               (void **)&psp->cmd_buf_mem);
 431
 432         return 0;
 433 }
 434
 435 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 436                  uint32_t reg_val, uint32_t mask, bool check_changed)
 437 {
 438         uint32_t val;
 439         int i;
 440         struct amdgpu_device *adev = psp->adev;
 441
 442         if (psp->adev->no_hw_access)
 443                 return 0;
 444
 445         for (i = 0; i < adev->usec_timeout; i++) {
 446                 val = RREG32(reg_index);
 447                 if (check_changed) {
 448                         if (val != reg_val)
 449                                 return 0;
 450                 } else {
 451                         if ((val & mask) == reg_val)
 452                                 return 0;
 453                 }
 454                 udelay(1);
 455         }
 456
 457         return -ETIME;
 458 }
 459
 460 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 461 {
 462         switch (cmd_id) {
 463         case GFX_CMD_ID_LOAD_TA:
 464                 return "LOAD_TA";
 465         case GFX_CMD_ID_UNLOAD_TA:
 466                 return "UNLOAD_TA";
 467         case GFX_CMD_ID_INVOKE_CMD:
 468                 return "INVOKE_CMD";
 469         case GFX_CMD_ID_LOAD_ASD:
 470                 return "LOAD_ASD";
 471         case GFX_CMD_ID_SETUP_TMR:
 472                 return "SETUP_TMR";
 473         case GFX_CMD_ID_LOAD_IP_FW:
 474                 return "LOAD_IP_FW";
 475         case GFX_CMD_ID_DESTROY_TMR:
 476                 return "DESTROY_TMR";
 477         case GFX_CMD_ID_SAVE_RESTORE:
 478                 return "SAVE_RESTORE_IP_FW";
 479         case GFX_CMD_ID_SETUP_VMR:
 480                 return "SETUP_VMR";
 481         case GFX_CMD_ID_DESTROY_VMR:
 482                 return "DESTROY_VMR";
 483         case GFX_CMD_ID_PROG_REG:
 484                 return "PROG_REG";
 485         case GFX_CMD_ID_GET_FW_ATTESTATION:
 486                 return "GET_FW_ATTESTATION";
 487         case GFX_CMD_ID_LOAD_TOC:
 488                 return "ID_LOAD_TOC";
 489         case GFX_CMD_ID_AUTOLOAD_RLC:
 490                 return "AUTOLOAD_RLC";
 491         case GFX_CMD_ID_BOOT_CFG:
 492                 return "BOOT_CFG";
 493         default:
 494                 return "UNKNOWN CMD";
 495         }
 496 }
 497
 498 static int
 499 psp_cmd_submit_buf(struct psp_context *psp,
 500                    struct amdgpu_firmware_info *ucode,
 501                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 502 {
 503         int ret;
 504         int index, idx;
 505         int timeout = 20000;
 506         bool ras_intr = false;
 507         bool skip_unsupport = false;
 508
 509         if (psp->adev->no_hw_access)
 510                 return 0;
 511
 512         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
 513                 return 0;
 514
 515         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 516
 517         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 518
 519         index = atomic_inc_return(&psp->fence_value);
 520         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 521         if (ret) {
 522                 atomic_dec(&psp->fence_value);
 523                 goto exit;
 524         }
 525
 526         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 527         while (*((unsigned int *)psp->fence_buf) != index) {
 528                 if (--timeout == 0)
 529                         break;
 530                 /*
 531                  * Shouldn't wait for timeout when err_event_athub occurs,
 532                  * because gpu reset thread triggered and lock resource should
 533                  * be released for psp resume sequence.
 534                  */
 535                 ras_intr = amdgpu_ras_intr_triggered();
 536                 if (ras_intr)
 537                         break;
 538                 usleep_range(10, 100);
 539                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 540         }
 541
 542         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 543         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 544                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 545
 546         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 547
 548         /* In some cases, psp response status is not 0 even there is no
 549          * problem while the command is submitted. Some version of PSP FW
 550          * doesn't write 0 to that field.
 551          * So here we would like to only print a warning instead of an error
 552          * during psp initialization to avoid breaking hw_init and it doesn't
 553          * return -EINVAL.
 554          */
 555         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 556                 if (ucode)
 557                         DRM_WARN("failed to load ucode %s(0x%X) ",
 558                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 559                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 560                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 561                          psp->cmd_buf_mem->resp.status);
 562                 /* If we load CAP FW, PSP must return 0 under SRIOV
 563                  * also return failure in case of timeout
 564                  */
 565                 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) {
 566                         ret = -EINVAL;
 567                         goto exit;
 568                 }
 569         }
 570
 571         if (ucode) {
 572                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 573                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 574         }
 575
 576 exit:
 577         drm_dev_exit(idx);
 578         return ret;
 579 }
 580
 581 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 582 {
 583         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 584
 585         mutex_lock(&psp->mutex);
 586
 587         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 588
 589         return cmd;
 590 }
 591
 592 static void release_psp_cmd_buf(struct psp_context *psp)
 593 {
 594         mutex_unlock(&psp->mutex);
 595 }
 596
 597 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 598                                  struct psp_gfx_cmd_resp *cmd,
 599                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 600 {
 601         struct amdgpu_device *adev = psp->adev;
 602         uint32_t size = amdgpu_bo_size(tmr_bo);
 603         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 604
 605         if (amdgpu_sriov_vf(psp->adev))
 606                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 607         else
 608                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 609         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 610         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 611         cmd->cmd.cmd_setup_tmr.buf_size = size;
 612         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 613         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 614         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 615 }
 616
 617 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 618                                       uint64_t pri_buf_mc, uint32_t size)
 619 {
 620         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 621         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 622         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 623         cmd->cmd.cmd_load_toc.toc_size = size;
 624 }
 625
 626 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 627 static int psp_load_toc(struct psp_context *psp,
 628                         uint32_t *tmr_size)
 629 {
 630         int ret;
 631         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 632
 633         /* Copy toc to psp firmware private buffer */
 634         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 635
 636         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 637
 638         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 639                                  psp->fence_buf_mc_addr);
 640         if (!ret)
 641                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 642
 643         release_psp_cmd_buf(psp);
 644
 645         return ret;
 646 }
 647
 648 /* Set up Trusted Memory Region */
 649 static int psp_tmr_init(struct psp_context *psp)
 650 {
 651         int ret;
 652         int tmr_size;
 653         void *tmr_buf;
 654         void **pptr;
 655
 656         /*
 657          * According to HW engineer, they prefer the TMR address be "naturally
 658          * aligned" , e.g. the start address be an integer divide of TMR size.
 659          *
 660          * Note: this memory need be reserved till the driver
 661          * uninitializes.
 662          */
 663         tmr_size = PSP_TMR_SIZE(psp->adev);
 664
 665         /* For ASICs support RLC autoload, psp will parse the toc
 666          * and calculate the total size of TMR needed */
 667         if (!amdgpu_sriov_vf(psp->adev) &&
 668             psp->toc.start_addr &&
 669             psp->toc.size_bytes &&
 670             psp->fw_pri_buf) {
 671                 ret = psp_load_toc(psp, &tmr_size);
 672                 if (ret) {
 673                         DRM_ERROR("Failed to load toc\n");
 674                         return ret;
 675                 }
 676         }
 677
 678         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 679         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
 680                                       AMDGPU_GEM_DOMAIN_VRAM,
 681                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 682
 683         return ret;
 684 }
 685
 686 static bool psp_skip_tmr(struct psp_context *psp)
 687 {
 688         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 689         case IP_VERSION(11, 0, 9):
 690         case IP_VERSION(11, 0, 7):
 691         case IP_VERSION(13, 0, 2):
 692                 return true;
 693         default:
 694                 return false;
 695         }
 696 }
 697
 698 static int psp_tmr_load(struct psp_context *psp)
 699 {
 700         int ret;
 701         struct psp_gfx_cmd_resp *cmd;
 702
 703         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 704          * Already set up by host driver.
 705          */
 706         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 707                 return 0;
 708
 709         cmd = acquire_psp_cmd_buf(psp);
 710
 711         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 712         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 713                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 714
 715         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 716                                  psp->fence_buf_mc_addr);
 717
 718         release_psp_cmd_buf(psp);
 719
 720         return ret;
 721 }
 722
 723 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 724                                         struct psp_gfx_cmd_resp *cmd)
 725 {
 726         if (amdgpu_sriov_vf(psp->adev))
 727                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 728         else
 729                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 730 }
 731
 732 static int psp_tmr_unload(struct psp_context *psp)
 733 {
 734         int ret;
 735         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 736
 737         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 738         DRM_INFO("free PSP TMR buffer\n");
 739
 740         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 741                                  psp->fence_buf_mc_addr);
 742
 743         release_psp_cmd_buf(psp);
 744
 745         return ret;
 746 }
 747
 748 static int psp_tmr_terminate(struct psp_context *psp)
 749 {
 750         int ret;
 751         void *tmr_buf;
 752         void **pptr;
 753
 754         ret = psp_tmr_unload(psp);
 755
 756         /* free TMR memory buffer */
 757         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 758         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 759
 760         return ret;
 761 }
 762
 763 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 764                                         uint64_t *output_ptr)
 765 {
 766         int ret;
 767         struct psp_gfx_cmd_resp *cmd;
 768
 769         if (!output_ptr)
 770                 return -EINVAL;
 771
 772         if (amdgpu_sriov_vf(psp->adev))
 773                 return 0;
 774
 775         cmd = acquire_psp_cmd_buf(psp);
 776
 777         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 778
 779         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 780                                  psp->fence_buf_mc_addr);
 781
 782         if (!ret) {
 783                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 784                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 785         }
 786
 787         release_psp_cmd_buf(psp);
 788
 789         return ret;
 790 }
 791
 792 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 793 {
 794         struct psp_context *psp = &adev->psp;
 795         struct psp_gfx_cmd_resp *cmd;
 796         int ret;
 797
 798         if (amdgpu_sriov_vf(adev))
 799                 return 0;
 800
 801         cmd = acquire_psp_cmd_buf(psp);
 802
 803         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 804         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 805
 806         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 807         if (!ret) {
 808                 *boot_cfg =
 809                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 810         }
 811
 812         release_psp_cmd_buf(psp);
 813
 814         return ret;
 815 }
 816
 817 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 818 {
 819         int ret;
 820         struct psp_context *psp = &adev->psp;
 821         struct psp_gfx_cmd_resp *cmd;
 822
 823         if (amdgpu_sriov_vf(adev))
 824                 return 0;
 825
 826         cmd = acquire_psp_cmd_buf(psp);
 827
 828         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 829         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 830         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 831         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 832
 833         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 834
 835         release_psp_cmd_buf(psp);
 836
 837         return ret;
 838 }
 839
 840 static int psp_rl_load(struct amdgpu_device *adev)
 841 {
 842         int ret;
 843         struct psp_context *psp = &adev->psp;
 844         struct psp_gfx_cmd_resp *cmd;
 845
 846         if (!is_psp_fw_valid(psp->rl))
 847                 return 0;
 848
 849         cmd = acquire_psp_cmd_buf(psp);
 850
 851         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 852         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 853
 854         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 855         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 856         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 857         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 858         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 859
 860         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 861
 862         release_psp_cmd_buf(psp);
 863
 864         return ret;
 865 }
 866
 867 static int psp_asd_initialize(struct psp_context *psp)
 868 {
 869         int ret;
 870
 871         /* If PSP version doesn't match ASD version, asd loading will be failed.
 872          * add workaround to bypass it for sriov now.
 873          * TODO: add version check to make it common
 874          */
 875         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 876                 return 0;
 877
 878         psp->asd_context.mem_context.shared_mc_addr  = 0;
 879         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 880         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 881
 882         ret = psp_ta_load(psp, &psp->asd_context);
 883         if (!ret)
 884                 psp->asd_context.initialized = true;
 885
 886         return ret;
 887 }
 888
 889 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 890                                        uint32_t session_id)
 891 {
 892         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 893         cmd->cmd.cmd_unload_ta.session_id = session_id;
 894 }
 895
 896 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
 897 {
 898         int ret;
 899         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 900
 901         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
 902
 903         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 904
 905         release_psp_cmd_buf(psp);
 906
 907         return ret;
 908 }
 909
 910 static int psp_asd_terminate(struct psp_context *psp)
 911 {
 912         int ret;
 913
 914         if (amdgpu_sriov_vf(psp->adev))
 915                 return 0;
 916
 917         if (!psp->asd_context.initialized)
 918                 return 0;
 919
 920         ret = psp_ta_unload(psp, &psp->asd_context);
 921         if (!ret)
 922                 psp->asd_context.initialized = false;
 923
 924         return ret;
 925 }
 926
 927 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 928                 uint32_t id, uint32_t value)
 929 {
 930         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 931         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 932         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 933 }
 934
 935 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 936                 uint32_t value)
 937 {
 938         struct psp_gfx_cmd_resp *cmd;
 939         int ret = 0;
 940
 941         if (reg >= PSP_REG_LAST)
 942                 return -EINVAL;
 943
 944         cmd = acquire_psp_cmd_buf(psp);
 945
 946         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 947         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 948         if (ret)
 949                 DRM_ERROR("PSP failed to program reg id %d", reg);
 950
 951         release_psp_cmd_buf(psp);
 952
 953         return ret;
 954 }
 955
 956 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 957                                      uint64_t ta_bin_mc,
 958                                      struct ta_context *context)
 959 {
 960         cmd->cmd_id                             = context->ta_load_type;
 961         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 962         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 963         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
 964
 965         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
 966                 lower_32_bits(context->mem_context.shared_mc_addr);
 967         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
 968                 upper_32_bits(context->mem_context.shared_mc_addr);
 969         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
 970 }
 971
 972 int psp_ta_init_shared_buf(struct psp_context *psp,
 973                                   struct ta_mem_context *mem_ctx)
 974 {
 975         /*
 976         * Allocate 16k memory aligned to 4k from Frame Buffer (local
 977         * physical) for ta to host memory
 978         */
 979         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
 980                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 981                                       &mem_ctx->shared_bo,
 982                                       &mem_ctx->shared_mc_addr,
 983                                       &mem_ctx->shared_buf);
 984 }
 985
 986 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 987 {
 988         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 989                               &mem_ctx->shared_buf);
 990 }
 991
 992 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 993                                        uint32_t ta_cmd_id,
 994                                        struct ta_context *context)
 995 {
 996         cmd->cmd_id                         = GFX_CMD_ID_INVOKE_CMD;
 997         cmd->cmd.cmd_invoke_cmd.session_id  = context->session_id;
 998         cmd->cmd.cmd_invoke_cmd.ta_cmd_id   = ta_cmd_id;
 999
1000         cmd->cmd.cmd_invoke_cmd.buf.num_desc   = 1;
1001         cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size;
1002         cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size;
1003         cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo =
1004                                      lower_32_bits(context->mem_context.shared_mc_addr);
1005         cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi =
1006                                      upper_32_bits(context->mem_context.shared_mc_addr);
1007 }
1008
1009 int psp_ta_invoke_indirect(struct psp_context *psp,
1010                   uint32_t ta_cmd_id,
1011                   struct ta_context *context)
1012 {
1013         int ret;
1014         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1015
1016         psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context);
1017
1018         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1019                                  psp->fence_buf_mc_addr);
1020
1021         context->resp_status = cmd->resp.status;
1022
1023         release_psp_cmd_buf(psp);
1024
1025         return ret;
1026 }
1027
1028 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1029                                        uint32_t ta_cmd_id,
1030                                        uint32_t session_id)
1031 {
1032         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1033         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1034         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1035 }
1036
1037 int psp_ta_invoke(struct psp_context *psp,
1038                   uint32_t ta_cmd_id,
1039                   struct ta_context *context)
1040 {
1041         int ret;
1042         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1043
1044         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1045
1046         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1047                                  psp->fence_buf_mc_addr);
1048
1049         context->resp_status = cmd->resp.status;
1050
1051         release_psp_cmd_buf(psp);
1052
1053         return ret;
1054 }
1055
1056 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1057 {
1058         int ret;
1059         struct psp_gfx_cmd_resp *cmd;
1060
1061         cmd = acquire_psp_cmd_buf(psp);
1062
1063         psp_copy_fw(psp, context->bin_desc.start_addr,
1064                     context->bin_desc.size_bytes);
1065
1066         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1067
1068         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1069                                  psp->fence_buf_mc_addr);
1070
1071         context->resp_status = cmd->resp.status;
1072
1073         if (!ret) {
1074                 context->session_id = cmd->resp.session_id;
1075         }
1076
1077         release_psp_cmd_buf(psp);
1078
1079         return ret;
1080 }
1081
1082 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1083 {
1084         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1085 }
1086
1087 int psp_xgmi_terminate(struct psp_context *psp)
1088 {
1089         int ret;
1090         struct amdgpu_device *adev = psp->adev;
1091
1092         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1093         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1094             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1095              adev->gmc.xgmi.connected_to_cpu))
1096                 return 0;
1097
1098         if (!psp->xgmi_context.context.initialized)
1099                 return 0;
1100
1101         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1102
1103         psp->xgmi_context.context.initialized = false;
1104
1105         /* free xgmi shared memory */
1106         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
1107
1108         return ret;
1109 }
1110
1111 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1112 {
1113         struct ta_xgmi_shared_memory *xgmi_cmd;
1114         int ret;
1115
1116         if (!psp->ta_fw ||
1117             !psp->xgmi_context.context.bin_desc.size_bytes ||
1118             !psp->xgmi_context.context.bin_desc.start_addr)
1119                 return -ENOENT;
1120
1121         if (!load_ta)
1122                 goto invoke;
1123
1124         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1125         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1126
1127         if (!psp->xgmi_context.context.initialized) {
1128                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1129                 if (ret)
1130                         return ret;
1131         }
1132
1133         /* Load XGMI TA */
1134         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1135         if (!ret)
1136                 psp->xgmi_context.context.initialized = true;
1137         else
1138                 return ret;
1139
1140 invoke:
1141         /* Initialize XGMI session */
1142         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1143         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1144         xgmi_cmd->flag_extend_link_record = set_extended_data;
1145         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1146
1147         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1148
1149         return ret;
1150 }
1151
1152 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1153 {
1154         struct ta_xgmi_shared_memory *xgmi_cmd;
1155         int ret;
1156
1157         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1158         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1159
1160         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1161
1162         /* Invoke xgmi ta to get hive id */
1163         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1164         if (ret)
1165                 return ret;
1166
1167         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1168
1169         return 0;
1170 }
1171
1172 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1173 {
1174         struct ta_xgmi_shared_memory *xgmi_cmd;
1175         int ret;
1176
1177         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1178         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1179
1180         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1181
1182         /* Invoke xgmi ta to get the node id */
1183         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1184         if (ret)
1185                 return ret;
1186
1187         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1188
1189         return 0;
1190 }
1191
1192 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1193 {
1194         return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1195                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1196 }
1197
1198 /*
1199  * Chips that support extended topology information require the driver to
1200  * reflect topology information in the opposite direction.  This is
1201  * because the TA has already exceeded its link record limit and if the
1202  * TA holds bi-directional information, the driver would have to do
1203  * multiple fetches instead of just two.
1204  */
1205 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1206                                         struct psp_xgmi_node_info node_info)
1207 {
1208         struct amdgpu_device *mirror_adev;
1209         struct amdgpu_hive_info *hive;
1210         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1211         uint64_t dst_node_id = node_info.node_id;
1212         uint8_t dst_num_hops = node_info.num_hops;
1213         uint8_t dst_num_links = node_info.num_links;
1214
1215         hive = amdgpu_get_xgmi_hive(psp->adev);
1216         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1217                 struct psp_xgmi_topology_info *mirror_top_info;
1218                 int j;
1219
1220                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1221                         continue;
1222
1223                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1224                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1225                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1226                                 continue;
1227
1228                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1229                         /*
1230                          * prevent 0 num_links value re-reflection since reflection
1231                          * criteria is based on num_hops (direct or indirect).
1232                          *
1233                          */
1234                         if (dst_num_links)
1235                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1236
1237                         break;
1238                 }
1239
1240                 break;
1241         }
1242 }
1243
1244 int psp_xgmi_get_topology_info(struct psp_context *psp,
1245                                int number_devices,
1246                                struct psp_xgmi_topology_info *topology,
1247                                bool get_extended_data)
1248 {
1249         struct ta_xgmi_shared_memory *xgmi_cmd;
1250         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1251         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1252         int i;
1253         int ret;
1254
1255         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1256                 return -EINVAL;
1257
1258         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1259         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1260         xgmi_cmd->flag_extend_link_record = get_extended_data;
1261
1262         /* Fill in the shared memory with topology information as input */
1263         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1264         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1265         topology_info_input->num_nodes = number_devices;
1266
1267         for (i = 0; i < topology_info_input->num_nodes; i++) {
1268                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1269                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1270                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1271                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1272         }
1273
1274         /* Invoke xgmi ta to get the topology information */
1275         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1276         if (ret)
1277                 return ret;
1278
1279         /* Read the output topology information from the shared memory */
1280         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1281         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1282         for (i = 0; i < topology->num_nodes; i++) {
1283                 /* extended data will either be 0 or equal to non-extended data */
1284                 if (topology_info_output->nodes[i].num_hops)
1285                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1286
1287                 /* non-extended data gets everything here so no need to update */
1288                 if (!get_extended_data) {
1289                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1290                         topology->nodes[i].is_sharing_enabled =
1291                                         topology_info_output->nodes[i].is_sharing_enabled;
1292                         topology->nodes[i].sdma_engine =
1293                                         topology_info_output->nodes[i].sdma_engine;
1294                 }
1295
1296         }
1297
1298         /* Invoke xgmi ta again to get the link information */
1299         if (psp_xgmi_peer_link_info_supported(psp)) {
1300                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1301
1302                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1303
1304                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1305
1306                 if (ret)
1307                         return ret;
1308
1309                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1310                 for (i = 0; i < topology->num_nodes; i++) {
1311                         /* accumulate num_links on extended data */
1312                         topology->nodes[i].num_links = get_extended_data ?
1313                                         topology->nodes[i].num_links +
1314                                                         link_info_output->nodes[i].num_links :
1315                                         link_info_output->nodes[i].num_links;
1316
1317                         /* reflect the topology information for bi-directionality */
1318                         if (psp->xgmi_context.supports_extended_data &&
1319                                         get_extended_data && topology->nodes[i].num_hops)
1320                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1321                 }
1322         }
1323
1324         return 0;
1325 }
1326
1327 int psp_xgmi_set_topology_info(struct psp_context *psp,
1328                                int number_devices,
1329                                struct psp_xgmi_topology_info *topology)
1330 {
1331         struct ta_xgmi_shared_memory *xgmi_cmd;
1332         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1333         int i;
1334
1335         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1336                 return -EINVAL;
1337
1338         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1339         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1340
1341         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1342         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1343         topology_info_input->num_nodes = number_devices;
1344
1345         for (i = 0; i < topology_info_input->num_nodes; i++) {
1346                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1347                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1348                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1349                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1350         }
1351
1352         /* Invoke xgmi ta to set topology information */
1353         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1354 }
1355
1356 // ras begin
1357 static void psp_ras_ta_check_status(struct psp_context *psp)
1358 {
1359         struct ta_ras_shared_memory *ras_cmd =
1360                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1361
1362         switch (ras_cmd->ras_status) {
1363         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1364                 dev_warn(psp->adev->dev,
1365                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1366                 break;
1367         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1368                 dev_warn(psp->adev->dev,
1369                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1370                 break;
1371         case TA_RAS_STATUS__SUCCESS:
1372                 break;
1373         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1374                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1375                         dev_warn(psp->adev->dev,
1376                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1377                 break;
1378         default:
1379                 dev_warn(psp->adev->dev,
1380                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1381                 break;
1382         }
1383 }
1384
1385 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1386 {
1387         struct ta_ras_shared_memory *ras_cmd;
1388         int ret;
1389
1390         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1391
1392         /*
1393          * TODO: bypass the loading in sriov for now
1394          */
1395         if (amdgpu_sriov_vf(psp->adev))
1396                 return 0;
1397
1398         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1399
1400         if (amdgpu_ras_intr_triggered())
1401                 return ret;
1402
1403         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1404         {
1405                 DRM_WARN("RAS: Unsupported Interface");
1406                 return -EINVAL;
1407         }
1408
1409         if (!ret) {
1410                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1411                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1412
1413                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1414                 }
1415                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1416                         dev_warn(psp->adev->dev,
1417                                  "RAS internal register access blocked\n");
1418
1419                 psp_ras_ta_check_status(psp);
1420         }
1421
1422         return ret;
1423 }
1424
1425 int psp_ras_enable_features(struct psp_context *psp,
1426                 union ta_ras_cmd_input *info, bool enable)
1427 {
1428         struct ta_ras_shared_memory *ras_cmd;
1429         int ret;
1430
1431         if (!psp->ras_context.context.initialized)
1432                 return -EINVAL;
1433
1434         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1435         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1436
1437         if (enable)
1438                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1439         else
1440                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1441
1442         ras_cmd->ras_in_message = *info;
1443
1444         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1445         if (ret)
1446                 return -EINVAL;
1447
1448         return 0;
1449 }
1450
1451 int psp_ras_terminate(struct psp_context *psp)
1452 {
1453         int ret;
1454
1455         /*
1456          * TODO: bypass the terminate in sriov for now
1457          */
1458         if (amdgpu_sriov_vf(psp->adev))
1459                 return 0;
1460
1461         if (!psp->ras_context.context.initialized)
1462                 return 0;
1463
1464         ret = psp_ta_unload(psp, &psp->ras_context.context);
1465
1466         psp->ras_context.context.initialized = false;
1467
1468         /* free ras shared memory */
1469         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
1470
1471         return ret;
1472 }
1473
1474 static int psp_ras_initialize(struct psp_context *psp)
1475 {
1476         int ret;
1477         uint32_t boot_cfg = 0xFF;
1478         struct amdgpu_device *adev = psp->adev;
1479         struct ta_ras_shared_memory *ras_cmd;
1480
1481         /*
1482          * TODO: bypass the initialize in sriov for now
1483          */
1484         if (amdgpu_sriov_vf(adev))
1485                 return 0;
1486
1487         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1488             !adev->psp.ras_context.context.bin_desc.start_addr) {
1489                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1490                 return 0;
1491         }
1492
1493         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1494                 /* query GECC enablement status from boot config
1495                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1496                  */
1497                 ret = psp_boot_config_get(adev, &boot_cfg);
1498                 if (ret)
1499                         dev_warn(adev->dev, "PSP get boot config failed\n");
1500
1501                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1502                         if (!boot_cfg) {
1503                                 dev_info(adev->dev, "GECC is disabled\n");
1504                         } else {
1505                                 /* disable GECC in next boot cycle if ras is
1506                                  * disabled by module parameter amdgpu_ras_enable
1507                                  * and/or amdgpu_ras_mask, or boot_config_get call
1508                                  * is failed
1509                                  */
1510                                 ret = psp_boot_config_set(adev, 0);
1511                                 if (ret)
1512                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1513                                 else
1514                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1515                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1516                         }
1517                 } else {
1518                         if (1 == boot_cfg) {
1519                                 dev_info(adev->dev, "GECC is enabled\n");
1520                         } else {
1521                                 /* enable GECC in next boot cycle if it is disabled
1522                                  * in boot config, or force enable GECC if failed to
1523                                  * get boot configuration
1524                                  */
1525                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1526                                 if (ret)
1527                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1528                                 else
1529                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1530                         }
1531                 }
1532         }
1533
1534         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1535         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1536
1537         if (!psp->ras_context.context.initialized) {
1538                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1539                 if (ret)
1540                         return ret;
1541         }
1542
1543         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1544         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1545
1546         if (amdgpu_ras_is_poison_mode_supported(adev))
1547                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1548         if (!adev->gmc.xgmi.connected_to_cpu)
1549                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1550
1551         ret = psp_ta_load(psp, &psp->ras_context.context);
1552
1553         if (!ret && !ras_cmd->ras_status)
1554                 psp->ras_context.context.initialized = true;
1555         else {
1556                 if (ras_cmd->ras_status)
1557                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1558                 amdgpu_ras_fini(psp->adev);
1559         }
1560
1561         return ret;
1562 }
1563
1564 int psp_ras_trigger_error(struct psp_context *psp,
1565                           struct ta_ras_trigger_error_input *info)
1566 {
1567         struct ta_ras_shared_memory *ras_cmd;
1568         int ret;
1569
1570         if (!psp->ras_context.context.initialized)
1571                 return -EINVAL;
1572
1573         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1574         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1575
1576         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1577         ras_cmd->ras_in_message.trigger_error = *info;
1578
1579         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1580         if (ret)
1581                 return -EINVAL;
1582
1583         /* If err_event_athub occurs error inject was successful, however
1584            return status from TA is no long reliable */
1585         if (amdgpu_ras_intr_triggered())
1586                 return 0;
1587
1588         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1589                 return -EACCES;
1590         else if (ras_cmd->ras_status)
1591                 return -EINVAL;
1592
1593         return 0;
1594 }
1595 // ras end
1596
1597 // HDCP start
1598 static int psp_hdcp_initialize(struct psp_context *psp)
1599 {
1600         int ret;
1601
1602         /*
1603          * TODO: bypass the initialize in sriov for now
1604          */
1605         if (amdgpu_sriov_vf(psp->adev))
1606                 return 0;
1607
1608         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1609             !psp->hdcp_context.context.bin_desc.start_addr) {
1610                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1611                 return 0;
1612         }
1613
1614         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1615         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1616
1617         if (!psp->hdcp_context.context.initialized) {
1618                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1619                 if (ret)
1620                         return ret;
1621         }
1622
1623         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1624         if (!ret) {
1625                 psp->hdcp_context.context.initialized = true;
1626                 mutex_init(&psp->hdcp_context.mutex);
1627         }
1628
1629         return ret;
1630 }
1631
1632 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1633 {
1634         /*
1635          * TODO: bypass the loading in sriov for now
1636          */
1637         if (amdgpu_sriov_vf(psp->adev))
1638                 return 0;
1639
1640         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1641 }
1642
1643 static int psp_hdcp_terminate(struct psp_context *psp)
1644 {
1645         int ret;
1646
1647         /*
1648          * TODO: bypass the terminate in sriov for now
1649          */
1650         if (amdgpu_sriov_vf(psp->adev))
1651                 return 0;
1652
1653         if (!psp->hdcp_context.context.initialized) {
1654                 if (psp->hdcp_context.context.mem_context.shared_buf) {
1655                         ret = 0;
1656                         goto out;
1657                 } else {
1658                         return 0;
1659                 }
1660         }
1661
1662         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1663
1664         psp->hdcp_context.context.initialized = false;
1665
1666 out:
1667         /* free hdcp shared memory */
1668         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
1669
1670         return ret;
1671 }
1672 // HDCP end
1673
1674 // DTM start
1675 static int psp_dtm_initialize(struct psp_context *psp)
1676 {
1677         int ret;
1678
1679         /*
1680          * TODO: bypass the initialize in sriov for now
1681          */
1682         if (amdgpu_sriov_vf(psp->adev))
1683                 return 0;
1684
1685         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1686             !psp->dtm_context.context.bin_desc.start_addr) {
1687                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1688                 return 0;
1689         }
1690
1691         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1692         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1693
1694         if (!psp->dtm_context.context.initialized) {
1695                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1696                 if (ret)
1697                         return ret;
1698         }
1699
1700         ret = psp_ta_load(psp, &psp->dtm_context.context);
1701         if (!ret) {
1702                 psp->dtm_context.context.initialized = true;
1703                 mutex_init(&psp->dtm_context.mutex);
1704         }
1705
1706         return ret;
1707 }
1708
1709 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1710 {
1711         /*
1712          * TODO: bypass the loading in sriov for now
1713          */
1714         if (amdgpu_sriov_vf(psp->adev))
1715                 return 0;
1716
1717         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1718 }
1719
1720 static int psp_dtm_terminate(struct psp_context *psp)
1721 {
1722         int ret;
1723
1724         /*
1725          * TODO: bypass the terminate in sriov for now
1726          */
1727         if (amdgpu_sriov_vf(psp->adev))
1728                 return 0;
1729
1730         if (!psp->dtm_context.context.initialized) {
1731                 if (psp->dtm_context.context.mem_context.shared_buf) {
1732                         ret = 0;
1733                         goto out;
1734                 } else {
1735                         return 0;
1736                 }
1737         }
1738
1739         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1740
1741         psp->dtm_context.context.initialized = false;
1742
1743 out:
1744         /* free dtm shared memory */
1745         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
1746
1747         return ret;
1748 }
1749 // DTM end
1750
1751 // RAP start
1752 static int psp_rap_initialize(struct psp_context *psp)
1753 {
1754         int ret;
1755         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1756
1757         /*
1758          * TODO: bypass the initialize in sriov for now
1759          */
1760         if (amdgpu_sriov_vf(psp->adev))
1761                 return 0;
1762
1763         if (!psp->rap_context.context.bin_desc.size_bytes ||
1764             !psp->rap_context.context.bin_desc.start_addr) {
1765                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1766                 return 0;
1767         }
1768
1769         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1770         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1771
1772         if (!psp->rap_context.context.initialized) {
1773                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1774                 if (ret)
1775                         return ret;
1776         }
1777
1778         ret = psp_ta_load(psp, &psp->rap_context.context);
1779         if (!ret) {
1780                 psp->rap_context.context.initialized = true;
1781                 mutex_init(&psp->rap_context.mutex);
1782         } else
1783                 return ret;
1784
1785         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1786         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1787                 psp_rap_terminate(psp);
1788
1789                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1790                          ret, status);
1791
1792                 return ret;
1793         }
1794
1795         return 0;
1796 }
1797
1798 static int psp_rap_terminate(struct psp_context *psp)
1799 {
1800         int ret;
1801
1802         if (!psp->rap_context.context.initialized)
1803                 return 0;
1804
1805         ret = psp_ta_unload(psp, &psp->rap_context.context);
1806
1807         psp->rap_context.context.initialized = false;
1808
1809         /* free rap shared memory */
1810         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1811
1812         return ret;
1813 }
1814
1815 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1816 {
1817         struct ta_rap_shared_memory *rap_cmd;
1818         int ret = 0;
1819
1820         if (!psp->rap_context.context.initialized)
1821                 return 0;
1822
1823         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1824             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1825                 return -EINVAL;
1826
1827         mutex_lock(&psp->rap_context.mutex);
1828
1829         rap_cmd = (struct ta_rap_shared_memory *)
1830                   psp->rap_context.context.mem_context.shared_buf;
1831         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1832
1833         rap_cmd->cmd_id = ta_cmd_id;
1834         rap_cmd->validation_method_id = METHOD_A;
1835
1836         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1837         if (ret)
1838                 goto out_unlock;
1839
1840         if (status)
1841                 *status = rap_cmd->rap_status;
1842
1843 out_unlock:
1844         mutex_unlock(&psp->rap_context.mutex);
1845
1846         return ret;
1847 }
1848 // RAP end
1849
1850 /* securedisplay start */
1851 static int psp_securedisplay_initialize(struct psp_context *psp)
1852 {
1853         int ret;
1854         struct securedisplay_cmd *securedisplay_cmd;
1855
1856         /*
1857          * TODO: bypass the initialize in sriov for now
1858          */
1859         if (amdgpu_sriov_vf(psp->adev))
1860                 return 0;
1861
1862         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1863             !psp->securedisplay_context.context.bin_desc.start_addr) {
1864                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1865                 return 0;
1866         }
1867
1868         psp->securedisplay_context.context.mem_context.shared_mem_size =
1869                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1870         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1871
1872         if (!psp->securedisplay_context.context.initialized) {
1873                 ret = psp_ta_init_shared_buf(psp,
1874                                              &psp->securedisplay_context.context.mem_context);
1875                 if (ret)
1876                         return ret;
1877         }
1878
1879         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1880         if (!ret) {
1881                 psp->securedisplay_context.context.initialized = true;
1882                 mutex_init(&psp->securedisplay_context.mutex);
1883         } else
1884                 return ret;
1885
1886         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1887                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1888
1889         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1890         if (ret) {
1891                 psp_securedisplay_terminate(psp);
1892                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1893                 return -EINVAL;
1894         }
1895
1896         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1897                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1898                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1899                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1900         }
1901
1902         return 0;
1903 }
1904
1905 static int psp_securedisplay_terminate(struct psp_context *psp)
1906 {
1907         int ret;
1908
1909         /*
1910          * TODO:bypass the terminate in sriov for now
1911          */
1912         if (amdgpu_sriov_vf(psp->adev))
1913                 return 0;
1914
1915         if (!psp->securedisplay_context.context.initialized)
1916                 return 0;
1917
1918         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1919
1920         psp->securedisplay_context.context.initialized = false;
1921
1922         /* free securedisplay shared memory */
1923         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1924
1925         return ret;
1926 }
1927
1928 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1929 {
1930         int ret;
1931
1932         if (!psp->securedisplay_context.context.initialized)
1933                 return -EINVAL;
1934
1935         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1936             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1937                 return -EINVAL;
1938
1939         mutex_lock(&psp->securedisplay_context.mutex);
1940
1941         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1942
1943         mutex_unlock(&psp->securedisplay_context.mutex);
1944
1945         return ret;
1946 }
1947 /* SECUREDISPLAY end */
1948
1949 static int psp_hw_start(struct psp_context *psp)
1950 {
1951         struct amdgpu_device *adev = psp->adev;
1952         int ret;
1953
1954         if (!amdgpu_sriov_vf(adev)) {
1955                 if ((is_psp_fw_valid(psp->kdb)) &&
1956                     (psp->funcs->bootloader_load_kdb != NULL)) {
1957                         ret = psp_bootloader_load_kdb(psp);
1958                         if (ret) {
1959                                 DRM_ERROR("PSP load kdb failed!\n");
1960                                 return ret;
1961                         }
1962                 }
1963
1964                 if ((is_psp_fw_valid(psp->spl)) &&
1965                     (psp->funcs->bootloader_load_spl != NULL)) {
1966                         ret = psp_bootloader_load_spl(psp);
1967                         if (ret) {
1968                                 DRM_ERROR("PSP load spl failed!\n");
1969                                 return ret;
1970                         }
1971                 }
1972
1973                 if ((is_psp_fw_valid(psp->sys)) &&
1974                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
1975                         ret = psp_bootloader_load_sysdrv(psp);
1976                         if (ret) {
1977                                 DRM_ERROR("PSP load sys drv failed!\n");
1978                                 return ret;
1979                         }
1980                 }
1981
1982                 if ((is_psp_fw_valid(psp->soc_drv)) &&
1983                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
1984                         ret = psp_bootloader_load_soc_drv(psp);
1985                         if (ret) {
1986                                 DRM_ERROR("PSP load soc drv failed!\n");
1987                                 return ret;
1988                         }
1989                 }
1990
1991                 if ((is_psp_fw_valid(psp->intf_drv)) &&
1992                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
1993                         ret = psp_bootloader_load_intf_drv(psp);
1994                         if (ret) {
1995                                 DRM_ERROR("PSP load intf drv failed!\n");
1996                                 return ret;
1997                         }
1998                 }
1999
2000                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2001                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2002                         ret = psp_bootloader_load_dbg_drv(psp);
2003                         if (ret) {
2004                                 DRM_ERROR("PSP load dbg drv failed!\n");
2005                                 return ret;
2006                         }
2007                 }
2008
2009                 if ((is_psp_fw_valid(psp->sos)) &&
2010                     (psp->funcs->bootloader_load_sos != NULL)) {
2011                         ret = psp_bootloader_load_sos(psp);
2012                         if (ret) {
2013                                 DRM_ERROR("PSP load sos failed!\n");
2014                                 return ret;
2015                         }
2016                 }
2017         }
2018
2019         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2020         if (ret) {
2021                 DRM_ERROR("PSP create ring failed!\n");
2022                 return ret;
2023         }
2024
2025         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2026                 goto skip_pin_bo;
2027
2028         ret = psp_tmr_init(psp);
2029         if (ret) {
2030                 DRM_ERROR("PSP tmr init failed!\n");
2031                 return ret;
2032         }
2033
2034 skip_pin_bo:
2035         /*
2036          * For ASICs with DF Cstate management centralized
2037          * to PMFW, TMR setup should be performed after PMFW
2038          * loaded and before other non-psp firmware loaded.
2039          */
2040         if (psp->pmfw_centralized_cstate_management) {
2041                 ret = psp_load_smu_fw(psp);
2042                 if (ret)
2043                         return ret;
2044         }
2045
2046         ret = psp_tmr_load(psp);
2047         if (ret) {
2048                 DRM_ERROR("PSP load tmr failed!\n");
2049                 return ret;
2050         }
2051
2052         return 0;
2053 }
2054
2055 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2056                            enum psp_gfx_fw_type *type)
2057 {
2058         switch (ucode->ucode_id) {
2059         case AMDGPU_UCODE_ID_CAP:
2060                 *type = GFX_FW_TYPE_CAP;
2061                 break;
2062         case AMDGPU_UCODE_ID_SDMA0:
2063                 *type = GFX_FW_TYPE_SDMA0;
2064                 break;
2065         case AMDGPU_UCODE_ID_SDMA1:
2066                 *type = GFX_FW_TYPE_SDMA1;
2067                 break;
2068         case AMDGPU_UCODE_ID_SDMA2:
2069                 *type = GFX_FW_TYPE_SDMA2;
2070                 break;
2071         case AMDGPU_UCODE_ID_SDMA3:
2072                 *type = GFX_FW_TYPE_SDMA3;
2073                 break;
2074         case AMDGPU_UCODE_ID_SDMA4:
2075                 *type = GFX_FW_TYPE_SDMA4;
2076                 break;
2077         case AMDGPU_UCODE_ID_SDMA5:
2078                 *type = GFX_FW_TYPE_SDMA5;
2079                 break;
2080         case AMDGPU_UCODE_ID_SDMA6:
2081                 *type = GFX_FW_TYPE_SDMA6;
2082                 break;
2083         case AMDGPU_UCODE_ID_SDMA7:
2084                 *type = GFX_FW_TYPE_SDMA7;
2085                 break;
2086         case AMDGPU_UCODE_ID_CP_MES:
2087                 *type = GFX_FW_TYPE_CP_MES;
2088                 break;
2089         case AMDGPU_UCODE_ID_CP_MES_DATA:
2090                 *type = GFX_FW_TYPE_MES_STACK;
2091                 break;
2092         case AMDGPU_UCODE_ID_CP_CE:
2093                 *type = GFX_FW_TYPE_CP_CE;
2094                 break;
2095         case AMDGPU_UCODE_ID_CP_PFP:
2096                 *type = GFX_FW_TYPE_CP_PFP;
2097                 break;
2098         case AMDGPU_UCODE_ID_CP_ME:
2099                 *type = GFX_FW_TYPE_CP_ME;
2100                 break;
2101         case AMDGPU_UCODE_ID_CP_MEC1:
2102                 *type = GFX_FW_TYPE_CP_MEC;
2103                 break;
2104         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2105                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2106                 break;
2107         case AMDGPU_UCODE_ID_CP_MEC2:
2108                 *type = GFX_FW_TYPE_CP_MEC;
2109                 break;
2110         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2111                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2112                 break;
2113         case AMDGPU_UCODE_ID_RLC_G:
2114                 *type = GFX_FW_TYPE_RLC_G;
2115                 break;
2116         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2117                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2118                 break;
2119         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2120                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2121                 break;
2122         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2123                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2124                 break;
2125         case AMDGPU_UCODE_ID_RLC_IRAM:
2126                 *type = GFX_FW_TYPE_RLC_IRAM;
2127                 break;
2128         case AMDGPU_UCODE_ID_RLC_DRAM:
2129                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2130                 break;
2131         case AMDGPU_UCODE_ID_SMC:
2132                 *type = GFX_FW_TYPE_SMU;
2133                 break;
2134         case AMDGPU_UCODE_ID_UVD:
2135                 *type = GFX_FW_TYPE_UVD;
2136                 break;
2137         case AMDGPU_UCODE_ID_UVD1:
2138                 *type = GFX_FW_TYPE_UVD1;
2139                 break;
2140         case AMDGPU_UCODE_ID_VCE:
2141                 *type = GFX_FW_TYPE_VCE;
2142                 break;
2143         case AMDGPU_UCODE_ID_VCN:
2144                 *type = GFX_FW_TYPE_VCN;
2145                 break;
2146         case AMDGPU_UCODE_ID_VCN1:
2147                 *type = GFX_FW_TYPE_VCN1;
2148                 break;
2149         case AMDGPU_UCODE_ID_DMCU_ERAM:
2150                 *type = GFX_FW_TYPE_DMCU_ERAM;
2151                 break;
2152         case AMDGPU_UCODE_ID_DMCU_INTV:
2153                 *type = GFX_FW_TYPE_DMCU_ISR;
2154                 break;
2155         case AMDGPU_UCODE_ID_VCN0_RAM:
2156                 *type = GFX_FW_TYPE_VCN0_RAM;
2157                 break;
2158         case AMDGPU_UCODE_ID_VCN1_RAM:
2159                 *type = GFX_FW_TYPE_VCN1_RAM;
2160                 break;
2161         case AMDGPU_UCODE_ID_DMCUB:
2162                 *type = GFX_FW_TYPE_DMUB;
2163                 break;
2164         case AMDGPU_UCODE_ID_MAXIMUM:
2165         default:
2166                 return -EINVAL;
2167         }
2168
2169         return 0;
2170 }
2171
2172 static void psp_print_fw_hdr(struct psp_context *psp,
2173                              struct amdgpu_firmware_info *ucode)
2174 {
2175         struct amdgpu_device *adev = psp->adev;
2176         struct common_firmware_header *hdr;
2177
2178         switch (ucode->ucode_id) {
2179         case AMDGPU_UCODE_ID_SDMA0:
2180         case AMDGPU_UCODE_ID_SDMA1:
2181         case AMDGPU_UCODE_ID_SDMA2:
2182         case AMDGPU_UCODE_ID_SDMA3:
2183         case AMDGPU_UCODE_ID_SDMA4:
2184         case AMDGPU_UCODE_ID_SDMA5:
2185         case AMDGPU_UCODE_ID_SDMA6:
2186         case AMDGPU_UCODE_ID_SDMA7:
2187                 hdr = (struct common_firmware_header *)
2188                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2189                 amdgpu_ucode_print_sdma_hdr(hdr);
2190                 break;
2191         case AMDGPU_UCODE_ID_CP_CE:
2192                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2193                 amdgpu_ucode_print_gfx_hdr(hdr);
2194                 break;
2195         case AMDGPU_UCODE_ID_CP_PFP:
2196                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2197                 amdgpu_ucode_print_gfx_hdr(hdr);
2198                 break;
2199         case AMDGPU_UCODE_ID_CP_ME:
2200                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2201                 amdgpu_ucode_print_gfx_hdr(hdr);
2202                 break;
2203         case AMDGPU_UCODE_ID_CP_MEC1:
2204                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2205                 amdgpu_ucode_print_gfx_hdr(hdr);
2206                 break;
2207         case AMDGPU_UCODE_ID_RLC_G:
2208                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2209                 amdgpu_ucode_print_rlc_hdr(hdr);
2210                 break;
2211         case AMDGPU_UCODE_ID_SMC:
2212                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2213                 amdgpu_ucode_print_smc_hdr(hdr);
2214                 break;
2215         default:
2216                 break;
2217         }
2218 }
2219
2220 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2221                                        struct psp_gfx_cmd_resp *cmd)
2222 {
2223         int ret;
2224         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2225
2226         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2227         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2228         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2229         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2230
2231         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2232         if (ret)
2233                 DRM_ERROR("Unknown firmware type\n");
2234
2235         return ret;
2236 }
2237
2238 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2239                                   struct amdgpu_firmware_info *ucode)
2240 {
2241         int ret = 0;
2242         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2243
2244         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2245         if (!ret) {
2246                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2247                                          psp->fence_buf_mc_addr);
2248         }
2249
2250         release_psp_cmd_buf(psp);
2251
2252         return ret;
2253 }
2254
2255 static int psp_load_smu_fw(struct psp_context *psp)
2256 {
2257         int ret;
2258         struct amdgpu_device *adev = psp->adev;
2259         struct amdgpu_firmware_info *ucode =
2260                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2261         struct amdgpu_ras *ras = psp->ras_context.ras;
2262
2263         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2264                 return 0;
2265
2266         if ((amdgpu_in_reset(adev) &&
2267              ras && adev->ras_enabled &&
2268              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2269               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2270                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2271                 if (ret) {
2272                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2273                 }
2274         }
2275
2276         ret = psp_execute_non_psp_fw_load(psp, ucode);
2277
2278         if (ret)
2279                 DRM_ERROR("PSP load smu failed!\n");
2280
2281         return ret;
2282 }
2283
2284 static bool fw_load_skip_check(struct psp_context *psp,
2285                                struct amdgpu_firmware_info *ucode)
2286 {
2287         if (!ucode->fw)
2288                 return true;
2289
2290         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2291             (psp_smu_reload_quirk(psp) ||
2292              psp->autoload_supported ||
2293              psp->pmfw_centralized_cstate_management))
2294                 return true;
2295
2296         if (amdgpu_sriov_vf(psp->adev) &&
2297            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2298             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2299             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2300             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2301             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2302             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2303             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2304             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2305             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2306             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2307             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2308             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2309             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2310                 /*skip ucode loading in SRIOV VF */
2311                 return true;
2312
2313         if (psp->autoload_supported &&
2314             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2315              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2316                 /* skip mec JT when autoload is enabled */
2317                 return true;
2318
2319         return false;
2320 }
2321
2322 int psp_load_fw_list(struct psp_context *psp,
2323                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2324 {
2325         int ret = 0, i;
2326         struct amdgpu_firmware_info *ucode;
2327
2328         for (i = 0; i < ucode_count; ++i) {
2329                 ucode = ucode_list[i];
2330                 psp_print_fw_hdr(psp, ucode);
2331                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2332                 if (ret)
2333                         return ret;
2334         }
2335         return ret;
2336 }
2337
2338 static int psp_load_non_psp_fw(struct psp_context *psp)
2339 {
2340         int i, ret;
2341         struct amdgpu_firmware_info *ucode;
2342         struct amdgpu_device *adev = psp->adev;
2343
2344         if (psp->autoload_supported &&
2345             !psp->pmfw_centralized_cstate_management) {
2346                 ret = psp_load_smu_fw(psp);
2347                 if (ret)
2348                         return ret;
2349         }
2350
2351         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2352                 ucode = &adev->firmware.ucode[i];
2353
2354                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2355                     !fw_load_skip_check(psp, ucode)) {
2356                         ret = psp_load_smu_fw(psp);
2357                         if (ret)
2358                                 return ret;
2359                         continue;
2360                 }
2361
2362                 if (fw_load_skip_check(psp, ucode))
2363                         continue;
2364
2365                 if (psp->autoload_supported &&
2366                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2367                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2368                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2369                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2370                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2371                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2372                         /* PSP only receive one SDMA fw for sienna_cichlid,
2373                          * as all four sdma fw are same */
2374                         continue;
2375
2376                 psp_print_fw_hdr(psp, ucode);
2377
2378                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2379                 if (ret)
2380                         return ret;
2381
2382                 /* Start rlc autoload after psp recieved all the gfx firmware */
2383                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2384                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2385                         ret = psp_rlc_autoload_start(psp);
2386                         if (ret) {
2387                                 DRM_ERROR("Failed to start rlc autoload\n");
2388                                 return ret;
2389                         }
2390                 }
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int psp_load_fw(struct amdgpu_device *adev)
2397 {
2398         int ret;
2399         struct psp_context *psp = &adev->psp;
2400
2401         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2402                 /* should not destroy ring, only stop */
2403                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2404         } else {
2405                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2406
2407                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2408                 if (ret) {
2409                         DRM_ERROR("PSP ring init failed!\n");
2410                         goto failed;
2411                 }
2412         }
2413
2414         ret = psp_hw_start(psp);
2415         if (ret)
2416                 goto failed;
2417
2418         ret = psp_load_non_psp_fw(psp);
2419         if (ret)
2420                 goto failed;
2421
2422         ret = psp_asd_initialize(psp);
2423         if (ret) {
2424                 DRM_ERROR("PSP load asd failed!\n");
2425                 return ret;
2426         }
2427
2428         ret = psp_rl_load(adev);
2429         if (ret) {
2430                 DRM_ERROR("PSP load RL failed!\n");
2431                 return ret;
2432         }
2433
2434         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2435                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2436                         ret = psp_xgmi_initialize(psp, false, true);
2437                         /* Warning the XGMI seesion initialize failure
2438                         * Instead of stop driver initialization
2439                         */
2440                         if (ret)
2441                                 dev_err(psp->adev->dev,
2442                                         "XGMI: Failed to initialize XGMI session\n");
2443                 }
2444         }
2445
2446         if (psp->ta_fw) {
2447                 ret = psp_ras_initialize(psp);
2448                 if (ret)
2449                         dev_err(psp->adev->dev,
2450                                         "RAS: Failed to initialize RAS\n");
2451
2452                 ret = psp_hdcp_initialize(psp);
2453                 if (ret)
2454                         dev_err(psp->adev->dev,
2455                                 "HDCP: Failed to initialize HDCP\n");
2456
2457                 ret = psp_dtm_initialize(psp);
2458                 if (ret)
2459                         dev_err(psp->adev->dev,
2460                                 "DTM: Failed to initialize DTM\n");
2461
2462                 ret = psp_rap_initialize(psp);
2463                 if (ret)
2464                         dev_err(psp->adev->dev,
2465                                 "RAP: Failed to initialize RAP\n");
2466
2467                 ret = psp_securedisplay_initialize(psp);
2468                 if (ret)
2469                         dev_err(psp->adev->dev,
2470                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2471         }
2472
2473         return 0;
2474
2475 failed:
2476         /*
2477          * all cleanup jobs (xgmi terminate, ras terminate,
2478          * ring destroy, cmd/fence/fw buffers destory,
2479          * psp->cmd destory) are delayed to psp_hw_fini
2480          */
2481         return ret;
2482 }
2483
2484 static int psp_hw_init(void *handle)
2485 {
2486         int ret;
2487         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2488
2489         mutex_lock(&adev->firmware.mutex);
2490         /*
2491          * This sequence is just used on hw_init only once, no need on
2492          * resume.
2493          */
2494         ret = amdgpu_ucode_init_bo(adev);
2495         if (ret)
2496                 goto failed;
2497
2498         ret = psp_load_fw(adev);
2499         if (ret) {
2500                 DRM_ERROR("PSP firmware loading failed\n");
2501                 goto failed;
2502         }
2503
2504         mutex_unlock(&adev->firmware.mutex);
2505         return 0;
2506
2507 failed:
2508         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2509         mutex_unlock(&adev->firmware.mutex);
2510         return -EINVAL;
2511 }
2512
2513 static int psp_hw_fini(void *handle)
2514 {
2515         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2516         struct psp_context *psp = &adev->psp;
2517
2518         if (psp->ta_fw) {
2519                 psp_ras_terminate(psp);
2520                 psp_securedisplay_terminate(psp);
2521                 psp_rap_terminate(psp);
2522                 psp_dtm_terminate(psp);
2523                 psp_hdcp_terminate(psp);
2524         }
2525
2526         psp_asd_terminate(psp);
2527
2528         psp_tmr_terminate(psp);
2529         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2530
2531         return 0;
2532 }
2533
2534 static int psp_suspend(void *handle)
2535 {
2536         int ret;
2537         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2538         struct psp_context *psp = &adev->psp;
2539
2540         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2541             psp->xgmi_context.context.initialized) {
2542                 ret = psp_xgmi_terminate(psp);
2543                 if (ret) {
2544                         DRM_ERROR("Failed to terminate xgmi ta\n");
2545                         return ret;
2546                 }
2547         }
2548
2549         if (psp->ta_fw) {
2550                 ret = psp_ras_terminate(psp);
2551                 if (ret) {
2552                         DRM_ERROR("Failed to terminate ras ta\n");
2553                         return ret;
2554                 }
2555                 ret = psp_hdcp_terminate(psp);
2556                 if (ret) {
2557                         DRM_ERROR("Failed to terminate hdcp ta\n");
2558                         return ret;
2559                 }
2560                 ret = psp_dtm_terminate(psp);
2561                 if (ret) {
2562                         DRM_ERROR("Failed to terminate dtm ta\n");
2563                         return ret;
2564                 }
2565                 ret = psp_rap_terminate(psp);
2566                 if (ret) {
2567                         DRM_ERROR("Failed to terminate rap ta\n");
2568                         return ret;
2569                 }
2570                 ret = psp_securedisplay_terminate(psp);
2571                 if (ret) {
2572                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2573                         return ret;
2574                 }
2575         }
2576
2577         ret = psp_asd_terminate(psp);
2578         if (ret) {
2579                 DRM_ERROR("Failed to terminate asd\n");
2580                 return ret;
2581         }
2582
2583         ret = psp_tmr_terminate(psp);
2584         if (ret) {
2585                 DRM_ERROR("Failed to terminate tmr\n");
2586                 return ret;
2587         }
2588
2589         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2590         if (ret) {
2591                 DRM_ERROR("PSP ring stop failed\n");
2592                 return ret;
2593         }
2594
2595         return 0;
2596 }
2597
2598 static int psp_resume(void *handle)
2599 {
2600         int ret;
2601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2602         struct psp_context *psp = &adev->psp;
2603
2604         DRM_INFO("PSP is resuming...\n");
2605
2606         if (psp->mem_train_ctx.enable_mem_training) {
2607                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2608                 if (ret) {
2609                         DRM_ERROR("Failed to process memory training!\n");
2610                         return ret;
2611                 }
2612         }
2613
2614         mutex_lock(&adev->firmware.mutex);
2615
2616         ret = psp_hw_start(psp);
2617         if (ret)
2618                 goto failed;
2619
2620         ret = psp_load_non_psp_fw(psp);
2621         if (ret)
2622                 goto failed;
2623
2624         ret = psp_asd_initialize(psp);
2625         if (ret) {
2626                 DRM_ERROR("PSP load asd failed!\n");
2627                 goto failed;
2628         }
2629
2630         ret = psp_rl_load(adev);
2631         if (ret) {
2632                 dev_err(adev->dev, "PSP load RL failed!\n");
2633                 goto failed;
2634         }
2635
2636         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2637                 ret = psp_xgmi_initialize(psp, false, true);
2638                 /* Warning the XGMI seesion initialize failure
2639                  * Instead of stop driver initialization
2640                  */
2641                 if (ret)
2642                         dev_err(psp->adev->dev,
2643                                 "XGMI: Failed to initialize XGMI session\n");
2644         }
2645
2646         if (psp->ta_fw) {
2647                 ret = psp_ras_initialize(psp);
2648                 if (ret)
2649                         dev_err(psp->adev->dev,
2650                                         "RAS: Failed to initialize RAS\n");
2651
2652                 ret = psp_hdcp_initialize(psp);
2653                 if (ret)
2654                         dev_err(psp->adev->dev,
2655                                 "HDCP: Failed to initialize HDCP\n");
2656
2657                 ret = psp_dtm_initialize(psp);
2658                 if (ret)
2659                         dev_err(psp->adev->dev,
2660                                 "DTM: Failed to initialize DTM\n");
2661
2662                 ret = psp_rap_initialize(psp);
2663                 if (ret)
2664                         dev_err(psp->adev->dev,
2665                                 "RAP: Failed to initialize RAP\n");
2666
2667                 ret = psp_securedisplay_initialize(psp);
2668                 if (ret)
2669                         dev_err(psp->adev->dev,
2670                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2671         }
2672
2673         mutex_unlock(&adev->firmware.mutex);
2674
2675         return 0;
2676
2677 failed:
2678         DRM_ERROR("PSP resume failed\n");
2679         mutex_unlock(&adev->firmware.mutex);
2680         return ret;
2681 }
2682
2683 int psp_gpu_reset(struct amdgpu_device *adev)
2684 {
2685         int ret;
2686
2687         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2688                 return 0;
2689
2690         mutex_lock(&adev->psp.mutex);
2691         ret = psp_mode1_reset(&adev->psp);
2692         mutex_unlock(&adev->psp.mutex);
2693
2694         return ret;
2695 }
2696
2697 int psp_rlc_autoload_start(struct psp_context *psp)
2698 {
2699         int ret;
2700         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2701
2702         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2703
2704         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2705                                  psp->fence_buf_mc_addr);
2706
2707         release_psp_cmd_buf(psp);
2708
2709         return ret;
2710 }
2711
2712 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2713                         uint64_t cmd_gpu_addr, int cmd_size)
2714 {
2715         struct amdgpu_firmware_info ucode = {0};
2716
2717         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2718                 AMDGPU_UCODE_ID_VCN0_RAM;
2719         ucode.mc_addr = cmd_gpu_addr;
2720         ucode.ucode_size = cmd_size;
2721
2722         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2723 }
2724
2725 int psp_ring_cmd_submit(struct psp_context *psp,
2726                         uint64_t cmd_buf_mc_addr,
2727                         uint64_t fence_mc_addr,
2728                         int index)
2729 {
2730         unsigned int psp_write_ptr_reg = 0;
2731         struct psp_gfx_rb_frame *write_frame;
2732         struct psp_ring *ring = &psp->km_ring;
2733         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2734         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2735                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2736         struct amdgpu_device *adev = psp->adev;
2737         uint32_t ring_size_dw = ring->ring_size / 4;
2738         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2739
2740         /* KM (GPCOM) prepare write pointer */
2741         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2742
2743         /* Update KM RB frame pointer to new frame */
2744         /* write_frame ptr increments by size of rb_frame in bytes */
2745         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2746         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2747                 write_frame = ring_buffer_start;
2748         else
2749                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2750         /* Check invalid write_frame ptr address */
2751         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2752                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2753                           ring_buffer_start, ring_buffer_end, write_frame);
2754                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2755                 return -EINVAL;
2756         }
2757
2758         /* Initialize KM RB frame */
2759         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2760
2761         /* Update KM RB frame */
2762         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2763         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2764         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2765         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2766         write_frame->fence_value = index;
2767         amdgpu_device_flush_hdp(adev, NULL);
2768
2769         /* Update the write Pointer in DWORDs */
2770         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2771         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2772         return 0;
2773 }
2774
2775 int psp_init_asd_microcode(struct psp_context *psp,
2776                            const char *chip_name)
2777 {
2778         struct amdgpu_device *adev = psp->adev;
2779         char fw_name[PSP_FW_NAME_LEN];
2780         const struct psp_firmware_header_v1_0 *asd_hdr;
2781         int err = 0;
2782
2783         if (!chip_name) {
2784                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2785                 return -EINVAL;
2786         }
2787
2788         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2789         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2790         if (err)
2791                 goto out;
2792
2793         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2794         if (err)
2795                 goto out;
2796
2797         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2798         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2799         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2800         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2801         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2802                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2803         return 0;
2804 out:
2805         dev_err(adev->dev, "fail to initialize asd microcode\n");
2806         release_firmware(adev->psp.asd_fw);
2807         adev->psp.asd_fw = NULL;
2808         return err;
2809 }
2810
2811 int psp_init_toc_microcode(struct psp_context *psp,
2812                            const char *chip_name)
2813 {
2814         struct amdgpu_device *adev = psp->adev;
2815         char fw_name[PSP_FW_NAME_LEN];
2816         const struct psp_firmware_header_v1_0 *toc_hdr;
2817         int err = 0;
2818
2819         if (!chip_name) {
2820                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2821                 return -EINVAL;
2822         }
2823
2824         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2825         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2826         if (err)
2827                 goto out;
2828
2829         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2830         if (err)
2831                 goto out;
2832
2833         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2834         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2835         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2836         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2837         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2838                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2839         return 0;
2840 out:
2841         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2842         release_firmware(adev->psp.toc_fw);
2843         adev->psp.toc_fw = NULL;
2844         return err;
2845 }
2846
2847 static int parse_sos_bin_descriptor(struct psp_context *psp,
2848                                    const struct psp_fw_bin_desc *desc,
2849                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2850 {
2851         uint8_t *ucode_start_addr  = NULL;
2852
2853         if (!psp || !desc || !sos_hdr)
2854                 return -EINVAL;
2855
2856         ucode_start_addr  = (uint8_t *)sos_hdr +
2857                             le32_to_cpu(desc->offset_bytes) +
2858                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2859
2860         switch (desc->fw_type) {
2861         case PSP_FW_TYPE_PSP_SOS:
2862                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2863                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
2864                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
2865                 psp->sos.start_addr        = ucode_start_addr;
2866                 break;
2867         case PSP_FW_TYPE_PSP_SYS_DRV:
2868                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
2869                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
2870                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
2871                 psp->sys.start_addr        = ucode_start_addr;
2872                 break;
2873         case PSP_FW_TYPE_PSP_KDB:
2874                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
2875                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
2876                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
2877                 psp->kdb.start_addr        = ucode_start_addr;
2878                 break;
2879         case PSP_FW_TYPE_PSP_TOC:
2880                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
2881                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
2882                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
2883                 psp->toc.start_addr        = ucode_start_addr;
2884                 break;
2885         case PSP_FW_TYPE_PSP_SPL:
2886                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
2887                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
2888                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
2889                 psp->spl.start_addr        = ucode_start_addr;
2890                 break;
2891         case PSP_FW_TYPE_PSP_RL:
2892                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
2893                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
2894                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
2895                 psp->rl.start_addr         = ucode_start_addr;
2896                 break;
2897         case PSP_FW_TYPE_PSP_SOC_DRV:
2898                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
2899                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
2900                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
2901                 psp->soc_drv.start_addr         = ucode_start_addr;
2902                 break;
2903         case PSP_FW_TYPE_PSP_INTF_DRV:
2904                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
2905                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
2906                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
2907                 psp->intf_drv.start_addr        = ucode_start_addr;
2908                 break;
2909         case PSP_FW_TYPE_PSP_DBG_DRV:
2910                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
2911                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
2912                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
2913                 psp->dbg_drv.start_addr         = ucode_start_addr;
2914                 break;
2915         default:
2916                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
2917                 break;
2918         }
2919
2920         return 0;
2921 }
2922
2923 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
2924 {
2925         const struct psp_firmware_header_v1_0 *sos_hdr;
2926         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2927         uint8_t *ucode_array_start_addr;
2928
2929         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2930         ucode_array_start_addr = (uint8_t *)sos_hdr +
2931                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2932
2933         if (adev->gmc.xgmi.connected_to_cpu ||
2934             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
2935                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2936                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
2937
2938                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
2939                 adev->psp.sys.start_addr = ucode_array_start_addr;
2940
2941                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
2942                 adev->psp.sos.start_addr = ucode_array_start_addr +
2943                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
2944         } else {
2945                 /* Load alternate PSP SOS FW */
2946                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2947
2948                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2949                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2950
2951                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
2952                 adev->psp.sys.start_addr = ucode_array_start_addr +
2953                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
2954
2955                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
2956                 adev->psp.sos.start_addr = ucode_array_start_addr +
2957                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
2958         }
2959
2960         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
2961                 dev_warn(adev->dev, "PSP SOS FW not available");
2962                 return -EINVAL;
2963         }
2964
2965         return 0;
2966 }
2967
2968 int psp_init_sos_microcode(struct psp_context *psp,
2969                            const char *chip_name)
2970 {
2971         struct amdgpu_device *adev = psp->adev;
2972         char fw_name[PSP_FW_NAME_LEN];
2973         const struct psp_firmware_header_v1_0 *sos_hdr;
2974         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2975         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2976         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2977         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
2978         int err = 0;
2979         uint8_t *ucode_array_start_addr;
2980         int fw_index = 0;
2981
2982         if (!chip_name) {
2983                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2984                 return -EINVAL;
2985         }
2986
2987         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2988         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2989         if (err)
2990                 goto out;
2991
2992         err = amdgpu_ucode_validate(adev->psp.sos_fw);
2993         if (err)
2994                 goto out;
2995
2996         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2997         ucode_array_start_addr = (uint8_t *)sos_hdr +
2998                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2999         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3000
3001         switch (sos_hdr->header.header_version_major) {
3002         case 1:
3003                 err = psp_init_sos_base_fw(adev);
3004                 if (err)
3005                         goto out;
3006
3007                 if (sos_hdr->header.header_version_minor == 1) {
3008                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3009                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3010                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3011                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3012                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3013                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3014                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3015                 }
3016                 if (sos_hdr->header.header_version_minor == 2) {
3017                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3018                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3019                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3020                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3021                 }
3022                 if (sos_hdr->header.header_version_minor == 3) {
3023                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3024                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3025                         adev->psp.toc.start_addr = ucode_array_start_addr +
3026                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3027                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3028                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3029                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3030                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3031                         adev->psp.spl.start_addr = ucode_array_start_addr +
3032                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3033                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3034                         adev->psp.rl.start_addr = ucode_array_start_addr +
3035                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3036                 }
3037                 break;
3038         case 2:
3039                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3040
3041                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3042                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3043                         err = -EINVAL;
3044                         goto out;
3045                 }
3046
3047                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3048                         err = parse_sos_bin_descriptor(psp,
3049                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3050                                                        sos_hdr_v2_0);
3051                         if (err)
3052                                 goto out;
3053                 }
3054                 break;
3055         default:
3056                 dev_err(adev->dev,
3057                         "unsupported psp sos firmware\n");
3058                 err = -EINVAL;
3059                 goto out;
3060         }
3061
3062         return 0;
3063 out:
3064         dev_err(adev->dev,
3065                 "failed to init sos firmware\n");
3066         release_firmware(adev->psp.sos_fw);
3067         adev->psp.sos_fw = NULL;
3068
3069         return err;
3070 }
3071
3072 static int parse_ta_bin_descriptor(struct psp_context *psp,
3073                                    const struct psp_fw_bin_desc *desc,
3074                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3075 {
3076         uint8_t *ucode_start_addr  = NULL;
3077
3078         if (!psp || !desc || !ta_hdr)
3079                 return -EINVAL;
3080
3081         ucode_start_addr  = (uint8_t *)ta_hdr +
3082                             le32_to_cpu(desc->offset_bytes) +
3083                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3084
3085         switch (desc->fw_type) {
3086         case TA_FW_TYPE_PSP_ASD:
3087                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3088                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3089                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3090                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3091                 break;
3092         case TA_FW_TYPE_PSP_XGMI:
3093                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3094                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3095                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3096                 break;
3097         case TA_FW_TYPE_PSP_RAS:
3098                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3099                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3100                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3101                 break;
3102         case TA_FW_TYPE_PSP_HDCP:
3103                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3104                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3105                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3106                 break;
3107         case TA_FW_TYPE_PSP_DTM:
3108                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3109                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3110                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3111                 break;
3112         case TA_FW_TYPE_PSP_RAP:
3113                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3114                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3115                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3116                 break;
3117         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3118                 psp->securedisplay_context.context.bin_desc.fw_version =
3119                         le32_to_cpu(desc->fw_version);
3120                 psp->securedisplay_context.context.bin_desc.size_bytes =
3121                         le32_to_cpu(desc->size_bytes);
3122                 psp->securedisplay_context.context.bin_desc.start_addr =
3123                         ucode_start_addr;
3124                 break;
3125         default:
3126                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3127                 break;
3128         }
3129
3130         return 0;
3131 }
3132
3133 int psp_init_ta_microcode(struct psp_context *psp,
3134                           const char *chip_name)
3135 {
3136         struct amdgpu_device *adev = psp->adev;
3137         char fw_name[PSP_FW_NAME_LEN];
3138         const struct ta_firmware_header_v2_0 *ta_hdr;
3139         int err = 0;
3140         int ta_index = 0;
3141
3142         if (!chip_name) {
3143                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3144                 return -EINVAL;
3145         }
3146
3147         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3148         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3149         if (err)
3150                 goto out;
3151
3152         err = amdgpu_ucode_validate(adev->psp.ta_fw);
3153         if (err)
3154                 goto out;
3155
3156         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3157
3158         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3159                 dev_err(adev->dev, "unsupported TA header version\n");
3160                 err = -EINVAL;
3161                 goto out;
3162         }
3163
3164         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3165                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3166                 err = -EINVAL;
3167                 goto out;
3168         }
3169
3170         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3171                 err = parse_ta_bin_descriptor(psp,
3172                                               &ta_hdr->ta_fw_bin[ta_index],
3173                                               ta_hdr);
3174                 if (err)
3175                         goto out;
3176         }
3177
3178         return 0;
3179 out:
3180         dev_err(adev->dev, "fail to initialize ta microcode\n");
3181         release_firmware(adev->psp.ta_fw);
3182         adev->psp.ta_fw = NULL;
3183         return err;
3184 }
3185
3186 int psp_init_cap_microcode(struct psp_context *psp,
3187                           const char *chip_name)
3188 {
3189         struct amdgpu_device *adev = psp->adev;
3190         char fw_name[PSP_FW_NAME_LEN];
3191         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3192         struct amdgpu_firmware_info *info = NULL;
3193         int err = 0;
3194
3195         if (!chip_name) {
3196                 dev_err(adev->dev, "invalid chip name for cap microcode\n");
3197                 return -EINVAL;
3198         }
3199
3200         if (!amdgpu_sriov_vf(adev)) {
3201                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3202                 return -EINVAL;
3203         }
3204
3205         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3206         err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3207         if (err) {
3208                 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3209                 err = 0;
3210                 goto out;
3211         }
3212
3213         err = amdgpu_ucode_validate(adev->psp.cap_fw);
3214         if (err) {
3215                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3216                 goto out;
3217         }
3218
3219         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3220         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3221         info->fw = adev->psp.cap_fw;
3222         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3223                 adev->psp.cap_fw->data;
3224         adev->firmware.fw_size += ALIGN(
3225                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3226         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3227         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3228         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3229
3230         return 0;
3231
3232 out:
3233         release_firmware(adev->psp.cap_fw);
3234         adev->psp.cap_fw = NULL;
3235         return err;
3236 }
3237
3238 static int psp_set_clockgating_state(void *handle,
3239                                      enum amd_clockgating_state state)
3240 {
3241         return 0;
3242 }
3243
3244 static int psp_set_powergating_state(void *handle,
3245                                      enum amd_powergating_state state)
3246 {
3247         return 0;
3248 }
3249
3250 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3251                                          struct device_attribute *attr,
3252                                          char *buf)
3253 {
3254         struct drm_device *ddev = dev_get_drvdata(dev);
3255         struct amdgpu_device *adev = drm_to_adev(ddev);
3256         uint32_t fw_ver;
3257         int ret;
3258
3259         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3260                 DRM_INFO("PSP block is not ready yet.");
3261                 return -EBUSY;
3262         }
3263
3264         mutex_lock(&adev->psp.mutex);
3265         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3266         mutex_unlock(&adev->psp.mutex);
3267
3268         if (ret) {
3269                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3270                 return ret;
3271         }
3272
3273         return sysfs_emit(buf, "%x\n", fw_ver);
3274 }
3275
3276 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3277                                                        struct device_attribute *attr,
3278                                                        const char *buf,
3279                                                        size_t count)
3280 {
3281         struct drm_device *ddev = dev_get_drvdata(dev);
3282         struct amdgpu_device *adev = drm_to_adev(ddev);
3283         int ret, idx;
3284         char fw_name[100];
3285         const struct firmware *usbc_pd_fw;
3286         struct amdgpu_bo *fw_buf_bo = NULL;
3287         uint64_t fw_pri_mc_addr;
3288         void *fw_pri_cpu_addr;
3289
3290         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3291                 DRM_INFO("PSP block is not ready yet.");
3292                 return -EBUSY;
3293         }
3294
3295         if (!drm_dev_enter(ddev, &idx))
3296                 return -ENODEV;
3297
3298         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3299         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3300         if (ret)
3301                 goto fail;
3302
3303         /* LFB address which is aligned to 1MB boundary per PSP request */
3304         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3305                                                 AMDGPU_GEM_DOMAIN_VRAM,
3306                                                 &fw_buf_bo,
3307                                                 &fw_pri_mc_addr,
3308                                                 &fw_pri_cpu_addr);
3309         if (ret)
3310                 goto rel_buf;
3311
3312         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3313
3314         mutex_lock(&adev->psp.mutex);
3315         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3316         mutex_unlock(&adev->psp.mutex);
3317
3318         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3319
3320 rel_buf:
3321         release_firmware(usbc_pd_fw);
3322 fail:
3323         if (ret) {
3324                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3325                 count = ret;
3326         }
3327
3328         drm_dev_exit(idx);
3329         return count;
3330 }
3331
3332 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3333 {
3334         int idx;
3335
3336         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3337                 return;
3338
3339         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3340         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3341
3342         drm_dev_exit(idx);
3343 }
3344
3345 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3346                    psp_usbc_pd_fw_sysfs_read,
3347                    psp_usbc_pd_fw_sysfs_write);
3348
3349 int is_psp_fw_valid(struct psp_bin_desc bin)
3350 {
3351         return bin.size_bytes;
3352 }
3353
3354 const struct amd_ip_funcs psp_ip_funcs = {
3355         .name = "psp",
3356         .early_init = psp_early_init,
3357         .late_init = NULL,
3358         .sw_init = psp_sw_init,
3359         .sw_fini = psp_sw_fini,
3360         .hw_init = psp_hw_init,
3361         .hw_fini = psp_hw_fini,
3362         .suspend = psp_suspend,
3363         .resume = psp_resume,
3364         .is_idle = NULL,
3365         .check_soft_reset = NULL,
3366         .wait_for_idle = NULL,
3367         .soft_reset = NULL,
3368         .set_clockgating_state = psp_set_clockgating_state,
3369         .set_powergating_state = psp_set_powergating_state,
3370 };
3371
3372 static int psp_sysfs_init(struct amdgpu_device *adev)
3373 {
3374         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3375
3376         if (ret)
3377                 DRM_ERROR("Failed to create USBC PD FW control file!");
3378
3379         return ret;
3380 }
3381
3382 static void psp_sysfs_fini(struct amdgpu_device *adev)
3383 {
3384         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3385 }
3386
3387 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3388 {
3389         .type = AMD_IP_BLOCK_TYPE_PSP,
3390         .major = 3,
3391         .minor = 1,
3392         .rev = 0,
3393         .funcs = &psp_ip_funcs,
3394 };
3395
3396 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3397 {
3398         .type = AMD_IP_BLOCK_TYPE_PSP,
3399         .major = 10,
3400         .minor = 0,
3401         .rev = 0,
3402         .funcs = &psp_ip_funcs,
3403 };
3404
3405 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3406 {
3407         .type = AMD_IP_BLOCK_TYPE_PSP,
3408         .major = 11,
3409         .minor = 0,
3410         .rev = 0,
3411         .funcs = &psp_ip_funcs,
3412 };
3413
3414 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3415         .type = AMD_IP_BLOCK_TYPE_PSP,
3416         .major = 11,
3417         .minor = 0,
3418         .rev = 8,
3419         .funcs = &psp_ip_funcs,
3420 };
3421
3422 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3423 {
3424         .type = AMD_IP_BLOCK_TYPE_PSP,
3425         .major = 12,
3426         .minor = 0,
3427         .rev = 0,
3428         .funcs = &psp_ip_funcs,
3429 };
3430
3431 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3432         .type = AMD_IP_BLOCK_TYPE_PSP,
3433         .major = 13,
3434         .minor = 0,
3435         .rev = 0,
3436         .funcs = &psp_ip_funcs,
3437 };