drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
  38 {
  39         struct amd_pp_init pp_init;
  40         struct amd_powerplay *amd_pp;
  41         int ret;
  42
  43         amd_pp = &(adev->powerplay);
  44         pp_init.chip_family = adev->family;
  45         pp_init.chip_id = adev->asic_type;
  46         pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
  47         pp_init.feature_mask = amdgpu_pp_feature_mask;
  48         pp_init.device = amdgpu_cgs_create_device(adev);
  49         ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
  50         if (ret)
  51                 return -EINVAL;
  52         return 0;
  53 }
  54
  55 static int amdgpu_pp_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58         struct amd_powerplay *amd_pp;
  59         int ret = 0;
  60
  61         amd_pp = &(adev->powerplay);
  62         adev->pp_enabled = false;
  63         amd_pp->pp_handle = (void *)adev;
  64
  65         switch (adev->asic_type) {
  66         case CHIP_POLARIS11:
  67         case CHIP_POLARIS10:
  68         case CHIP_POLARIS12:
  69         case CHIP_TONGA:
  70         case CHIP_FIJI:
  71         case CHIP_TOPAZ:
  72         case CHIP_CARRIZO:
  73         case CHIP_STONEY:
  74         case CHIP_VEGA10:
  75         case CHIP_RAVEN:
  76                 adev->pp_enabled = true;
  77                 if (amdgpu_create_pp_handle(adev))
  78                         return -EINVAL;
  79                 amd_pp->ip_funcs = &pp_ip_funcs;
  80                 amd_pp->pp_funcs = &pp_dpm_funcs;
  81                 break;
  82         /* These chips don't have powerplay implemenations */
  83 #ifdef CONFIG_DRM_AMDGPU_SI
  84         case CHIP_TAHITI:
  85         case CHIP_PITCAIRN:
  86         case CHIP_VERDE:
  87         case CHIP_OLAND:
  88         case CHIP_HAINAN:
  89                 amd_pp->ip_funcs = &si_dpm_ip_funcs;
  90                 amd_pp->pp_funcs = &si_dpm_funcs;
  91         break;
  92 #endif
  93 #ifdef CONFIG_DRM_AMDGPU_CIK
  94         case CHIP_BONAIRE:
  95         case CHIP_HAWAII:
  96                 if (amdgpu_dpm == -1) {
  97                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  98                         amd_pp->pp_funcs = &ci_dpm_funcs;
  99                 } else {
 100                         adev->pp_enabled = true;
 101                         if (amdgpu_create_pp_handle(adev))
 102                                 return -EINVAL;
 103                         amd_pp->ip_funcs = &pp_ip_funcs;
 104                         amd_pp->pp_funcs = &pp_dpm_funcs;
 105                 }
 106                 break;
 107         case CHIP_KABINI:
 108         case CHIP_MULLINS:
 109         case CHIP_KAVERI:
 110                 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
 111                 amd_pp->pp_funcs = &kv_dpm_funcs;
 112                 break;
 113 #endif
 114         default:
 115                 ret = -EINVAL;
 116                 break;
 117         }
 118
 119         if (adev->powerplay.ip_funcs->early_init)
 120                 ret = adev->powerplay.ip_funcs->early_init(
 121                                         adev->powerplay.pp_handle);
 122
 123         if (ret == PP_DPM_DISABLED) {
 124                 adev->pm.dpm_enabled = false;
 125                 return 0;
 126         }
 127         return ret;
 128 }
 129
 130
 131 static int amdgpu_pp_late_init(void *handle)
 132 {
 133         int ret = 0;
 134         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 135
 136         if (adev->powerplay.ip_funcs->late_init)
 137                 ret = adev->powerplay.ip_funcs->late_init(
 138                                         adev->powerplay.pp_handle);
 139
 140         if (adev->pp_enabled && adev->pm.dpm_enabled)
 141                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
 142
 143         return ret;
 144 }
 145
 146 static int amdgpu_pp_sw_init(void *handle)
 147 {
 148         int ret = 0;
 149         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 150
 151         if (adev->powerplay.ip_funcs->sw_init)
 152                 ret = adev->powerplay.ip_funcs->sw_init(
 153                                         adev->powerplay.pp_handle);
 154
 155         return ret;
 156 }
 157
 158 static int amdgpu_pp_sw_fini(void *handle)
 159 {
 160         int ret = 0;
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162
 163         if (adev->powerplay.ip_funcs->sw_fini)
 164                 ret = adev->powerplay.ip_funcs->sw_fini(
 165                                         adev->powerplay.pp_handle);
 166         if (ret)
 167                 return ret;
 168
 169         return ret;
 170 }
 171
 172 static int amdgpu_pp_hw_init(void *handle)
 173 {
 174         int ret = 0;
 175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 176
 177
 178         if (adev->powerplay.ip_funcs->hw_init)
 179                 ret = adev->powerplay.ip_funcs->hw_init(
 180                                         adev->powerplay.pp_handle);
 181
 182         if (ret == PP_DPM_DISABLED) {
 183                 adev->pm.dpm_enabled = false;
 184                 return 0;
 185         }
 186
 187         if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
 188                 adev->pm.dpm_enabled = true;
 189
 190         return ret;
 191 }
 192
 193 static int amdgpu_pp_hw_fini(void *handle)
 194 {
 195         int ret = 0;
 196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 197
 198         if (adev->powerplay.ip_funcs->hw_fini)
 199                 ret = adev->powerplay.ip_funcs->hw_fini(
 200                                         adev->powerplay.pp_handle);
 201
 202         return ret;
 203 }
 204
 205 static void amdgpu_pp_late_fini(void *handle)
 206 {
 207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 208
 209         if (adev->powerplay.ip_funcs->late_fini)
 210                 adev->powerplay.ip_funcs->late_fini(
 211                           adev->powerplay.pp_handle);
 212
 213
 214         if (adev->pp_enabled)
 215                 amd_powerplay_destroy(adev->powerplay.pp_handle);
 216 }
 217
 218 static int amdgpu_pp_suspend(void *handle)
 219 {
 220         int ret = 0;
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222
 223         if (adev->powerplay.ip_funcs->suspend)
 224                 ret = adev->powerplay.ip_funcs->suspend(
 225                                          adev->powerplay.pp_handle);
 226         return ret;
 227 }
 228
 229 static int amdgpu_pp_resume(void *handle)
 230 {
 231         int ret = 0;
 232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 233
 234         if (adev->powerplay.ip_funcs->resume)
 235                 ret = adev->powerplay.ip_funcs->resume(
 236                                         adev->powerplay.pp_handle);
 237         return ret;
 238 }
 239
 240 static int amdgpu_pp_set_clockgating_state(void *handle,
 241                                         enum amd_clockgating_state state)
 242 {
 243         int ret = 0;
 244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 245
 246         if (adev->powerplay.ip_funcs->set_clockgating_state)
 247                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 248                                 adev->powerplay.pp_handle, state);
 249         return ret;
 250 }
 251
 252 static int amdgpu_pp_set_powergating_state(void *handle,
 253                                         enum amd_powergating_state state)
 254 {
 255         int ret = 0;
 256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 257
 258         if (adev->powerplay.ip_funcs->set_powergating_state)
 259                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 260                                  adev->powerplay.pp_handle, state);
 261         return ret;
 262 }
 263
 264
 265 static bool amdgpu_pp_is_idle(void *handle)
 266 {
 267         bool ret = true;
 268         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 269
 270         if (adev->powerplay.ip_funcs->is_idle)
 271                 ret = adev->powerplay.ip_funcs->is_idle(
 272                                         adev->powerplay.pp_handle);
 273         return ret;
 274 }
 275
 276 static int amdgpu_pp_wait_for_idle(void *handle)
 277 {
 278         int ret = 0;
 279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 280
 281         if (adev->powerplay.ip_funcs->wait_for_idle)
 282                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 283                                         adev->powerplay.pp_handle);
 284         return ret;
 285 }
 286
 287 static int amdgpu_pp_soft_reset(void *handle)
 288 {
 289         int ret = 0;
 290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 291
 292         if (adev->powerplay.ip_funcs->soft_reset)
 293                 ret = adev->powerplay.ip_funcs->soft_reset(
 294                                         adev->powerplay.pp_handle);
 295         return ret;
 296 }
 297
 298 static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 299         .name = "amdgpu_powerplay",
 300         .early_init = amdgpu_pp_early_init,
 301         .late_init = amdgpu_pp_late_init,
 302         .sw_init = amdgpu_pp_sw_init,
 303         .sw_fini = amdgpu_pp_sw_fini,
 304         .hw_init = amdgpu_pp_hw_init,
 305         .hw_fini = amdgpu_pp_hw_fini,
 306         .late_fini = amdgpu_pp_late_fini,
 307         .suspend = amdgpu_pp_suspend,
 308         .resume = amdgpu_pp_resume,
 309         .is_idle = amdgpu_pp_is_idle,
 310         .wait_for_idle = amdgpu_pp_wait_for_idle,
 311         .soft_reset = amdgpu_pp_soft_reset,
 312         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 313         .set_powergating_state = amdgpu_pp_set_powergating_state,
 314 };
 315
 316 const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
 317 {
 318         .type = AMD_IP_BLOCK_TYPE_SMC,
 319         .major = 1,
 320         .minor = 0,
 321         .rev = 0,
 322         .funcs = &amdgpu_pp_ip_funcs,
 323 };