drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
  38 {
  39         struct amd_pp_init pp_init;
  40         struct amd_powerplay *amd_pp;
  41         int ret;
  42
  43         amd_pp = &(adev->powerplay);
  44         pp_init.chip_family = adev->family;
  45         pp_init.chip_id = adev->asic_type;
  46         pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
  47         pp_init.feature_mask = amdgpu_pp_feature_mask;
  48         pp_init.device = amd_pp->cgs_device;
  49         ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
  50         if (ret)
  51                 return -EINVAL;
  52         return 0;
  53 }
  54
  55 static int amdgpu_pp_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58         struct amd_powerplay *amd_pp;
  59         int ret = 0;
  60
  61         amd_pp = &(adev->powerplay);
  62         adev->pp_enabled = false;
  63         amd_pp->pp_handle = (void *)adev;
  64
  65         switch (adev->asic_type) {
  66         case CHIP_POLARIS11:
  67         case CHIP_POLARIS10:
  68         case CHIP_POLARIS12:
  69         case CHIP_TONGA:
  70         case CHIP_FIJI:
  71         case CHIP_TOPAZ:
  72         case CHIP_CARRIZO:
  73         case CHIP_STONEY:
  74         case CHIP_VEGA10:
  75         case CHIP_RAVEN:
  76                 adev->pp_enabled = true;
  77                 amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
  78                 if (amdgpu_create_pp_handle(adev))
  79                         return -EINVAL;
  80                 amd_pp->ip_funcs = &pp_ip_funcs;
  81                 amd_pp->pp_funcs = &pp_dpm_funcs;
  82                 break;
  83         /* These chips don't have powerplay implemenations */
  84 #ifdef CONFIG_DRM_AMDGPU_SI
  85         case CHIP_TAHITI:
  86         case CHIP_PITCAIRN:
  87         case CHIP_VERDE:
  88         case CHIP_OLAND:
  89         case CHIP_HAINAN:
  90                 amd_pp->ip_funcs = &si_dpm_ip_funcs;
  91                 amd_pp->pp_funcs = &si_dpm_funcs;
  92         break;
  93 #endif
  94 #ifdef CONFIG_DRM_AMDGPU_CIK
  95         case CHIP_BONAIRE:
  96         case CHIP_HAWAII:
  97                 if (amdgpu_dpm == -1) {
  98                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  99                         amd_pp->pp_funcs = &ci_dpm_funcs;
 100                 } else {
 101                         amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
 102                         if (amdgpu_create_pp_handle(adev))
 103                                 return -EINVAL;
 104                         amd_pp->ip_funcs = &pp_ip_funcs;
 105                         amd_pp->pp_funcs = &pp_dpm_funcs;
 106                 }
 107                 break;
 108         case CHIP_KABINI:
 109         case CHIP_MULLINS:
 110         case CHIP_KAVERI:
 111                 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
 112                 amd_pp->pp_funcs = &kv_dpm_funcs;
 113                 break;
 114 #endif
 115         default:
 116                 ret = -EINVAL;
 117                 break;
 118         }
 119
 120         if (adev->powerplay.ip_funcs->early_init)
 121                 ret = adev->powerplay.ip_funcs->early_init(
 122                                         adev->powerplay.pp_handle);
 123
 124         if (ret == PP_DPM_DISABLED) {
 125                 adev->pm.dpm_enabled = false;
 126                 return 0;
 127         }
 128         return ret;
 129 }
 130
 131
 132 static int amdgpu_pp_late_init(void *handle)
 133 {
 134         int ret = 0;
 135         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 136
 137         if (adev->powerplay.ip_funcs->late_init)
 138                 ret = adev->powerplay.ip_funcs->late_init(
 139                                         adev->powerplay.pp_handle);
 140
 141         if (adev->pp_enabled && adev->pm.dpm_enabled)
 142                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
 143
 144         return ret;
 145 }
 146
 147 static int amdgpu_pp_sw_init(void *handle)
 148 {
 149         int ret = 0;
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151
 152         if (adev->powerplay.ip_funcs->sw_init)
 153                 ret = adev->powerplay.ip_funcs->sw_init(
 154                                         adev->powerplay.pp_handle);
 155
 156         return ret;
 157 }
 158
 159 static int amdgpu_pp_sw_fini(void *handle)
 160 {
 161         int ret = 0;
 162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 163
 164         if (adev->powerplay.ip_funcs->sw_fini)
 165                 ret = adev->powerplay.ip_funcs->sw_fini(
 166                                         adev->powerplay.pp_handle);
 167         if (ret)
 168                 return ret;
 169
 170         return ret;
 171 }
 172
 173 static int amdgpu_pp_hw_init(void *handle)
 174 {
 175         int ret = 0;
 176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 177
 178
 179         if (adev->powerplay.ip_funcs->hw_init)
 180                 ret = adev->powerplay.ip_funcs->hw_init(
 181                                         adev->powerplay.pp_handle);
 182
 183         if (ret == PP_DPM_DISABLED) {
 184                 adev->pm.dpm_enabled = false;
 185                 return 0;
 186         }
 187
 188         if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
 189                 adev->pm.dpm_enabled = true;
 190
 191         return ret;
 192 }
 193
 194 static int amdgpu_pp_hw_fini(void *handle)
 195 {
 196         int ret = 0;
 197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 198
 199         if (adev->powerplay.ip_funcs->hw_fini)
 200                 ret = adev->powerplay.ip_funcs->hw_fini(
 201                                         adev->powerplay.pp_handle);
 202
 203         return ret;
 204 }
 205
 206 static void amdgpu_pp_late_fini(void *handle)
 207 {
 208         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 209
 210         if (adev->powerplay.ip_funcs->late_fini)
 211                 adev->powerplay.ip_funcs->late_fini(
 212                           adev->powerplay.pp_handle);
 213
 214
 215         if (adev->pp_enabled) {
 216                 amd_powerplay_destroy(adev->powerplay.pp_handle);
 217                 amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
 218         }
 219 }
 220
 221 static int amdgpu_pp_suspend(void *handle)
 222 {
 223         int ret = 0;
 224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 225
 226         if (adev->powerplay.ip_funcs->suspend)
 227                 ret = adev->powerplay.ip_funcs->suspend(
 228                                          adev->powerplay.pp_handle);
 229         return ret;
 230 }
 231
 232 static int amdgpu_pp_resume(void *handle)
 233 {
 234         int ret = 0;
 235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 236
 237         if (adev->powerplay.ip_funcs->resume)
 238                 ret = adev->powerplay.ip_funcs->resume(
 239                                         adev->powerplay.pp_handle);
 240         return ret;
 241 }
 242
 243 static int amdgpu_pp_set_clockgating_state(void *handle,
 244                                         enum amd_clockgating_state state)
 245 {
 246         int ret = 0;
 247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 248
 249         if (adev->powerplay.ip_funcs->set_clockgating_state)
 250                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 251                                 adev->powerplay.pp_handle, state);
 252         return ret;
 253 }
 254
 255 static int amdgpu_pp_set_powergating_state(void *handle,
 256                                         enum amd_powergating_state state)
 257 {
 258         int ret = 0;
 259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 260
 261         if (adev->powerplay.ip_funcs->set_powergating_state)
 262                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 263                                  adev->powerplay.pp_handle, state);
 264         return ret;
 265 }
 266
 267
 268 static bool amdgpu_pp_is_idle(void *handle)
 269 {
 270         bool ret = true;
 271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 272
 273         if (adev->powerplay.ip_funcs->is_idle)
 274                 ret = adev->powerplay.ip_funcs->is_idle(
 275                                         adev->powerplay.pp_handle);
 276         return ret;
 277 }
 278
 279 static int amdgpu_pp_wait_for_idle(void *handle)
 280 {
 281         int ret = 0;
 282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 283
 284         if (adev->powerplay.ip_funcs->wait_for_idle)
 285                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 286                                         adev->powerplay.pp_handle);
 287         return ret;
 288 }
 289
 290 static int amdgpu_pp_soft_reset(void *handle)
 291 {
 292         int ret = 0;
 293         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 294
 295         if (adev->powerplay.ip_funcs->soft_reset)
 296                 ret = adev->powerplay.ip_funcs->soft_reset(
 297                                         adev->powerplay.pp_handle);
 298         return ret;
 299 }
 300
 301 static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 302         .name = "amdgpu_powerplay",
 303         .early_init = amdgpu_pp_early_init,
 304         .late_init = amdgpu_pp_late_init,
 305         .sw_init = amdgpu_pp_sw_init,
 306         .sw_fini = amdgpu_pp_sw_fini,
 307         .hw_init = amdgpu_pp_hw_init,
 308         .hw_fini = amdgpu_pp_hw_fini,
 309         .late_fini = amdgpu_pp_late_fini,
 310         .suspend = amdgpu_pp_suspend,
 311         .resume = amdgpu_pp_resume,
 312         .is_idle = amdgpu_pp_is_idle,
 313         .wait_for_idle = amdgpu_pp_wait_for_idle,
 314         .soft_reset = amdgpu_pp_soft_reset,
 315         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 316         .set_powergating_state = amdgpu_pp_set_powergating_state,
 317 };
 318
 319 const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
 320 {
 321         .type = AMD_IP_BLOCK_TYPE_SMC,
 322         .major = 1,
 323         .minor = 0,
 324         .rev = 0,
 325         .funcs = &amdgpu_pp_ip_funcs,
 326 };