drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include <linux/pm_runtime.h>
  41 #include "hwmgr.h"
  42 #define WIDTH_4K 3840
  43
  44 static const struct cg_flag_name clocks[] = {
  45         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  55         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  58         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  61         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  64         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  67         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  69
  70         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  72         {0, NULL},
  73 };
  74
  75 static const struct hwmon_temp_label {
  76         enum PP_HWMON_TEMP channel;
  77         const char *label;
  78 } temp_label[] = {
  79         {PP_TEMP_EDGE, "edge"},
  80         {PP_TEMP_JUNCTION, "junction"},
  81         {PP_TEMP_MEM, "mem"},
  82 };
  83
  84 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  85 {
  86         if (adev->pm.dpm_enabled) {
  87                 mutex_lock(&adev->pm.mutex);
  88                 if (power_supply_is_system_supplied() > 0)
  89                         adev->pm.ac_power = true;
  90                 else
  91                         adev->pm.ac_power = false;
  92                 if (adev->powerplay.pp_funcs &&
  93                     adev->powerplay.pp_funcs->enable_bapm)
  94                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  95                 mutex_unlock(&adev->pm.mutex);
  96
  97                 if (is_support_sw_smu(adev))
  98                         smu_set_ac_dc(&adev->smu);
  99         }
 100 }
 101
 102 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 103                            void *data, uint32_t *size)
 104 {
 105         int ret = 0;
 106
 107         if (!data || !size)
 108                 return -EINVAL;
 109
 110         if (is_support_sw_smu(adev))
 111                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 112         else {
 113                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 114                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 115                                                                     sensor, data, size);
 116                 else
 117                         ret = -EINVAL;
 118         }
 119
 120         return ret;
 121 }
 122
 123 /**
 124  * DOC: power_dpm_state
 125  *
 126  * The power_dpm_state file is a legacy interface and is only provided for
 127  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 128  * certain power related parameters.  The file power_dpm_state is used for this.
 129  * It accepts the following arguments:
 130  *
 131  * - battery
 132  *
 133  * - balanced
 134  *
 135  * - performance
 136  *
 137  * battery
 138  *
 139  * On older GPUs, the vbios provided a special power state for battery
 140  * operation.  Selecting battery switched to this state.  This is no
 141  * longer provided on newer GPUs so the option does nothing in that case.
 142  *
 143  * balanced
 144  *
 145  * On older GPUs, the vbios provided a special power state for balanced
 146  * operation.  Selecting balanced switched to this state.  This is no
 147  * longer provided on newer GPUs so the option does nothing in that case.
 148  *
 149  * performance
 150  *
 151  * On older GPUs, the vbios provided a special power state for performance
 152  * operation.  Selecting performance switched to this state.  This is no
 153  * longer provided on newer GPUs so the option does nothing in that case.
 154  *
 155  */
 156
 157 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 158                                           struct device_attribute *attr,
 159                                           char *buf)
 160 {
 161         struct drm_device *ddev = dev_get_drvdata(dev);
 162         struct amdgpu_device *adev = ddev->dev_private;
 163         enum amd_pm_state_type pm;
 164         int ret;
 165
 166         ret = pm_runtime_get_sync(ddev->dev);
 167         if (ret < 0)
 168                 return ret;
 169
 170         if (is_support_sw_smu(adev)) {
 171                 if (adev->smu.ppt_funcs->get_current_power_state)
 172                         pm = smu_get_current_power_state(&adev->smu);
 173                 else
 174                         pm = adev->pm.dpm.user_state;
 175         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 176                 pm = amdgpu_dpm_get_current_power_state(adev);
 177         } else {
 178                 pm = adev->pm.dpm.user_state;
 179         }
 180
 181         pm_runtime_mark_last_busy(ddev->dev);
 182         pm_runtime_put_autosuspend(ddev->dev);
 183
 184         return snprintf(buf, PAGE_SIZE, "%s\n",
 185                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 186                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 187 }
 188
 189 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 190                                           struct device_attribute *attr,
 191                                           const char *buf,
 192                                           size_t count)
 193 {
 194         struct drm_device *ddev = dev_get_drvdata(dev);
 195         struct amdgpu_device *adev = ddev->dev_private;
 196         enum amd_pm_state_type  state;
 197         int ret;
 198
 199         if (strncmp("battery", buf, strlen("battery")) == 0)
 200                 state = POWER_STATE_TYPE_BATTERY;
 201         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 202                 state = POWER_STATE_TYPE_BALANCED;
 203         else if (strncmp("performance", buf, strlen("performance")) == 0)
 204                 state = POWER_STATE_TYPE_PERFORMANCE;
 205         else
 206                 return -EINVAL;
 207
 208         ret = pm_runtime_get_sync(ddev->dev);
 209         if (ret < 0)
 210                 return ret;
 211
 212         if (is_support_sw_smu(adev)) {
 213                 mutex_lock(&adev->pm.mutex);
 214                 adev->pm.dpm.user_state = state;
 215                 mutex_unlock(&adev->pm.mutex);
 216         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 217                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 218         } else {
 219                 mutex_lock(&adev->pm.mutex);
 220                 adev->pm.dpm.user_state = state;
 221                 mutex_unlock(&adev->pm.mutex);
 222
 223                 amdgpu_pm_compute_clocks(adev);
 224         }
 225         pm_runtime_mark_last_busy(ddev->dev);
 226         pm_runtime_put_autosuspend(ddev->dev);
 227
 228         return count;
 229 }
 230
 231
 232 /**
 233  * DOC: power_dpm_force_performance_level
 234  *
 235  * The amdgpu driver provides a sysfs API for adjusting certain power
 236  * related parameters.  The file power_dpm_force_performance_level is
 237  * used for this.  It accepts the following arguments:
 238  *
 239  * - auto
 240  *
 241  * - low
 242  *
 243  * - high
 244  *
 245  * - manual
 246  *
 247  * - profile_standard
 248  *
 249  * - profile_min_sclk
 250  *
 251  * - profile_min_mclk
 252  *
 253  * - profile_peak
 254  *
 255  * auto
 256  *
 257  * When auto is selected, the driver will attempt to dynamically select
 258  * the optimal power profile for current conditions in the driver.
 259  *
 260  * low
 261  *
 262  * When low is selected, the clocks are forced to the lowest power state.
 263  *
 264  * high
 265  *
 266  * When high is selected, the clocks are forced to the highest power state.
 267  *
 268  * manual
 269  *
 270  * When manual is selected, the user can manually adjust which power states
 271  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 272  * and pp_dpm_pcie files and adjust the power state transition heuristics
 273  * via the pp_power_profile_mode sysfs file.
 274  *
 275  * profile_standard
 276  * profile_min_sclk
 277  * profile_min_mclk
 278  * profile_peak
 279  *
 280  * When the profiling modes are selected, clock and power gating are
 281  * disabled and the clocks are set for different profiling cases. This
 282  * mode is recommended for profiling specific work loads where you do
 283  * not want clock or power gating for clock fluctuation to interfere
 284  * with your results. profile_standard sets the clocks to a fixed clock
 285  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 286  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 287  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 288  *
 289  */
 290
 291 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 292                                                             struct device_attribute *attr,
 293                                                             char *buf)
 294 {
 295         struct drm_device *ddev = dev_get_drvdata(dev);
 296         struct amdgpu_device *adev = ddev->dev_private;
 297         enum amd_dpm_forced_level level = 0xff;
 298         int ret;
 299
 300         ret = pm_runtime_get_sync(ddev->dev);
 301         if (ret < 0)
 302                 return ret;
 303
 304         if (is_support_sw_smu(adev))
 305                 level = smu_get_performance_level(&adev->smu);
 306         else if (adev->powerplay.pp_funcs->get_performance_level)
 307                 level = amdgpu_dpm_get_performance_level(adev);
 308         else
 309                 level = adev->pm.dpm.forced_level;
 310
 311         pm_runtime_mark_last_busy(ddev->dev);
 312         pm_runtime_put_autosuspend(ddev->dev);
 313
 314         return snprintf(buf, PAGE_SIZE, "%s\n",
 315                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 316                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 317                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 318                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 319                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 320                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 321                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 322                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 323                         "unknown");
 324 }
 325
 326 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 327                                                             struct device_attribute *attr,
 328                                                             const char *buf,
 329                                                             size_t count)
 330 {
 331         struct drm_device *ddev = dev_get_drvdata(dev);
 332         struct amdgpu_device *adev = ddev->dev_private;
 333         enum amd_dpm_forced_level level;
 334         enum amd_dpm_forced_level current_level = 0xff;
 335         int ret = 0;
 336
 337         if (strncmp("low", buf, strlen("low")) == 0) {
 338                 level = AMD_DPM_FORCED_LEVEL_LOW;
 339         } else if (strncmp("high", buf, strlen("high")) == 0) {
 340                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 341         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 342                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 343         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 344                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 345         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 346                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 347         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 348                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 349         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 350                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 351         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 352                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 353         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 354                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 355         }  else {
 356                 return -EINVAL;
 357         }
 358
 359         ret = pm_runtime_get_sync(ddev->dev);
 360         if (ret < 0)
 361                 return ret;
 362
 363         if (is_support_sw_smu(adev))
 364                 current_level = smu_get_performance_level(&adev->smu);
 365         else if (adev->powerplay.pp_funcs->get_performance_level)
 366                 current_level = amdgpu_dpm_get_performance_level(adev);
 367
 368         if (current_level == level) {
 369                 pm_runtime_mark_last_busy(ddev->dev);
 370                 pm_runtime_put_autosuspend(ddev->dev);
 371                 return count;
 372         }
 373
 374         if (adev->asic_type == CHIP_RAVEN) {
 375                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 376                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 377                                 amdgpu_gfx_off_ctrl(adev, false);
 378                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 379                                 amdgpu_gfx_off_ctrl(adev, true);
 380                 }
 381         }
 382
 383         /* profile_exit setting is valid only when current mode is in profile mode */
 384         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 385             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 386             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 387             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 388             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 389                 pr_err("Currently not in any profile mode!\n");
 390                 pm_runtime_mark_last_busy(ddev->dev);
 391                 pm_runtime_put_autosuspend(ddev->dev);
 392                 return -EINVAL;
 393         }
 394
 395         if (is_support_sw_smu(adev)) {
 396                 ret = smu_force_performance_level(&adev->smu, level);
 397                 if (ret) {
 398                         pm_runtime_mark_last_busy(ddev->dev);
 399                         pm_runtime_put_autosuspend(ddev->dev);
 400                         return -EINVAL;
 401                 }
 402         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 403                 mutex_lock(&adev->pm.mutex);
 404                 if (adev->pm.dpm.thermal_active) {
 405                         mutex_unlock(&adev->pm.mutex);
 406                         pm_runtime_mark_last_busy(ddev->dev);
 407                         pm_runtime_put_autosuspend(ddev->dev);
 408                         return -EINVAL;
 409                 }
 410                 ret = amdgpu_dpm_force_performance_level(adev, level);
 411                 if (ret) {
 412                         mutex_unlock(&adev->pm.mutex);
 413                         pm_runtime_mark_last_busy(ddev->dev);
 414                         pm_runtime_put_autosuspend(ddev->dev);
 415                         return -EINVAL;
 416                 } else {
 417                         adev->pm.dpm.forced_level = level;
 418                 }
 419                 mutex_unlock(&adev->pm.mutex);
 420         }
 421         pm_runtime_mark_last_busy(ddev->dev);
 422         pm_runtime_put_autosuspend(ddev->dev);
 423
 424         return count;
 425 }
 426
 427 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 428                 struct device_attribute *attr,
 429                 char *buf)
 430 {
 431         struct drm_device *ddev = dev_get_drvdata(dev);
 432         struct amdgpu_device *adev = ddev->dev_private;
 433         struct pp_states_info data;
 434         int i, buf_len, ret;
 435
 436         ret = pm_runtime_get_sync(ddev->dev);
 437         if (ret < 0)
 438                 return ret;
 439
 440         if (is_support_sw_smu(adev)) {
 441                 ret = smu_get_power_num_states(&adev->smu, &data);
 442                 if (ret)
 443                         return ret;
 444         } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
 445                 amdgpu_dpm_get_pp_num_states(adev, &data);
 446         } else {
 447                 memset(&data, 0, sizeof(data));
 448         }
 449
 450         pm_runtime_mark_last_busy(ddev->dev);
 451         pm_runtime_put_autosuspend(ddev->dev);
 452
 453         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 454         for (i = 0; i < data.nums; i++)
 455                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 456                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 457                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 458                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 459                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 460
 461         return buf_len;
 462 }
 463
 464 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 465                 struct device_attribute *attr,
 466                 char *buf)
 467 {
 468         struct drm_device *ddev = dev_get_drvdata(dev);
 469         struct amdgpu_device *adev = ddev->dev_private;
 470         struct pp_states_info data;
 471         struct smu_context *smu = &adev->smu;
 472         enum amd_pm_state_type pm = 0;
 473         int i = 0, ret = 0;
 474
 475         ret = pm_runtime_get_sync(ddev->dev);
 476         if (ret < 0)
 477                 return ret;
 478
 479         if (is_support_sw_smu(adev)) {
 480                 pm = smu_get_current_power_state(smu);
 481                 ret = smu_get_power_num_states(smu, &data);
 482                 if (ret)
 483                         return ret;
 484         } else if (adev->powerplay.pp_funcs->get_current_power_state
 485                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 486                 pm = amdgpu_dpm_get_current_power_state(adev);
 487                 amdgpu_dpm_get_pp_num_states(adev, &data);
 488         }
 489
 490         pm_runtime_mark_last_busy(ddev->dev);
 491         pm_runtime_put_autosuspend(ddev->dev);
 492
 493         for (i = 0; i < data.nums; i++) {
 494                 if (pm == data.states[i])
 495                         break;
 496         }
 497
 498         if (i == data.nums)
 499                 i = -EINVAL;
 500
 501         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 502 }
 503
 504 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 505                 struct device_attribute *attr,
 506                 char *buf)
 507 {
 508         struct drm_device *ddev = dev_get_drvdata(dev);
 509         struct amdgpu_device *adev = ddev->dev_private;
 510
 511         if (adev->pp_force_state_enabled)
 512                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 513         else
 514                 return snprintf(buf, PAGE_SIZE, "\n");
 515 }
 516
 517 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 518                 struct device_attribute *attr,
 519                 const char *buf,
 520                 size_t count)
 521 {
 522         struct drm_device *ddev = dev_get_drvdata(dev);
 523         struct amdgpu_device *adev = ddev->dev_private;
 524         enum amd_pm_state_type state = 0;
 525         unsigned long idx;
 526         int ret;
 527
 528         if (strlen(buf) == 1)
 529                 adev->pp_force_state_enabled = false;
 530         else if (is_support_sw_smu(adev))
 531                 adev->pp_force_state_enabled = false;
 532         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 533                         adev->powerplay.pp_funcs->get_pp_num_states) {
 534                 struct pp_states_info data;
 535
 536                 ret = kstrtoul(buf, 0, &idx);
 537                 if (ret || idx >= ARRAY_SIZE(data.states))
 538                         return -EINVAL;
 539
 540                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 541
 542                 amdgpu_dpm_get_pp_num_states(adev, &data);
 543                 state = data.states[idx];
 544
 545                 ret = pm_runtime_get_sync(ddev->dev);
 546                 if (ret < 0)
 547                         return ret;
 548
 549                 /* only set user selected power states */
 550                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 551                     state != POWER_STATE_TYPE_DEFAULT) {
 552                         amdgpu_dpm_dispatch_task(adev,
 553                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 554                         adev->pp_force_state_enabled = true;
 555                 }
 556                 pm_runtime_mark_last_busy(ddev->dev);
 557                 pm_runtime_put_autosuspend(ddev->dev);
 558         }
 559
 560         return count;
 561 }
 562
 563 /**
 564  * DOC: pp_table
 565  *
 566  * The amdgpu driver provides a sysfs API for uploading new powerplay
 567  * tables.  The file pp_table is used for this.  Reading the file
 568  * will dump the current power play table.  Writing to the file
 569  * will attempt to upload a new powerplay table and re-initialize
 570  * powerplay using that new table.
 571  *
 572  */
 573
 574 static ssize_t amdgpu_get_pp_table(struct device *dev,
 575                 struct device_attribute *attr,
 576                 char *buf)
 577 {
 578         struct drm_device *ddev = dev_get_drvdata(dev);
 579         struct amdgpu_device *adev = ddev->dev_private;
 580         char *table = NULL;
 581         int size, ret;
 582
 583         ret = pm_runtime_get_sync(ddev->dev);
 584         if (ret < 0)
 585                 return ret;
 586
 587         if (is_support_sw_smu(adev)) {
 588                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 589                 pm_runtime_mark_last_busy(ddev->dev);
 590                 pm_runtime_put_autosuspend(ddev->dev);
 591                 if (size < 0)
 592                         return size;
 593         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 594                 size = amdgpu_dpm_get_pp_table(adev, &table);
 595                 pm_runtime_mark_last_busy(ddev->dev);
 596                 pm_runtime_put_autosuspend(ddev->dev);
 597                 if (size < 0)
 598                         return size;
 599         } else {
 600                 pm_runtime_mark_last_busy(ddev->dev);
 601                 pm_runtime_put_autosuspend(ddev->dev);
 602                 return 0;
 603         }
 604
 605         if (size >= PAGE_SIZE)
 606                 size = PAGE_SIZE - 1;
 607
 608         memcpy(buf, table, size);
 609
 610         return size;
 611 }
 612
 613 static ssize_t amdgpu_set_pp_table(struct device *dev,
 614                 struct device_attribute *attr,
 615                 const char *buf,
 616                 size_t count)
 617 {
 618         struct drm_device *ddev = dev_get_drvdata(dev);
 619         struct amdgpu_device *adev = ddev->dev_private;
 620         int ret = 0;
 621
 622         ret = pm_runtime_get_sync(ddev->dev);
 623         if (ret < 0)
 624                 return ret;
 625
 626         if (is_support_sw_smu(adev)) {
 627                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 628                 if (ret) {
 629                         pm_runtime_mark_last_busy(ddev->dev);
 630                         pm_runtime_put_autosuspend(ddev->dev);
 631                         return ret;
 632                 }
 633         } else if (adev->powerplay.pp_funcs->set_pp_table)
 634                 amdgpu_dpm_set_pp_table(adev, buf, count);
 635
 636         pm_runtime_mark_last_busy(ddev->dev);
 637         pm_runtime_put_autosuspend(ddev->dev);
 638
 639         return count;
 640 }
 641
 642 /**
 643  * DOC: pp_od_clk_voltage
 644  *
 645  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 646  * in each power level within a power state.  The pp_od_clk_voltage is used for
 647  * this.
 648  *
 649  * < For Vega10 and previous ASICs >
 650  *
 651  * Reading the file will display:
 652  *
 653  * - a list of engine clock levels and voltages labeled OD_SCLK
 654  *
 655  * - a list of memory clock levels and voltages labeled OD_MCLK
 656  *
 657  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 658  *
 659  * To manually adjust these settings, first select manual using
 660  * power_dpm_force_performance_level. Enter a new value for each
 661  * level by writing a string that contains "s/m level clock voltage" to
 662  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 663  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 664  * 810 mV.  When you have edited all of the states as needed, write
 665  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 666  * default power levels, write "r" (reset) to the file to reset them.
 667  *
 668  *
 669  * < For Vega20 >
 670  *
 671  * Reading the file will display:
 672  *
 673  * - minimum and maximum engine clock labeled OD_SCLK
 674  *
 675  * - maximum memory clock labeled OD_MCLK
 676  *
 677  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 678  *   They can be used to calibrate the sclk voltage curve.
 679  *
 680  * - a list of valid ranges for sclk, mclk, and voltage curve points
 681  *   labeled OD_RANGE
 682  *
 683  * To manually adjust these settings:
 684  *
 685  * - First select manual using power_dpm_force_performance_level
 686  *
 687  * - For clock frequency setting, enter a new value by writing a
 688  *   string that contains "s/m index clock" to the file. The index
 689  *   should be 0 if to set minimum clock. And 1 if to set maximum
 690  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 691  *   "m 1 800" will update maximum mclk to be 800Mhz.
 692  *
 693  *   For sclk voltage curve, enter the new values by writing a
 694  *   string that contains "vc point clock voltage" to the file. The
 695  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 696  *   update point1 with clock set as 300Mhz and voltage as
 697  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 698  *   as 1000Mhz and voltage 1000mV.
 699  *
 700  * - When you have edited all of the states as needed, write "c" (commit)
 701  *   to the file to commit your changes
 702  *
 703  * - If you want to reset to the default power levels, write "r" (reset)
 704  *   to the file to reset them
 705  *
 706  */
 707
 708 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 709                 struct device_attribute *attr,
 710                 const char *buf,
 711                 size_t count)
 712 {
 713         struct drm_device *ddev = dev_get_drvdata(dev);
 714         struct amdgpu_device *adev = ddev->dev_private;
 715         int ret;
 716         uint32_t parameter_size = 0;
 717         long parameter[64];
 718         char buf_cpy[128];
 719         char *tmp_str;
 720         char *sub_str;
 721         const char delimiter[3] = {' ', '\n', '\0'};
 722         uint32_t type;
 723
 724         if (count > 127)
 725                 return -EINVAL;
 726
 727         if (*buf == 's')
 728                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 729         else if (*buf == 'm')
 730                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 731         else if(*buf == 'r')
 732                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 733         else if (*buf == 'c')
 734                 type = PP_OD_COMMIT_DPM_TABLE;
 735         else if (!strncmp(buf, "vc", 2))
 736                 type = PP_OD_EDIT_VDDC_CURVE;
 737         else
 738                 return -EINVAL;
 739
 740         memcpy(buf_cpy, buf, count+1);
 741
 742         tmp_str = buf_cpy;
 743
 744         if (type == PP_OD_EDIT_VDDC_CURVE)
 745                 tmp_str++;
 746         while (isspace(*++tmp_str));
 747
 748         while (tmp_str[0]) {
 749                 sub_str = strsep(&tmp_str, delimiter);
 750                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 751                 if (ret)
 752                         return -EINVAL;
 753                 parameter_size++;
 754
 755                 while (isspace(*tmp_str))
 756                         tmp_str++;
 757         }
 758
 759         ret = pm_runtime_get_sync(ddev->dev);
 760         if (ret < 0)
 761                 return ret;
 762
 763         if (is_support_sw_smu(adev)) {
 764                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 765                                             parameter, parameter_size);
 766
 767                 if (ret) {
 768                         pm_runtime_mark_last_busy(ddev->dev);
 769                         pm_runtime_put_autosuspend(ddev->dev);
 770                         return -EINVAL;
 771                 }
 772         } else {
 773                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 774                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 775                                                 parameter, parameter_size);
 776                         if (ret) {
 777                                 pm_runtime_mark_last_busy(ddev->dev);
 778                                 pm_runtime_put_autosuspend(ddev->dev);
 779                                 return -EINVAL;
 780                         }
 781                 }
 782
 783                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 784                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 785                                 amdgpu_dpm_dispatch_task(adev,
 786                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 787                                                 NULL);
 788                                 pm_runtime_mark_last_busy(ddev->dev);
 789                                 pm_runtime_put_autosuspend(ddev->dev);
 790                                 return count;
 791                         } else {
 792                                 pm_runtime_mark_last_busy(ddev->dev);
 793                                 pm_runtime_put_autosuspend(ddev->dev);
 794                                 return -EINVAL;
 795                         }
 796                 }
 797         }
 798         pm_runtime_mark_last_busy(ddev->dev);
 799         pm_runtime_put_autosuspend(ddev->dev);
 800
 801         return count;
 802 }
 803
 804 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 805                 struct device_attribute *attr,
 806                 char *buf)
 807 {
 808         struct drm_device *ddev = dev_get_drvdata(dev);
 809         struct amdgpu_device *adev = ddev->dev_private;
 810         ssize_t size;
 811         int ret;
 812
 813         ret = pm_runtime_get_sync(ddev->dev);
 814         if (ret < 0)
 815                 return ret;
 816
 817         if (is_support_sw_smu(adev)) {
 818                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 819                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 820                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 821                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 822         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 823                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 824                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 825                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 826                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 827         } else {
 828                 size = snprintf(buf, PAGE_SIZE, "\n");
 829         }
 830         pm_runtime_mark_last_busy(ddev->dev);
 831         pm_runtime_put_autosuspend(ddev->dev);
 832
 833         return size;
 834 }
 835
 836 /**
 837  * DOC: pp_features
 838  *
 839  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 840  * features to be enabled. The file pp_features is used for this. And
 841  * this is only available for Vega10 and later dGPUs.
 842  *
 843  * Reading back the file will show you the followings:
 844  * - Current ppfeature masks
 845  * - List of the all supported powerplay features with their naming,
 846  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 847  *
 848  * To manually enable or disable a specific feature, just set or clear
 849  * the corresponding bit from original ppfeature masks and input the
 850  * new ppfeature masks.
 851  */
 852 static ssize_t amdgpu_set_pp_features(struct device *dev,
 853                                       struct device_attribute *attr,
 854                                       const char *buf,
 855                                       size_t count)
 856 {
 857         struct drm_device *ddev = dev_get_drvdata(dev);
 858         struct amdgpu_device *adev = ddev->dev_private;
 859         uint64_t featuremask;
 860         int ret;
 861
 862         ret = kstrtou64(buf, 0, &featuremask);
 863         if (ret)
 864                 return -EINVAL;
 865
 866         pr_debug("featuremask = 0x%llx\n", featuremask);
 867
 868         ret = pm_runtime_get_sync(ddev->dev);
 869         if (ret < 0)
 870                 return ret;
 871
 872         if (is_support_sw_smu(adev)) {
 873                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 874                 if (ret) {
 875                         pm_runtime_mark_last_busy(ddev->dev);
 876                         pm_runtime_put_autosuspend(ddev->dev);
 877                         return -EINVAL;
 878                 }
 879         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 880                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 881                 if (ret) {
 882                         pm_runtime_mark_last_busy(ddev->dev);
 883                         pm_runtime_put_autosuspend(ddev->dev);
 884                         return -EINVAL;
 885                 }
 886         }
 887         pm_runtime_mark_last_busy(ddev->dev);
 888         pm_runtime_put_autosuspend(ddev->dev);
 889
 890         return count;
 891 }
 892
 893 static ssize_t amdgpu_get_pp_features(struct device *dev,
 894                                       struct device_attribute *attr,
 895                                       char *buf)
 896 {
 897         struct drm_device *ddev = dev_get_drvdata(dev);
 898         struct amdgpu_device *adev = ddev->dev_private;
 899         ssize_t size;
 900         int ret;
 901
 902         ret = pm_runtime_get_sync(ddev->dev);
 903         if (ret < 0)
 904                 return ret;
 905
 906         if (is_support_sw_smu(adev))
 907                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
 908         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 909                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 910         else
 911                 size = snprintf(buf, PAGE_SIZE, "\n");
 912
 913         pm_runtime_mark_last_busy(ddev->dev);
 914         pm_runtime_put_autosuspend(ddev->dev);
 915
 916         return size;
 917 }
 918
 919 /**
 920  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 921  *
 922  * The amdgpu driver provides a sysfs API for adjusting what power levels
 923  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 924  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 925  * this.
 926  *
 927  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 928  * Vega10 and later ASICs.
 929  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 930  *
 931  * Reading back the files will show you the available power levels within
 932  * the power state and the clock information for those levels.
 933  *
 934  * To manually adjust these states, first select manual using
 935  * power_dpm_force_performance_level.
 936  * Secondly, enter a new value for each level by inputing a string that
 937  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 938  * E.g.,
 939  *
 940  * .. code-block:: bash
 941  *
 942  *      echo "4 5 6" > pp_dpm_sclk
 943  *
 944  * will enable sclk levels 4, 5, and 6.
 945  *
 946  * NOTE: change to the dcefclk max dpm level is not supported now
 947  */
 948
 949 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 950                 struct device_attribute *attr,
 951                 char *buf)
 952 {
 953         struct drm_device *ddev = dev_get_drvdata(dev);
 954         struct amdgpu_device *adev = ddev->dev_private;
 955         ssize_t size;
 956         int ret;
 957
 958         ret = pm_runtime_get_sync(ddev->dev);
 959         if (ret < 0)
 960                 return ret;
 961
 962         if (is_support_sw_smu(adev))
 963                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
 964         else if (adev->powerplay.pp_funcs->print_clock_levels)
 965                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 966         else
 967                 size = snprintf(buf, PAGE_SIZE, "\n");
 968
 969         pm_runtime_mark_last_busy(ddev->dev);
 970         pm_runtime_put_autosuspend(ddev->dev);
 971
 972         return size;
 973 }
 974
 975 /*
 976  * Worst case: 32 bits individually specified, in octal at 12 characters
 977  * per line (+1 for \n).
 978  */
 979 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 980
 981 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 982 {
 983         int ret;
 984         long level;
 985         char *sub_str = NULL;
 986         char *tmp;
 987         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 988         const char delimiter[3] = {' ', '\n', '\0'};
 989         size_t bytes;
 990
 991         *mask = 0;
 992
 993         bytes = min(count, sizeof(buf_cpy) - 1);
 994         memcpy(buf_cpy, buf, bytes);
 995         buf_cpy[bytes] = '\0';
 996         tmp = buf_cpy;
 997         while (tmp[0]) {
 998                 sub_str = strsep(&tmp, delimiter);
 999                 if (strlen(sub_str)) {
1000                         ret = kstrtol(sub_str, 0, &level);
1001                         if (ret)
1002                                 return -EINVAL;
1003                         *mask |= 1 << level;
1004                 } else
1005                         break;
1006         }
1007
1008         return 0;
1009 }
1010
1011 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1012                 struct device_attribute *attr,
1013                 const char *buf,
1014                 size_t count)
1015 {
1016         struct drm_device *ddev = dev_get_drvdata(dev);
1017         struct amdgpu_device *adev = ddev->dev_private;
1018         int ret;
1019         uint32_t mask = 0;
1020
1021         ret = amdgpu_read_mask(buf, count, &mask);
1022         if (ret)
1023                 return ret;
1024
1025         ret = pm_runtime_get_sync(ddev->dev);
1026         if (ret < 0)
1027                 return ret;
1028
1029         if (is_support_sw_smu(adev))
1030                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
1031         else if (adev->powerplay.pp_funcs->force_clock_level)
1032                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1033
1034         pm_runtime_mark_last_busy(ddev->dev);
1035         pm_runtime_put_autosuspend(ddev->dev);
1036
1037         if (ret)
1038                 return -EINVAL;
1039
1040         return count;
1041 }
1042
1043 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1044                 struct device_attribute *attr,
1045                 char *buf)
1046 {
1047         struct drm_device *ddev = dev_get_drvdata(dev);
1048         struct amdgpu_device *adev = ddev->dev_private;
1049         ssize_t size;
1050         int ret;
1051
1052         ret = pm_runtime_get_sync(ddev->dev);
1053         if (ret < 0)
1054                 return ret;
1055
1056         if (is_support_sw_smu(adev))
1057                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1058         else if (adev->powerplay.pp_funcs->print_clock_levels)
1059                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1060         else
1061                 size = snprintf(buf, PAGE_SIZE, "\n");
1062
1063         pm_runtime_mark_last_busy(ddev->dev);
1064         pm_runtime_put_autosuspend(ddev->dev);
1065
1066         return size;
1067 }
1068
1069 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1070                 struct device_attribute *attr,
1071                 const char *buf,
1072                 size_t count)
1073 {
1074         struct drm_device *ddev = dev_get_drvdata(dev);
1075         struct amdgpu_device *adev = ddev->dev_private;
1076         uint32_t mask = 0;
1077         int ret;
1078
1079         ret = amdgpu_read_mask(buf, count, &mask);
1080         if (ret)
1081                 return ret;
1082
1083         ret = pm_runtime_get_sync(ddev->dev);
1084         if (ret < 0)
1085                 return ret;
1086
1087         if (is_support_sw_smu(adev))
1088                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
1089         else if (adev->powerplay.pp_funcs->force_clock_level)
1090                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1091
1092         pm_runtime_mark_last_busy(ddev->dev);
1093         pm_runtime_put_autosuspend(ddev->dev);
1094
1095         if (ret)
1096                 return -EINVAL;
1097
1098         return count;
1099 }
1100
1101 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1102                 struct device_attribute *attr,
1103                 char *buf)
1104 {
1105         struct drm_device *ddev = dev_get_drvdata(dev);
1106         struct amdgpu_device *adev = ddev->dev_private;
1107         ssize_t size;
1108         int ret;
1109
1110         ret = pm_runtime_get_sync(ddev->dev);
1111         if (ret < 0)
1112                 return ret;
1113
1114         if (is_support_sw_smu(adev))
1115                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1116         else if (adev->powerplay.pp_funcs->print_clock_levels)
1117                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1118         else
1119                 size = snprintf(buf, PAGE_SIZE, "\n");
1120
1121         pm_runtime_mark_last_busy(ddev->dev);
1122         pm_runtime_put_autosuspend(ddev->dev);
1123
1124         return size;
1125 }
1126
1127 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1128                 struct device_attribute *attr,
1129                 const char *buf,
1130                 size_t count)
1131 {
1132         struct drm_device *ddev = dev_get_drvdata(dev);
1133         struct amdgpu_device *adev = ddev->dev_private;
1134         int ret;
1135         uint32_t mask = 0;
1136
1137         ret = amdgpu_read_mask(buf, count, &mask);
1138         if (ret)
1139                 return ret;
1140
1141         ret = pm_runtime_get_sync(ddev->dev);
1142         if (ret < 0)
1143                 return ret;
1144
1145         if (is_support_sw_smu(adev))
1146                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
1147         else if (adev->powerplay.pp_funcs->force_clock_level)
1148                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1149         else
1150                 ret = 0;
1151
1152         pm_runtime_mark_last_busy(ddev->dev);
1153         pm_runtime_put_autosuspend(ddev->dev);
1154
1155         if (ret)
1156                 return -EINVAL;
1157
1158         return count;
1159 }
1160
1161 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1162                 struct device_attribute *attr,
1163                 char *buf)
1164 {
1165         struct drm_device *ddev = dev_get_drvdata(dev);
1166         struct amdgpu_device *adev = ddev->dev_private;
1167         ssize_t size;
1168         int ret;
1169
1170         ret = pm_runtime_get_sync(ddev->dev);
1171         if (ret < 0)
1172                 return ret;
1173
1174         if (is_support_sw_smu(adev))
1175                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1176         else if (adev->powerplay.pp_funcs->print_clock_levels)
1177                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1178         else
1179                 size = snprintf(buf, PAGE_SIZE, "\n");
1180
1181         pm_runtime_mark_last_busy(ddev->dev);
1182         pm_runtime_put_autosuspend(ddev->dev);
1183
1184         return size;
1185 }
1186
1187 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1188                 struct device_attribute *attr,
1189                 const char *buf,
1190                 size_t count)
1191 {
1192         struct drm_device *ddev = dev_get_drvdata(dev);
1193         struct amdgpu_device *adev = ddev->dev_private;
1194         int ret;
1195         uint32_t mask = 0;
1196
1197         ret = amdgpu_read_mask(buf, count, &mask);
1198         if (ret)
1199                 return ret;
1200
1201         ret = pm_runtime_get_sync(ddev->dev);
1202         if (ret < 0)
1203                 return ret;
1204
1205         if (is_support_sw_smu(adev))
1206                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
1207         else if (adev->powerplay.pp_funcs->force_clock_level)
1208                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1209         else
1210                 ret = 0;
1211
1212         pm_runtime_mark_last_busy(ddev->dev);
1213         pm_runtime_put_autosuspend(ddev->dev);
1214
1215         if (ret)
1216                 return -EINVAL;
1217
1218         return count;
1219 }
1220
1221 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1222                 struct device_attribute *attr,
1223                 char *buf)
1224 {
1225         struct drm_device *ddev = dev_get_drvdata(dev);
1226         struct amdgpu_device *adev = ddev->dev_private;
1227         ssize_t size;
1228         int ret;
1229
1230         ret = pm_runtime_get_sync(ddev->dev);
1231         if (ret < 0)
1232                 return ret;
1233
1234         if (is_support_sw_smu(adev))
1235                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1236         else if (adev->powerplay.pp_funcs->print_clock_levels)
1237                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1238         else
1239                 size = snprintf(buf, PAGE_SIZE, "\n");
1240
1241         pm_runtime_mark_last_busy(ddev->dev);
1242         pm_runtime_put_autosuspend(ddev->dev);
1243
1244         return size;
1245 }
1246
1247 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1248                 struct device_attribute *attr,
1249                 const char *buf,
1250                 size_t count)
1251 {
1252         struct drm_device *ddev = dev_get_drvdata(dev);
1253         struct amdgpu_device *adev = ddev->dev_private;
1254         int ret;
1255         uint32_t mask = 0;
1256
1257         ret = amdgpu_read_mask(buf, count, &mask);
1258         if (ret)
1259                 return ret;
1260
1261         ret = pm_runtime_get_sync(ddev->dev);
1262         if (ret < 0)
1263                 return ret;
1264
1265         if (is_support_sw_smu(adev))
1266                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
1267         else if (adev->powerplay.pp_funcs->force_clock_level)
1268                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1269         else
1270                 ret = 0;
1271
1272         pm_runtime_mark_last_busy(ddev->dev);
1273         pm_runtime_put_autosuspend(ddev->dev);
1274
1275         if (ret)
1276                 return -EINVAL;
1277
1278         return count;
1279 }
1280
1281 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1282                 struct device_attribute *attr,
1283                 char *buf)
1284 {
1285         struct drm_device *ddev = dev_get_drvdata(dev);
1286         struct amdgpu_device *adev = ddev->dev_private;
1287         ssize_t size;
1288         int ret;
1289
1290         ret = pm_runtime_get_sync(ddev->dev);
1291         if (ret < 0)
1292                 return ret;
1293
1294         if (is_support_sw_smu(adev))
1295                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1296         else if (adev->powerplay.pp_funcs->print_clock_levels)
1297                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1298         else
1299                 size = snprintf(buf, PAGE_SIZE, "\n");
1300
1301         pm_runtime_mark_last_busy(ddev->dev);
1302         pm_runtime_put_autosuspend(ddev->dev);
1303
1304         return size;
1305 }
1306
1307 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1308                 struct device_attribute *attr,
1309                 const char *buf,
1310                 size_t count)
1311 {
1312         struct drm_device *ddev = dev_get_drvdata(dev);
1313         struct amdgpu_device *adev = ddev->dev_private;
1314         int ret;
1315         uint32_t mask = 0;
1316
1317         ret = amdgpu_read_mask(buf, count, &mask);
1318         if (ret)
1319                 return ret;
1320
1321         ret = pm_runtime_get_sync(ddev->dev);
1322         if (ret < 0)
1323                 return ret;
1324
1325         if (is_support_sw_smu(adev))
1326                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
1327         else if (adev->powerplay.pp_funcs->force_clock_level)
1328                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1329         else
1330                 ret = 0;
1331
1332         pm_runtime_mark_last_busy(ddev->dev);
1333         pm_runtime_put_autosuspend(ddev->dev);
1334
1335         if (ret)
1336                 return -EINVAL;
1337
1338         return count;
1339 }
1340
1341 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1342                 struct device_attribute *attr,
1343                 char *buf)
1344 {
1345         struct drm_device *ddev = dev_get_drvdata(dev);
1346         struct amdgpu_device *adev = ddev->dev_private;
1347         uint32_t value = 0;
1348         int ret;
1349
1350         ret = pm_runtime_get_sync(ddev->dev);
1351         if (ret < 0)
1352                 return ret;
1353
1354         if (is_support_sw_smu(adev))
1355                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1356         else if (adev->powerplay.pp_funcs->get_sclk_od)
1357                 value = amdgpu_dpm_get_sclk_od(adev);
1358
1359         pm_runtime_mark_last_busy(ddev->dev);
1360         pm_runtime_put_autosuspend(ddev->dev);
1361
1362         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1363 }
1364
1365 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1366                 struct device_attribute *attr,
1367                 const char *buf,
1368                 size_t count)
1369 {
1370         struct drm_device *ddev = dev_get_drvdata(dev);
1371         struct amdgpu_device *adev = ddev->dev_private;
1372         int ret;
1373         long int value;
1374
1375         ret = kstrtol(buf, 0, &value);
1376
1377         if (ret)
1378                 return -EINVAL;
1379
1380         ret = pm_runtime_get_sync(ddev->dev);
1381         if (ret < 0)
1382                 return ret;
1383
1384         if (is_support_sw_smu(adev)) {
1385                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1386         } else {
1387                 if (adev->powerplay.pp_funcs->set_sclk_od)
1388                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1389
1390                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1391                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1392                 } else {
1393                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1394                         amdgpu_pm_compute_clocks(adev);
1395                 }
1396         }
1397
1398         pm_runtime_mark_last_busy(ddev->dev);
1399         pm_runtime_put_autosuspend(ddev->dev);
1400
1401         return count;
1402 }
1403
1404 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1405                 struct device_attribute *attr,
1406                 char *buf)
1407 {
1408         struct drm_device *ddev = dev_get_drvdata(dev);
1409         struct amdgpu_device *adev = ddev->dev_private;
1410         uint32_t value = 0;
1411         int ret;
1412
1413         ret = pm_runtime_get_sync(ddev->dev);
1414         if (ret < 0)
1415                 return ret;
1416
1417         if (is_support_sw_smu(adev))
1418                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1419         else if (adev->powerplay.pp_funcs->get_mclk_od)
1420                 value = amdgpu_dpm_get_mclk_od(adev);
1421
1422         pm_runtime_mark_last_busy(ddev->dev);
1423         pm_runtime_put_autosuspend(ddev->dev);
1424
1425         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1426 }
1427
1428 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1429                 struct device_attribute *attr,
1430                 const char *buf,
1431                 size_t count)
1432 {
1433         struct drm_device *ddev = dev_get_drvdata(dev);
1434         struct amdgpu_device *adev = ddev->dev_private;
1435         int ret;
1436         long int value;
1437
1438         ret = kstrtol(buf, 0, &value);
1439
1440         if (ret)
1441                 return -EINVAL;
1442
1443         ret = pm_runtime_get_sync(ddev->dev);
1444         if (ret < 0)
1445                 return ret;
1446
1447         if (is_support_sw_smu(adev)) {
1448                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1449         } else {
1450                 if (adev->powerplay.pp_funcs->set_mclk_od)
1451                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1452
1453                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1454                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1455                 } else {
1456                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1457                         amdgpu_pm_compute_clocks(adev);
1458                 }
1459         }
1460
1461         pm_runtime_mark_last_busy(ddev->dev);
1462         pm_runtime_put_autosuspend(ddev->dev);
1463
1464         return count;
1465 }
1466
1467 /**
1468  * DOC: pp_power_profile_mode
1469  *
1470  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1471  * related to switching between power levels in a power state.  The file
1472  * pp_power_profile_mode is used for this.
1473  *
1474  * Reading this file outputs a list of all of the predefined power profiles
1475  * and the relevant heuristics settings for that profile.
1476  *
1477  * To select a profile or create a custom profile, first select manual using
1478  * power_dpm_force_performance_level.  Writing the number of a predefined
1479  * profile to pp_power_profile_mode will enable those heuristics.  To
1480  * create a custom set of heuristics, write a string of numbers to the file
1481  * starting with the number of the custom profile along with a setting
1482  * for each heuristic parameter.  Due to differences across asic families
1483  * the heuristic parameters vary from family to family.
1484  *
1485  */
1486
1487 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1488                 struct device_attribute *attr,
1489                 char *buf)
1490 {
1491         struct drm_device *ddev = dev_get_drvdata(dev);
1492         struct amdgpu_device *adev = ddev->dev_private;
1493         ssize_t size;
1494         int ret;
1495
1496         ret = pm_runtime_get_sync(ddev->dev);
1497         if (ret < 0)
1498                 return ret;
1499
1500         if (is_support_sw_smu(adev))
1501                 size = smu_get_power_profile_mode(&adev->smu, buf);
1502         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1503                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1504         else
1505                 size = snprintf(buf, PAGE_SIZE, "\n");
1506
1507         pm_runtime_mark_last_busy(ddev->dev);
1508         pm_runtime_put_autosuspend(ddev->dev);
1509
1510         return size;
1511 }
1512
1513
1514 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1515                 struct device_attribute *attr,
1516                 const char *buf,
1517                 size_t count)
1518 {
1519         int ret = 0xff;
1520         struct drm_device *ddev = dev_get_drvdata(dev);
1521         struct amdgpu_device *adev = ddev->dev_private;
1522         uint32_t parameter_size = 0;
1523         long parameter[64];
1524         char *sub_str, buf_cpy[128];
1525         char *tmp_str;
1526         uint32_t i = 0;
1527         char tmp[2];
1528         long int profile_mode = 0;
1529         const char delimiter[3] = {' ', '\n', '\0'};
1530
1531         tmp[0] = *(buf);
1532         tmp[1] = '\0';
1533         ret = kstrtol(tmp, 0, &profile_mode);
1534         if (ret)
1535                 return -EINVAL;
1536
1537         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1538                 if (count < 2 || count > 127)
1539                         return -EINVAL;
1540                 while (isspace(*++buf))
1541                         i++;
1542                 memcpy(buf_cpy, buf, count-i);
1543                 tmp_str = buf_cpy;
1544                 while (tmp_str[0]) {
1545                         sub_str = strsep(&tmp_str, delimiter);
1546                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1547                         if (ret)
1548                                 return -EINVAL;
1549                         parameter_size++;
1550                         while (isspace(*tmp_str))
1551                                 tmp_str++;
1552                 }
1553         }
1554         parameter[parameter_size] = profile_mode;
1555
1556         ret = pm_runtime_get_sync(ddev->dev);
1557         if (ret < 0)
1558                 return ret;
1559
1560         if (is_support_sw_smu(adev))
1561                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1562         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1563                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1564
1565         pm_runtime_mark_last_busy(ddev->dev);
1566         pm_runtime_put_autosuspend(ddev->dev);
1567
1568         if (!ret)
1569                 return count;
1570
1571         return -EINVAL;
1572 }
1573
1574 /**
1575  * DOC: busy_percent
1576  *
1577  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1578  * is as a percentage.  The file gpu_busy_percent is used for this.
1579  * The SMU firmware computes a percentage of load based on the
1580  * aggregate activity level in the IP cores.
1581  */
1582 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1583                                            struct device_attribute *attr,
1584                                            char *buf)
1585 {
1586         struct drm_device *ddev = dev_get_drvdata(dev);
1587         struct amdgpu_device *adev = ddev->dev_private;
1588         int r, value, size = sizeof(value);
1589
1590         r = pm_runtime_get_sync(ddev->dev);
1591         if (r < 0)
1592                 return r;
1593
1594         /* read the IP busy sensor */
1595         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1596                                    (void *)&value, &size);
1597
1598         pm_runtime_mark_last_busy(ddev->dev);
1599         pm_runtime_put_autosuspend(ddev->dev);
1600
1601         if (r)
1602                 return r;
1603
1604         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1605 }
1606
1607 /**
1608  * DOC: mem_busy_percent
1609  *
1610  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1611  * is as a percentage.  The file mem_busy_percent is used for this.
1612  * The SMU firmware computes a percentage of load based on the
1613  * aggregate activity level in the IP cores.
1614  */
1615 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1616                                            struct device_attribute *attr,
1617                                            char *buf)
1618 {
1619         struct drm_device *ddev = dev_get_drvdata(dev);
1620         struct amdgpu_device *adev = ddev->dev_private;
1621         int r, value, size = sizeof(value);
1622
1623         r = pm_runtime_get_sync(ddev->dev);
1624         if (r < 0)
1625                 return r;
1626
1627         /* read the IP busy sensor */
1628         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1629                                    (void *)&value, &size);
1630
1631         pm_runtime_mark_last_busy(ddev->dev);
1632         pm_runtime_put_autosuspend(ddev->dev);
1633
1634         if (r)
1635                 return r;
1636
1637         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1638 }
1639
1640 /**
1641  * DOC: pcie_bw
1642  *
1643  * The amdgpu driver provides a sysfs API for estimating how much data
1644  * has been received and sent by the GPU in the last second through PCIe.
1645  * The file pcie_bw is used for this.
1646  * The Perf counters count the number of received and sent messages and return
1647  * those values, as well as the maximum payload size of a PCIe packet (mps).
1648  * Note that it is not possible to easily and quickly obtain the size of each
1649  * packet transmitted, so we output the max payload size (mps) to allow for
1650  * quick estimation of the PCIe bandwidth usage
1651  */
1652 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1653                 struct device_attribute *attr,
1654                 char *buf)
1655 {
1656         struct drm_device *ddev = dev_get_drvdata(dev);
1657         struct amdgpu_device *adev = ddev->dev_private;
1658         uint64_t count0 = 0, count1 = 0;
1659         int ret;
1660
1661         if (adev->flags & AMD_IS_APU)
1662                 return -ENODATA;
1663
1664         if (!adev->asic_funcs->get_pcie_usage)
1665                 return -ENODATA;
1666
1667         ret = pm_runtime_get_sync(ddev->dev);
1668         if (ret < 0)
1669                 return ret;
1670
1671         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1672
1673         pm_runtime_mark_last_busy(ddev->dev);
1674         pm_runtime_put_autosuspend(ddev->dev);
1675
1676         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1677                         count0, count1, pcie_get_mps(adev->pdev));
1678 }
1679
1680 /**
1681  * DOC: unique_id
1682  *
1683  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1684  * The file unique_id is used for this.
1685  * This will provide a Unique ID that will persist from machine to machine
1686  *
1687  * NOTE: This will only work for GFX9 and newer. This file will be absent
1688  * on unsupported ASICs (GFX8 and older)
1689  */
1690 static ssize_t amdgpu_get_unique_id(struct device *dev,
1691                 struct device_attribute *attr,
1692                 char *buf)
1693 {
1694         struct drm_device *ddev = dev_get_drvdata(dev);
1695         struct amdgpu_device *adev = ddev->dev_private;
1696
1697         if (adev->unique_id)
1698                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1699
1700         return 0;
1701 }
1702
1703 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1704         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1705         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1706         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
1707         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
1708         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
1709         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
1710         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1711         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1712         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1713         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1714         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
1715         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
1716         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
1717         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
1718         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
1719         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
1720         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
1721         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
1722         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
1723         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
1724         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
1725 };
1726
1727 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1728                                uint32_t mask, enum amdgpu_device_attr_states *states)
1729 {
1730         struct device_attribute *dev_attr = &attr->dev_attr;
1731         const char *attr_name = dev_attr->attr.name;
1732         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1733         enum amd_asic_type asic_type = adev->asic_type;
1734
1735         if (!(attr->flags & mask)) {
1736                 *states = ATTR_STATE_UNSUPPORTED;
1737                 return 0;
1738         }
1739
1740 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
1741
1742         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1743                 if (asic_type < CHIP_VEGA10)
1744                         *states = ATTR_STATE_UNSUPPORTED;
1745         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1746                 if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
1747                         *states = ATTR_STATE_UNSUPPORTED;
1748         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
1749                 if (asic_type < CHIP_VEGA20)
1750                         *states = ATTR_STATE_UNSUPPORTED;
1751         } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
1752                 if (asic_type == CHIP_ARCTURUS)
1753                         *states = ATTR_STATE_UNSUPPORTED;
1754         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
1755                 *states = ATTR_STATE_UNSUPPORTED;
1756                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
1757                     (!is_support_sw_smu(adev) && hwmgr->od_enabled))
1758                         *states = ATTR_STATE_SUPPORTED;
1759         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
1760                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
1761                         *states = ATTR_STATE_UNSUPPORTED;
1762         } else if (DEVICE_ATTR_IS(pcie_bw)) {
1763                 /* PCIe Perf counters won't work on APU nodes */
1764                 if (adev->flags & AMD_IS_APU)
1765                         *states = ATTR_STATE_UNSUPPORTED;
1766         } else if (DEVICE_ATTR_IS(unique_id)) {
1767                 if (!adev->unique_id)
1768                         *states = ATTR_STATE_UNSUPPORTED;
1769         } else if (DEVICE_ATTR_IS(pp_features)) {
1770                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
1771                         *states = ATTR_STATE_UNSUPPORTED;
1772         }
1773
1774         if (asic_type == CHIP_ARCTURUS) {
1775                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
1776                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
1777                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
1778                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
1779                         dev_attr->attr.mode &= ~S_IWUGO;
1780                         dev_attr->store = NULL;
1781                 }
1782         }
1783
1784 #undef DEVICE_ATTR_IS
1785
1786         return 0;
1787 }
1788
1789
1790 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
1791                                      struct amdgpu_device_attr *attr,
1792                                      uint32_t mask, struct list_head *attr_list)
1793 {
1794         int ret = 0;
1795         struct device_attribute *dev_attr = &attr->dev_attr;
1796         const char *name = dev_attr->attr.name;
1797         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
1798         struct amdgpu_device_attr_entry *attr_entry;
1799
1800         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1801                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
1802
1803         BUG_ON(!attr);
1804
1805         attr_update = attr->attr_update ? attr_update : default_attr_update;
1806
1807         ret = attr_update(adev, attr, mask, &attr_states);
1808         if (ret) {
1809                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
1810                         name, ret);
1811                 return ret;
1812         }
1813
1814         if (attr_states == ATTR_STATE_UNSUPPORTED)
1815                 return 0;
1816
1817         ret = device_create_file(adev->dev, dev_attr);
1818         if (ret) {
1819                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
1820                         name, ret);
1821         }
1822
1823         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
1824         if (!attr_entry)
1825                 return -ENOMEM;
1826
1827         attr_entry->attr = attr;
1828         INIT_LIST_HEAD(&attr_entry->entry);
1829
1830         list_add_tail(&attr_entry->entry, attr_list);
1831
1832         return ret;
1833 }
1834
1835 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
1836 {
1837         struct device_attribute *dev_attr = &attr->dev_attr;
1838
1839         device_remove_file(adev->dev, dev_attr);
1840 }
1841
1842 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
1843                                              struct list_head *attr_list);
1844
1845 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
1846                                             struct amdgpu_device_attr *attrs,
1847                                             uint32_t counts,
1848                                             uint32_t mask,
1849                                             struct list_head *attr_list)
1850 {
1851         int ret = 0;
1852         uint32_t i = 0;
1853
1854         for (i = 0; i < counts; i++) {
1855                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
1856                 if (ret)
1857                         goto failed;
1858         }
1859
1860         return 0;
1861
1862 failed:
1863         amdgpu_device_attr_remove_groups(adev, attr_list);
1864
1865         return ret;
1866 }
1867
1868 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
1869                                              struct list_head *attr_list)
1870 {
1871         struct amdgpu_device_attr_entry *entry, *entry_tmp;
1872
1873         if (list_empty(attr_list))
1874                 return ;
1875
1876         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
1877                 amdgpu_device_attr_remove(adev, entry->attr);
1878                 list_del(&entry->entry);
1879                 kfree(entry);
1880         }
1881 }
1882
1883 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1884                                       struct device_attribute *attr,
1885                                       char *buf)
1886 {
1887         struct amdgpu_device *adev = dev_get_drvdata(dev);
1888         int channel = to_sensor_dev_attr(attr)->index;
1889         int r, temp = 0, size = sizeof(temp);
1890
1891         if (channel >= PP_TEMP_MAX)
1892                 return -EINVAL;
1893
1894         r = pm_runtime_get_sync(adev->ddev->dev);
1895         if (r < 0)
1896                 return r;
1897
1898         switch (channel) {
1899         case PP_TEMP_JUNCTION:
1900                 /* get current junction temperature */
1901                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1902                                            (void *)&temp, &size);
1903                 break;
1904         case PP_TEMP_EDGE:
1905                 /* get current edge temperature */
1906                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1907                                            (void *)&temp, &size);
1908                 break;
1909         case PP_TEMP_MEM:
1910                 /* get current memory temperature */
1911                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1912                                            (void *)&temp, &size);
1913                 break;
1914         default:
1915                 r = -EINVAL;
1916                 break;
1917         }
1918
1919         pm_runtime_mark_last_busy(adev->ddev->dev);
1920         pm_runtime_put_autosuspend(adev->ddev->dev);
1921
1922         if (r)
1923                 return r;
1924
1925         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1926 }
1927
1928 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1929                                              struct device_attribute *attr,
1930                                              char *buf)
1931 {
1932         struct amdgpu_device *adev = dev_get_drvdata(dev);
1933         int hyst = to_sensor_dev_attr(attr)->index;
1934         int temp;
1935
1936         if (hyst)
1937                 temp = adev->pm.dpm.thermal.min_temp;
1938         else
1939                 temp = adev->pm.dpm.thermal.max_temp;
1940
1941         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1942 }
1943
1944 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1945                                              struct device_attribute *attr,
1946                                              char *buf)
1947 {
1948         struct amdgpu_device *adev = dev_get_drvdata(dev);
1949         int hyst = to_sensor_dev_attr(attr)->index;
1950         int temp;
1951
1952         if (hyst)
1953                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1954         else
1955                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1956
1957         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1958 }
1959
1960 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1961                                              struct device_attribute *attr,
1962                                              char *buf)
1963 {
1964         struct amdgpu_device *adev = dev_get_drvdata(dev);
1965         int hyst = to_sensor_dev_attr(attr)->index;
1966         int temp;
1967
1968         if (hyst)
1969                 temp = adev->pm.dpm.thermal.min_mem_temp;
1970         else
1971                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1972
1973         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1974 }
1975
1976 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1977                                              struct device_attribute *attr,
1978                                              char *buf)
1979 {
1980         int channel = to_sensor_dev_attr(attr)->index;
1981
1982         if (channel >= PP_TEMP_MAX)
1983                 return -EINVAL;
1984
1985         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1986 }
1987
1988 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1989                                              struct device_attribute *attr,
1990                                              char *buf)
1991 {
1992         struct amdgpu_device *adev = dev_get_drvdata(dev);
1993         int channel = to_sensor_dev_attr(attr)->index;
1994         int temp = 0;
1995
1996         if (channel >= PP_TEMP_MAX)
1997                 return -EINVAL;
1998
1999         switch (channel) {
2000         case PP_TEMP_JUNCTION:
2001                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2002                 break;
2003         case PP_TEMP_EDGE:
2004                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2005                 break;
2006         case PP_TEMP_MEM:
2007                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2008                 break;
2009         }
2010
2011         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2012 }
2013
2014 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2015                                             struct device_attribute *attr,
2016                                             char *buf)
2017 {
2018         struct amdgpu_device *adev = dev_get_drvdata(dev);
2019         u32 pwm_mode = 0;
2020         int ret;
2021
2022         ret = pm_runtime_get_sync(adev->ddev->dev);
2023         if (ret < 0)
2024                 return ret;
2025
2026         if (is_support_sw_smu(adev)) {
2027                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2028         } else {
2029                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2030                         pm_runtime_mark_last_busy(adev->ddev->dev);
2031                         pm_runtime_put_autosuspend(adev->ddev->dev);
2032                         return -EINVAL;
2033                 }
2034
2035                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2036         }
2037
2038         pm_runtime_mark_last_busy(adev->ddev->dev);
2039         pm_runtime_put_autosuspend(adev->ddev->dev);
2040
2041         return sprintf(buf, "%i\n", pwm_mode);
2042 }
2043
2044 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2045                                             struct device_attribute *attr,
2046                                             const char *buf,
2047                                             size_t count)
2048 {
2049         struct amdgpu_device *adev = dev_get_drvdata(dev);
2050         int err, ret;
2051         int value;
2052
2053         err = kstrtoint(buf, 10, &value);
2054         if (err)
2055                 return err;
2056
2057         ret = pm_runtime_get_sync(adev->ddev->dev);
2058         if (ret < 0)
2059                 return ret;
2060
2061         if (is_support_sw_smu(adev)) {
2062                 smu_set_fan_control_mode(&adev->smu, value);
2063         } else {
2064                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2065                         pm_runtime_mark_last_busy(adev->ddev->dev);
2066                         pm_runtime_put_autosuspend(adev->ddev->dev);
2067                         return -EINVAL;
2068                 }
2069
2070                 amdgpu_dpm_set_fan_control_mode(adev, value);
2071         }
2072
2073         pm_runtime_mark_last_busy(adev->ddev->dev);
2074         pm_runtime_put_autosuspend(adev->ddev->dev);
2075
2076         return count;
2077 }
2078
2079 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2080                                          struct device_attribute *attr,
2081                                          char *buf)
2082 {
2083         return sprintf(buf, "%i\n", 0);
2084 }
2085
2086 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2087                                          struct device_attribute *attr,
2088                                          char *buf)
2089 {
2090         return sprintf(buf, "%i\n", 255);
2091 }
2092
2093 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2094                                      struct device_attribute *attr,
2095                                      const char *buf, size_t count)
2096 {
2097         struct amdgpu_device *adev = dev_get_drvdata(dev);
2098         int err;
2099         u32 value;
2100         u32 pwm_mode;
2101
2102         err = pm_runtime_get_sync(adev->ddev->dev);
2103         if (err < 0)
2104                 return err;
2105
2106         if (is_support_sw_smu(adev))
2107                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2108         else
2109                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2110
2111         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2112                 pr_info("manual fan speed control should be enabled first\n");
2113                 pm_runtime_mark_last_busy(adev->ddev->dev);
2114                 pm_runtime_put_autosuspend(adev->ddev->dev);
2115                 return -EINVAL;
2116         }
2117
2118         err = kstrtou32(buf, 10, &value);
2119         if (err) {
2120                 pm_runtime_mark_last_busy(adev->ddev->dev);
2121                 pm_runtime_put_autosuspend(adev->ddev->dev);
2122                 return err;
2123         }
2124
2125         value = (value * 100) / 255;
2126
2127         if (is_support_sw_smu(adev))
2128                 err = smu_set_fan_speed_percent(&adev->smu, value);
2129         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2130                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2131         else
2132                 err = -EINVAL;
2133
2134         pm_runtime_mark_last_busy(adev->ddev->dev);
2135         pm_runtime_put_autosuspend(adev->ddev->dev);
2136
2137         if (err)
2138                 return err;
2139
2140         return count;
2141 }
2142
2143 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2144                                      struct device_attribute *attr,
2145                                      char *buf)
2146 {
2147         struct amdgpu_device *adev = dev_get_drvdata(dev);
2148         int err;
2149         u32 speed = 0;
2150
2151         err = pm_runtime_get_sync(adev->ddev->dev);
2152         if (err < 0)
2153                 return err;
2154
2155         if (is_support_sw_smu(adev))
2156                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2157         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2158                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2159         else
2160                 err = -EINVAL;
2161
2162         pm_runtime_mark_last_busy(adev->ddev->dev);
2163         pm_runtime_put_autosuspend(adev->ddev->dev);
2164
2165         if (err)
2166                 return err;
2167
2168         speed = (speed * 255) / 100;
2169
2170         return sprintf(buf, "%i\n", speed);
2171 }
2172
2173 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2174                                            struct device_attribute *attr,
2175                                            char *buf)
2176 {
2177         struct amdgpu_device *adev = dev_get_drvdata(dev);
2178         int err;
2179         u32 speed = 0;
2180
2181         err = pm_runtime_get_sync(adev->ddev->dev);
2182         if (err < 0)
2183                 return err;
2184
2185         if (is_support_sw_smu(adev))
2186                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2187         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2188                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2189         else
2190                 err = -EINVAL;
2191
2192         pm_runtime_mark_last_busy(adev->ddev->dev);
2193         pm_runtime_put_autosuspend(adev->ddev->dev);
2194
2195         if (err)
2196                 return err;
2197
2198         return sprintf(buf, "%i\n", speed);
2199 }
2200
2201 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2202                                          struct device_attribute *attr,
2203                                          char *buf)
2204 {
2205         struct amdgpu_device *adev = dev_get_drvdata(dev);
2206         u32 min_rpm = 0;
2207         u32 size = sizeof(min_rpm);
2208         int r;
2209
2210         r = pm_runtime_get_sync(adev->ddev->dev);
2211         if (r < 0)
2212                 return r;
2213
2214         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2215                                    (void *)&min_rpm, &size);
2216
2217         pm_runtime_mark_last_busy(adev->ddev->dev);
2218         pm_runtime_put_autosuspend(adev->ddev->dev);
2219
2220         if (r)
2221                 return r;
2222
2223         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2224 }
2225
2226 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2227                                          struct device_attribute *attr,
2228                                          char *buf)
2229 {
2230         struct amdgpu_device *adev = dev_get_drvdata(dev);
2231         u32 max_rpm = 0;
2232         u32 size = sizeof(max_rpm);
2233         int r;
2234
2235         r = pm_runtime_get_sync(adev->ddev->dev);
2236         if (r < 0)
2237                 return r;
2238
2239         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2240                                    (void *)&max_rpm, &size);
2241
2242         pm_runtime_mark_last_busy(adev->ddev->dev);
2243         pm_runtime_put_autosuspend(adev->ddev->dev);
2244
2245         if (r)
2246                 return r;
2247
2248         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2249 }
2250
2251 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2252                                            struct device_attribute *attr,
2253                                            char *buf)
2254 {
2255         struct amdgpu_device *adev = dev_get_drvdata(dev);
2256         int err;
2257         u32 rpm = 0;
2258
2259         err = pm_runtime_get_sync(adev->ddev->dev);
2260         if (err < 0)
2261                 return err;
2262
2263         if (is_support_sw_smu(adev))
2264                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2265         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2266                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2267         else
2268                 err = -EINVAL;
2269
2270         pm_runtime_mark_last_busy(adev->ddev->dev);
2271         pm_runtime_put_autosuspend(adev->ddev->dev);
2272
2273         if (err)
2274                 return err;
2275
2276         return sprintf(buf, "%i\n", rpm);
2277 }
2278
2279 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2280                                      struct device_attribute *attr,
2281                                      const char *buf, size_t count)
2282 {
2283         struct amdgpu_device *adev = dev_get_drvdata(dev);
2284         int err;
2285         u32 value;
2286         u32 pwm_mode;
2287
2288         err = pm_runtime_get_sync(adev->ddev->dev);
2289         if (err < 0)
2290                 return err;
2291
2292         if (is_support_sw_smu(adev))
2293                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2294         else
2295                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2296
2297         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2298                 pm_runtime_mark_last_busy(adev->ddev->dev);
2299                 pm_runtime_put_autosuspend(adev->ddev->dev);
2300                 return -ENODATA;
2301         }
2302
2303         err = kstrtou32(buf, 10, &value);
2304         if (err) {
2305                 pm_runtime_mark_last_busy(adev->ddev->dev);
2306                 pm_runtime_put_autosuspend(adev->ddev->dev);
2307                 return err;
2308         }
2309
2310         if (is_support_sw_smu(adev))
2311                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2312         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2313                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2314         else
2315                 err = -EINVAL;
2316
2317         pm_runtime_mark_last_busy(adev->ddev->dev);
2318         pm_runtime_put_autosuspend(adev->ddev->dev);
2319
2320         if (err)
2321                 return err;
2322
2323         return count;
2324 }
2325
2326 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2327                                             struct device_attribute *attr,
2328                                             char *buf)
2329 {
2330         struct amdgpu_device *adev = dev_get_drvdata(dev);
2331         u32 pwm_mode = 0;
2332         int ret;
2333
2334         ret = pm_runtime_get_sync(adev->ddev->dev);
2335         if (ret < 0)
2336                 return ret;
2337
2338         if (is_support_sw_smu(adev)) {
2339                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2340         } else {
2341                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2342                         pm_runtime_mark_last_busy(adev->ddev->dev);
2343                         pm_runtime_put_autosuspend(adev->ddev->dev);
2344                         return -EINVAL;
2345                 }
2346
2347                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2348         }
2349
2350         pm_runtime_mark_last_busy(adev->ddev->dev);
2351         pm_runtime_put_autosuspend(adev->ddev->dev);
2352
2353         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2354 }
2355
2356 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2357                                             struct device_attribute *attr,
2358                                             const char *buf,
2359                                             size_t count)
2360 {
2361         struct amdgpu_device *adev = dev_get_drvdata(dev);
2362         int err;
2363         int value;
2364         u32 pwm_mode;
2365
2366         err = kstrtoint(buf, 10, &value);
2367         if (err)
2368                 return err;
2369
2370         if (value == 0)
2371                 pwm_mode = AMD_FAN_CTRL_AUTO;
2372         else if (value == 1)
2373                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2374         else
2375                 return -EINVAL;
2376
2377         err = pm_runtime_get_sync(adev->ddev->dev);
2378         if (err < 0)
2379                 return err;
2380
2381         if (is_support_sw_smu(adev)) {
2382                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2383         } else {
2384                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2385                         pm_runtime_mark_last_busy(adev->ddev->dev);
2386                         pm_runtime_put_autosuspend(adev->ddev->dev);
2387                         return -EINVAL;
2388                 }
2389                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2390         }
2391
2392         pm_runtime_mark_last_busy(adev->ddev->dev);
2393         pm_runtime_put_autosuspend(adev->ddev->dev);
2394
2395         return count;
2396 }
2397
2398 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2399                                         struct device_attribute *attr,
2400                                         char *buf)
2401 {
2402         struct amdgpu_device *adev = dev_get_drvdata(dev);
2403         u32 vddgfx;
2404         int r, size = sizeof(vddgfx);
2405
2406         r = pm_runtime_get_sync(adev->ddev->dev);
2407         if (r < 0)
2408                 return r;
2409
2410         /* get the voltage */
2411         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2412                                    (void *)&vddgfx, &size);
2413
2414         pm_runtime_mark_last_busy(adev->ddev->dev);
2415         pm_runtime_put_autosuspend(adev->ddev->dev);
2416
2417         if (r)
2418                 return r;
2419
2420         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2421 }
2422
2423 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2424                                               struct device_attribute *attr,
2425                                               char *buf)
2426 {
2427         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2428 }
2429
2430 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2431                                        struct device_attribute *attr,
2432                                        char *buf)
2433 {
2434         struct amdgpu_device *adev = dev_get_drvdata(dev);
2435         u32 vddnb;
2436         int r, size = sizeof(vddnb);
2437
2438         /* only APUs have vddnb */
2439         if  (!(adev->flags & AMD_IS_APU))
2440                 return -EINVAL;
2441
2442         r = pm_runtime_get_sync(adev->ddev->dev);
2443         if (r < 0)
2444                 return r;
2445
2446         /* get the voltage */
2447         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2448                                    (void *)&vddnb, &size);
2449
2450         pm_runtime_mark_last_busy(adev->ddev->dev);
2451         pm_runtime_put_autosuspend(adev->ddev->dev);
2452
2453         if (r)
2454                 return r;
2455
2456         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
2457 }
2458
2459 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2460                                               struct device_attribute *attr,
2461                                               char *buf)
2462 {
2463         return snprintf(buf, PAGE_SIZE, "vddnb\n");
2464 }
2465
2466 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2467                                            struct device_attribute *attr,
2468                                            char *buf)
2469 {
2470         struct amdgpu_device *adev = dev_get_drvdata(dev);
2471         u32 query = 0;
2472         int r, size = sizeof(u32);
2473         unsigned uw;
2474
2475         r = pm_runtime_get_sync(adev->ddev->dev);
2476         if (r < 0)
2477                 return r;
2478
2479         /* get the voltage */
2480         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2481                                    (void *)&query, &size);
2482
2483         pm_runtime_mark_last_busy(adev->ddev->dev);
2484         pm_runtime_put_autosuspend(adev->ddev->dev);
2485
2486         if (r)
2487                 return r;
2488
2489         /* convert to microwatts */
2490         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2491
2492         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2493 }
2494
2495 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2496                                          struct device_attribute *attr,
2497                                          char *buf)
2498 {
2499         return sprintf(buf, "%i\n", 0);
2500 }
2501
2502 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2503                                          struct device_attribute *attr,
2504                                          char *buf)
2505 {
2506         struct amdgpu_device *adev = dev_get_drvdata(dev);
2507         uint32_t limit = 0;
2508         ssize_t size;
2509         int r;
2510
2511         r = pm_runtime_get_sync(adev->ddev->dev);
2512         if (r < 0)
2513                 return r;
2514
2515         if (is_support_sw_smu(adev)) {
2516                 smu_get_power_limit(&adev->smu, &limit, true, true);
2517                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2518         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2519                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2520                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2521         } else {
2522                 size = snprintf(buf, PAGE_SIZE, "\n");
2523         }
2524
2525         pm_runtime_mark_last_busy(adev->ddev->dev);
2526         pm_runtime_put_autosuspend(adev->ddev->dev);
2527
2528         return size;
2529 }
2530
2531 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2532                                          struct device_attribute *attr,
2533                                          char *buf)
2534 {
2535         struct amdgpu_device *adev = dev_get_drvdata(dev);
2536         uint32_t limit = 0;
2537         ssize_t size;
2538         int r;
2539
2540         r = pm_runtime_get_sync(adev->ddev->dev);
2541         if (r < 0)
2542                 return r;
2543
2544         if (is_support_sw_smu(adev)) {
2545                 smu_get_power_limit(&adev->smu, &limit, false,  true);
2546                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2547         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2548                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2549                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2550         } else {
2551                 size = snprintf(buf, PAGE_SIZE, "\n");
2552         }
2553
2554         pm_runtime_mark_last_busy(adev->ddev->dev);
2555         pm_runtime_put_autosuspend(adev->ddev->dev);
2556
2557         return size;
2558 }
2559
2560
2561 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2562                 struct device_attribute *attr,
2563                 const char *buf,
2564                 size_t count)
2565 {
2566         struct amdgpu_device *adev = dev_get_drvdata(dev);
2567         int err;
2568         u32 value;
2569
2570         if (amdgpu_sriov_vf(adev))
2571                 return -EINVAL;
2572
2573         err = kstrtou32(buf, 10, &value);
2574         if (err)
2575                 return err;
2576
2577         value = value / 1000000; /* convert to Watt */
2578
2579
2580         err = pm_runtime_get_sync(adev->ddev->dev);
2581         if (err < 0)
2582                 return err;
2583
2584         if (is_support_sw_smu(adev))
2585                 err = smu_set_power_limit(&adev->smu, value);
2586         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
2587                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2588         else
2589                 err = -EINVAL;
2590
2591         pm_runtime_mark_last_busy(adev->ddev->dev);
2592         pm_runtime_put_autosuspend(adev->ddev->dev);
2593
2594         if (err)
2595                 return err;
2596
2597         return count;
2598 }
2599
2600 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2601                                       struct device_attribute *attr,
2602                                       char *buf)
2603 {
2604         struct amdgpu_device *adev = dev_get_drvdata(dev);
2605         uint32_t sclk;
2606         int r, size = sizeof(sclk);
2607
2608         r = pm_runtime_get_sync(adev->ddev->dev);
2609         if (r < 0)
2610                 return r;
2611
2612         /* get the sclk */
2613         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2614                                    (void *)&sclk, &size);
2615
2616         pm_runtime_mark_last_busy(adev->ddev->dev);
2617         pm_runtime_put_autosuspend(adev->ddev->dev);
2618
2619         if (r)
2620                 return r;
2621
2622         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2623 }
2624
2625 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2626                                             struct device_attribute *attr,
2627                                             char *buf)
2628 {
2629         return snprintf(buf, PAGE_SIZE, "sclk\n");
2630 }
2631
2632 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2633                                       struct device_attribute *attr,
2634                                       char *buf)
2635 {
2636         struct amdgpu_device *adev = dev_get_drvdata(dev);
2637         uint32_t mclk;
2638         int r, size = sizeof(mclk);
2639
2640         r = pm_runtime_get_sync(adev->ddev->dev);
2641         if (r < 0)
2642                 return r;
2643
2644         /* get the sclk */
2645         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2646                                    (void *)&mclk, &size);
2647
2648         pm_runtime_mark_last_busy(adev->ddev->dev);
2649         pm_runtime_put_autosuspend(adev->ddev->dev);
2650
2651         if (r)
2652                 return r;
2653
2654         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2655 }
2656
2657 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2658                                             struct device_attribute *attr,
2659                                             char *buf)
2660 {
2661         return snprintf(buf, PAGE_SIZE, "mclk\n");
2662 }
2663
2664 /**
2665  * DOC: hwmon
2666  *
2667  * The amdgpu driver exposes the following sensor interfaces:
2668  *
2669  * - GPU temperature (via the on-die sensor)
2670  *
2671  * - GPU voltage
2672  *
2673  * - Northbridge voltage (APUs only)
2674  *
2675  * - GPU power
2676  *
2677  * - GPU fan
2678  *
2679  * - GPU gfx/compute engine clock
2680  *
2681  * - GPU memory clock (dGPU only)
2682  *
2683  * hwmon interfaces for GPU temperature:
2684  *
2685  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2686  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2687  *
2688  * - temp[1-3]_label: temperature channel label
2689  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2690  *
2691  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2692  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2693  *
2694  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2695  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2696  *
2697  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2698  *   - these are supported on SOC15 dGPUs only
2699  *
2700  * hwmon interfaces for GPU voltage:
2701  *
2702  * - in0_input: the voltage on the GPU in millivolts
2703  *
2704  * - in1_input: the voltage on the Northbridge in millivolts
2705  *
2706  * hwmon interfaces for GPU power:
2707  *
2708  * - power1_average: average power used by the GPU in microWatts
2709  *
2710  * - power1_cap_min: minimum cap supported in microWatts
2711  *
2712  * - power1_cap_max: maximum cap supported in microWatts
2713  *
2714  * - power1_cap: selected power cap in microWatts
2715  *
2716  * hwmon interfaces for GPU fan:
2717  *
2718  * - pwm1: pulse width modulation fan level (0-255)
2719  *
2720  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2721  *
2722  * - pwm1_min: pulse width modulation fan control minimum level (0)
2723  *
2724  * - pwm1_max: pulse width modulation fan control maximum level (255)
2725  *
2726  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2727  *
2728  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2729  *
2730  * - fan1_input: fan speed in RPM
2731  *
2732  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
2733  *
2734  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2735  *
2736  * hwmon interfaces for GPU clocks:
2737  *
2738  * - freq1_input: the gfx/compute clock in hertz
2739  *
2740  * - freq2_input: the memory clock in hertz
2741  *
2742  * You can use hwmon tools like sensors to view this information on your system.
2743  *
2744  */
2745
2746 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2747 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2748 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2749 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2750 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2751 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2752 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2753 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2754 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2755 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2756 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2757 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2758 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2759 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2760 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2761 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2762 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2763 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2764 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2765 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2766 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2767 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2768 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2769 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2770 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2771 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2772 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2773 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2774 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2775 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2776 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2777 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2778 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2779 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2780 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2781 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2782
2783 static struct attribute *hwmon_attributes[] = {
2784         &sensor_dev_attr_temp1_input.dev_attr.attr,
2785         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2786         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2787         &sensor_dev_attr_temp2_input.dev_attr.attr,
2788         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2789         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2790         &sensor_dev_attr_temp3_input.dev_attr.attr,
2791         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2792         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2793         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2794         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2795         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2796         &sensor_dev_attr_temp1_label.dev_attr.attr,
2797         &sensor_dev_attr_temp2_label.dev_attr.attr,
2798         &sensor_dev_attr_temp3_label.dev_attr.attr,
2799         &sensor_dev_attr_pwm1.dev_attr.attr,
2800         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2801         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2802         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2803         &sensor_dev_attr_fan1_input.dev_attr.attr,
2804         &sensor_dev_attr_fan1_min.dev_attr.attr,
2805         &sensor_dev_attr_fan1_max.dev_attr.attr,
2806         &sensor_dev_attr_fan1_target.dev_attr.attr,
2807         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2808         &sensor_dev_attr_in0_input.dev_attr.attr,
2809         &sensor_dev_attr_in0_label.dev_attr.attr,
2810         &sensor_dev_attr_in1_input.dev_attr.attr,
2811         &sensor_dev_attr_in1_label.dev_attr.attr,
2812         &sensor_dev_attr_power1_average.dev_attr.attr,
2813         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2814         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2815         &sensor_dev_attr_power1_cap.dev_attr.attr,
2816         &sensor_dev_attr_freq1_input.dev_attr.attr,
2817         &sensor_dev_attr_freq1_label.dev_attr.attr,
2818         &sensor_dev_attr_freq2_input.dev_attr.attr,
2819         &sensor_dev_attr_freq2_label.dev_attr.attr,
2820         NULL
2821 };
2822
2823 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2824                                         struct attribute *attr, int index)
2825 {
2826         struct device *dev = kobj_to_dev(kobj);
2827         struct amdgpu_device *adev = dev_get_drvdata(dev);
2828         umode_t effective_mode = attr->mode;
2829
2830         /* under multi-vf mode, the hwmon attributes are all not supported */
2831         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
2832                 return 0;
2833
2834         /* there is no fan under pp one vf mode */
2835         if (amdgpu_sriov_is_pp_one_vf(adev) &&
2836             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2837              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2838              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2839              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2840              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2841              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2842              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2843              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2844              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2845                 return 0;
2846
2847         /* Skip fan attributes if fan is not present */
2848         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2849             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2850             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2851             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2852             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2853             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2854             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2855             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2856             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2857                 return 0;
2858
2859         /* Skip fan attributes on APU */
2860         if ((adev->flags & AMD_IS_APU) &&
2861             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2862              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2863              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2864              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2865              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2866              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2867              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2868              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2869              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2870                 return 0;
2871
2872         /* Skip limit attributes if DPM is not enabled */
2873         if (!adev->pm.dpm_enabled &&
2874             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2875              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2876              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2877              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2878              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2879              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2880              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2881              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2882              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2883              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2884              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2885                 return 0;
2886
2887         if (!is_support_sw_smu(adev)) {
2888                 /* mask fan attributes if we have no bindings for this asic to expose */
2889                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2890                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2891                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2892                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2893                         effective_mode &= ~S_IRUGO;
2894
2895                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2896                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2897                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2898                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2899                         effective_mode &= ~S_IWUSR;
2900         }
2901
2902         if (((adev->flags & AMD_IS_APU) ||
2903              adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2904              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2905             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2906              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2907              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2908              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2909                 return 0;
2910
2911         if (!is_support_sw_smu(adev)) {
2912                 /* hide max/min values if we can't both query and manage the fan */
2913                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2914                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2915                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2916                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2917                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2918                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2919                         return 0;
2920
2921                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2922                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2923                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2924                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2925                         return 0;
2926         }
2927
2928         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2929              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2930             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
2931              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
2932                 return 0;
2933
2934         /* only APUs have vddnb */
2935         if (!(adev->flags & AMD_IS_APU) &&
2936             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2937              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2938                 return 0;
2939
2940         /* no mclk on APUs */
2941         if ((adev->flags & AMD_IS_APU) &&
2942             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2943              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2944                 return 0;
2945
2946         /* only SOC15 dGPUs support hotspot and mem temperatures */
2947         if (((adev->flags & AMD_IS_APU) ||
2948              adev->asic_type < CHIP_VEGA10) &&
2949             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2950              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2951              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2952              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2953              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2954              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2955              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2956              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2957              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2958              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2959              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2960                 return 0;
2961
2962         return effective_mode;
2963 }
2964
2965 static const struct attribute_group hwmon_attrgroup = {
2966         .attrs = hwmon_attributes,
2967         .is_visible = hwmon_attributes_visible,
2968 };
2969
2970 static const struct attribute_group *hwmon_groups[] = {
2971         &hwmon_attrgroup,
2972         NULL
2973 };
2974
2975 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2976 {
2977         struct amdgpu_device *adev =
2978                 container_of(work, struct amdgpu_device,
2979                              pm.dpm.thermal.work);
2980         /* switch to the thermal state */
2981         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2982         int temp, size = sizeof(temp);
2983
2984         if (!adev->pm.dpm_enabled)
2985                 return;
2986
2987         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2988                                     (void *)&temp, &size)) {
2989                 if (temp < adev->pm.dpm.thermal.min_temp)
2990                         /* switch back the user state */
2991                         dpm_state = adev->pm.dpm.user_state;
2992         } else {
2993                 if (adev->pm.dpm.thermal.high_to_low)
2994                         /* switch back the user state */
2995                         dpm_state = adev->pm.dpm.user_state;
2996         }
2997         mutex_lock(&adev->pm.mutex);
2998         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2999                 adev->pm.dpm.thermal_active = true;
3000         else
3001                 adev->pm.dpm.thermal_active = false;
3002         adev->pm.dpm.state = dpm_state;
3003         mutex_unlock(&adev->pm.mutex);
3004
3005         amdgpu_pm_compute_clocks(adev);
3006 }
3007
3008 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
3009                                                      enum amd_pm_state_type dpm_state)
3010 {
3011         int i;
3012         struct amdgpu_ps *ps;
3013         u32 ui_class;
3014         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
3015                 true : false;
3016
3017         /* check if the vblank period is too short to adjust the mclk */
3018         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
3019                 if (amdgpu_dpm_vblank_too_short(adev))
3020                         single_display = false;
3021         }
3022
3023         /* certain older asics have a separare 3D performance state,
3024          * so try that first if the user selected performance
3025          */
3026         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
3027                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
3028         /* balanced states don't exist at the moment */
3029         if (dpm_state == POWER_STATE_TYPE_BALANCED)
3030                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3031
3032 restart_search:
3033         /* Pick the best power state based on current conditions */
3034         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
3035                 ps = &adev->pm.dpm.ps[i];
3036                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
3037                 switch (dpm_state) {
3038                 /* user states */
3039                 case POWER_STATE_TYPE_BATTERY:
3040                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
3041                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3042                                         if (single_display)
3043                                                 return ps;
3044                                 } else
3045                                         return ps;
3046                         }
3047                         break;
3048                 case POWER_STATE_TYPE_BALANCED:
3049                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
3050                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3051                                         if (single_display)
3052                                                 return ps;
3053                                 } else
3054                                         return ps;
3055                         }
3056                         break;
3057                 case POWER_STATE_TYPE_PERFORMANCE:
3058                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3059                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3060                                         if (single_display)
3061                                                 return ps;
3062                                 } else
3063                                         return ps;
3064                         }
3065                         break;
3066                 /* internal states */
3067                 case POWER_STATE_TYPE_INTERNAL_UVD:
3068                         if (adev->pm.dpm.uvd_ps)
3069                                 return adev->pm.dpm.uvd_ps;
3070                         else
3071                                 break;
3072                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3073                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3074                                 return ps;
3075                         break;
3076                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3077                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3078                                 return ps;
3079                         break;
3080                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3081                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3082                                 return ps;
3083                         break;
3084                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3085                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3086                                 return ps;
3087                         break;
3088                 case POWER_STATE_TYPE_INTERNAL_BOOT:
3089                         return adev->pm.dpm.boot_ps;
3090                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
3091                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
3092                                 return ps;
3093                         break;
3094                 case POWER_STATE_TYPE_INTERNAL_ACPI:
3095                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
3096                                 return ps;
3097                         break;
3098                 case POWER_STATE_TYPE_INTERNAL_ULV:
3099                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
3100                                 return ps;
3101                         break;
3102                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
3103                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
3104                                 return ps;
3105                         break;
3106                 default:
3107                         break;
3108                 }
3109         }
3110         /* use a fallback state if we didn't match */
3111         switch (dpm_state) {
3112         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3113                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
3114                 goto restart_search;
3115         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3116         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3117         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3118                 if (adev->pm.dpm.uvd_ps) {
3119                         return adev->pm.dpm.uvd_ps;
3120                 } else {
3121                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3122                         goto restart_search;
3123                 }
3124         case POWER_STATE_TYPE_INTERNAL_THERMAL:
3125                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
3126                 goto restart_search;
3127         case POWER_STATE_TYPE_INTERNAL_ACPI:
3128                 dpm_state = POWER_STATE_TYPE_BATTERY;
3129                 goto restart_search;
3130         case POWER_STATE_TYPE_BATTERY:
3131         case POWER_STATE_TYPE_BALANCED:
3132         case POWER_STATE_TYPE_INTERNAL_3DPERF:
3133                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3134                 goto restart_search;
3135         default:
3136                 break;
3137         }
3138
3139         return NULL;
3140 }
3141
3142 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
3143 {
3144         struct amdgpu_ps *ps;
3145         enum amd_pm_state_type dpm_state;
3146         int ret;
3147         bool equal = false;
3148
3149         /* if dpm init failed */
3150         if (!adev->pm.dpm_enabled)
3151                 return;
3152
3153         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
3154                 /* add other state override checks here */
3155                 if ((!adev->pm.dpm.thermal_active) &&
3156                     (!adev->pm.dpm.uvd_active))
3157                         adev->pm.dpm.state = adev->pm.dpm.user_state;
3158         }
3159         dpm_state = adev->pm.dpm.state;
3160
3161         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
3162         if (ps)
3163                 adev->pm.dpm.requested_ps = ps;
3164         else
3165                 return;
3166
3167         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
3168                 printk("switching from power state:\n");
3169                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
3170                 printk("switching to power state:\n");
3171                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
3172         }
3173
3174         /* update whether vce is active */
3175         ps->vce_active = adev->pm.dpm.vce_active;
3176         if (adev->powerplay.pp_funcs->display_configuration_changed)
3177                 amdgpu_dpm_display_configuration_changed(adev);
3178
3179         ret = amdgpu_dpm_pre_set_power_state(adev);
3180         if (ret)
3181                 return;
3182
3183         if (adev->powerplay.pp_funcs->check_state_equal) {
3184                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
3185                         equal = false;
3186         }
3187
3188         if (equal)
3189                 return;
3190
3191         amdgpu_dpm_set_power_state(adev);
3192         amdgpu_dpm_post_set_power_state(adev);
3193
3194         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
3195         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
3196
3197         if (adev->powerplay.pp_funcs->force_performance_level) {
3198                 if (adev->pm.dpm.thermal_active) {
3199                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
3200                         /* force low perf level for thermal */
3201                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
3202                         /* save the user's level */
3203                         adev->pm.dpm.forced_level = level;
3204                 } else {
3205                         /* otherwise, user selected level */
3206                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
3207                 }
3208         }
3209 }
3210
3211 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
3212 {
3213         int ret = 0;
3214
3215         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
3216         if (ret)
3217                 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
3218                           enable ? "enable" : "disable", ret);
3219
3220         /* enable/disable Low Memory PState for UVD (4k videos) */
3221         if (adev->asic_type == CHIP_STONEY &&
3222                 adev->uvd.decode_image_width >= WIDTH_4K) {
3223                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3224
3225                 if (hwmgr && hwmgr->hwmgr_func &&
3226                     hwmgr->hwmgr_func->update_nbdpm_pstate)
3227                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
3228                                                                !enable,
3229                                                                true);
3230         }
3231 }
3232
3233 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
3234 {
3235         int ret = 0;
3236
3237         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
3238         if (ret)
3239                 DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
3240                           enable ? "enable" : "disable", ret);
3241 }
3242
3243 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
3244 {
3245         int i;
3246
3247         if (adev->powerplay.pp_funcs->print_power_state == NULL)
3248                 return;
3249
3250         for (i = 0; i < adev->pm.dpm.num_ps; i++)
3251                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
3252
3253 }
3254
3255 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
3256 {
3257         int ret = 0;
3258
3259         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
3260         if (ret)
3261                 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
3262                           enable ? "enable" : "disable", ret);
3263 }
3264
3265 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
3266 {
3267         int r;
3268
3269         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
3270                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
3271                 if (r) {
3272                         pr_err("smu firmware loading failed\n");
3273                         return r;
3274                 }
3275                 *smu_version = adev->pm.fw_version;
3276         }
3277         return 0;
3278 }
3279
3280 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3281 {
3282         int ret;
3283         uint32_t mask = 0;
3284
3285         if (adev->pm.sysfs_initialized)
3286                 return 0;
3287
3288         if (adev->pm.dpm_enabled == 0)
3289                 return 0;
3290
3291         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3292
3293         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3294                                                                    DRIVER_NAME, adev,
3295                                                                    hwmon_groups);
3296         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3297                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3298                 dev_err(adev->dev,
3299                         "Unable to register hwmon device: %d\n", ret);
3300                 return ret;
3301         }
3302
3303         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3304         case SRIOV_VF_MODE_ONE_VF:
3305                 mask = ATTR_FLAG_ONEVF;
3306                 break;
3307         case SRIOV_VF_MODE_MULTI_VF:
3308                 mask = 0;
3309                 break;
3310         case SRIOV_VF_MODE_BARE_METAL:
3311         default:
3312                 mask = ATTR_FLAG_MASK_ALL;
3313                 break;
3314         }
3315
3316         ret = amdgpu_device_attr_create_groups(adev,
3317                                                amdgpu_device_attrs,
3318                                                ARRAY_SIZE(amdgpu_device_attrs),
3319                                                mask,
3320                                                &adev->pm.pm_attr_list);
3321         if (ret)
3322                 return ret;
3323
3324         adev->pm.sysfs_initialized = true;
3325
3326         return 0;
3327 }
3328
3329 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3330 {
3331         if (adev->pm.dpm_enabled == 0)
3332                 return;
3333
3334         if (adev->pm.int_hwmon_dev)
3335                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3336
3337         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3338 }
3339
3340 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
3341 {
3342         int i = 0;
3343
3344         if (!adev->pm.dpm_enabled)
3345                 return;
3346
3347         if (adev->mode_info.num_crtc)
3348                 amdgpu_display_bandwidth_update(adev);
3349
3350         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3351                 struct amdgpu_ring *ring = adev->rings[i];
3352                 if (ring && ring->sched.ready)
3353                         amdgpu_fence_wait_empty(ring);
3354         }
3355
3356         if (is_support_sw_smu(adev)) {
3357                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3358                 smu_handle_task(&adev->smu,
3359                                 smu_dpm->dpm_level,
3360                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
3361                                 true);
3362         } else {
3363                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3364                         if (!amdgpu_device_has_dc_support(adev)) {
3365                                 mutex_lock(&adev->pm.mutex);
3366                                 amdgpu_dpm_get_active_displays(adev);
3367                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3368                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3369                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3370                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3371                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3372                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3373                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3374                                         adev->powerplay.pp_funcs->display_configuration_change(
3375                                                                         adev->powerplay.pp_handle,
3376                                                                         &adev->pm.pm_display_cfg);
3377                                 mutex_unlock(&adev->pm.mutex);
3378                         }
3379                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3380                 } else {
3381                         mutex_lock(&adev->pm.mutex);
3382                         amdgpu_dpm_get_active_displays(adev);
3383                         amdgpu_dpm_change_power_state_locked(adev);
3384                         mutex_unlock(&adev->pm.mutex);
3385                 }
3386         }
3387 }
3388
3389 /*
3390  * Debugfs info
3391  */
3392 #if defined(CONFIG_DEBUG_FS)
3393
3394 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3395 {
3396         uint32_t value;
3397         uint64_t value64;
3398         uint32_t query = 0;
3399         int size;
3400
3401         /* GPU Clocks */
3402         size = sizeof(value);
3403         seq_printf(m, "GFX Clocks and Power:\n");
3404         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3405                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3406         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3407                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3408         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3409                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3410         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3411                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3412         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3413                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3414         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3415                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3416         size = sizeof(uint32_t);
3417         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3418                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3419         size = sizeof(value);
3420         seq_printf(m, "\n");
3421
3422         /* GPU Temp */
3423         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3424                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3425
3426         /* GPU Load */
3427         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3428                 seq_printf(m, "GPU Load: %u %%\n", value);
3429         /* MEM Load */
3430         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3431                 seq_printf(m, "MEM Load: %u %%\n", value);
3432
3433         seq_printf(m, "\n");
3434
3435         /* SMC feature mask */
3436         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3437                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3438
3439         if (adev->asic_type > CHIP_VEGA20) {
3440                 /* VCN clocks */
3441                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3442                         if (!value) {
3443                                 seq_printf(m, "VCN: Disabled\n");
3444                         } else {
3445                                 seq_printf(m, "VCN: Enabled\n");
3446                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3447                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3448                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3449                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3450                         }
3451                 }
3452                 seq_printf(m, "\n");
3453         } else {
3454                 /* UVD clocks */
3455                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3456                         if (!value) {
3457                                 seq_printf(m, "UVD: Disabled\n");
3458                         } else {
3459                                 seq_printf(m, "UVD: Enabled\n");
3460                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3461                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3462                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3463                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3464                         }
3465                 }
3466                 seq_printf(m, "\n");
3467
3468                 /* VCE clocks */
3469                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3470                         if (!value) {
3471                                 seq_printf(m, "VCE: Disabled\n");
3472                         } else {
3473                                 seq_printf(m, "VCE: Enabled\n");
3474                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3475                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3476                         }
3477                 }
3478         }
3479
3480         return 0;
3481 }
3482
3483 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3484 {
3485         int i;
3486
3487         for (i = 0; clocks[i].flag; i++)
3488                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3489                            (flags & clocks[i].flag) ? "On" : "Off");
3490 }
3491
3492 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3493 {
3494         struct drm_info_node *node = (struct drm_info_node *) m->private;
3495         struct drm_device *dev = node->minor->dev;
3496         struct amdgpu_device *adev = dev->dev_private;
3497         u32 flags = 0;
3498         int r;
3499
3500         r = pm_runtime_get_sync(dev->dev);
3501         if (r < 0)
3502                 return r;
3503
3504         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3505         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3506         amdgpu_parse_cg_state(m, flags);
3507         seq_printf(m, "\n");
3508
3509         if (!adev->pm.dpm_enabled) {
3510                 seq_printf(m, "dpm not enabled\n");
3511                 pm_runtime_mark_last_busy(dev->dev);
3512                 pm_runtime_put_autosuspend(dev->dev);
3513                 return 0;
3514         }
3515
3516         if (!is_support_sw_smu(adev) &&
3517             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3518                 mutex_lock(&adev->pm.mutex);
3519                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3520                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3521                 else
3522                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3523                 mutex_unlock(&adev->pm.mutex);
3524                 r = 0;
3525         } else {
3526                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3527         }
3528
3529         pm_runtime_mark_last_busy(dev->dev);
3530         pm_runtime_put_autosuspend(dev->dev);
3531
3532         return r;
3533 }
3534
3535 static const struct drm_info_list amdgpu_pm_info_list[] = {
3536         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3537 };
3538 #endif
3539
3540 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3541 {
3542 #if defined(CONFIG_DEBUG_FS)
3543         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3544 #else
3545         return 0;
3546 #endif
3547 }