drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include <linux/pm_runtime.h>
  41 #include "hwmgr.h"
  42 #define WIDTH_4K 3840
  43
  44 static const struct cg_flag_name clocks[] = {
  45         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  55         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  58         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  61         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  64         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  67         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  69
  70         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  72         {0, NULL},
  73 };
  74
  75 static const struct hwmon_temp_label {
  76         enum PP_HWMON_TEMP channel;
  77         const char *label;
  78 } temp_label[] = {
  79         {PP_TEMP_EDGE, "edge"},
  80         {PP_TEMP_JUNCTION, "junction"},
  81         {PP_TEMP_MEM, "mem"},
  82 };
  83
  84 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  85 {
  86         if (adev->pm.dpm_enabled) {
  87                 mutex_lock(&adev->pm.mutex);
  88                 if (power_supply_is_system_supplied() > 0)
  89                         adev->pm.ac_power = true;
  90                 else
  91                         adev->pm.ac_power = false;
  92                 if (adev->powerplay.pp_funcs &&
  93                     adev->powerplay.pp_funcs->enable_bapm)
  94                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  95                 mutex_unlock(&adev->pm.mutex);
  96
  97                 if (is_support_sw_smu(adev))
  98                         smu_set_ac_dc(&adev->smu);
  99         }
 100 }
 101
 102 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 103                            void *data, uint32_t *size)
 104 {
 105         int ret = 0;
 106
 107         if (!data || !size)
 108                 return -EINVAL;
 109
 110         if (is_support_sw_smu(adev))
 111                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 112         else {
 113                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 114                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 115                                                                     sensor, data, size);
 116                 else
 117                         ret = -EINVAL;
 118         }
 119
 120         return ret;
 121 }
 122
 123 /**
 124  * DOC: power_dpm_state
 125  *
 126  * The power_dpm_state file is a legacy interface and is only provided for
 127  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 128  * certain power related parameters.  The file power_dpm_state is used for this.
 129  * It accepts the following arguments:
 130  *
 131  * - battery
 132  *
 133  * - balanced
 134  *
 135  * - performance
 136  *
 137  * battery
 138  *
 139  * On older GPUs, the vbios provided a special power state for battery
 140  * operation.  Selecting battery switched to this state.  This is no
 141  * longer provided on newer GPUs so the option does nothing in that case.
 142  *
 143  * balanced
 144  *
 145  * On older GPUs, the vbios provided a special power state for balanced
 146  * operation.  Selecting balanced switched to this state.  This is no
 147  * longer provided on newer GPUs so the option does nothing in that case.
 148  *
 149  * performance
 150  *
 151  * On older GPUs, the vbios provided a special power state for performance
 152  * operation.  Selecting performance switched to this state.  This is no
 153  * longer provided on newer GPUs so the option does nothing in that case.
 154  *
 155  */
 156
 157 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 158                                     struct device_attribute *attr,
 159                                     char *buf)
 160 {
 161         struct drm_device *ddev = dev_get_drvdata(dev);
 162         struct amdgpu_device *adev = ddev->dev_private;
 163         enum amd_pm_state_type pm;
 164         int ret;
 165
 166         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 167                 return 0;
 168
 169         ret = pm_runtime_get_sync(ddev->dev);
 170         if (ret < 0)
 171                 return ret;
 172
 173         if (is_support_sw_smu(adev)) {
 174                 if (adev->smu.ppt_funcs->get_current_power_state)
 175                         pm = smu_get_current_power_state(&adev->smu);
 176                 else
 177                         pm = adev->pm.dpm.user_state;
 178         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 179                 pm = amdgpu_dpm_get_current_power_state(adev);
 180         } else {
 181                 pm = adev->pm.dpm.user_state;
 182         }
 183
 184         pm_runtime_mark_last_busy(ddev->dev);
 185         pm_runtime_put_autosuspend(ddev->dev);
 186
 187         return snprintf(buf, PAGE_SIZE, "%s\n",
 188                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 189                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 190 }
 191
 192 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 193                                     struct device_attribute *attr,
 194                                     const char *buf,
 195                                     size_t count)
 196 {
 197         struct drm_device *ddev = dev_get_drvdata(dev);
 198         struct amdgpu_device *adev = ddev->dev_private;
 199         enum amd_pm_state_type  state;
 200         int ret;
 201
 202         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 203                 return -EINVAL;
 204
 205         if (strncmp("battery", buf, strlen("battery")) == 0)
 206                 state = POWER_STATE_TYPE_BATTERY;
 207         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 208                 state = POWER_STATE_TYPE_BALANCED;
 209         else if (strncmp("performance", buf, strlen("performance")) == 0)
 210                 state = POWER_STATE_TYPE_PERFORMANCE;
 211         else
 212                 return -EINVAL;
 213
 214         ret = pm_runtime_get_sync(ddev->dev);
 215         if (ret < 0)
 216                 return ret;
 217
 218         if (is_support_sw_smu(adev)) {
 219                 mutex_lock(&adev->pm.mutex);
 220                 adev->pm.dpm.user_state = state;
 221                 mutex_unlock(&adev->pm.mutex);
 222         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 223                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 224         } else {
 225                 mutex_lock(&adev->pm.mutex);
 226                 adev->pm.dpm.user_state = state;
 227                 mutex_unlock(&adev->pm.mutex);
 228
 229                 amdgpu_pm_compute_clocks(adev);
 230         }
 231         pm_runtime_mark_last_busy(ddev->dev);
 232         pm_runtime_put_autosuspend(ddev->dev);
 233
 234         return count;
 235 }
 236
 237
 238 /**
 239  * DOC: power_dpm_force_performance_level
 240  *
 241  * The amdgpu driver provides a sysfs API for adjusting certain power
 242  * related parameters.  The file power_dpm_force_performance_level is
 243  * used for this.  It accepts the following arguments:
 244  *
 245  * - auto
 246  *
 247  * - low
 248  *
 249  * - high
 250  *
 251  * - manual
 252  *
 253  * - profile_standard
 254  *
 255  * - profile_min_sclk
 256  *
 257  * - profile_min_mclk
 258  *
 259  * - profile_peak
 260  *
 261  * auto
 262  *
 263  * When auto is selected, the driver will attempt to dynamically select
 264  * the optimal power profile for current conditions in the driver.
 265  *
 266  * low
 267  *
 268  * When low is selected, the clocks are forced to the lowest power state.
 269  *
 270  * high
 271  *
 272  * When high is selected, the clocks are forced to the highest power state.
 273  *
 274  * manual
 275  *
 276  * When manual is selected, the user can manually adjust which power states
 277  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 278  * and pp_dpm_pcie files and adjust the power state transition heuristics
 279  * via the pp_power_profile_mode sysfs file.
 280  *
 281  * profile_standard
 282  * profile_min_sclk
 283  * profile_min_mclk
 284  * profile_peak
 285  *
 286  * When the profiling modes are selected, clock and power gating are
 287  * disabled and the clocks are set for different profiling cases. This
 288  * mode is recommended for profiling specific work loads where you do
 289  * not want clock or power gating for clock fluctuation to interfere
 290  * with your results. profile_standard sets the clocks to a fixed clock
 291  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 292  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 293  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 294  *
 295  */
 296
 297 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 298                                                 struct device_attribute *attr,
 299                                                                 char *buf)
 300 {
 301         struct drm_device *ddev = dev_get_drvdata(dev);
 302         struct amdgpu_device *adev = ddev->dev_private;
 303         enum amd_dpm_forced_level level = 0xff;
 304         int ret;
 305
 306         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 307                 return 0;
 308
 309         ret = pm_runtime_get_sync(ddev->dev);
 310         if (ret < 0)
 311                 return ret;
 312
 313         if (is_support_sw_smu(adev))
 314                 level = smu_get_performance_level(&adev->smu);
 315         else if (adev->powerplay.pp_funcs->get_performance_level)
 316                 level = amdgpu_dpm_get_performance_level(adev);
 317         else
 318                 level = adev->pm.dpm.forced_level;
 319
 320         pm_runtime_mark_last_busy(ddev->dev);
 321         pm_runtime_put_autosuspend(ddev->dev);
 322
 323         return snprintf(buf, PAGE_SIZE, "%s\n",
 324                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 325                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 326                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 327                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 328                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 329                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 330                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 331                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 332                         "unknown");
 333 }
 334
 335 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 336                                                        struct device_attribute *attr,
 337                                                        const char *buf,
 338                                                        size_t count)
 339 {
 340         struct drm_device *ddev = dev_get_drvdata(dev);
 341         struct amdgpu_device *adev = ddev->dev_private;
 342         enum amd_dpm_forced_level level;
 343         enum amd_dpm_forced_level current_level = 0xff;
 344         int ret = 0;
 345
 346         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 347                 return -EINVAL;
 348
 349         if (strncmp("low", buf, strlen("low")) == 0) {
 350                 level = AMD_DPM_FORCED_LEVEL_LOW;
 351         } else if (strncmp("high", buf, strlen("high")) == 0) {
 352                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 353         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 354                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 355         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 356                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 357         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 358                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 359         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 360                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 361         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 362                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 363         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 364                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 365         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 366                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 367         }  else {
 368                 return -EINVAL;
 369         }
 370
 371         ret = pm_runtime_get_sync(ddev->dev);
 372         if (ret < 0)
 373                 return ret;
 374
 375         if (is_support_sw_smu(adev))
 376                 current_level = smu_get_performance_level(&adev->smu);
 377         else if (adev->powerplay.pp_funcs->get_performance_level)
 378                 current_level = amdgpu_dpm_get_performance_level(adev);
 379
 380         if (current_level == level) {
 381                 pm_runtime_mark_last_busy(ddev->dev);
 382                 pm_runtime_put_autosuspend(ddev->dev);
 383                 return count;
 384         }
 385
 386         /* profile_exit setting is valid only when current mode is in profile mode */
 387         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 388             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 389             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 390             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 391             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 392                 pr_err("Currently not in any profile mode!\n");
 393                 pm_runtime_mark_last_busy(ddev->dev);
 394                 pm_runtime_put_autosuspend(ddev->dev);
 395                 return -EINVAL;
 396         }
 397
 398         if (is_support_sw_smu(adev)) {
 399                 ret = smu_force_performance_level(&adev->smu, level);
 400                 if (ret) {
 401                         pm_runtime_mark_last_busy(ddev->dev);
 402                         pm_runtime_put_autosuspend(ddev->dev);
 403                         return -EINVAL;
 404                 }
 405         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 406                 mutex_lock(&adev->pm.mutex);
 407                 if (adev->pm.dpm.thermal_active) {
 408                         mutex_unlock(&adev->pm.mutex);
 409                         pm_runtime_mark_last_busy(ddev->dev);
 410                         pm_runtime_put_autosuspend(ddev->dev);
 411                         return -EINVAL;
 412                 }
 413                 ret = amdgpu_dpm_force_performance_level(adev, level);
 414                 if (ret) {
 415                         mutex_unlock(&adev->pm.mutex);
 416                         pm_runtime_mark_last_busy(ddev->dev);
 417                         pm_runtime_put_autosuspend(ddev->dev);
 418                         return -EINVAL;
 419                 } else {
 420                         adev->pm.dpm.forced_level = level;
 421                 }
 422                 mutex_unlock(&adev->pm.mutex);
 423         }
 424         pm_runtime_mark_last_busy(ddev->dev);
 425         pm_runtime_put_autosuspend(ddev->dev);
 426
 427         return count;
 428 }
 429
 430 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 431                 struct device_attribute *attr,
 432                 char *buf)
 433 {
 434         struct drm_device *ddev = dev_get_drvdata(dev);
 435         struct amdgpu_device *adev = ddev->dev_private;
 436         struct pp_states_info data;
 437         int i, buf_len, ret;
 438
 439         ret = pm_runtime_get_sync(ddev->dev);
 440         if (ret < 0)
 441                 return ret;
 442
 443         if (is_support_sw_smu(adev)) {
 444                 ret = smu_get_power_num_states(&adev->smu, &data);
 445                 if (ret)
 446                         return ret;
 447         } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
 448                 amdgpu_dpm_get_pp_num_states(adev, &data);
 449         } else {
 450                 memset(&data, 0, sizeof(data));
 451         }
 452
 453         pm_runtime_mark_last_busy(ddev->dev);
 454         pm_runtime_put_autosuspend(ddev->dev);
 455
 456         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 457         for (i = 0; i < data.nums; i++)
 458                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 459                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 460                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 461                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 462                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 463
 464         return buf_len;
 465 }
 466
 467 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 468                 struct device_attribute *attr,
 469                 char *buf)
 470 {
 471         struct drm_device *ddev = dev_get_drvdata(dev);
 472         struct amdgpu_device *adev = ddev->dev_private;
 473         struct pp_states_info data;
 474         struct smu_context *smu = &adev->smu;
 475         enum amd_pm_state_type pm = 0;
 476         int i = 0, ret = 0;
 477
 478         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 479                 return 0;
 480
 481         ret = pm_runtime_get_sync(ddev->dev);
 482         if (ret < 0)
 483                 return ret;
 484
 485         if (is_support_sw_smu(adev)) {
 486                 pm = smu_get_current_power_state(smu);
 487                 ret = smu_get_power_num_states(smu, &data);
 488                 if (ret)
 489                         return ret;
 490         } else if (adev->powerplay.pp_funcs->get_current_power_state
 491                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 492                 pm = amdgpu_dpm_get_current_power_state(adev);
 493                 amdgpu_dpm_get_pp_num_states(adev, &data);
 494         }
 495
 496         pm_runtime_mark_last_busy(ddev->dev);
 497         pm_runtime_put_autosuspend(ddev->dev);
 498
 499         for (i = 0; i < data.nums; i++) {
 500                 if (pm == data.states[i])
 501                         break;
 502         }
 503
 504         if (i == data.nums)
 505                 i = -EINVAL;
 506
 507         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 508 }
 509
 510 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 511                 struct device_attribute *attr,
 512                 char *buf)
 513 {
 514         struct drm_device *ddev = dev_get_drvdata(dev);
 515         struct amdgpu_device *adev = ddev->dev_private;
 516
 517         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 518                 return 0;
 519
 520         if (adev->pp_force_state_enabled)
 521                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 522         else
 523                 return snprintf(buf, PAGE_SIZE, "\n");
 524 }
 525
 526 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 527                 struct device_attribute *attr,
 528                 const char *buf,
 529                 size_t count)
 530 {
 531         struct drm_device *ddev = dev_get_drvdata(dev);
 532         struct amdgpu_device *adev = ddev->dev_private;
 533         enum amd_pm_state_type state = 0;
 534         unsigned long idx;
 535         int ret;
 536
 537         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 538                 return -EINVAL;
 539
 540         if (strlen(buf) == 1)
 541                 adev->pp_force_state_enabled = false;
 542         else if (is_support_sw_smu(adev))
 543                 adev->pp_force_state_enabled = false;
 544         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 545                         adev->powerplay.pp_funcs->get_pp_num_states) {
 546                 struct pp_states_info data;
 547
 548                 ret = kstrtoul(buf, 0, &idx);
 549                 if (ret || idx >= ARRAY_SIZE(data.states))
 550                         return -EINVAL;
 551
 552                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 553
 554                 amdgpu_dpm_get_pp_num_states(adev, &data);
 555                 state = data.states[idx];
 556
 557                 ret = pm_runtime_get_sync(ddev->dev);
 558                 if (ret < 0)
 559                         return ret;
 560
 561                 /* only set user selected power states */
 562                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 563                     state != POWER_STATE_TYPE_DEFAULT) {
 564                         amdgpu_dpm_dispatch_task(adev,
 565                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 566                         adev->pp_force_state_enabled = true;
 567                 }
 568                 pm_runtime_mark_last_busy(ddev->dev);
 569                 pm_runtime_put_autosuspend(ddev->dev);
 570         }
 571
 572         return count;
 573 }
 574
 575 /**
 576  * DOC: pp_table
 577  *
 578  * The amdgpu driver provides a sysfs API for uploading new powerplay
 579  * tables.  The file pp_table is used for this.  Reading the file
 580  * will dump the current power play table.  Writing to the file
 581  * will attempt to upload a new powerplay table and re-initialize
 582  * powerplay using that new table.
 583  *
 584  */
 585
 586 static ssize_t amdgpu_get_pp_table(struct device *dev,
 587                 struct device_attribute *attr,
 588                 char *buf)
 589 {
 590         struct drm_device *ddev = dev_get_drvdata(dev);
 591         struct amdgpu_device *adev = ddev->dev_private;
 592         char *table = NULL;
 593         int size, ret;
 594
 595         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 596                 return 0;
 597
 598         ret = pm_runtime_get_sync(ddev->dev);
 599         if (ret < 0)
 600                 return ret;
 601
 602         if (is_support_sw_smu(adev)) {
 603                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 604                 pm_runtime_mark_last_busy(ddev->dev);
 605                 pm_runtime_put_autosuspend(ddev->dev);
 606                 if (size < 0)
 607                         return size;
 608         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 609                 size = amdgpu_dpm_get_pp_table(adev, &table);
 610                 pm_runtime_mark_last_busy(ddev->dev);
 611                 pm_runtime_put_autosuspend(ddev->dev);
 612                 if (size < 0)
 613                         return size;
 614         } else {
 615                 pm_runtime_mark_last_busy(ddev->dev);
 616                 pm_runtime_put_autosuspend(ddev->dev);
 617                 return 0;
 618         }
 619
 620         if (size >= PAGE_SIZE)
 621                 size = PAGE_SIZE - 1;
 622
 623         memcpy(buf, table, size);
 624
 625         return size;
 626 }
 627
 628 static ssize_t amdgpu_set_pp_table(struct device *dev,
 629                 struct device_attribute *attr,
 630                 const char *buf,
 631                 size_t count)
 632 {
 633         struct drm_device *ddev = dev_get_drvdata(dev);
 634         struct amdgpu_device *adev = ddev->dev_private;
 635         int ret = 0;
 636
 637         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 638                 return -EINVAL;
 639
 640         ret = pm_runtime_get_sync(ddev->dev);
 641         if (ret < 0)
 642                 return ret;
 643
 644         if (is_support_sw_smu(adev)) {
 645                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 646                 if (ret) {
 647                         pm_runtime_mark_last_busy(ddev->dev);
 648                         pm_runtime_put_autosuspend(ddev->dev);
 649                         return ret;
 650                 }
 651         } else if (adev->powerplay.pp_funcs->set_pp_table)
 652                 amdgpu_dpm_set_pp_table(adev, buf, count);
 653
 654         pm_runtime_mark_last_busy(ddev->dev);
 655         pm_runtime_put_autosuspend(ddev->dev);
 656
 657         return count;
 658 }
 659
 660 /**
 661  * DOC: pp_od_clk_voltage
 662  *
 663  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 664  * in each power level within a power state.  The pp_od_clk_voltage is used for
 665  * this.
 666  *
 667  * < For Vega10 and previous ASICs >
 668  *
 669  * Reading the file will display:
 670  *
 671  * - a list of engine clock levels and voltages labeled OD_SCLK
 672  *
 673  * - a list of memory clock levels and voltages labeled OD_MCLK
 674  *
 675  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 676  *
 677  * To manually adjust these settings, first select manual using
 678  * power_dpm_force_performance_level. Enter a new value for each
 679  * level by writing a string that contains "s/m level clock voltage" to
 680  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 681  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 682  * 810 mV.  When you have edited all of the states as needed, write
 683  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 684  * default power levels, write "r" (reset) to the file to reset them.
 685  *
 686  *
 687  * < For Vega20 >
 688  *
 689  * Reading the file will display:
 690  *
 691  * - minimum and maximum engine clock labeled OD_SCLK
 692  *
 693  * - maximum memory clock labeled OD_MCLK
 694  *
 695  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 696  *   They can be used to calibrate the sclk voltage curve.
 697  *
 698  * - a list of valid ranges for sclk, mclk, and voltage curve points
 699  *   labeled OD_RANGE
 700  *
 701  * To manually adjust these settings:
 702  *
 703  * - First select manual using power_dpm_force_performance_level
 704  *
 705  * - For clock frequency setting, enter a new value by writing a
 706  *   string that contains "s/m index clock" to the file. The index
 707  *   should be 0 if to set minimum clock. And 1 if to set maximum
 708  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 709  *   "m 1 800" will update maximum mclk to be 800Mhz.
 710  *
 711  *   For sclk voltage curve, enter the new values by writing a
 712  *   string that contains "vc point clock voltage" to the file. The
 713  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 714  *   update point1 with clock set as 300Mhz and voltage as
 715  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 716  *   as 1000Mhz and voltage 1000mV.
 717  *
 718  * - When you have edited all of the states as needed, write "c" (commit)
 719  *   to the file to commit your changes
 720  *
 721  * - If you want to reset to the default power levels, write "r" (reset)
 722  *   to the file to reset them
 723  *
 724  */
 725
 726 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 727                 struct device_attribute *attr,
 728                 const char *buf,
 729                 size_t count)
 730 {
 731         struct drm_device *ddev = dev_get_drvdata(dev);
 732         struct amdgpu_device *adev = ddev->dev_private;
 733         int ret;
 734         uint32_t parameter_size = 0;
 735         long parameter[64];
 736         char buf_cpy[128];
 737         char *tmp_str;
 738         char *sub_str;
 739         const char delimiter[3] = {' ', '\n', '\0'};
 740         uint32_t type;
 741
 742         if (amdgpu_sriov_vf(adev))
 743                 return -EINVAL;
 744
 745         if (count > 127)
 746                 return -EINVAL;
 747
 748         if (*buf == 's')
 749                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 750         else if (*buf == 'm')
 751                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 752         else if(*buf == 'r')
 753                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 754         else if (*buf == 'c')
 755                 type = PP_OD_COMMIT_DPM_TABLE;
 756         else if (!strncmp(buf, "vc", 2))
 757                 type = PP_OD_EDIT_VDDC_CURVE;
 758         else
 759                 return -EINVAL;
 760
 761         memcpy(buf_cpy, buf, count+1);
 762
 763         tmp_str = buf_cpy;
 764
 765         if (type == PP_OD_EDIT_VDDC_CURVE)
 766                 tmp_str++;
 767         while (isspace(*++tmp_str));
 768
 769         while (tmp_str[0]) {
 770                 sub_str = strsep(&tmp_str, delimiter);
 771                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 772                 if (ret)
 773                         return -EINVAL;
 774                 parameter_size++;
 775
 776                 while (isspace(*tmp_str))
 777                         tmp_str++;
 778         }
 779
 780         ret = pm_runtime_get_sync(ddev->dev);
 781         if (ret < 0)
 782                 return ret;
 783
 784         if (is_support_sw_smu(adev)) {
 785                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 786                                             parameter, parameter_size);
 787
 788                 if (ret) {
 789                         pm_runtime_mark_last_busy(ddev->dev);
 790                         pm_runtime_put_autosuspend(ddev->dev);
 791                         return -EINVAL;
 792                 }
 793         } else {
 794                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 795                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 796                                                 parameter, parameter_size);
 797                         if (ret) {
 798                                 pm_runtime_mark_last_busy(ddev->dev);
 799                                 pm_runtime_put_autosuspend(ddev->dev);
 800                                 return -EINVAL;
 801                         }
 802                 }
 803
 804                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 805                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 806                                 amdgpu_dpm_dispatch_task(adev,
 807                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 808                                                 NULL);
 809                                 pm_runtime_mark_last_busy(ddev->dev);
 810                                 pm_runtime_put_autosuspend(ddev->dev);
 811                                 return count;
 812                         } else {
 813                                 pm_runtime_mark_last_busy(ddev->dev);
 814                                 pm_runtime_put_autosuspend(ddev->dev);
 815                                 return -EINVAL;
 816                         }
 817                 }
 818         }
 819         pm_runtime_mark_last_busy(ddev->dev);
 820         pm_runtime_put_autosuspend(ddev->dev);
 821
 822         return count;
 823 }
 824
 825 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 826                 struct device_attribute *attr,
 827                 char *buf)
 828 {
 829         struct drm_device *ddev = dev_get_drvdata(dev);
 830         struct amdgpu_device *adev = ddev->dev_private;
 831         ssize_t size;
 832         int ret;
 833
 834         if (amdgpu_sriov_vf(adev))
 835                 return 0;
 836
 837         ret = pm_runtime_get_sync(ddev->dev);
 838         if (ret < 0)
 839                 return ret;
 840
 841         if (is_support_sw_smu(adev)) {
 842                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 843                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 844                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 845                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 846         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 847                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 848                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 849                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 850                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 851         } else {
 852                 size = snprintf(buf, PAGE_SIZE, "\n");
 853         }
 854         pm_runtime_mark_last_busy(ddev->dev);
 855         pm_runtime_put_autosuspend(ddev->dev);
 856
 857         return size;
 858 }
 859
 860 /**
 861  * DOC: pp_features
 862  *
 863  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 864  * features to be enabled. The file pp_features is used for this. And
 865  * this is only available for Vega10 and later dGPUs.
 866  *
 867  * Reading back the file will show you the followings:
 868  * - Current ppfeature masks
 869  * - List of the all supported powerplay features with their naming,
 870  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 871  *
 872  * To manually enable or disable a specific feature, just set or clear
 873  * the corresponding bit from original ppfeature masks and input the
 874  * new ppfeature masks.
 875  */
 876 static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
 877                 struct device_attribute *attr,
 878                 const char *buf,
 879                 size_t count)
 880 {
 881         struct drm_device *ddev = dev_get_drvdata(dev);
 882         struct amdgpu_device *adev = ddev->dev_private;
 883         uint64_t featuremask;
 884         int ret;
 885
 886         if (amdgpu_sriov_vf(adev))
 887                 return -EINVAL;
 888
 889         ret = kstrtou64(buf, 0, &featuremask);
 890         if (ret)
 891                 return -EINVAL;
 892
 893         pr_debug("featuremask = 0x%llx\n", featuremask);
 894
 895         ret = pm_runtime_get_sync(ddev->dev);
 896         if (ret < 0)
 897                 return ret;
 898
 899         if (is_support_sw_smu(adev)) {
 900                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 901                 if (ret) {
 902                         pm_runtime_mark_last_busy(ddev->dev);
 903                         pm_runtime_put_autosuspend(ddev->dev);
 904                         return -EINVAL;
 905                 }
 906         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 907                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 908                 if (ret) {
 909                         pm_runtime_mark_last_busy(ddev->dev);
 910                         pm_runtime_put_autosuspend(ddev->dev);
 911                         return -EINVAL;
 912                 }
 913         }
 914         pm_runtime_mark_last_busy(ddev->dev);
 915         pm_runtime_put_autosuspend(ddev->dev);
 916
 917         return count;
 918 }
 919
 920 static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
 921                 struct device_attribute *attr,
 922                 char *buf)
 923 {
 924         struct drm_device *ddev = dev_get_drvdata(dev);
 925         struct amdgpu_device *adev = ddev->dev_private;
 926         ssize_t size;
 927         int ret;
 928
 929         if (amdgpu_sriov_vf(adev))
 930                 return 0;
 931
 932         ret = pm_runtime_get_sync(ddev->dev);
 933         if (ret < 0)
 934                 return ret;
 935
 936         if (is_support_sw_smu(adev))
 937                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
 938         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 939                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 940         else
 941                 size = snprintf(buf, PAGE_SIZE, "\n");
 942
 943         pm_runtime_mark_last_busy(ddev->dev);
 944         pm_runtime_put_autosuspend(ddev->dev);
 945
 946         return size;
 947 }
 948
 949 /**
 950  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 951  *
 952  * The amdgpu driver provides a sysfs API for adjusting what power levels
 953  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 954  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 955  * this.
 956  *
 957  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 958  * Vega10 and later ASICs.
 959  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 960  *
 961  * Reading back the files will show you the available power levels within
 962  * the power state and the clock information for those levels.
 963  *
 964  * To manually adjust these states, first select manual using
 965  * power_dpm_force_performance_level.
 966  * Secondly, enter a new value for each level by inputing a string that
 967  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 968  * E.g.,
 969  *
 970  * .. code-block:: bash
 971  *
 972  *      echo "4 5 6" > pp_dpm_sclk
 973  *
 974  * will enable sclk levels 4, 5, and 6.
 975  *
 976  * NOTE: change to the dcefclk max dpm level is not supported now
 977  */
 978
 979 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 980                 struct device_attribute *attr,
 981                 char *buf)
 982 {
 983         struct drm_device *ddev = dev_get_drvdata(dev);
 984         struct amdgpu_device *adev = ddev->dev_private;
 985         ssize_t size;
 986         int ret;
 987
 988         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 989                 return 0;
 990
 991         ret = pm_runtime_get_sync(ddev->dev);
 992         if (ret < 0)
 993                 return ret;
 994
 995         if (is_support_sw_smu(adev))
 996                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
 997         else if (adev->powerplay.pp_funcs->print_clock_levels)
 998                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 999         else
1000                 size = snprintf(buf, PAGE_SIZE, "\n");
1001
1002         pm_runtime_mark_last_busy(ddev->dev);
1003         pm_runtime_put_autosuspend(ddev->dev);
1004
1005         return size;
1006 }
1007
1008 /*
1009  * Worst case: 32 bits individually specified, in octal at 12 characters
1010  * per line (+1 for \n).
1011  */
1012 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1013
1014 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1015 {
1016         int ret;
1017         long level;
1018         char *sub_str = NULL;
1019         char *tmp;
1020         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1021         const char delimiter[3] = {' ', '\n', '\0'};
1022         size_t bytes;
1023
1024         *mask = 0;
1025
1026         bytes = min(count, sizeof(buf_cpy) - 1);
1027         memcpy(buf_cpy, buf, bytes);
1028         buf_cpy[bytes] = '\0';
1029         tmp = buf_cpy;
1030         while (tmp[0]) {
1031                 sub_str = strsep(&tmp, delimiter);
1032                 if (strlen(sub_str)) {
1033                         ret = kstrtol(sub_str, 0, &level);
1034                         if (ret)
1035                                 return -EINVAL;
1036                         *mask |= 1 << level;
1037                 } else
1038                         break;
1039         }
1040
1041         return 0;
1042 }
1043
1044 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1045                 struct device_attribute *attr,
1046                 const char *buf,
1047                 size_t count)
1048 {
1049         struct drm_device *ddev = dev_get_drvdata(dev);
1050         struct amdgpu_device *adev = ddev->dev_private;
1051         int ret;
1052         uint32_t mask = 0;
1053
1054         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1055                 return -EINVAL;
1056
1057         ret = amdgpu_read_mask(buf, count, &mask);
1058         if (ret)
1059                 return ret;
1060
1061         ret = pm_runtime_get_sync(ddev->dev);
1062         if (ret < 0)
1063                 return ret;
1064
1065         if (is_support_sw_smu(adev))
1066                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
1067         else if (adev->powerplay.pp_funcs->force_clock_level)
1068                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1069
1070         pm_runtime_mark_last_busy(ddev->dev);
1071         pm_runtime_put_autosuspend(ddev->dev);
1072
1073         if (ret)
1074                 return -EINVAL;
1075
1076         return count;
1077 }
1078
1079 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1080                 struct device_attribute *attr,
1081                 char *buf)
1082 {
1083         struct drm_device *ddev = dev_get_drvdata(dev);
1084         struct amdgpu_device *adev = ddev->dev_private;
1085         ssize_t size;
1086         int ret;
1087
1088         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1089                 return 0;
1090
1091         ret = pm_runtime_get_sync(ddev->dev);
1092         if (ret < 0)
1093                 return ret;
1094
1095         if (is_support_sw_smu(adev))
1096                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1097         else if (adev->powerplay.pp_funcs->print_clock_levels)
1098                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1099         else
1100                 size = snprintf(buf, PAGE_SIZE, "\n");
1101
1102         pm_runtime_mark_last_busy(ddev->dev);
1103         pm_runtime_put_autosuspend(ddev->dev);
1104
1105         return size;
1106 }
1107
1108 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1109                 struct device_attribute *attr,
1110                 const char *buf,
1111                 size_t count)
1112 {
1113         struct drm_device *ddev = dev_get_drvdata(dev);
1114         struct amdgpu_device *adev = ddev->dev_private;
1115         uint32_t mask = 0;
1116         int ret;
1117
1118         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1119                         return -EINVAL;
1120
1121         ret = amdgpu_read_mask(buf, count, &mask);
1122         if (ret)
1123                 return ret;
1124
1125         ret = pm_runtime_get_sync(ddev->dev);
1126         if (ret < 0)
1127                 return ret;
1128
1129         if (is_support_sw_smu(adev))
1130                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
1131         else if (adev->powerplay.pp_funcs->force_clock_level)
1132                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1133
1134         pm_runtime_mark_last_busy(ddev->dev);
1135         pm_runtime_put_autosuspend(ddev->dev);
1136
1137         if (ret)
1138                 return -EINVAL;
1139
1140         return count;
1141 }
1142
1143 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1144                 struct device_attribute *attr,
1145                 char *buf)
1146 {
1147         struct drm_device *ddev = dev_get_drvdata(dev);
1148         struct amdgpu_device *adev = ddev->dev_private;
1149         ssize_t size;
1150         int ret;
1151
1152         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1153                 return 0;
1154
1155         ret = pm_runtime_get_sync(ddev->dev);
1156         if (ret < 0)
1157                 return ret;
1158
1159         if (is_support_sw_smu(adev))
1160                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1161         else if (adev->powerplay.pp_funcs->print_clock_levels)
1162                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1163         else
1164                 size = snprintf(buf, PAGE_SIZE, "\n");
1165
1166         pm_runtime_mark_last_busy(ddev->dev);
1167         pm_runtime_put_autosuspend(ddev->dev);
1168
1169         return size;
1170 }
1171
1172 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1173                 struct device_attribute *attr,
1174                 const char *buf,
1175                 size_t count)
1176 {
1177         struct drm_device *ddev = dev_get_drvdata(dev);
1178         struct amdgpu_device *adev = ddev->dev_private;
1179         int ret;
1180         uint32_t mask = 0;
1181
1182         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1183                 return -EINVAL;
1184
1185         ret = amdgpu_read_mask(buf, count, &mask);
1186         if (ret)
1187                 return ret;
1188
1189         ret = pm_runtime_get_sync(ddev->dev);
1190         if (ret < 0)
1191                 return ret;
1192
1193         if (is_support_sw_smu(adev))
1194                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
1195         else if (adev->powerplay.pp_funcs->force_clock_level)
1196                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1197         else
1198                 ret = 0;
1199
1200         pm_runtime_mark_last_busy(ddev->dev);
1201         pm_runtime_put_autosuspend(ddev->dev);
1202
1203         if (ret)
1204                 return -EINVAL;
1205
1206         return count;
1207 }
1208
1209 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1210                 struct device_attribute *attr,
1211                 char *buf)
1212 {
1213         struct drm_device *ddev = dev_get_drvdata(dev);
1214         struct amdgpu_device *adev = ddev->dev_private;
1215         ssize_t size;
1216         int ret;
1217
1218         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1219                 return 0;
1220
1221         ret = pm_runtime_get_sync(ddev->dev);
1222         if (ret < 0)
1223                 return ret;
1224
1225         if (is_support_sw_smu(adev))
1226                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1227         else if (adev->powerplay.pp_funcs->print_clock_levels)
1228                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1229         else
1230                 size = snprintf(buf, PAGE_SIZE, "\n");
1231
1232         pm_runtime_mark_last_busy(ddev->dev);
1233         pm_runtime_put_autosuspend(ddev->dev);
1234
1235         return size;
1236 }
1237
1238 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1239                 struct device_attribute *attr,
1240                 const char *buf,
1241                 size_t count)
1242 {
1243         struct drm_device *ddev = dev_get_drvdata(dev);
1244         struct amdgpu_device *adev = ddev->dev_private;
1245         int ret;
1246         uint32_t mask = 0;
1247
1248         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1249                 return -EINVAL;
1250
1251         ret = amdgpu_read_mask(buf, count, &mask);
1252         if (ret)
1253                 return ret;
1254
1255         ret = pm_runtime_get_sync(ddev->dev);
1256         if (ret < 0)
1257                 return ret;
1258
1259         if (is_support_sw_smu(adev))
1260                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
1261         else if (adev->powerplay.pp_funcs->force_clock_level)
1262                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1263         else
1264                 ret = 0;
1265
1266         pm_runtime_mark_last_busy(ddev->dev);
1267         pm_runtime_put_autosuspend(ddev->dev);
1268
1269         if (ret)
1270                 return -EINVAL;
1271
1272         return count;
1273 }
1274
1275 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1276                 struct device_attribute *attr,
1277                 char *buf)
1278 {
1279         struct drm_device *ddev = dev_get_drvdata(dev);
1280         struct amdgpu_device *adev = ddev->dev_private;
1281         ssize_t size;
1282         int ret;
1283
1284         if (amdgpu_sriov_vf(adev))
1285                 return 0;
1286
1287         ret = pm_runtime_get_sync(ddev->dev);
1288         if (ret < 0)
1289                 return ret;
1290
1291         if (is_support_sw_smu(adev))
1292                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1293         else if (adev->powerplay.pp_funcs->print_clock_levels)
1294                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1295         else
1296                 size = snprintf(buf, PAGE_SIZE, "\n");
1297
1298         pm_runtime_mark_last_busy(ddev->dev);
1299         pm_runtime_put_autosuspend(ddev->dev);
1300
1301         return size;
1302 }
1303
1304 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1305                 struct device_attribute *attr,
1306                 const char *buf,
1307                 size_t count)
1308 {
1309         struct drm_device *ddev = dev_get_drvdata(dev);
1310         struct amdgpu_device *adev = ddev->dev_private;
1311         int ret;
1312         uint32_t mask = 0;
1313
1314         if (amdgpu_sriov_vf(adev))
1315                 return -EINVAL;
1316
1317         ret = amdgpu_read_mask(buf, count, &mask);
1318         if (ret)
1319                 return ret;
1320
1321         ret = pm_runtime_get_sync(ddev->dev);
1322         if (ret < 0)
1323                 return ret;
1324
1325         if (is_support_sw_smu(adev))
1326                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
1327         else if (adev->powerplay.pp_funcs->force_clock_level)
1328                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1329         else
1330                 ret = 0;
1331
1332         pm_runtime_mark_last_busy(ddev->dev);
1333         pm_runtime_put_autosuspend(ddev->dev);
1334
1335         if (ret)
1336                 return -EINVAL;
1337
1338         return count;
1339 }
1340
1341 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1342                 struct device_attribute *attr,
1343                 char *buf)
1344 {
1345         struct drm_device *ddev = dev_get_drvdata(dev);
1346         struct amdgpu_device *adev = ddev->dev_private;
1347         ssize_t size;
1348         int ret;
1349
1350         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1351                 return 0;
1352
1353         ret = pm_runtime_get_sync(ddev->dev);
1354         if (ret < 0)
1355                 return ret;
1356
1357         if (is_support_sw_smu(adev))
1358                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1359         else if (adev->powerplay.pp_funcs->print_clock_levels)
1360                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1361         else
1362                 size = snprintf(buf, PAGE_SIZE, "\n");
1363
1364         pm_runtime_mark_last_busy(ddev->dev);
1365         pm_runtime_put_autosuspend(ddev->dev);
1366
1367         return size;
1368 }
1369
1370 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1371                 struct device_attribute *attr,
1372                 const char *buf,
1373                 size_t count)
1374 {
1375         struct drm_device *ddev = dev_get_drvdata(dev);
1376         struct amdgpu_device *adev = ddev->dev_private;
1377         int ret;
1378         uint32_t mask = 0;
1379
1380         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1381                 return -EINVAL;
1382
1383         ret = amdgpu_read_mask(buf, count, &mask);
1384         if (ret)
1385                 return ret;
1386
1387         ret = pm_runtime_get_sync(ddev->dev);
1388         if (ret < 0)
1389                 return ret;
1390
1391         if (is_support_sw_smu(adev))
1392                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
1393         else if (adev->powerplay.pp_funcs->force_clock_level)
1394                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1395         else
1396                 ret = 0;
1397
1398         pm_runtime_mark_last_busy(ddev->dev);
1399         pm_runtime_put_autosuspend(ddev->dev);
1400
1401         if (ret)
1402                 return -EINVAL;
1403
1404         return count;
1405 }
1406
1407 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1408                 struct device_attribute *attr,
1409                 char *buf)
1410 {
1411         struct drm_device *ddev = dev_get_drvdata(dev);
1412         struct amdgpu_device *adev = ddev->dev_private;
1413         uint32_t value = 0;
1414         int ret;
1415
1416         if (amdgpu_sriov_vf(adev))
1417                 return 0;
1418
1419         ret = pm_runtime_get_sync(ddev->dev);
1420         if (ret < 0)
1421                 return ret;
1422
1423         if (is_support_sw_smu(adev))
1424                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1425         else if (adev->powerplay.pp_funcs->get_sclk_od)
1426                 value = amdgpu_dpm_get_sclk_od(adev);
1427
1428         pm_runtime_mark_last_busy(ddev->dev);
1429         pm_runtime_put_autosuspend(ddev->dev);
1430
1431         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1432 }
1433
1434 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1435                 struct device_attribute *attr,
1436                 const char *buf,
1437                 size_t count)
1438 {
1439         struct drm_device *ddev = dev_get_drvdata(dev);
1440         struct amdgpu_device *adev = ddev->dev_private;
1441         int ret;
1442         long int value;
1443
1444         if (amdgpu_sriov_vf(adev))
1445                 return -EINVAL;
1446
1447         ret = kstrtol(buf, 0, &value);
1448
1449         if (ret)
1450                 return -EINVAL;
1451
1452         ret = pm_runtime_get_sync(ddev->dev);
1453         if (ret < 0)
1454                 return ret;
1455
1456         if (is_support_sw_smu(adev)) {
1457                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1458         } else {
1459                 if (adev->powerplay.pp_funcs->set_sclk_od)
1460                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1461
1462                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1463                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1464                 } else {
1465                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1466                         amdgpu_pm_compute_clocks(adev);
1467                 }
1468         }
1469
1470         pm_runtime_mark_last_busy(ddev->dev);
1471         pm_runtime_put_autosuspend(ddev->dev);
1472
1473         return count;
1474 }
1475
1476 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1477                 struct device_attribute *attr,
1478                 char *buf)
1479 {
1480         struct drm_device *ddev = dev_get_drvdata(dev);
1481         struct amdgpu_device *adev = ddev->dev_private;
1482         uint32_t value = 0;
1483         int ret;
1484
1485         if (amdgpu_sriov_vf(adev))
1486                 return 0;
1487
1488         ret = pm_runtime_get_sync(ddev->dev);
1489         if (ret < 0)
1490                 return ret;
1491
1492         if (is_support_sw_smu(adev))
1493                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1494         else if (adev->powerplay.pp_funcs->get_mclk_od)
1495                 value = amdgpu_dpm_get_mclk_od(adev);
1496
1497         pm_runtime_mark_last_busy(ddev->dev);
1498         pm_runtime_put_autosuspend(ddev->dev);
1499
1500         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1501 }
1502
1503 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1504                 struct device_attribute *attr,
1505                 const char *buf,
1506                 size_t count)
1507 {
1508         struct drm_device *ddev = dev_get_drvdata(dev);
1509         struct amdgpu_device *adev = ddev->dev_private;
1510         int ret;
1511         long int value;
1512
1513         if (amdgpu_sriov_vf(adev))
1514                 return 0;
1515
1516         ret = kstrtol(buf, 0, &value);
1517
1518         if (ret)
1519                 return -EINVAL;
1520
1521         ret = pm_runtime_get_sync(ddev->dev);
1522         if (ret < 0)
1523                 return ret;
1524
1525         if (is_support_sw_smu(adev)) {
1526                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1527         } else {
1528                 if (adev->powerplay.pp_funcs->set_mclk_od)
1529                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1530
1531                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1532                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1533                 } else {
1534                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1535                         amdgpu_pm_compute_clocks(adev);
1536                 }
1537         }
1538
1539         pm_runtime_mark_last_busy(ddev->dev);
1540         pm_runtime_put_autosuspend(ddev->dev);
1541
1542         return count;
1543 }
1544
1545 /**
1546  * DOC: pp_power_profile_mode
1547  *
1548  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1549  * related to switching between power levels in a power state.  The file
1550  * pp_power_profile_mode is used for this.
1551  *
1552  * Reading this file outputs a list of all of the predefined power profiles
1553  * and the relevant heuristics settings for that profile.
1554  *
1555  * To select a profile or create a custom profile, first select manual using
1556  * power_dpm_force_performance_level.  Writing the number of a predefined
1557  * profile to pp_power_profile_mode will enable those heuristics.  To
1558  * create a custom set of heuristics, write a string of numbers to the file
1559  * starting with the number of the custom profile along with a setting
1560  * for each heuristic parameter.  Due to differences across asic families
1561  * the heuristic parameters vary from family to family.
1562  *
1563  */
1564
1565 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1566                 struct device_attribute *attr,
1567                 char *buf)
1568 {
1569         struct drm_device *ddev = dev_get_drvdata(dev);
1570         struct amdgpu_device *adev = ddev->dev_private;
1571         ssize_t size;
1572         int ret;
1573
1574         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1575                 return 0;
1576
1577         ret = pm_runtime_get_sync(ddev->dev);
1578         if (ret < 0)
1579                 return ret;
1580
1581         if (is_support_sw_smu(adev))
1582                 size = smu_get_power_profile_mode(&adev->smu, buf);
1583         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1584                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1585         else
1586                 size = snprintf(buf, PAGE_SIZE, "\n");
1587
1588         pm_runtime_mark_last_busy(ddev->dev);
1589         pm_runtime_put_autosuspend(ddev->dev);
1590
1591         return size;
1592 }
1593
1594
1595 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1596                 struct device_attribute *attr,
1597                 const char *buf,
1598                 size_t count)
1599 {
1600         int ret = 0xff;
1601         struct drm_device *ddev = dev_get_drvdata(dev);
1602         struct amdgpu_device *adev = ddev->dev_private;
1603         uint32_t parameter_size = 0;
1604         long parameter[64];
1605         char *sub_str, buf_cpy[128];
1606         char *tmp_str;
1607         uint32_t i = 0;
1608         char tmp[2];
1609         long int profile_mode = 0;
1610         const char delimiter[3] = {' ', '\n', '\0'};
1611
1612         tmp[0] = *(buf);
1613         tmp[1] = '\0';
1614         ret = kstrtol(tmp, 0, &profile_mode);
1615         if (ret)
1616                 return -EINVAL;
1617
1618         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1619                 return -EINVAL;
1620
1621         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1622                 if (count < 2 || count > 127)
1623                         return -EINVAL;
1624                 while (isspace(*++buf))
1625                         i++;
1626                 memcpy(buf_cpy, buf, count-i);
1627                 tmp_str = buf_cpy;
1628                 while (tmp_str[0]) {
1629                         sub_str = strsep(&tmp_str, delimiter);
1630                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1631                         if (ret)
1632                                 return -EINVAL;
1633                         parameter_size++;
1634                         while (isspace(*tmp_str))
1635                                 tmp_str++;
1636                 }
1637         }
1638         parameter[parameter_size] = profile_mode;
1639
1640         ret = pm_runtime_get_sync(ddev->dev);
1641         if (ret < 0)
1642                 return ret;
1643
1644         if (is_support_sw_smu(adev))
1645                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1646         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1647                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1648
1649         pm_runtime_mark_last_busy(ddev->dev);
1650         pm_runtime_put_autosuspend(ddev->dev);
1651
1652         if (!ret)
1653                 return count;
1654
1655         return -EINVAL;
1656 }
1657
1658 /**
1659  * DOC: busy_percent
1660  *
1661  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1662  * is as a percentage.  The file gpu_busy_percent is used for this.
1663  * The SMU firmware computes a percentage of load based on the
1664  * aggregate activity level in the IP cores.
1665  */
1666 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1667                 struct device_attribute *attr,
1668                 char *buf)
1669 {
1670         struct drm_device *ddev = dev_get_drvdata(dev);
1671         struct amdgpu_device *adev = ddev->dev_private;
1672         int r, value, size = sizeof(value);
1673
1674         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1675                 return 0;
1676
1677         r = pm_runtime_get_sync(ddev->dev);
1678         if (r < 0)
1679                 return r;
1680
1681         /* read the IP busy sensor */
1682         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1683                                    (void *)&value, &size);
1684
1685         pm_runtime_mark_last_busy(ddev->dev);
1686         pm_runtime_put_autosuspend(ddev->dev);
1687
1688         if (r)
1689                 return r;
1690
1691         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1692 }
1693
1694 /**
1695  * DOC: mem_busy_percent
1696  *
1697  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1698  * is as a percentage.  The file mem_busy_percent is used for this.
1699  * The SMU firmware computes a percentage of load based on the
1700  * aggregate activity level in the IP cores.
1701  */
1702 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1703                 struct device_attribute *attr,
1704                 char *buf)
1705 {
1706         struct drm_device *ddev = dev_get_drvdata(dev);
1707         struct amdgpu_device *adev = ddev->dev_private;
1708         int r, value, size = sizeof(value);
1709
1710         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1711                 return 0;
1712
1713         r = pm_runtime_get_sync(ddev->dev);
1714         if (r < 0)
1715                 return r;
1716
1717         /* read the IP busy sensor */
1718         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1719                                    (void *)&value, &size);
1720
1721         pm_runtime_mark_last_busy(ddev->dev);
1722         pm_runtime_put_autosuspend(ddev->dev);
1723
1724         if (r)
1725                 return r;
1726
1727         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1728 }
1729
1730 /**
1731  * DOC: pcie_bw
1732  *
1733  * The amdgpu driver provides a sysfs API for estimating how much data
1734  * has been received and sent by the GPU in the last second through PCIe.
1735  * The file pcie_bw is used for this.
1736  * The Perf counters count the number of received and sent messages and return
1737  * those values, as well as the maximum payload size of a PCIe packet (mps).
1738  * Note that it is not possible to easily and quickly obtain the size of each
1739  * packet transmitted, so we output the max payload size (mps) to allow for
1740  * quick estimation of the PCIe bandwidth usage
1741  */
1742 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1743                 struct device_attribute *attr,
1744                 char *buf)
1745 {
1746         struct drm_device *ddev = dev_get_drvdata(dev);
1747         struct amdgpu_device *adev = ddev->dev_private;
1748         uint64_t count0, count1;
1749         int ret;
1750
1751         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1752                 return 0;
1753
1754         ret = pm_runtime_get_sync(ddev->dev);
1755         if (ret < 0)
1756                 return ret;
1757
1758         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1759
1760         pm_runtime_mark_last_busy(ddev->dev);
1761         pm_runtime_put_autosuspend(ddev->dev);
1762
1763         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1764                         count0, count1, pcie_get_mps(adev->pdev));
1765 }
1766
1767 /**
1768  * DOC: unique_id
1769  *
1770  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1771  * The file unique_id is used for this.
1772  * This will provide a Unique ID that will persist from machine to machine
1773  *
1774  * NOTE: This will only work for GFX9 and newer. This file will be absent
1775  * on unsupported ASICs (GFX8 and older)
1776  */
1777 static ssize_t amdgpu_get_unique_id(struct device *dev,
1778                 struct device_attribute *attr,
1779                 char *buf)
1780 {
1781         struct drm_device *ddev = dev_get_drvdata(dev);
1782         struct amdgpu_device *adev = ddev->dev_private;
1783
1784         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1785                 return 0;
1786
1787         if (adev->unique_id)
1788                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1789
1790         return 0;
1791 }
1792
1793 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1794 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1795                    amdgpu_get_dpm_forced_performance_level,
1796                    amdgpu_set_dpm_forced_performance_level);
1797 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1798 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1799 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1800                 amdgpu_get_pp_force_state,
1801                 amdgpu_set_pp_force_state);
1802 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1803                 amdgpu_get_pp_table,
1804                 amdgpu_set_pp_table);
1805 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1806                 amdgpu_get_pp_dpm_sclk,
1807                 amdgpu_set_pp_dpm_sclk);
1808 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1809                 amdgpu_get_pp_dpm_mclk,
1810                 amdgpu_set_pp_dpm_mclk);
1811 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1812                 amdgpu_get_pp_dpm_socclk,
1813                 amdgpu_set_pp_dpm_socclk);
1814 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1815                 amdgpu_get_pp_dpm_fclk,
1816                 amdgpu_set_pp_dpm_fclk);
1817 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1818                 amdgpu_get_pp_dpm_dcefclk,
1819                 amdgpu_set_pp_dpm_dcefclk);
1820 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1821                 amdgpu_get_pp_dpm_pcie,
1822                 amdgpu_set_pp_dpm_pcie);
1823 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1824                 amdgpu_get_pp_sclk_od,
1825                 amdgpu_set_pp_sclk_od);
1826 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1827                 amdgpu_get_pp_mclk_od,
1828                 amdgpu_set_pp_mclk_od);
1829 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1830                 amdgpu_get_pp_power_profile_mode,
1831                 amdgpu_set_pp_power_profile_mode);
1832 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1833                 amdgpu_get_pp_od_clk_voltage,
1834                 amdgpu_set_pp_od_clk_voltage);
1835 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1836                 amdgpu_get_busy_percent, NULL);
1837 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1838                 amdgpu_get_memory_busy_percent, NULL);
1839 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1840 static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
1841                 amdgpu_get_pp_feature_status,
1842                 amdgpu_set_pp_feature_status);
1843 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1844
1845 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1846                                       struct device_attribute *attr,
1847                                       char *buf)
1848 {
1849         struct amdgpu_device *adev = dev_get_drvdata(dev);
1850         int channel = to_sensor_dev_attr(attr)->index;
1851         int r, temp = 0, size = sizeof(temp);
1852
1853         if (channel >= PP_TEMP_MAX)
1854                 return -EINVAL;
1855
1856         r = pm_runtime_get_sync(adev->ddev->dev);
1857         if (r < 0)
1858                 return r;
1859
1860         switch (channel) {
1861         case PP_TEMP_JUNCTION:
1862                 /* get current junction temperature */
1863                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1864                                            (void *)&temp, &size);
1865                 break;
1866         case PP_TEMP_EDGE:
1867                 /* get current edge temperature */
1868                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1869                                            (void *)&temp, &size);
1870                 break;
1871         case PP_TEMP_MEM:
1872                 /* get current memory temperature */
1873                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1874                                            (void *)&temp, &size);
1875                 break;
1876         default:
1877                 r = -EINVAL;
1878                 break;
1879         }
1880
1881         pm_runtime_mark_last_busy(adev->ddev->dev);
1882         pm_runtime_put_autosuspend(adev->ddev->dev);
1883
1884         if (r)
1885                 return r;
1886
1887         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1888 }
1889
1890 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1891                                              struct device_attribute *attr,
1892                                              char *buf)
1893 {
1894         struct amdgpu_device *adev = dev_get_drvdata(dev);
1895         int hyst = to_sensor_dev_attr(attr)->index;
1896         int temp;
1897
1898         if (hyst)
1899                 temp = adev->pm.dpm.thermal.min_temp;
1900         else
1901                 temp = adev->pm.dpm.thermal.max_temp;
1902
1903         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1904 }
1905
1906 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1907                                              struct device_attribute *attr,
1908                                              char *buf)
1909 {
1910         struct amdgpu_device *adev = dev_get_drvdata(dev);
1911         int hyst = to_sensor_dev_attr(attr)->index;
1912         int temp;
1913
1914         if (hyst)
1915                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1916         else
1917                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1918
1919         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1920 }
1921
1922 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1923                                              struct device_attribute *attr,
1924                                              char *buf)
1925 {
1926         struct amdgpu_device *adev = dev_get_drvdata(dev);
1927         int hyst = to_sensor_dev_attr(attr)->index;
1928         int temp;
1929
1930         if (hyst)
1931                 temp = adev->pm.dpm.thermal.min_mem_temp;
1932         else
1933                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1934
1935         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1936 }
1937
1938 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1939                                              struct device_attribute *attr,
1940                                              char *buf)
1941 {
1942         int channel = to_sensor_dev_attr(attr)->index;
1943
1944         if (channel >= PP_TEMP_MAX)
1945                 return -EINVAL;
1946
1947         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1948 }
1949
1950 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1951                                              struct device_attribute *attr,
1952                                              char *buf)
1953 {
1954         struct amdgpu_device *adev = dev_get_drvdata(dev);
1955         int channel = to_sensor_dev_attr(attr)->index;
1956         int temp = 0;
1957
1958         if (channel >= PP_TEMP_MAX)
1959                 return -EINVAL;
1960
1961         switch (channel) {
1962         case PP_TEMP_JUNCTION:
1963                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1964                 break;
1965         case PP_TEMP_EDGE:
1966                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1967                 break;
1968         case PP_TEMP_MEM:
1969                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1970                 break;
1971         }
1972
1973         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1974 }
1975
1976 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1977                                             struct device_attribute *attr,
1978                                             char *buf)
1979 {
1980         struct amdgpu_device *adev = dev_get_drvdata(dev);
1981         u32 pwm_mode = 0;
1982         int ret;
1983
1984         ret = pm_runtime_get_sync(adev->ddev->dev);
1985         if (ret < 0)
1986                 return ret;
1987
1988         if (is_support_sw_smu(adev)) {
1989                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1990         } else {
1991                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
1992                         pm_runtime_mark_last_busy(adev->ddev->dev);
1993                         pm_runtime_put_autosuspend(adev->ddev->dev);
1994                         return -EINVAL;
1995                 }
1996
1997                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1998         }
1999
2000         pm_runtime_mark_last_busy(adev->ddev->dev);
2001         pm_runtime_put_autosuspend(adev->ddev->dev);
2002
2003         return sprintf(buf, "%i\n", pwm_mode);
2004 }
2005
2006 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2007                                             struct device_attribute *attr,
2008                                             const char *buf,
2009                                             size_t count)
2010 {
2011         struct amdgpu_device *adev = dev_get_drvdata(dev);
2012         int err, ret;
2013         int value;
2014
2015         err = kstrtoint(buf, 10, &value);
2016         if (err)
2017                 return err;
2018
2019         ret = pm_runtime_get_sync(adev->ddev->dev);
2020         if (ret < 0)
2021                 return ret;
2022
2023         if (is_support_sw_smu(adev)) {
2024                 smu_set_fan_control_mode(&adev->smu, value);
2025         } else {
2026                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2027                         pm_runtime_mark_last_busy(adev->ddev->dev);
2028                         pm_runtime_put_autosuspend(adev->ddev->dev);
2029                         return -EINVAL;
2030                 }
2031
2032                 amdgpu_dpm_set_fan_control_mode(adev, value);
2033         }
2034
2035         pm_runtime_mark_last_busy(adev->ddev->dev);
2036         pm_runtime_put_autosuspend(adev->ddev->dev);
2037
2038         return count;
2039 }
2040
2041 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2042                                          struct device_attribute *attr,
2043                                          char *buf)
2044 {
2045         return sprintf(buf, "%i\n", 0);
2046 }
2047
2048 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2049                                          struct device_attribute *attr,
2050                                          char *buf)
2051 {
2052         return sprintf(buf, "%i\n", 255);
2053 }
2054
2055 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2056                                      struct device_attribute *attr,
2057                                      const char *buf, size_t count)
2058 {
2059         struct amdgpu_device *adev = dev_get_drvdata(dev);
2060         int err;
2061         u32 value;
2062         u32 pwm_mode;
2063
2064         err = pm_runtime_get_sync(adev->ddev->dev);
2065         if (err < 0)
2066                 return err;
2067
2068         if (is_support_sw_smu(adev))
2069                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2070         else
2071                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2072
2073         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2074                 pr_info("manual fan speed control should be enabled first\n");
2075                 pm_runtime_mark_last_busy(adev->ddev->dev);
2076                 pm_runtime_put_autosuspend(adev->ddev->dev);
2077                 return -EINVAL;
2078         }
2079
2080         err = kstrtou32(buf, 10, &value);
2081         if (err) {
2082                 pm_runtime_mark_last_busy(adev->ddev->dev);
2083                 pm_runtime_put_autosuspend(adev->ddev->dev);
2084                 return err;
2085         }
2086
2087         value = (value * 100) / 255;
2088
2089         if (is_support_sw_smu(adev))
2090                 err = smu_set_fan_speed_percent(&adev->smu, value);
2091         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2092                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2093         else
2094                 err = -EINVAL;
2095
2096         pm_runtime_mark_last_busy(adev->ddev->dev);
2097         pm_runtime_put_autosuspend(adev->ddev->dev);
2098
2099         if (err)
2100                 return err;
2101
2102         return count;
2103 }
2104
2105 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2106                                      struct device_attribute *attr,
2107                                      char *buf)
2108 {
2109         struct amdgpu_device *adev = dev_get_drvdata(dev);
2110         int err;
2111         u32 speed = 0;
2112
2113         err = pm_runtime_get_sync(adev->ddev->dev);
2114         if (err < 0)
2115                 return err;
2116
2117         if (is_support_sw_smu(adev))
2118                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2119         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2120                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2121         else
2122                 err = -EINVAL;
2123
2124         pm_runtime_mark_last_busy(adev->ddev->dev);
2125         pm_runtime_put_autosuspend(adev->ddev->dev);
2126
2127         if (err)
2128                 return err;
2129
2130         speed = (speed * 255) / 100;
2131
2132         return sprintf(buf, "%i\n", speed);
2133 }
2134
2135 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2136                                            struct device_attribute *attr,
2137                                            char *buf)
2138 {
2139         struct amdgpu_device *adev = dev_get_drvdata(dev);
2140         int err;
2141         u32 speed = 0;
2142
2143         err = pm_runtime_get_sync(adev->ddev->dev);
2144         if (err < 0)
2145                 return err;
2146
2147         if (is_support_sw_smu(adev))
2148                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2149         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2150                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2151         else
2152                 err = -EINVAL;
2153
2154         pm_runtime_mark_last_busy(adev->ddev->dev);
2155         pm_runtime_put_autosuspend(adev->ddev->dev);
2156
2157         if (err)
2158                 return err;
2159
2160         return sprintf(buf, "%i\n", speed);
2161 }
2162
2163 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2164                                          struct device_attribute *attr,
2165                                          char *buf)
2166 {
2167         struct amdgpu_device *adev = dev_get_drvdata(dev);
2168         u32 min_rpm = 0;
2169         u32 size = sizeof(min_rpm);
2170         int r;
2171
2172         r = pm_runtime_get_sync(adev->ddev->dev);
2173         if (r < 0)
2174                 return r;
2175
2176         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2177                                    (void *)&min_rpm, &size);
2178
2179         pm_runtime_mark_last_busy(adev->ddev->dev);
2180         pm_runtime_put_autosuspend(adev->ddev->dev);
2181
2182         if (r)
2183                 return r;
2184
2185         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2186 }
2187
2188 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2189                                          struct device_attribute *attr,
2190                                          char *buf)
2191 {
2192         struct amdgpu_device *adev = dev_get_drvdata(dev);
2193         u32 max_rpm = 0;
2194         u32 size = sizeof(max_rpm);
2195         int r;
2196
2197         r = pm_runtime_get_sync(adev->ddev->dev);
2198         if (r < 0)
2199                 return r;
2200
2201         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2202                                    (void *)&max_rpm, &size);
2203
2204         pm_runtime_mark_last_busy(adev->ddev->dev);
2205         pm_runtime_put_autosuspend(adev->ddev->dev);
2206
2207         if (r)
2208                 return r;
2209
2210         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2211 }
2212
2213 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2214                                            struct device_attribute *attr,
2215                                            char *buf)
2216 {
2217         struct amdgpu_device *adev = dev_get_drvdata(dev);
2218         int err;
2219         u32 rpm = 0;
2220
2221         err = pm_runtime_get_sync(adev->ddev->dev);
2222         if (err < 0)
2223                 return err;
2224
2225         if (is_support_sw_smu(adev))
2226                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2227         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2228                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2229         else
2230                 err = -EINVAL;
2231
2232         pm_runtime_mark_last_busy(adev->ddev->dev);
2233         pm_runtime_put_autosuspend(adev->ddev->dev);
2234
2235         if (err)
2236                 return err;
2237
2238         return sprintf(buf, "%i\n", rpm);
2239 }
2240
2241 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2242                                      struct device_attribute *attr,
2243                                      const char *buf, size_t count)
2244 {
2245         struct amdgpu_device *adev = dev_get_drvdata(dev);
2246         int err;
2247         u32 value;
2248         u32 pwm_mode;
2249
2250         err = pm_runtime_get_sync(adev->ddev->dev);
2251         if (err < 0)
2252                 return err;
2253
2254         if (is_support_sw_smu(adev))
2255                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2256         else
2257                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2258
2259         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2260                 pm_runtime_mark_last_busy(adev->ddev->dev);
2261                 pm_runtime_put_autosuspend(adev->ddev->dev);
2262                 return -ENODATA;
2263         }
2264
2265         err = kstrtou32(buf, 10, &value);
2266         if (err) {
2267                 pm_runtime_mark_last_busy(adev->ddev->dev);
2268                 pm_runtime_put_autosuspend(adev->ddev->dev);
2269                 return err;
2270         }
2271
2272         if (is_support_sw_smu(adev))
2273                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2274         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2275                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2276         else
2277                 err = -EINVAL;
2278
2279         pm_runtime_mark_last_busy(adev->ddev->dev);
2280         pm_runtime_put_autosuspend(adev->ddev->dev);
2281
2282         if (err)
2283                 return err;
2284
2285         return count;
2286 }
2287
2288 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2289                                             struct device_attribute *attr,
2290                                             char *buf)
2291 {
2292         struct amdgpu_device *adev = dev_get_drvdata(dev);
2293         u32 pwm_mode = 0;
2294         int ret;
2295
2296         ret = pm_runtime_get_sync(adev->ddev->dev);
2297         if (ret < 0)
2298                 return ret;
2299
2300         if (is_support_sw_smu(adev)) {
2301                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2302         } else {
2303                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2304                         pm_runtime_mark_last_busy(adev->ddev->dev);
2305                         pm_runtime_put_autosuspend(adev->ddev->dev);
2306                         return -EINVAL;
2307                 }
2308
2309                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2310         }
2311
2312         pm_runtime_mark_last_busy(adev->ddev->dev);
2313         pm_runtime_put_autosuspend(adev->ddev->dev);
2314
2315         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2316 }
2317
2318 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2319                                             struct device_attribute *attr,
2320                                             const char *buf,
2321                                             size_t count)
2322 {
2323         struct amdgpu_device *adev = dev_get_drvdata(dev);
2324         int err;
2325         int value;
2326         u32 pwm_mode;
2327
2328         err = kstrtoint(buf, 10, &value);
2329         if (err)
2330                 return err;
2331
2332         if (value == 0)
2333                 pwm_mode = AMD_FAN_CTRL_AUTO;
2334         else if (value == 1)
2335                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2336         else
2337                 return -EINVAL;
2338
2339         err = pm_runtime_get_sync(adev->ddev->dev);
2340         if (err < 0)
2341                 return err;
2342
2343         if (is_support_sw_smu(adev)) {
2344                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2345         } else {
2346                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2347                         pm_runtime_mark_last_busy(adev->ddev->dev);
2348                         pm_runtime_put_autosuspend(adev->ddev->dev);
2349                         return -EINVAL;
2350                 }
2351                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2352         }
2353
2354         pm_runtime_mark_last_busy(adev->ddev->dev);
2355         pm_runtime_put_autosuspend(adev->ddev->dev);
2356
2357         return count;
2358 }
2359
2360 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2361                                         struct device_attribute *attr,
2362                                         char *buf)
2363 {
2364         struct amdgpu_device *adev = dev_get_drvdata(dev);
2365         u32 vddgfx;
2366         int r, size = sizeof(vddgfx);
2367
2368         r = pm_runtime_get_sync(adev->ddev->dev);
2369         if (r < 0)
2370                 return r;
2371
2372         /* get the voltage */
2373         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2374                                    (void *)&vddgfx, &size);
2375
2376         pm_runtime_mark_last_busy(adev->ddev->dev);
2377         pm_runtime_put_autosuspend(adev->ddev->dev);
2378
2379         if (r)
2380                 return r;
2381
2382         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2383 }
2384
2385 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2386                                               struct device_attribute *attr,
2387                                               char *buf)
2388 {
2389         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2390 }
2391
2392 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2393                                        struct device_attribute *attr,
2394                                        char *buf)
2395 {
2396         struct amdgpu_device *adev = dev_get_drvdata(dev);
2397         u32 vddnb;
2398         int r, size = sizeof(vddnb);
2399
2400         /* only APUs have vddnb */
2401         if  (!(adev->flags & AMD_IS_APU))
2402                 return -EINVAL;
2403
2404         r = pm_runtime_get_sync(adev->ddev->dev);
2405         if (r < 0)
2406                 return r;
2407
2408         /* get the voltage */
2409         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2410                                    (void *)&vddnb, &size);
2411
2412         pm_runtime_mark_last_busy(adev->ddev->dev);
2413         pm_runtime_put_autosuspend(adev->ddev->dev);
2414
2415         if (r)
2416                 return r;
2417
2418         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
2419 }
2420
2421 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2422                                               struct device_attribute *attr,
2423                                               char *buf)
2424 {
2425         return snprintf(buf, PAGE_SIZE, "vddnb\n");
2426 }
2427
2428 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2429                                            struct device_attribute *attr,
2430                                            char *buf)
2431 {
2432         struct amdgpu_device *adev = dev_get_drvdata(dev);
2433         u32 query = 0;
2434         int r, size = sizeof(u32);
2435         unsigned uw;
2436
2437         r = pm_runtime_get_sync(adev->ddev->dev);
2438         if (r < 0)
2439                 return r;
2440
2441         /* get the voltage */
2442         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2443                                    (void *)&query, &size);
2444
2445         pm_runtime_mark_last_busy(adev->ddev->dev);
2446         pm_runtime_put_autosuspend(adev->ddev->dev);
2447
2448         if (r)
2449                 return r;
2450
2451         /* convert to microwatts */
2452         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2453
2454         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2455 }
2456
2457 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2458                                          struct device_attribute *attr,
2459                                          char *buf)
2460 {
2461         return sprintf(buf, "%i\n", 0);
2462 }
2463
2464 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2465                                          struct device_attribute *attr,
2466                                          char *buf)
2467 {
2468         struct amdgpu_device *adev = dev_get_drvdata(dev);
2469         uint32_t limit = 0;
2470         ssize_t size;
2471         int r;
2472
2473         r = pm_runtime_get_sync(adev->ddev->dev);
2474         if (r < 0)
2475                 return r;
2476
2477         if (is_support_sw_smu(adev)) {
2478                 smu_get_power_limit(&adev->smu, &limit, true, true);
2479                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2480         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2481                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2482                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2483         } else {
2484                 size = snprintf(buf, PAGE_SIZE, "\n");
2485         }
2486
2487         pm_runtime_mark_last_busy(adev->ddev->dev);
2488         pm_runtime_put_autosuspend(adev->ddev->dev);
2489
2490         return size;
2491 }
2492
2493 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2494                                          struct device_attribute *attr,
2495                                          char *buf)
2496 {
2497         struct amdgpu_device *adev = dev_get_drvdata(dev);
2498         uint32_t limit = 0;
2499         ssize_t size;
2500         int r;
2501
2502         r = pm_runtime_get_sync(adev->ddev->dev);
2503         if (r < 0)
2504                 return r;
2505
2506         if (is_support_sw_smu(adev)) {
2507                 smu_get_power_limit(&adev->smu, &limit, false,  true);
2508                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2509         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2510                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2511                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2512         } else {
2513                 size = snprintf(buf, PAGE_SIZE, "\n");
2514         }
2515
2516         pm_runtime_mark_last_busy(adev->ddev->dev);
2517         pm_runtime_put_autosuspend(adev->ddev->dev);
2518
2519         return size;
2520 }
2521
2522
2523 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2524                 struct device_attribute *attr,
2525                 const char *buf,
2526                 size_t count)
2527 {
2528         struct amdgpu_device *adev = dev_get_drvdata(dev);
2529         int err;
2530         u32 value;
2531
2532         if (amdgpu_sriov_vf(adev))
2533                 return -EINVAL;
2534
2535         err = kstrtou32(buf, 10, &value);
2536         if (err)
2537                 return err;
2538
2539         value = value / 1000000; /* convert to Watt */
2540
2541
2542         err = pm_runtime_get_sync(adev->ddev->dev);
2543         if (err < 0)
2544                 return err;
2545
2546         if (is_support_sw_smu(adev))
2547                 err = smu_set_power_limit(&adev->smu, value);
2548         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
2549                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2550         else
2551                 err = -EINVAL;
2552
2553         pm_runtime_mark_last_busy(adev->ddev->dev);
2554         pm_runtime_put_autosuspend(adev->ddev->dev);
2555
2556         if (err)
2557                 return err;
2558
2559         return count;
2560 }
2561
2562 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2563                                       struct device_attribute *attr,
2564                                       char *buf)
2565 {
2566         struct amdgpu_device *adev = dev_get_drvdata(dev);
2567         uint32_t sclk;
2568         int r, size = sizeof(sclk);
2569
2570         r = pm_runtime_get_sync(adev->ddev->dev);
2571         if (r < 0)
2572                 return r;
2573
2574         /* get the sclk */
2575         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2576                                    (void *)&sclk, &size);
2577
2578         pm_runtime_mark_last_busy(adev->ddev->dev);
2579         pm_runtime_put_autosuspend(adev->ddev->dev);
2580
2581         if (r)
2582                 return r;
2583
2584         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2585 }
2586
2587 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2588                                             struct device_attribute *attr,
2589                                             char *buf)
2590 {
2591         return snprintf(buf, PAGE_SIZE, "sclk\n");
2592 }
2593
2594 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2595                                       struct device_attribute *attr,
2596                                       char *buf)
2597 {
2598         struct amdgpu_device *adev = dev_get_drvdata(dev);
2599         uint32_t mclk;
2600         int r, size = sizeof(mclk);
2601
2602         r = pm_runtime_get_sync(adev->ddev->dev);
2603         if (r < 0)
2604                 return r;
2605
2606         /* get the sclk */
2607         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2608                                    (void *)&mclk, &size);
2609
2610         pm_runtime_mark_last_busy(adev->ddev->dev);
2611         pm_runtime_put_autosuspend(adev->ddev->dev);
2612
2613         if (r)
2614                 return r;
2615
2616         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2617 }
2618
2619 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2620                                             struct device_attribute *attr,
2621                                             char *buf)
2622 {
2623         return snprintf(buf, PAGE_SIZE, "mclk\n");
2624 }
2625
2626 /**
2627  * DOC: hwmon
2628  *
2629  * The amdgpu driver exposes the following sensor interfaces:
2630  *
2631  * - GPU temperature (via the on-die sensor)
2632  *
2633  * - GPU voltage
2634  *
2635  * - Northbridge voltage (APUs only)
2636  *
2637  * - GPU power
2638  *
2639  * - GPU fan
2640  *
2641  * - GPU gfx/compute engine clock
2642  *
2643  * - GPU memory clock (dGPU only)
2644  *
2645  * hwmon interfaces for GPU temperature:
2646  *
2647  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2648  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2649  *
2650  * - temp[1-3]_label: temperature channel label
2651  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2652  *
2653  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2654  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2655  *
2656  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2657  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2658  *
2659  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2660  *   - these are supported on SOC15 dGPUs only
2661  *
2662  * hwmon interfaces for GPU voltage:
2663  *
2664  * - in0_input: the voltage on the GPU in millivolts
2665  *
2666  * - in1_input: the voltage on the Northbridge in millivolts
2667  *
2668  * hwmon interfaces for GPU power:
2669  *
2670  * - power1_average: average power used by the GPU in microWatts
2671  *
2672  * - power1_cap_min: minimum cap supported in microWatts
2673  *
2674  * - power1_cap_max: maximum cap supported in microWatts
2675  *
2676  * - power1_cap: selected power cap in microWatts
2677  *
2678  * hwmon interfaces for GPU fan:
2679  *
2680  * - pwm1: pulse width modulation fan level (0-255)
2681  *
2682  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2683  *
2684  * - pwm1_min: pulse width modulation fan control minimum level (0)
2685  *
2686  * - pwm1_max: pulse width modulation fan control maximum level (255)
2687  *
2688  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2689  *
2690  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2691  *
2692  * - fan1_input: fan speed in RPM
2693  *
2694  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
2695  *
2696  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2697  *
2698  * hwmon interfaces for GPU clocks:
2699  *
2700  * - freq1_input: the gfx/compute clock in hertz
2701  *
2702  * - freq2_input: the memory clock in hertz
2703  *
2704  * You can use hwmon tools like sensors to view this information on your system.
2705  *
2706  */
2707
2708 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2709 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2710 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2711 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2712 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2713 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2714 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2715 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2716 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2717 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2718 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2719 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2720 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2721 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2722 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2723 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2724 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2725 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2726 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2727 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2728 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2729 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2730 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2731 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2732 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2733 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2734 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2735 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2736 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2737 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2738 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2739 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2740 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2741 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2742 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2743 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2744
2745 static struct attribute *hwmon_attributes[] = {
2746         &sensor_dev_attr_temp1_input.dev_attr.attr,
2747         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2748         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2749         &sensor_dev_attr_temp2_input.dev_attr.attr,
2750         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2751         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2752         &sensor_dev_attr_temp3_input.dev_attr.attr,
2753         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2754         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2755         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2756         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2757         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2758         &sensor_dev_attr_temp1_label.dev_attr.attr,
2759         &sensor_dev_attr_temp2_label.dev_attr.attr,
2760         &sensor_dev_attr_temp3_label.dev_attr.attr,
2761         &sensor_dev_attr_pwm1.dev_attr.attr,
2762         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2763         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2764         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2765         &sensor_dev_attr_fan1_input.dev_attr.attr,
2766         &sensor_dev_attr_fan1_min.dev_attr.attr,
2767         &sensor_dev_attr_fan1_max.dev_attr.attr,
2768         &sensor_dev_attr_fan1_target.dev_attr.attr,
2769         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2770         &sensor_dev_attr_in0_input.dev_attr.attr,
2771         &sensor_dev_attr_in0_label.dev_attr.attr,
2772         &sensor_dev_attr_in1_input.dev_attr.attr,
2773         &sensor_dev_attr_in1_label.dev_attr.attr,
2774         &sensor_dev_attr_power1_average.dev_attr.attr,
2775         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2776         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2777         &sensor_dev_attr_power1_cap.dev_attr.attr,
2778         &sensor_dev_attr_freq1_input.dev_attr.attr,
2779         &sensor_dev_attr_freq1_label.dev_attr.attr,
2780         &sensor_dev_attr_freq2_input.dev_attr.attr,
2781         &sensor_dev_attr_freq2_label.dev_attr.attr,
2782         NULL
2783 };
2784
2785 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2786                                         struct attribute *attr, int index)
2787 {
2788         struct device *dev = kobj_to_dev(kobj);
2789         struct amdgpu_device *adev = dev_get_drvdata(dev);
2790         umode_t effective_mode = attr->mode;
2791
2792         /* under multi-vf mode, the hwmon attributes are all not supported */
2793         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
2794                 return 0;
2795
2796         /* there is no fan under pp one vf mode */
2797         if (amdgpu_sriov_is_pp_one_vf(adev) &&
2798             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2799              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2800              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2801              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2802              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2803              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2804              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2805              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2806              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2807                 return 0;
2808
2809         /* Skip fan attributes if fan is not present */
2810         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2811             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2812             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2813             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2814             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2815             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2816             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2817             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2818             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2819                 return 0;
2820
2821         /* Skip fan attributes on APU */
2822         if ((adev->flags & AMD_IS_APU) &&
2823             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2824              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2825              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2826              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2827              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2828              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2829              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2830              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2831              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2832                 return 0;
2833
2834         /* Skip limit attributes if DPM is not enabled */
2835         if (!adev->pm.dpm_enabled &&
2836             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2837              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2838              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2839              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2840              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2841              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2842              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2843              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2844              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2845              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2846              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2847                 return 0;
2848
2849         if (!is_support_sw_smu(adev)) {
2850                 /* mask fan attributes if we have no bindings for this asic to expose */
2851                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2852                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2853                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2854                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2855                         effective_mode &= ~S_IRUGO;
2856
2857                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2858                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2859                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2860                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2861                         effective_mode &= ~S_IWUSR;
2862         }
2863
2864         if (((adev->flags & AMD_IS_APU) ||
2865              adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2866              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2867             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2868              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2869              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2870              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2871                 return 0;
2872
2873         if (!is_support_sw_smu(adev)) {
2874                 /* hide max/min values if we can't both query and manage the fan */
2875                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2876                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2877                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2878                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2879                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2880                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2881                         return 0;
2882
2883                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2884                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2885                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2886                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2887                         return 0;
2888         }
2889
2890         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2891              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2892             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
2893              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
2894                 return 0;
2895
2896         /* only APUs have vddnb */
2897         if (!(adev->flags & AMD_IS_APU) &&
2898             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2899              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2900                 return 0;
2901
2902         /* no mclk on APUs */
2903         if ((adev->flags & AMD_IS_APU) &&
2904             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2905              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2906                 return 0;
2907
2908         /* only SOC15 dGPUs support hotspot and mem temperatures */
2909         if (((adev->flags & AMD_IS_APU) ||
2910              adev->asic_type < CHIP_VEGA10) &&
2911             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2912              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2913              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2914              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2915              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2916              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2917              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2918              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2919              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2920              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2921              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2922                 return 0;
2923
2924         return effective_mode;
2925 }
2926
2927 static const struct attribute_group hwmon_attrgroup = {
2928         .attrs = hwmon_attributes,
2929         .is_visible = hwmon_attributes_visible,
2930 };
2931
2932 static const struct attribute_group *hwmon_groups[] = {
2933         &hwmon_attrgroup,
2934         NULL
2935 };
2936
2937 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2938 {
2939         struct amdgpu_device *adev =
2940                 container_of(work, struct amdgpu_device,
2941                              pm.dpm.thermal.work);
2942         /* switch to the thermal state */
2943         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2944         int temp, size = sizeof(temp);
2945
2946         if (!adev->pm.dpm_enabled)
2947                 return;
2948
2949         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2950                                     (void *)&temp, &size)) {
2951                 if (temp < adev->pm.dpm.thermal.min_temp)
2952                         /* switch back the user state */
2953                         dpm_state = adev->pm.dpm.user_state;
2954         } else {
2955                 if (adev->pm.dpm.thermal.high_to_low)
2956                         /* switch back the user state */
2957                         dpm_state = adev->pm.dpm.user_state;
2958         }
2959         mutex_lock(&adev->pm.mutex);
2960         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2961                 adev->pm.dpm.thermal_active = true;
2962         else
2963                 adev->pm.dpm.thermal_active = false;
2964         adev->pm.dpm.state = dpm_state;
2965         mutex_unlock(&adev->pm.mutex);
2966
2967         amdgpu_pm_compute_clocks(adev);
2968 }
2969
2970 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2971                                                      enum amd_pm_state_type dpm_state)
2972 {
2973         int i;
2974         struct amdgpu_ps *ps;
2975         u32 ui_class;
2976         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2977                 true : false;
2978
2979         /* check if the vblank period is too short to adjust the mclk */
2980         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2981                 if (amdgpu_dpm_vblank_too_short(adev))
2982                         single_display = false;
2983         }
2984
2985         /* certain older asics have a separare 3D performance state,
2986          * so try that first if the user selected performance
2987          */
2988         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2989                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2990         /* balanced states don't exist at the moment */
2991         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2992                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2993
2994 restart_search:
2995         /* Pick the best power state based on current conditions */
2996         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2997                 ps = &adev->pm.dpm.ps[i];
2998                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2999                 switch (dpm_state) {
3000                 /* user states */
3001                 case POWER_STATE_TYPE_BATTERY:
3002                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
3003                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3004                                         if (single_display)
3005                                                 return ps;
3006                                 } else
3007                                         return ps;
3008                         }
3009                         break;
3010                 case POWER_STATE_TYPE_BALANCED:
3011                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
3012                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3013                                         if (single_display)
3014                                                 return ps;
3015                                 } else
3016                                         return ps;
3017                         }
3018                         break;
3019                 case POWER_STATE_TYPE_PERFORMANCE:
3020                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3021                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3022                                         if (single_display)
3023                                                 return ps;
3024                                 } else
3025                                         return ps;
3026                         }
3027                         break;
3028                 /* internal states */
3029                 case POWER_STATE_TYPE_INTERNAL_UVD:
3030                         if (adev->pm.dpm.uvd_ps)
3031                                 return adev->pm.dpm.uvd_ps;
3032                         else
3033                                 break;
3034                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3035                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3036                                 return ps;
3037                         break;
3038                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3039                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3040                                 return ps;
3041                         break;
3042                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3043                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3044                                 return ps;
3045                         break;
3046                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3047                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3048                                 return ps;
3049                         break;
3050                 case POWER_STATE_TYPE_INTERNAL_BOOT:
3051                         return adev->pm.dpm.boot_ps;
3052                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
3053                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
3054                                 return ps;
3055                         break;
3056                 case POWER_STATE_TYPE_INTERNAL_ACPI:
3057                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
3058                                 return ps;
3059                         break;
3060                 case POWER_STATE_TYPE_INTERNAL_ULV:
3061                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
3062                                 return ps;
3063                         break;
3064                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
3065                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
3066                                 return ps;
3067                         break;
3068                 default:
3069                         break;
3070                 }
3071         }
3072         /* use a fallback state if we didn't match */
3073         switch (dpm_state) {
3074         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3075                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
3076                 goto restart_search;
3077         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3078         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3079         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3080                 if (adev->pm.dpm.uvd_ps) {
3081                         return adev->pm.dpm.uvd_ps;
3082                 } else {
3083                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3084                         goto restart_search;
3085                 }
3086         case POWER_STATE_TYPE_INTERNAL_THERMAL:
3087                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
3088                 goto restart_search;
3089         case POWER_STATE_TYPE_INTERNAL_ACPI:
3090                 dpm_state = POWER_STATE_TYPE_BATTERY;
3091                 goto restart_search;
3092         case POWER_STATE_TYPE_BATTERY:
3093         case POWER_STATE_TYPE_BALANCED:
3094         case POWER_STATE_TYPE_INTERNAL_3DPERF:
3095                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3096                 goto restart_search;
3097         default:
3098                 break;
3099         }
3100
3101         return NULL;
3102 }
3103
3104 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
3105 {
3106         struct amdgpu_ps *ps;
3107         enum amd_pm_state_type dpm_state;
3108         int ret;
3109         bool equal = false;
3110
3111         /* if dpm init failed */
3112         if (!adev->pm.dpm_enabled)
3113                 return;
3114
3115         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
3116                 /* add other state override checks here */
3117                 if ((!adev->pm.dpm.thermal_active) &&
3118                     (!adev->pm.dpm.uvd_active))
3119                         adev->pm.dpm.state = adev->pm.dpm.user_state;
3120         }
3121         dpm_state = adev->pm.dpm.state;
3122
3123         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
3124         if (ps)
3125                 adev->pm.dpm.requested_ps = ps;
3126         else
3127                 return;
3128
3129         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
3130                 printk("switching from power state:\n");
3131                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
3132                 printk("switching to power state:\n");
3133                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
3134         }
3135
3136         /* update whether vce is active */
3137         ps->vce_active = adev->pm.dpm.vce_active;
3138         if (adev->powerplay.pp_funcs->display_configuration_changed)
3139                 amdgpu_dpm_display_configuration_changed(adev);
3140
3141         ret = amdgpu_dpm_pre_set_power_state(adev);
3142         if (ret)
3143                 return;
3144
3145         if (adev->powerplay.pp_funcs->check_state_equal) {
3146                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
3147                         equal = false;
3148         }
3149
3150         if (equal)
3151                 return;
3152
3153         amdgpu_dpm_set_power_state(adev);
3154         amdgpu_dpm_post_set_power_state(adev);
3155
3156         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
3157         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
3158
3159         if (adev->powerplay.pp_funcs->force_performance_level) {
3160                 if (adev->pm.dpm.thermal_active) {
3161                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
3162                         /* force low perf level for thermal */
3163                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
3164                         /* save the user's level */
3165                         adev->pm.dpm.forced_level = level;
3166                 } else {
3167                         /* otherwise, user selected level */
3168                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
3169                 }
3170         }
3171 }
3172
3173 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
3174 {
3175         int ret = 0;
3176
3177         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
3178         if (ret)
3179                 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
3180                           enable ? "enable" : "disable", ret);
3181
3182         /* enable/disable Low Memory PState for UVD (4k videos) */
3183         if (adev->asic_type == CHIP_STONEY &&
3184                 adev->uvd.decode_image_width >= WIDTH_4K) {
3185                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3186
3187                 if (hwmgr && hwmgr->hwmgr_func &&
3188                     hwmgr->hwmgr_func->update_nbdpm_pstate)
3189                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
3190                                                                !enable,
3191                                                                true);
3192         }
3193 }
3194
3195 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
3196 {
3197         int ret = 0;
3198
3199         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
3200         if (ret)
3201                 DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
3202                           enable ? "enable" : "disable", ret);
3203 }
3204
3205 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
3206 {
3207         int i;
3208
3209         if (adev->powerplay.pp_funcs->print_power_state == NULL)
3210                 return;
3211
3212         for (i = 0; i < adev->pm.dpm.num_ps; i++)
3213                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
3214
3215 }
3216
3217 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
3218 {
3219         int ret = 0;
3220
3221         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
3222         if (ret)
3223                 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
3224                           enable ? "enable" : "disable", ret);
3225 }
3226
3227 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
3228 {
3229         int r;
3230
3231         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
3232                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
3233                 if (r) {
3234                         pr_err("smu firmware loading failed\n");
3235                         return r;
3236                 }
3237                 *smu_version = adev->pm.fw_version;
3238         }
3239         return 0;
3240 }
3241
3242 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3243 {
3244         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3245         int ret;
3246
3247         if (adev->pm.sysfs_initialized)
3248                 return 0;
3249
3250         if (adev->pm.dpm_enabled == 0)
3251                 return 0;
3252
3253         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3254                                                                    DRIVER_NAME, adev,
3255                                                                    hwmon_groups);
3256         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3257                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3258                 dev_err(adev->dev,
3259                         "Unable to register hwmon device: %d\n", ret);
3260                 return ret;
3261         }
3262
3263         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
3264         if (ret) {
3265                 DRM_ERROR("failed to create device file for dpm state\n");
3266                 return ret;
3267         }
3268         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
3269         if (ret) {
3270                 DRM_ERROR("failed to create device file for dpm state\n");
3271                 return ret;
3272         }
3273
3274
3275         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
3276         if (ret) {
3277                 DRM_ERROR("failed to create device file pp_num_states\n");
3278                 return ret;
3279         }
3280         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
3281         if (ret) {
3282                 DRM_ERROR("failed to create device file pp_cur_state\n");
3283                 return ret;
3284         }
3285         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
3286         if (ret) {
3287                 DRM_ERROR("failed to create device file pp_force_state\n");
3288                 return ret;
3289         }
3290         ret = device_create_file(adev->dev, &dev_attr_pp_table);
3291         if (ret) {
3292                 DRM_ERROR("failed to create device file pp_table\n");
3293                 return ret;
3294         }
3295
3296         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
3297         if (ret) {
3298                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
3299                 return ret;
3300         }
3301
3302         /* Arcturus does not support standalone mclk/socclk/fclk level setting */
3303         if (adev->asic_type == CHIP_ARCTURUS) {
3304                 dev_attr_pp_dpm_mclk.attr.mode &= ~S_IWUGO;
3305                 dev_attr_pp_dpm_mclk.store = NULL;
3306
3307                 dev_attr_pp_dpm_socclk.attr.mode &= ~S_IWUGO;
3308                 dev_attr_pp_dpm_socclk.store = NULL;
3309
3310                 dev_attr_pp_dpm_fclk.attr.mode &= ~S_IWUGO;
3311                 dev_attr_pp_dpm_fclk.store = NULL;
3312         }
3313
3314         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
3315         if (ret) {
3316                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
3317                 return ret;
3318         }
3319         if (adev->asic_type >= CHIP_VEGA10) {
3320                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
3321                 if (ret) {
3322                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
3323                         return ret;
3324                 }
3325                 if (adev->asic_type != CHIP_ARCTURUS) {
3326                         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
3327                         if (ret) {
3328                                 DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
3329                                 return ret;
3330                         }
3331                 }
3332         }
3333         if (adev->asic_type >= CHIP_VEGA20) {
3334                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
3335                 if (ret) {
3336                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
3337                         return ret;
3338                 }
3339         }
3340         if (adev->asic_type != CHIP_ARCTURUS) {
3341                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
3342                 if (ret) {
3343                         DRM_ERROR("failed to create device file pp_dpm_pcie\n");
3344                         return ret;
3345                 }
3346         }
3347         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
3348         if (ret) {
3349                 DRM_ERROR("failed to create device file pp_sclk_od\n");
3350                 return ret;
3351         }
3352         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
3353         if (ret) {
3354                 DRM_ERROR("failed to create device file pp_mclk_od\n");
3355                 return ret;
3356         }
3357         ret = device_create_file(adev->dev,
3358                         &dev_attr_pp_power_profile_mode);
3359         if (ret) {
3360                 DRM_ERROR("failed to create device file "
3361                                 "pp_power_profile_mode\n");
3362                 return ret;
3363         }
3364         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
3365             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
3366                 ret = device_create_file(adev->dev,
3367                                 &dev_attr_pp_od_clk_voltage);
3368                 if (ret) {
3369                         DRM_ERROR("failed to create device file "
3370                                         "pp_od_clk_voltage\n");
3371                         return ret;
3372                 }
3373         }
3374         ret = device_create_file(adev->dev,
3375                         &dev_attr_gpu_busy_percent);
3376         if (ret) {
3377                 DRM_ERROR("failed to create device file "
3378                                 "gpu_busy_level\n");
3379                 return ret;
3380         }
3381         /* APU does not have its own dedicated memory */
3382         if (!(adev->flags & AMD_IS_APU) &&
3383              (adev->asic_type != CHIP_VEGA10)) {
3384                 ret = device_create_file(adev->dev,
3385                                 &dev_attr_mem_busy_percent);
3386                 if (ret) {
3387                         DRM_ERROR("failed to create device file "
3388                                         "mem_busy_percent\n");
3389                         return ret;
3390                 }
3391         }
3392         /* PCIe Perf counters won't work on APU nodes */
3393         if (!(adev->flags & AMD_IS_APU)) {
3394                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
3395                 if (ret) {
3396                         DRM_ERROR("failed to create device file pcie_bw\n");
3397                         return ret;
3398                 }
3399         }
3400         if (adev->unique_id)
3401                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
3402         if (ret) {
3403                 DRM_ERROR("failed to create device file unique_id\n");
3404                 return ret;
3405         }
3406
3407         if ((adev->asic_type >= CHIP_VEGA10) &&
3408             !(adev->flags & AMD_IS_APU)) {
3409                 ret = device_create_file(adev->dev,
3410                                 &dev_attr_pp_features);
3411                 if (ret) {
3412                         DRM_ERROR("failed to create device file "
3413                                         "pp_features\n");
3414                         return ret;
3415                 }
3416         }
3417
3418         adev->pm.sysfs_initialized = true;
3419
3420         return 0;
3421 }
3422
3423 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3424 {
3425         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3426
3427         if (adev->pm.dpm_enabled == 0)
3428                 return;
3429
3430         if (adev->pm.int_hwmon_dev)
3431                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3432         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
3433         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
3434
3435         device_remove_file(adev->dev, &dev_attr_pp_num_states);
3436         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
3437         device_remove_file(adev->dev, &dev_attr_pp_force_state);
3438         device_remove_file(adev->dev, &dev_attr_pp_table);
3439
3440         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
3441         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
3442         if (adev->asic_type >= CHIP_VEGA10) {
3443                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
3444                 if (adev->asic_type != CHIP_ARCTURUS)
3445                         device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
3446         }
3447         if (adev->asic_type != CHIP_ARCTURUS)
3448                 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
3449         if (adev->asic_type >= CHIP_VEGA20)
3450                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
3451         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
3452         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
3453         device_remove_file(adev->dev,
3454                         &dev_attr_pp_power_profile_mode);
3455         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
3456             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
3457                 device_remove_file(adev->dev,
3458                                 &dev_attr_pp_od_clk_voltage);
3459         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
3460         if (!(adev->flags & AMD_IS_APU) &&
3461              (adev->asic_type != CHIP_VEGA10))
3462                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
3463         if (!(adev->flags & AMD_IS_APU))
3464                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
3465         if (adev->unique_id)
3466                 device_remove_file(adev->dev, &dev_attr_unique_id);
3467         if ((adev->asic_type >= CHIP_VEGA10) &&
3468             !(adev->flags & AMD_IS_APU))
3469                 device_remove_file(adev->dev, &dev_attr_pp_features);
3470 }
3471
3472 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
3473 {
3474         int i = 0;
3475
3476         if (!adev->pm.dpm_enabled)
3477                 return;
3478
3479         if (adev->mode_info.num_crtc)
3480                 amdgpu_display_bandwidth_update(adev);
3481
3482         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3483                 struct amdgpu_ring *ring = adev->rings[i];
3484                 if (ring && ring->sched.ready)
3485                         amdgpu_fence_wait_empty(ring);
3486         }
3487
3488         if (is_support_sw_smu(adev)) {
3489                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3490                 smu_handle_task(&adev->smu,
3491                                 smu_dpm->dpm_level,
3492                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
3493                                 true);
3494         } else {
3495                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3496                         if (!amdgpu_device_has_dc_support(adev)) {
3497                                 mutex_lock(&adev->pm.mutex);
3498                                 amdgpu_dpm_get_active_displays(adev);
3499                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3500                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3501                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3502                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3503                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3504                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3505                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3506                                         adev->powerplay.pp_funcs->display_configuration_change(
3507                                                                         adev->powerplay.pp_handle,
3508                                                                         &adev->pm.pm_display_cfg);
3509                                 mutex_unlock(&adev->pm.mutex);
3510                         }
3511                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3512                 } else {
3513                         mutex_lock(&adev->pm.mutex);
3514                         amdgpu_dpm_get_active_displays(adev);
3515                         amdgpu_dpm_change_power_state_locked(adev);
3516                         mutex_unlock(&adev->pm.mutex);
3517                 }
3518         }
3519 }
3520
3521 /*
3522  * Debugfs info
3523  */
3524 #if defined(CONFIG_DEBUG_FS)
3525
3526 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3527 {
3528         uint32_t value;
3529         uint64_t value64;
3530         uint32_t query = 0;
3531         int size;
3532
3533         /* GPU Clocks */
3534         size = sizeof(value);
3535         seq_printf(m, "GFX Clocks and Power:\n");
3536         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3537                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3538         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3539                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3540         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3541                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3542         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3543                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3544         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3545                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3546         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3547                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3548         size = sizeof(uint32_t);
3549         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3550                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3551         size = sizeof(value);
3552         seq_printf(m, "\n");
3553
3554         /* GPU Temp */
3555         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3556                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3557
3558         /* GPU Load */
3559         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3560                 seq_printf(m, "GPU Load: %u %%\n", value);
3561         /* MEM Load */
3562         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3563                 seq_printf(m, "MEM Load: %u %%\n", value);
3564
3565         seq_printf(m, "\n");
3566
3567         /* SMC feature mask */
3568         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3569                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3570
3571         if (adev->asic_type > CHIP_VEGA20) {
3572                 /* VCN clocks */
3573                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3574                         if (!value) {
3575                                 seq_printf(m, "VCN: Disabled\n");
3576                         } else {
3577                                 seq_printf(m, "VCN: Enabled\n");
3578                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3579                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3580                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3581                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3582                         }
3583                 }
3584                 seq_printf(m, "\n");
3585         } else {
3586                 /* UVD clocks */
3587                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3588                         if (!value) {
3589                                 seq_printf(m, "UVD: Disabled\n");
3590                         } else {
3591                                 seq_printf(m, "UVD: Enabled\n");
3592                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3593                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3594                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3595                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3596                         }
3597                 }
3598                 seq_printf(m, "\n");
3599
3600                 /* VCE clocks */
3601                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3602                         if (!value) {
3603                                 seq_printf(m, "VCE: Disabled\n");
3604                         } else {
3605                                 seq_printf(m, "VCE: Enabled\n");
3606                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3607                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3608                         }
3609                 }
3610         }
3611
3612         return 0;
3613 }
3614
3615 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3616 {
3617         int i;
3618
3619         for (i = 0; clocks[i].flag; i++)
3620                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3621                            (flags & clocks[i].flag) ? "On" : "Off");
3622 }
3623
3624 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3625 {
3626         struct drm_info_node *node = (struct drm_info_node *) m->private;
3627         struct drm_device *dev = node->minor->dev;
3628         struct amdgpu_device *adev = dev->dev_private;
3629         u32 flags = 0;
3630         int r;
3631
3632         r = pm_runtime_get_sync(dev->dev);
3633         if (r < 0)
3634                 return r;
3635
3636         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3637         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3638         amdgpu_parse_cg_state(m, flags);
3639         seq_printf(m, "\n");
3640
3641         if (!adev->pm.dpm_enabled) {
3642                 seq_printf(m, "dpm not enabled\n");
3643                 pm_runtime_mark_last_busy(dev->dev);
3644                 pm_runtime_put_autosuspend(dev->dev);
3645                 return 0;
3646         }
3647
3648         if (!is_support_sw_smu(adev) &&
3649             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3650                 mutex_lock(&adev->pm.mutex);
3651                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3652                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3653                 else
3654                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3655                 mutex_unlock(&adev->pm.mutex);
3656                 r = 0;
3657         } else {
3658                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3659         }
3660
3661         pm_runtime_mark_last_busy(dev->dev);
3662         pm_runtime_put_autosuspend(dev->dev);
3663
3664         return r;
3665 }
3666
3667 static const struct drm_info_list amdgpu_pm_info_list[] = {
3668         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3669 };
3670 #endif
3671
3672 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3673 {
3674 #if defined(CONFIG_DEBUG_FS)
3675         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3676 #else
3677         return 0;
3678 #endif
3679 }