drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {0, NULL},
  68 };
  69
  70 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  71 {
  72         if (adev->pm.dpm_enabled) {
  73                 mutex_lock(&adev->pm.mutex);
  74                 if (power_supply_is_system_supplied() > 0)
  75                         adev->pm.ac_power = true;
  76                 else
  77                         adev->pm.ac_power = false;
  78                 if (adev->powerplay.pp_funcs->enable_bapm)
  79                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  80                 mutex_unlock(&adev->pm.mutex);
  81         }
  82 }
  83
  84 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  85                            void *data, uint32_t *size)
  86 {
  87         int ret = 0;
  88
  89         if (!data || !size)
  90                 return -EINVAL;
  91
  92         if (is_support_sw_smu(adev))
  93                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
  94         else {
  95                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
  96                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
  97                                                                     sensor, data, size);
  98                 else
  99                         ret = -EINVAL;
 100         }
 101
 102         return ret;
 103 }
 104
 105 /**
 106  * DOC: power_dpm_state
 107  *
 108  * The power_dpm_state file is a legacy interface and is only provided for
 109  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 110  * certain power related parameters.  The file power_dpm_state is used for this.
 111  * It accepts the following arguments:
 112  *
 113  * - battery
 114  *
 115  * - balanced
 116  *
 117  * - performance
 118  *
 119  * battery
 120  *
 121  * On older GPUs, the vbios provided a special power state for battery
 122  * operation.  Selecting battery switched to this state.  This is no
 123  * longer provided on newer GPUs so the option does nothing in that case.
 124  *
 125  * balanced
 126  *
 127  * On older GPUs, the vbios provided a special power state for balanced
 128  * operation.  Selecting balanced switched to this state.  This is no
 129  * longer provided on newer GPUs so the option does nothing in that case.
 130  *
 131  * performance
 132  *
 133  * On older GPUs, the vbios provided a special power state for performance
 134  * operation.  Selecting performance switched to this state.  This is no
 135  * longer provided on newer GPUs so the option does nothing in that case.
 136  *
 137  */
 138
 139 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 140                                     struct device_attribute *attr,
 141                                     char *buf)
 142 {
 143         struct drm_device *ddev = dev_get_drvdata(dev);
 144         struct amdgpu_device *adev = ddev->dev_private;
 145         enum amd_pm_state_type pm;
 146
 147         if (adev->smu.ppt_funcs->get_current_power_state)
 148                 pm = amdgpu_smu_get_current_power_state(adev);
 149         else if (adev->powerplay.pp_funcs->get_current_power_state)
 150                 pm = amdgpu_dpm_get_current_power_state(adev);
 151         else
 152                 pm = adev->pm.dpm.user_state;
 153
 154         return snprintf(buf, PAGE_SIZE, "%s\n",
 155                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 156                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 157 }
 158
 159 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 160                                     struct device_attribute *attr,
 161                                     const char *buf,
 162                                     size_t count)
 163 {
 164         struct drm_device *ddev = dev_get_drvdata(dev);
 165         struct amdgpu_device *adev = ddev->dev_private;
 166         enum amd_pm_state_type  state;
 167
 168         if (strncmp("battery", buf, strlen("battery")) == 0)
 169                 state = POWER_STATE_TYPE_BATTERY;
 170         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 171                 state = POWER_STATE_TYPE_BALANCED;
 172         else if (strncmp("performance", buf, strlen("performance")) == 0)
 173                 state = POWER_STATE_TYPE_PERFORMANCE;
 174         else {
 175                 count = -EINVAL;
 176                 goto fail;
 177         }
 178
 179         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 180                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 181         } else {
 182                 mutex_lock(&adev->pm.mutex);
 183                 adev->pm.dpm.user_state = state;
 184                 mutex_unlock(&adev->pm.mutex);
 185
 186                 /* Can't set dpm state when the card is off */
 187                 if (!(adev->flags & AMD_IS_PX) ||
 188                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 189                         amdgpu_pm_compute_clocks(adev);
 190         }
 191 fail:
 192         return count;
 193 }
 194
 195
 196 /**
 197  * DOC: power_dpm_force_performance_level
 198  *
 199  * The amdgpu driver provides a sysfs API for adjusting certain power
 200  * related parameters.  The file power_dpm_force_performance_level is
 201  * used for this.  It accepts the following arguments:
 202  *
 203  * - auto
 204  *
 205  * - low
 206  *
 207  * - high
 208  *
 209  * - manual
 210  *
 211  * - profile_standard
 212  *
 213  * - profile_min_sclk
 214  *
 215  * - profile_min_mclk
 216  *
 217  * - profile_peak
 218  *
 219  * auto
 220  *
 221  * When auto is selected, the driver will attempt to dynamically select
 222  * the optimal power profile for current conditions in the driver.
 223  *
 224  * low
 225  *
 226  * When low is selected, the clocks are forced to the lowest power state.
 227  *
 228  * high
 229  *
 230  * When high is selected, the clocks are forced to the highest power state.
 231  *
 232  * manual
 233  *
 234  * When manual is selected, the user can manually adjust which power states
 235  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 236  * and pp_dpm_pcie files and adjust the power state transition heuristics
 237  * via the pp_power_profile_mode sysfs file.
 238  *
 239  * profile_standard
 240  * profile_min_sclk
 241  * profile_min_mclk
 242  * profile_peak
 243  *
 244  * When the profiling modes are selected, clock and power gating are
 245  * disabled and the clocks are set for different profiling cases. This
 246  * mode is recommended for profiling specific work loads where you do
 247  * not want clock or power gating for clock fluctuation to interfere
 248  * with your results. profile_standard sets the clocks to a fixed clock
 249  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 250  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 251  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 252  *
 253  */
 254
 255 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 256                                                 struct device_attribute *attr,
 257                                                                 char *buf)
 258 {
 259         struct drm_device *ddev = dev_get_drvdata(dev);
 260         struct amdgpu_device *adev = ddev->dev_private;
 261         enum amd_dpm_forced_level level = 0xff;
 262
 263         if  ((adev->flags & AMD_IS_PX) &&
 264              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 265                 return snprintf(buf, PAGE_SIZE, "off\n");
 266
 267         if (is_support_sw_smu(adev))
 268                 level = smu_get_performance_level(&adev->smu);
 269         else if (adev->powerplay.pp_funcs->get_performance_level)
 270                 level = amdgpu_dpm_get_performance_level(adev);
 271         else
 272                 level = adev->pm.dpm.forced_level;
 273
 274         return snprintf(buf, PAGE_SIZE, "%s\n",
 275                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 276                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 277                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 278                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 279                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 280                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 281                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 282                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 283                         "unknown");
 284 }
 285
 286 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 287                                                        struct device_attribute *attr,
 288                                                        const char *buf,
 289                                                        size_t count)
 290 {
 291         struct drm_device *ddev = dev_get_drvdata(dev);
 292         struct amdgpu_device *adev = ddev->dev_private;
 293         enum amd_dpm_forced_level level;
 294         enum amd_dpm_forced_level current_level = 0xff;
 295         int ret = 0;
 296
 297         /* Can't force performance level when the card is off */
 298         if  ((adev->flags & AMD_IS_PX) &&
 299              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 300                 return -EINVAL;
 301
 302         if (is_support_sw_smu(adev))
 303                 current_level = smu_get_performance_level(&adev->smu);
 304         else if (adev->powerplay.pp_funcs->get_performance_level)
 305                 current_level = amdgpu_dpm_get_performance_level(adev);
 306
 307         if (strncmp("low", buf, strlen("low")) == 0) {
 308                 level = AMD_DPM_FORCED_LEVEL_LOW;
 309         } else if (strncmp("high", buf, strlen("high")) == 0) {
 310                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 311         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 312                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 313         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 315         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 317         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 319         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 321         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 323         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 325         }  else {
 326                 count = -EINVAL;
 327                 goto fail;
 328         }
 329
 330         if (current_level == level)
 331                 return count;
 332
 333         if (is_support_sw_smu(adev)) {
 334                 mutex_lock(&adev->pm.mutex);
 335                 if (adev->pm.dpm.thermal_active) {
 336                         count = -EINVAL;
 337                         mutex_unlock(&adev->pm.mutex);
 338                         goto fail;
 339                 }
 340                 ret = smu_force_performance_level(&adev->smu, level);
 341                 if (ret)
 342                         count = -EINVAL;
 343                 else
 344                         adev->pm.dpm.forced_level = level;
 345                 mutex_unlock(&adev->pm.mutex);
 346         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 347                 mutex_lock(&adev->pm.mutex);
 348                 if (adev->pm.dpm.thermal_active) {
 349                         count = -EINVAL;
 350                         mutex_unlock(&adev->pm.mutex);
 351                         goto fail;
 352                 }
 353                 ret = amdgpu_dpm_force_performance_level(adev, level);
 354                 if (ret)
 355                         count = -EINVAL;
 356                 else
 357                         adev->pm.dpm.forced_level = level;
 358                 mutex_unlock(&adev->pm.mutex);
 359         }
 360
 361 fail:
 362         return count;
 363 }
 364
 365 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 366                 struct device_attribute *attr,
 367                 char *buf)
 368 {
 369         struct drm_device *ddev = dev_get_drvdata(dev);
 370         struct amdgpu_device *adev = ddev->dev_private;
 371         struct pp_states_info data;
 372         int i, buf_len, ret;
 373
 374         if (is_support_sw_smu(adev)) {
 375                 ret = smu_get_power_num_states(&adev->smu, &data);
 376                 if (ret)
 377                         return ret;
 378         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 379                 amdgpu_dpm_get_pp_num_states(adev, &data);
 380
 381         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 382         for (i = 0; i < data.nums; i++)
 383                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 384                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 385                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 386                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 387                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 388
 389         return buf_len;
 390 }
 391
 392 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 393                 struct device_attribute *attr,
 394                 char *buf)
 395 {
 396         struct drm_device *ddev = dev_get_drvdata(dev);
 397         struct amdgpu_device *adev = ddev->dev_private;
 398         struct pp_states_info data;
 399         struct smu_context *smu = &adev->smu;
 400         enum amd_pm_state_type pm = 0;
 401         int i = 0, ret = 0;
 402
 403         if (is_support_sw_smu(adev)) {
 404                 pm = smu_get_current_power_state(smu);
 405                 ret = smu_get_power_num_states(smu, &data);
 406                 if (ret)
 407                         return ret;
 408         } else if (adev->powerplay.pp_funcs->get_current_power_state
 409                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 410                 pm = amdgpu_dpm_get_current_power_state(adev);
 411                 amdgpu_dpm_get_pp_num_states(adev, &data);
 412         }
 413
 414         for (i = 0; i < data.nums; i++) {
 415                 if (pm == data.states[i])
 416                         break;
 417         }
 418
 419         if (i == data.nums)
 420                 i = -EINVAL;
 421
 422         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 423 }
 424
 425 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 426                 struct device_attribute *attr,
 427                 char *buf)
 428 {
 429         struct drm_device *ddev = dev_get_drvdata(dev);
 430         struct amdgpu_device *adev = ddev->dev_private;
 431
 432         if (adev->pp_force_state_enabled)
 433                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 434         else
 435                 return snprintf(buf, PAGE_SIZE, "\n");
 436 }
 437
 438 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 439                 struct device_attribute *attr,
 440                 const char *buf,
 441                 size_t count)
 442 {
 443         struct drm_device *ddev = dev_get_drvdata(dev);
 444         struct amdgpu_device *adev = ddev->dev_private;
 445         enum amd_pm_state_type state = 0;
 446         unsigned long idx;
 447         int ret;
 448
 449         if (strlen(buf) == 1)
 450                 adev->pp_force_state_enabled = false;
 451         else if (is_support_sw_smu(adev))
 452                 adev->pp_force_state_enabled = false;
 453         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 454                         adev->powerplay.pp_funcs->get_pp_num_states) {
 455                 struct pp_states_info data;
 456
 457                 ret = kstrtoul(buf, 0, &idx);
 458                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 459                         count = -EINVAL;
 460                         goto fail;
 461                 }
 462                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 463
 464                 amdgpu_dpm_get_pp_num_states(adev, &data);
 465                 state = data.states[idx];
 466                 /* only set user selected power states */
 467                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 468                     state != POWER_STATE_TYPE_DEFAULT) {
 469                         amdgpu_dpm_dispatch_task(adev,
 470                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 471                         adev->pp_force_state_enabled = true;
 472                 }
 473         }
 474 fail:
 475         return count;
 476 }
 477
 478 /**
 479  * DOC: pp_table
 480  *
 481  * The amdgpu driver provides a sysfs API for uploading new powerplay
 482  * tables.  The file pp_table is used for this.  Reading the file
 483  * will dump the current power play table.  Writing to the file
 484  * will attempt to upload a new powerplay table and re-initialize
 485  * powerplay using that new table.
 486  *
 487  */
 488
 489 static ssize_t amdgpu_get_pp_table(struct device *dev,
 490                 struct device_attribute *attr,
 491                 char *buf)
 492 {
 493         struct drm_device *ddev = dev_get_drvdata(dev);
 494         struct amdgpu_device *adev = ddev->dev_private;
 495         char *table = NULL;
 496         int size;
 497
 498         if (is_support_sw_smu(adev)) {
 499                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 500                 if (size < 0)
 501                         return size;
 502         }
 503         else if (adev->powerplay.pp_funcs->get_pp_table)
 504                 size = amdgpu_dpm_get_pp_table(adev, &table);
 505         else
 506                 return 0;
 507
 508         if (size >= PAGE_SIZE)
 509                 size = PAGE_SIZE - 1;
 510
 511         memcpy(buf, table, size);
 512
 513         return size;
 514 }
 515
 516 static ssize_t amdgpu_set_pp_table(struct device *dev,
 517                 struct device_attribute *attr,
 518                 const char *buf,
 519                 size_t count)
 520 {
 521         struct drm_device *ddev = dev_get_drvdata(dev);
 522         struct amdgpu_device *adev = ddev->dev_private;
 523         int ret = 0;
 524
 525         if (is_support_sw_smu(adev)) {
 526                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 527                 if (ret)
 528                         return ret;
 529         } else if (adev->powerplay.pp_funcs->set_pp_table)
 530                 amdgpu_dpm_set_pp_table(adev, buf, count);
 531
 532         return count;
 533 }
 534
 535 /**
 536  * DOC: pp_od_clk_voltage
 537  *
 538  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 539  * in each power level within a power state.  The pp_od_clk_voltage is used for
 540  * this.
 541  *
 542  * < For Vega10 and previous ASICs >
 543  *
 544  * Reading the file will display:
 545  *
 546  * - a list of engine clock levels and voltages labeled OD_SCLK
 547  *
 548  * - a list of memory clock levels and voltages labeled OD_MCLK
 549  *
 550  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 551  *
 552  * To manually adjust these settings, first select manual using
 553  * power_dpm_force_performance_level. Enter a new value for each
 554  * level by writing a string that contains "s/m level clock voltage" to
 555  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 556  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 557  * 810 mV.  When you have edited all of the states as needed, write
 558  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 559  * default power levels, write "r" (reset) to the file to reset them.
 560  *
 561  *
 562  * < For Vega20 >
 563  *
 564  * Reading the file will display:
 565  *
 566  * - minimum and maximum engine clock labeled OD_SCLK
 567  *
 568  * - maximum memory clock labeled OD_MCLK
 569  *
 570  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 571  *   They can be used to calibrate the sclk voltage curve.
 572  *
 573  * - a list of valid ranges for sclk, mclk, and voltage curve points
 574  *   labeled OD_RANGE
 575  *
 576  * To manually adjust these settings:
 577  *
 578  * - First select manual using power_dpm_force_performance_level
 579  *
 580  * - For clock frequency setting, enter a new value by writing a
 581  *   string that contains "s/m index clock" to the file. The index
 582  *   should be 0 if to set minimum clock. And 1 if to set maximum
 583  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 584  *   "m 1 800" will update maximum mclk to be 800Mhz.
 585  *
 586  *   For sclk voltage curve, enter the new values by writing a
 587  *   string that contains "vc point clock voltage" to the file. The
 588  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 589  *   update point1 with clock set as 300Mhz and voltage as
 590  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 591  *   as 1000Mhz and voltage 1000mV.
 592  *
 593  * - When you have edited all of the states as needed, write "c" (commit)
 594  *   to the file to commit your changes
 595  *
 596  * - If you want to reset to the default power levels, write "r" (reset)
 597  *   to the file to reset them
 598  *
 599  */
 600
 601 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 602                 struct device_attribute *attr,
 603                 const char *buf,
 604                 size_t count)
 605 {
 606         struct drm_device *ddev = dev_get_drvdata(dev);
 607         struct amdgpu_device *adev = ddev->dev_private;
 608         int ret;
 609         uint32_t parameter_size = 0;
 610         long parameter[64];
 611         char buf_cpy[128];
 612         char *tmp_str;
 613         char *sub_str;
 614         const char delimiter[3] = {' ', '\n', '\0'};
 615         uint32_t type;
 616
 617         if (count > 127)
 618                 return -EINVAL;
 619
 620         if (*buf == 's')
 621                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 622         else if (*buf == 'm')
 623                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 624         else if(*buf == 'r')
 625                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 626         else if (*buf == 'c')
 627                 type = PP_OD_COMMIT_DPM_TABLE;
 628         else if (!strncmp(buf, "vc", 2))
 629                 type = PP_OD_EDIT_VDDC_CURVE;
 630         else
 631                 return -EINVAL;
 632
 633         memcpy(buf_cpy, buf, count+1);
 634
 635         tmp_str = buf_cpy;
 636
 637         if (type == PP_OD_EDIT_VDDC_CURVE)
 638                 tmp_str++;
 639         while (isspace(*++tmp_str));
 640
 641         while (tmp_str[0]) {
 642                 sub_str = strsep(&tmp_str, delimiter);
 643                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 644                 if (ret)
 645                         return -EINVAL;
 646                 parameter_size++;
 647
 648                 while (isspace(*tmp_str))
 649                         tmp_str++;
 650         }
 651
 652         if (is_support_sw_smu(adev)) {
 653                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 654                                             parameter, parameter_size);
 655
 656                 if (ret)
 657                         return -EINVAL;
 658         } else {
 659                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 660                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 661                                                 parameter, parameter_size);
 662
 663                 if (ret)
 664                         return -EINVAL;
 665
 666                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 667                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 668                                 amdgpu_dpm_dispatch_task(adev,
 669                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 670                                                 NULL);
 671                                 return count;
 672                         } else {
 673                                 return -EINVAL;
 674                         }
 675                 }
 676         }
 677
 678         return count;
 679 }
 680
 681 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 682                 struct device_attribute *attr,
 683                 char *buf)
 684 {
 685         struct drm_device *ddev = dev_get_drvdata(dev);
 686         struct amdgpu_device *adev = ddev->dev_private;
 687         uint32_t size = 0;
 688
 689         if (is_support_sw_smu(adev)) {
 690                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 691                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 692                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 693                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 694                 return size;
 695         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 696                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 697                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 698                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 699                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 700                 return size;
 701         } else {
 702                 return snprintf(buf, PAGE_SIZE, "\n");
 703         }
 704
 705 }
 706
 707 /**
 708  * DOC: ppfeatures
 709  *
 710  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 711  * features to be enabled. The file ppfeatures is used for this. And
 712  * this is only available for Vega10 and later dGPUs.
 713  *
 714  * Reading back the file will show you the followings:
 715  * - Current ppfeature masks
 716  * - List of the all supported powerplay features with their naming,
 717  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 718  *
 719  * To manually enable or disable a specific feature, just set or clear
 720  * the corresponding bit from original ppfeature masks and input the
 721  * new ppfeature masks.
 722  */
 723 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 724                 struct device_attribute *attr,
 725                 const char *buf,
 726                 size_t count)
 727 {
 728         struct drm_device *ddev = dev_get_drvdata(dev);
 729         struct amdgpu_device *adev = ddev->dev_private;
 730         uint64_t featuremask;
 731         int ret;
 732
 733         ret = kstrtou64(buf, 0, &featuremask);
 734         if (ret)
 735                 return -EINVAL;
 736
 737         pr_debug("featuremask = 0x%llx\n", featuremask);
 738
 739         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 740                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 741                 if (ret)
 742                         return -EINVAL;
 743         }
 744
 745         return count;
 746 }
 747
 748 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 749                 struct device_attribute *attr,
 750                 char *buf)
 751 {
 752         struct drm_device *ddev = dev_get_drvdata(dev);
 753         struct amdgpu_device *adev = ddev->dev_private;
 754
 755         if (adev->powerplay.pp_funcs->get_ppfeature_status)
 756                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 757
 758         return snprintf(buf, PAGE_SIZE, "\n");
 759 }
 760
 761 /**
 762  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 763  * pp_dpm_pcie
 764  *
 765  * The amdgpu driver provides a sysfs API for adjusting what power levels
 766  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 767  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 768  * this.
 769  *
 770  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 771  * Vega10 and later ASICs.
 772  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 773  *
 774  * Reading back the files will show you the available power levels within
 775  * the power state and the clock information for those levels.
 776  *
 777  * To manually adjust these states, first select manual using
 778  * power_dpm_force_performance_level.
 779  * Secondly,Enter a new value for each level by inputing a string that
 780  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 781  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 782  *
 783  * NOTE: change to the dcefclk max dpm level is not supported now
 784  */
 785
 786 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 787                 struct device_attribute *attr,
 788                 char *buf)
 789 {
 790         struct drm_device *ddev = dev_get_drvdata(dev);
 791         struct amdgpu_device *adev = ddev->dev_private;
 792
 793         if (is_support_sw_smu(adev))
 794                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 795         else if (adev->powerplay.pp_funcs->print_clock_levels)
 796                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 797         else
 798                 return snprintf(buf, PAGE_SIZE, "\n");
 799 }
 800
 801 /*
 802  * Worst case: 32 bits individually specified, in octal at 12 characters
 803  * per line (+1 for \n).
 804  */
 805 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 806
 807 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 808 {
 809         int ret;
 810         long level;
 811         char *sub_str = NULL;
 812         char *tmp;
 813         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 814         const char delimiter[3] = {' ', '\n', '\0'};
 815         size_t bytes;
 816
 817         *mask = 0;
 818
 819         bytes = min(count, sizeof(buf_cpy) - 1);
 820         memcpy(buf_cpy, buf, bytes);
 821         buf_cpy[bytes] = '\0';
 822         tmp = buf_cpy;
 823         while (tmp[0]) {
 824                 sub_str = strsep(&tmp, delimiter);
 825                 if (strlen(sub_str)) {
 826                         ret = kstrtol(sub_str, 0, &level);
 827                         if (ret)
 828                                 return -EINVAL;
 829                         *mask |= 1 << level;
 830                 } else
 831                         break;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 838                 struct device_attribute *attr,
 839                 const char *buf,
 840                 size_t count)
 841 {
 842         struct drm_device *ddev = dev_get_drvdata(dev);
 843         struct amdgpu_device *adev = ddev->dev_private;
 844         int ret;
 845         uint32_t mask = 0;
 846
 847         ret = amdgpu_read_mask(buf, count, &mask);
 848         if (ret)
 849                 return ret;
 850
 851         if (is_support_sw_smu(adev))
 852                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 853         else if (adev->powerplay.pp_funcs->force_clock_level)
 854                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 855
 856         if (ret)
 857                 return -EINVAL;
 858
 859         return count;
 860 }
 861
 862 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 863                 struct device_attribute *attr,
 864                 char *buf)
 865 {
 866         struct drm_device *ddev = dev_get_drvdata(dev);
 867         struct amdgpu_device *adev = ddev->dev_private;
 868
 869         if (is_support_sw_smu(adev))
 870                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 871         else if (adev->powerplay.pp_funcs->print_clock_levels)
 872                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 873         else
 874                 return snprintf(buf, PAGE_SIZE, "\n");
 875 }
 876
 877 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 878                 struct device_attribute *attr,
 879                 const char *buf,
 880                 size_t count)
 881 {
 882         struct drm_device *ddev = dev_get_drvdata(dev);
 883         struct amdgpu_device *adev = ddev->dev_private;
 884         int ret;
 885         uint32_t mask = 0;
 886
 887         ret = amdgpu_read_mask(buf, count, &mask);
 888         if (ret)
 889                 return ret;
 890
 891         if (is_support_sw_smu(adev))
 892                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 893         else if (adev->powerplay.pp_funcs->force_clock_level)
 894                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 895
 896         if (ret)
 897                 return -EINVAL;
 898
 899         return count;
 900 }
 901
 902 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 903                 struct device_attribute *attr,
 904                 char *buf)
 905 {
 906         struct drm_device *ddev = dev_get_drvdata(dev);
 907         struct amdgpu_device *adev = ddev->dev_private;
 908
 909         if (adev->powerplay.pp_funcs->print_clock_levels)
 910                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 911         else
 912                 return snprintf(buf, PAGE_SIZE, "\n");
 913 }
 914
 915 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 916                 struct device_attribute *attr,
 917                 const char *buf,
 918                 size_t count)
 919 {
 920         struct drm_device *ddev = dev_get_drvdata(dev);
 921         struct amdgpu_device *adev = ddev->dev_private;
 922         int ret;
 923         uint32_t mask = 0;
 924
 925         ret = amdgpu_read_mask(buf, count, &mask);
 926         if (ret)
 927                 return ret;
 928
 929         if (adev->powerplay.pp_funcs->force_clock_level)
 930                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 931
 932         if (ret)
 933                 return -EINVAL;
 934
 935         return count;
 936 }
 937
 938 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 939                 struct device_attribute *attr,
 940                 char *buf)
 941 {
 942         struct drm_device *ddev = dev_get_drvdata(dev);
 943         struct amdgpu_device *adev = ddev->dev_private;
 944
 945         if (adev->powerplay.pp_funcs->print_clock_levels)
 946                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 947         else
 948                 return snprintf(buf, PAGE_SIZE, "\n");
 949 }
 950
 951 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 952                 struct device_attribute *attr,
 953                 const char *buf,
 954                 size_t count)
 955 {
 956         struct drm_device *ddev = dev_get_drvdata(dev);
 957         struct amdgpu_device *adev = ddev->dev_private;
 958         int ret;
 959         uint32_t mask = 0;
 960
 961         ret = amdgpu_read_mask(buf, count, &mask);
 962         if (ret)
 963                 return ret;
 964
 965         if (adev->powerplay.pp_funcs->force_clock_level)
 966                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
 967
 968         if (ret)
 969                 return -EINVAL;
 970
 971         return count;
 972 }
 973
 974 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
 975                 struct device_attribute *attr,
 976                 char *buf)
 977 {
 978         struct drm_device *ddev = dev_get_drvdata(dev);
 979         struct amdgpu_device *adev = ddev->dev_private;
 980
 981         if (adev->powerplay.pp_funcs->print_clock_levels)
 982                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
 983         else
 984                 return snprintf(buf, PAGE_SIZE, "\n");
 985 }
 986
 987 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
 988                 struct device_attribute *attr,
 989                 const char *buf,
 990                 size_t count)
 991 {
 992         struct drm_device *ddev = dev_get_drvdata(dev);
 993         struct amdgpu_device *adev = ddev->dev_private;
 994         int ret;
 995         uint32_t mask = 0;
 996
 997         ret = amdgpu_read_mask(buf, count, &mask);
 998         if (ret)
 999                 return ret;
1000
1001         if (adev->powerplay.pp_funcs->force_clock_level)
1002                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1003
1004         if (ret)
1005                 return -EINVAL;
1006
1007         return count;
1008 }
1009
1010 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1011                 struct device_attribute *attr,
1012                 char *buf)
1013 {
1014         struct drm_device *ddev = dev_get_drvdata(dev);
1015         struct amdgpu_device *adev = ddev->dev_private;
1016
1017         if (is_support_sw_smu(adev))
1018                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1019         else if (adev->powerplay.pp_funcs->print_clock_levels)
1020                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1021         else
1022                 return snprintf(buf, PAGE_SIZE, "\n");
1023 }
1024
1025 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1026                 struct device_attribute *attr,
1027                 const char *buf,
1028                 size_t count)
1029 {
1030         struct drm_device *ddev = dev_get_drvdata(dev);
1031         struct amdgpu_device *adev = ddev->dev_private;
1032         int ret;
1033         uint32_t mask = 0;
1034
1035         ret = amdgpu_read_mask(buf, count, &mask);
1036         if (ret)
1037                 return ret;
1038
1039         if (is_support_sw_smu(adev))
1040                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1041         else if (adev->powerplay.pp_funcs->force_clock_level)
1042                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1043
1044         if (ret)
1045                 return -EINVAL;
1046
1047         return count;
1048 }
1049
1050 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1051                 struct device_attribute *attr,
1052                 char *buf)
1053 {
1054         struct drm_device *ddev = dev_get_drvdata(dev);
1055         struct amdgpu_device *adev = ddev->dev_private;
1056         uint32_t value = 0;
1057
1058         if (is_support_sw_smu(adev))
1059                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1060         else if (adev->powerplay.pp_funcs->get_sclk_od)
1061                 value = amdgpu_dpm_get_sclk_od(adev);
1062
1063         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1064 }
1065
1066 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1067                 struct device_attribute *attr,
1068                 const char *buf,
1069                 size_t count)
1070 {
1071         struct drm_device *ddev = dev_get_drvdata(dev);
1072         struct amdgpu_device *adev = ddev->dev_private;
1073         int ret;
1074         long int value;
1075
1076         ret = kstrtol(buf, 0, &value);
1077
1078         if (ret) {
1079                 count = -EINVAL;
1080                 goto fail;
1081         }
1082
1083         if (is_support_sw_smu(adev)) {
1084                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1085         } else {
1086                 if (adev->powerplay.pp_funcs->set_sclk_od)
1087                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1088
1089                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1090                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1091                 } else {
1092                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1093                         amdgpu_pm_compute_clocks(adev);
1094                 }
1095         }
1096
1097 fail:
1098         return count;
1099 }
1100
1101 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1102                 struct device_attribute *attr,
1103                 char *buf)
1104 {
1105         struct drm_device *ddev = dev_get_drvdata(dev);
1106         struct amdgpu_device *adev = ddev->dev_private;
1107         uint32_t value = 0;
1108
1109         if (is_support_sw_smu(adev))
1110                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1111         else if (adev->powerplay.pp_funcs->get_mclk_od)
1112                 value = amdgpu_dpm_get_mclk_od(adev);
1113
1114         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1115 }
1116
1117 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1118                 struct device_attribute *attr,
1119                 const char *buf,
1120                 size_t count)
1121 {
1122         struct drm_device *ddev = dev_get_drvdata(dev);
1123         struct amdgpu_device *adev = ddev->dev_private;
1124         int ret;
1125         long int value;
1126
1127         ret = kstrtol(buf, 0, &value);
1128
1129         if (ret) {
1130                 count = -EINVAL;
1131                 goto fail;
1132         }
1133
1134         if (is_support_sw_smu(adev)) {
1135                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1136         } else {
1137                 if (adev->powerplay.pp_funcs->set_mclk_od)
1138                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1139
1140                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1141                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1142                 } else {
1143                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1144                         amdgpu_pm_compute_clocks(adev);
1145                 }
1146         }
1147
1148 fail:
1149         return count;
1150 }
1151
1152 /**
1153  * DOC: pp_power_profile_mode
1154  *
1155  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1156  * related to switching between power levels in a power state.  The file
1157  * pp_power_profile_mode is used for this.
1158  *
1159  * Reading this file outputs a list of all of the predefined power profiles
1160  * and the relevant heuristics settings for that profile.
1161  *
1162  * To select a profile or create a custom profile, first select manual using
1163  * power_dpm_force_performance_level.  Writing the number of a predefined
1164  * profile to pp_power_profile_mode will enable those heuristics.  To
1165  * create a custom set of heuristics, write a string of numbers to the file
1166  * starting with the number of the custom profile along with a setting
1167  * for each heuristic parameter.  Due to differences across asic families
1168  * the heuristic parameters vary from family to family.
1169  *
1170  */
1171
1172 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1173                 struct device_attribute *attr,
1174                 char *buf)
1175 {
1176         struct drm_device *ddev = dev_get_drvdata(dev);
1177         struct amdgpu_device *adev = ddev->dev_private;
1178
1179         if (is_support_sw_smu(adev))
1180                 return smu_get_power_profile_mode(&adev->smu, buf);
1181         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1182                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1183
1184         return snprintf(buf, PAGE_SIZE, "\n");
1185 }
1186
1187
1188 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1189                 struct device_attribute *attr,
1190                 const char *buf,
1191                 size_t count)
1192 {
1193         int ret = 0xff;
1194         struct drm_device *ddev = dev_get_drvdata(dev);
1195         struct amdgpu_device *adev = ddev->dev_private;
1196         uint32_t parameter_size = 0;
1197         long parameter[64];
1198         char *sub_str, buf_cpy[128];
1199         char *tmp_str;
1200         uint32_t i = 0;
1201         char tmp[2];
1202         long int profile_mode = 0;
1203         const char delimiter[3] = {' ', '\n', '\0'};
1204
1205         tmp[0] = *(buf);
1206         tmp[1] = '\0';
1207         ret = kstrtol(tmp, 0, &profile_mode);
1208         if (ret)
1209                 goto fail;
1210
1211         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1212                 if (count < 2 || count > 127)
1213                         return -EINVAL;
1214                 while (isspace(*++buf))
1215                         i++;
1216                 memcpy(buf_cpy, buf, count-i);
1217                 tmp_str = buf_cpy;
1218                 while (tmp_str[0]) {
1219                         sub_str = strsep(&tmp_str, delimiter);
1220                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1221                         if (ret) {
1222                                 count = -EINVAL;
1223                                 goto fail;
1224                         }
1225                         parameter_size++;
1226                         while (isspace(*tmp_str))
1227                                 tmp_str++;
1228                 }
1229         }
1230         parameter[parameter_size] = profile_mode;
1231         if (is_support_sw_smu(adev))
1232                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1233         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1234                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1235         if (!ret)
1236                 return count;
1237 fail:
1238         return -EINVAL;
1239 }
1240
1241 /**
1242  * DOC: busy_percent
1243  *
1244  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1245  * is as a percentage.  The file gpu_busy_percent is used for this.
1246  * The SMU firmware computes a percentage of load based on the
1247  * aggregate activity level in the IP cores.
1248  */
1249 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1250                 struct device_attribute *attr,
1251                 char *buf)
1252 {
1253         struct drm_device *ddev = dev_get_drvdata(dev);
1254         struct amdgpu_device *adev = ddev->dev_private;
1255         int r, value, size = sizeof(value);
1256
1257         /* read the IP busy sensor */
1258         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1259                                    (void *)&value, &size);
1260
1261         if (r)
1262                 return r;
1263
1264         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1265 }
1266
1267 /**
1268  * DOC: pcie_bw
1269  *
1270  * The amdgpu driver provides a sysfs API for estimating how much data
1271  * has been received and sent by the GPU in the last second through PCIe.
1272  * The file pcie_bw is used for this.
1273  * The Perf counters count the number of received and sent messages and return
1274  * those values, as well as the maximum payload size of a PCIe packet (mps).
1275  * Note that it is not possible to easily and quickly obtain the size of each
1276  * packet transmitted, so we output the max payload size (mps) to allow for
1277  * quick estimation of the PCIe bandwidth usage
1278  */
1279 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1280                 struct device_attribute *attr,
1281                 char *buf)
1282 {
1283         struct drm_device *ddev = dev_get_drvdata(dev);
1284         struct amdgpu_device *adev = ddev->dev_private;
1285         uint64_t count0, count1;
1286
1287         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1288         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1289                         count0, count1, pcie_get_mps(adev->pdev));
1290 }
1291
1292 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1293 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1294                    amdgpu_get_dpm_forced_performance_level,
1295                    amdgpu_set_dpm_forced_performance_level);
1296 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1297 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1298 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1299                 amdgpu_get_pp_force_state,
1300                 amdgpu_set_pp_force_state);
1301 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1302                 amdgpu_get_pp_table,
1303                 amdgpu_set_pp_table);
1304 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1305                 amdgpu_get_pp_dpm_sclk,
1306                 amdgpu_set_pp_dpm_sclk);
1307 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1308                 amdgpu_get_pp_dpm_mclk,
1309                 amdgpu_set_pp_dpm_mclk);
1310 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1311                 amdgpu_get_pp_dpm_socclk,
1312                 amdgpu_set_pp_dpm_socclk);
1313 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1314                 amdgpu_get_pp_dpm_fclk,
1315                 amdgpu_set_pp_dpm_fclk);
1316 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1317                 amdgpu_get_pp_dpm_dcefclk,
1318                 amdgpu_set_pp_dpm_dcefclk);
1319 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1320                 amdgpu_get_pp_dpm_pcie,
1321                 amdgpu_set_pp_dpm_pcie);
1322 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1323                 amdgpu_get_pp_sclk_od,
1324                 amdgpu_set_pp_sclk_od);
1325 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1326                 amdgpu_get_pp_mclk_od,
1327                 amdgpu_set_pp_mclk_od);
1328 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1329                 amdgpu_get_pp_power_profile_mode,
1330                 amdgpu_set_pp_power_profile_mode);
1331 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1332                 amdgpu_get_pp_od_clk_voltage,
1333                 amdgpu_set_pp_od_clk_voltage);
1334 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1335                 amdgpu_get_busy_percent, NULL);
1336 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1337 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1338                 amdgpu_get_ppfeature_status,
1339                 amdgpu_set_ppfeature_status);
1340
1341 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1342                                       struct device_attribute *attr,
1343                                       char *buf)
1344 {
1345         struct amdgpu_device *adev = dev_get_drvdata(dev);
1346         struct drm_device *ddev = adev->ddev;
1347         int r, temp, size = sizeof(temp);
1348
1349         /* Can't get temperature when the card is off */
1350         if  ((adev->flags & AMD_IS_PX) &&
1351              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1352                 return -EINVAL;
1353
1354         /* get the temperature */
1355         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1356                                    (void *)&temp, &size);
1357         if (r)
1358                 return r;
1359
1360         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1361 }
1362
1363 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1364                                              struct device_attribute *attr,
1365                                              char *buf)
1366 {
1367         struct amdgpu_device *adev = dev_get_drvdata(dev);
1368         int hyst = to_sensor_dev_attr(attr)->index;
1369         int temp;
1370
1371         if (hyst)
1372                 temp = adev->pm.dpm.thermal.min_temp;
1373         else
1374                 temp = adev->pm.dpm.thermal.max_temp;
1375
1376         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1377 }
1378
1379 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1380                                             struct device_attribute *attr,
1381                                             char *buf)
1382 {
1383         struct amdgpu_device *adev = dev_get_drvdata(dev);
1384         u32 pwm_mode = 0;
1385
1386         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1387                 return -EINVAL;
1388
1389         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1390
1391         return sprintf(buf, "%i\n", pwm_mode);
1392 }
1393
1394 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1395                                             struct device_attribute *attr,
1396                                             const char *buf,
1397                                             size_t count)
1398 {
1399         struct amdgpu_device *adev = dev_get_drvdata(dev);
1400         int err;
1401         int value;
1402
1403         /* Can't adjust fan when the card is off */
1404         if  ((adev->flags & AMD_IS_PX) &&
1405              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1406                 return -EINVAL;
1407
1408         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1409                 return -EINVAL;
1410
1411         err = kstrtoint(buf, 10, &value);
1412         if (err)
1413                 return err;
1414
1415         amdgpu_dpm_set_fan_control_mode(adev, value);
1416
1417         return count;
1418 }
1419
1420 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1421                                          struct device_attribute *attr,
1422                                          char *buf)
1423 {
1424         return sprintf(buf, "%i\n", 0);
1425 }
1426
1427 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1428                                          struct device_attribute *attr,
1429                                          char *buf)
1430 {
1431         return sprintf(buf, "%i\n", 255);
1432 }
1433
1434 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1435                                      struct device_attribute *attr,
1436                                      const char *buf, size_t count)
1437 {
1438         struct amdgpu_device *adev = dev_get_drvdata(dev);
1439         int err;
1440         u32 value;
1441         u32 pwm_mode;
1442
1443         /* Can't adjust fan when the card is off */
1444         if  ((adev->flags & AMD_IS_PX) &&
1445              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1446                 return -EINVAL;
1447
1448         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1449         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1450                 pr_info("manual fan speed control should be enabled first\n");
1451                 return -EINVAL;
1452         }
1453
1454         err = kstrtou32(buf, 10, &value);
1455         if (err)
1456                 return err;
1457
1458         value = (value * 100) / 255;
1459
1460         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1461                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1462                 if (err)
1463                         return err;
1464         }
1465
1466         return count;
1467 }
1468
1469 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1470                                      struct device_attribute *attr,
1471                                      char *buf)
1472 {
1473         struct amdgpu_device *adev = dev_get_drvdata(dev);
1474         int err;
1475         u32 speed = 0;
1476
1477         /* Can't adjust fan when the card is off */
1478         if  ((adev->flags & AMD_IS_PX) &&
1479              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1480                 return -EINVAL;
1481
1482         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1483                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1484                 if (err)
1485                         return err;
1486         }
1487
1488         speed = (speed * 255) / 100;
1489
1490         return sprintf(buf, "%i\n", speed);
1491 }
1492
1493 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1494                                            struct device_attribute *attr,
1495                                            char *buf)
1496 {
1497         struct amdgpu_device *adev = dev_get_drvdata(dev);
1498         int err;
1499         u32 speed = 0;
1500
1501         /* Can't adjust fan when the card is off */
1502         if  ((adev->flags & AMD_IS_PX) &&
1503              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1504                 return -EINVAL;
1505
1506         if (is_support_sw_smu(adev)) {
1507                 err = smu_get_current_rpm(&adev->smu, &speed);
1508                 if (err)
1509                         return err;
1510         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1511                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1512                 if (err)
1513                         return err;
1514         }
1515
1516         return sprintf(buf, "%i\n", speed);
1517 }
1518
1519 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1520                                          struct device_attribute *attr,
1521                                          char *buf)
1522 {
1523         struct amdgpu_device *adev = dev_get_drvdata(dev);
1524         u32 min_rpm = 0;
1525         u32 size = sizeof(min_rpm);
1526         int r;
1527
1528         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1529                                    (void *)&min_rpm, &size);
1530         if (r)
1531                 return r;
1532
1533         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1534 }
1535
1536 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1537                                          struct device_attribute *attr,
1538                                          char *buf)
1539 {
1540         struct amdgpu_device *adev = dev_get_drvdata(dev);
1541         u32 max_rpm = 0;
1542         u32 size = sizeof(max_rpm);
1543         int r;
1544
1545         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1546                                    (void *)&max_rpm, &size);
1547         if (r)
1548                 return r;
1549
1550         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1551 }
1552
1553 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1554                                            struct device_attribute *attr,
1555                                            char *buf)
1556 {
1557         struct amdgpu_device *adev = dev_get_drvdata(dev);
1558         int err;
1559         u32 rpm = 0;
1560
1561         /* Can't adjust fan when the card is off */
1562         if  ((adev->flags & AMD_IS_PX) &&
1563              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1564                 return -EINVAL;
1565
1566         if (is_support_sw_smu(adev)) {
1567                 err = smu_get_current_rpm(&adev->smu, &rpm);
1568                 if (err)
1569                         return err;
1570         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1571                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1572                 if (err)
1573                         return err;
1574         }
1575
1576         return sprintf(buf, "%i\n", rpm);
1577 }
1578
1579 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1580                                      struct device_attribute *attr,
1581                                      const char *buf, size_t count)
1582 {
1583         struct amdgpu_device *adev = dev_get_drvdata(dev);
1584         int err;
1585         u32 value;
1586         u32 pwm_mode;
1587
1588         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1589         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1590                 return -ENODATA;
1591
1592         /* Can't adjust fan when the card is off */
1593         if  ((adev->flags & AMD_IS_PX) &&
1594              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1595                 return -EINVAL;
1596
1597         err = kstrtou32(buf, 10, &value);
1598         if (err)
1599                 return err;
1600
1601         if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1602                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1603                 if (err)
1604                         return err;
1605         }
1606
1607         return count;
1608 }
1609
1610 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1611                                             struct device_attribute *attr,
1612                                             char *buf)
1613 {
1614         struct amdgpu_device *adev = dev_get_drvdata(dev);
1615         u32 pwm_mode = 0;
1616
1617         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1618                 return -EINVAL;
1619
1620         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1621
1622         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1623 }
1624
1625 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1626                                             struct device_attribute *attr,
1627                                             const char *buf,
1628                                             size_t count)
1629 {
1630         struct amdgpu_device *adev = dev_get_drvdata(dev);
1631         int err;
1632         int value;
1633         u32 pwm_mode;
1634
1635         /* Can't adjust fan when the card is off */
1636         if  ((adev->flags & AMD_IS_PX) &&
1637              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1638                 return -EINVAL;
1639
1640         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1641                 return -EINVAL;
1642
1643         err = kstrtoint(buf, 10, &value);
1644         if (err)
1645                 return err;
1646
1647         if (value == 0)
1648                 pwm_mode = AMD_FAN_CTRL_AUTO;
1649         else if (value == 1)
1650                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1651         else
1652                 return -EINVAL;
1653
1654         amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1655
1656         return count;
1657 }
1658
1659 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1660                                         struct device_attribute *attr,
1661                                         char *buf)
1662 {
1663         struct amdgpu_device *adev = dev_get_drvdata(dev);
1664         struct drm_device *ddev = adev->ddev;
1665         u32 vddgfx;
1666         int r, size = sizeof(vddgfx);
1667
1668         /* Can't get voltage when the card is off */
1669         if  ((adev->flags & AMD_IS_PX) &&
1670              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1671                 return -EINVAL;
1672
1673         /* get the voltage */
1674         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1675                                    (void *)&vddgfx, &size);
1676         if (r)
1677                 return r;
1678
1679         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1680 }
1681
1682 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1683                                               struct device_attribute *attr,
1684                                               char *buf)
1685 {
1686         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1687 }
1688
1689 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1690                                        struct device_attribute *attr,
1691                                        char *buf)
1692 {
1693         struct amdgpu_device *adev = dev_get_drvdata(dev);
1694         struct drm_device *ddev = adev->ddev;
1695         u32 vddnb;
1696         int r, size = sizeof(vddnb);
1697
1698         /* only APUs have vddnb */
1699         if  (!(adev->flags & AMD_IS_APU))
1700                 return -EINVAL;
1701
1702         /* Can't get voltage when the card is off */
1703         if  ((adev->flags & AMD_IS_PX) &&
1704              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1705                 return -EINVAL;
1706
1707         /* get the voltage */
1708         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1709                                    (void *)&vddnb, &size);
1710         if (r)
1711                 return r;
1712
1713         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1714 }
1715
1716 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1717                                               struct device_attribute *attr,
1718                                               char *buf)
1719 {
1720         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1721 }
1722
1723 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1724                                            struct device_attribute *attr,
1725                                            char *buf)
1726 {
1727         struct amdgpu_device *adev = dev_get_drvdata(dev);
1728         struct drm_device *ddev = adev->ddev;
1729         u32 query = 0;
1730         int r, size = sizeof(u32);
1731         unsigned uw;
1732
1733         /* Can't get power when the card is off */
1734         if  ((adev->flags & AMD_IS_PX) &&
1735              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1736                 return -EINVAL;
1737
1738         /* get the voltage */
1739         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1740                                    (void *)&query, &size);
1741         if (r)
1742                 return r;
1743
1744         /* convert to microwatts */
1745         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1746
1747         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1748 }
1749
1750 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1751                                          struct device_attribute *attr,
1752                                          char *buf)
1753 {
1754         return sprintf(buf, "%i\n", 0);
1755 }
1756
1757 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1758                                          struct device_attribute *attr,
1759                                          char *buf)
1760 {
1761         struct amdgpu_device *adev = dev_get_drvdata(dev);
1762         uint32_t limit = 0;
1763
1764         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1765                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1766                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1767         } else {
1768                 return snprintf(buf, PAGE_SIZE, "\n");
1769         }
1770 }
1771
1772 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1773                                          struct device_attribute *attr,
1774                                          char *buf)
1775 {
1776         struct amdgpu_device *adev = dev_get_drvdata(dev);
1777         uint32_t limit = 0;
1778
1779         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1780                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1781                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1782         } else {
1783                 return snprintf(buf, PAGE_SIZE, "\n");
1784         }
1785 }
1786
1787
1788 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1789                 struct device_attribute *attr,
1790                 const char *buf,
1791                 size_t count)
1792 {
1793         struct amdgpu_device *adev = dev_get_drvdata(dev);
1794         int err;
1795         u32 value;
1796
1797         err = kstrtou32(buf, 10, &value);
1798         if (err)
1799                 return err;
1800
1801         value = value / 1000000; /* convert to Watt */
1802         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1803                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1804                 if (err)
1805                         return err;
1806         } else {
1807                 return -EINVAL;
1808         }
1809
1810         return count;
1811 }
1812
1813 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
1814                                       struct device_attribute *attr,
1815                                       char *buf)
1816 {
1817         struct amdgpu_device *adev = dev_get_drvdata(dev);
1818         struct drm_device *ddev = adev->ddev;
1819         uint32_t sclk;
1820         int r, size = sizeof(sclk);
1821
1822         /* Can't get voltage when the card is off */
1823         if  ((adev->flags & AMD_IS_PX) &&
1824              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1825                 return -EINVAL;
1826
1827         /* sanity check PP is enabled */
1828         if (!(adev->powerplay.pp_funcs &&
1829               adev->powerplay.pp_funcs->read_sensor))
1830               return -EINVAL;
1831
1832         /* get the sclk */
1833         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
1834                                    (void *)&sclk, &size);
1835         if (r)
1836                 return r;
1837
1838         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
1839 }
1840
1841 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
1842                                             struct device_attribute *attr,
1843                                             char *buf)
1844 {
1845         return snprintf(buf, PAGE_SIZE, "sclk\n");
1846 }
1847
1848 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
1849                                       struct device_attribute *attr,
1850                                       char *buf)
1851 {
1852         struct amdgpu_device *adev = dev_get_drvdata(dev);
1853         struct drm_device *ddev = adev->ddev;
1854         uint32_t mclk;
1855         int r, size = sizeof(mclk);
1856
1857         /* Can't get voltage when the card is off */
1858         if  ((adev->flags & AMD_IS_PX) &&
1859              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1860                 return -EINVAL;
1861
1862         /* sanity check PP is enabled */
1863         if (!(adev->powerplay.pp_funcs &&
1864               adev->powerplay.pp_funcs->read_sensor))
1865               return -EINVAL;
1866
1867         /* get the sclk */
1868         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
1869                                    (void *)&mclk, &size);
1870         if (r)
1871                 return r;
1872
1873         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
1874 }
1875
1876 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
1877                                             struct device_attribute *attr,
1878                                             char *buf)
1879 {
1880         return snprintf(buf, PAGE_SIZE, "mclk\n");
1881 }
1882
1883 /**
1884  * DOC: hwmon
1885  *
1886  * The amdgpu driver exposes the following sensor interfaces:
1887  *
1888  * - GPU temperature (via the on-die sensor)
1889  *
1890  * - GPU voltage
1891  *
1892  * - Northbridge voltage (APUs only)
1893  *
1894  * - GPU power
1895  *
1896  * - GPU fan
1897  *
1898  * - GPU gfx/compute engine clock
1899  *
1900  * - GPU memory clock (dGPU only)
1901  *
1902  * hwmon interfaces for GPU temperature:
1903  *
1904  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1905  *
1906  * - temp1_crit: temperature critical max value in millidegrees Celsius
1907  *
1908  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1909  *
1910  * hwmon interfaces for GPU voltage:
1911  *
1912  * - in0_input: the voltage on the GPU in millivolts
1913  *
1914  * - in1_input: the voltage on the Northbridge in millivolts
1915  *
1916  * hwmon interfaces for GPU power:
1917  *
1918  * - power1_average: average power used by the GPU in microWatts
1919  *
1920  * - power1_cap_min: minimum cap supported in microWatts
1921  *
1922  * - power1_cap_max: maximum cap supported in microWatts
1923  *
1924  * - power1_cap: selected power cap in microWatts
1925  *
1926  * hwmon interfaces for GPU fan:
1927  *
1928  * - pwm1: pulse width modulation fan level (0-255)
1929  *
1930  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1931  *
1932  * - pwm1_min: pulse width modulation fan control minimum level (0)
1933  *
1934  * - pwm1_max: pulse width modulation fan control maximum level (255)
1935  *
1936  * - fan1_min: an minimum value Unit: revolution/min (RPM)
1937  *
1938  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
1939  *
1940  * - fan1_input: fan speed in RPM
1941  *
1942  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
1943  *
1944  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
1945  *
1946  * hwmon interfaces for GPU clocks:
1947  *
1948  * - freq1_input: the gfx/compute clock in hertz
1949  *
1950  * - freq2_input: the memory clock in hertz
1951  *
1952  * You can use hwmon tools like sensors to view this information on your system.
1953  *
1954  */
1955
1956 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1957 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1958 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1959 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1960 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1961 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1962 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1963 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1964 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
1965 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
1966 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
1967 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
1968 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1969 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1970 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1971 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1972 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1973 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1974 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1975 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1976 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
1977 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
1978 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
1979 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
1980
1981 static struct attribute *hwmon_attributes[] = {
1982         &sensor_dev_attr_temp1_input.dev_attr.attr,
1983         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1984         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1985         &sensor_dev_attr_pwm1.dev_attr.attr,
1986         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1987         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1988         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1989         &sensor_dev_attr_fan1_input.dev_attr.attr,
1990         &sensor_dev_attr_fan1_min.dev_attr.attr,
1991         &sensor_dev_attr_fan1_max.dev_attr.attr,
1992         &sensor_dev_attr_fan1_target.dev_attr.attr,
1993         &sensor_dev_attr_fan1_enable.dev_attr.attr,
1994         &sensor_dev_attr_in0_input.dev_attr.attr,
1995         &sensor_dev_attr_in0_label.dev_attr.attr,
1996         &sensor_dev_attr_in1_input.dev_attr.attr,
1997         &sensor_dev_attr_in1_label.dev_attr.attr,
1998         &sensor_dev_attr_power1_average.dev_attr.attr,
1999         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2000         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2001         &sensor_dev_attr_power1_cap.dev_attr.attr,
2002         &sensor_dev_attr_freq1_input.dev_attr.attr,
2003         &sensor_dev_attr_freq1_label.dev_attr.attr,
2004         &sensor_dev_attr_freq2_input.dev_attr.attr,
2005         &sensor_dev_attr_freq2_label.dev_attr.attr,
2006         NULL
2007 };
2008
2009 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2010                                         struct attribute *attr, int index)
2011 {
2012         struct device *dev = kobj_to_dev(kobj);
2013         struct amdgpu_device *adev = dev_get_drvdata(dev);
2014         umode_t effective_mode = attr->mode;
2015
2016         /* Skip fan attributes if fan is not present */
2017         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2018             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2019             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2020             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2021             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2022             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2023             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2024             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2025             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2026                 return 0;
2027
2028         /* Skip fan attributes on APU */
2029         if ((adev->flags & AMD_IS_APU) &&
2030             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2031              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2032              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2033              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2034              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2035              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2036              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2037              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2038              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2039                 return 0;
2040
2041         /* Skip limit attributes if DPM is not enabled */
2042         if (!adev->pm.dpm_enabled &&
2043             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2044              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2045              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2046              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2047              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2048              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2049              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2050              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2051              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2052              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2053              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2054                 return 0;
2055
2056         if (!is_support_sw_smu(adev)) {
2057                 /* mask fan attributes if we have no bindings for this asic to expose */
2058                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2059                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2060                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2061                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2062                         effective_mode &= ~S_IRUGO;
2063
2064                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2065                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2066                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2067                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2068                         effective_mode &= ~S_IWUSR;
2069         }
2070
2071         if ((adev->flags & AMD_IS_APU) &&
2072             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2073              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2074              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2075              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2076                 return 0;
2077
2078         if (!is_support_sw_smu(adev)) {
2079                 /* hide max/min values if we can't both query and manage the fan */
2080                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2081                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2082                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2083                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2084                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2085                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2086                         return 0;
2087
2088                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2089                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2090                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2091                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2092                         return 0;
2093         }
2094
2095         /* only APUs have vddnb */
2096         if (!(adev->flags & AMD_IS_APU) &&
2097             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2098              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2099                 return 0;
2100
2101         /* no mclk on APUs */
2102         if ((adev->flags & AMD_IS_APU) &&
2103             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2104              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2105                 return 0;
2106
2107         return effective_mode;
2108 }
2109
2110 static const struct attribute_group hwmon_attrgroup = {
2111         .attrs = hwmon_attributes,
2112         .is_visible = hwmon_attributes_visible,
2113 };
2114
2115 static const struct attribute_group *hwmon_groups[] = {
2116         &hwmon_attrgroup,
2117         NULL
2118 };
2119
2120 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2121 {
2122         struct amdgpu_device *adev =
2123                 container_of(work, struct amdgpu_device,
2124                              pm.dpm.thermal.work);
2125         /* switch to the thermal state */
2126         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2127         int temp, size = sizeof(temp);
2128
2129         if (!adev->pm.dpm_enabled)
2130                 return;
2131
2132         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2133                                     (void *)&temp, &size)) {
2134                 if (temp < adev->pm.dpm.thermal.min_temp)
2135                         /* switch back the user state */
2136                         dpm_state = adev->pm.dpm.user_state;
2137         } else {
2138                 if (adev->pm.dpm.thermal.high_to_low)
2139                         /* switch back the user state */
2140                         dpm_state = adev->pm.dpm.user_state;
2141         }
2142         mutex_lock(&adev->pm.mutex);
2143         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2144                 adev->pm.dpm.thermal_active = true;
2145         else
2146                 adev->pm.dpm.thermal_active = false;
2147         adev->pm.dpm.state = dpm_state;
2148         mutex_unlock(&adev->pm.mutex);
2149
2150         amdgpu_pm_compute_clocks(adev);
2151 }
2152
2153 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2154                                                      enum amd_pm_state_type dpm_state)
2155 {
2156         int i;
2157         struct amdgpu_ps *ps;
2158         u32 ui_class;
2159         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2160                 true : false;
2161
2162         /* check if the vblank period is too short to adjust the mclk */
2163         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2164                 if (amdgpu_dpm_vblank_too_short(adev))
2165                         single_display = false;
2166         }
2167
2168         /* certain older asics have a separare 3D performance state,
2169          * so try that first if the user selected performance
2170          */
2171         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2172                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2173         /* balanced states don't exist at the moment */
2174         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2175                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2176
2177 restart_search:
2178         /* Pick the best power state based on current conditions */
2179         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2180                 ps = &adev->pm.dpm.ps[i];
2181                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2182                 switch (dpm_state) {
2183                 /* user states */
2184                 case POWER_STATE_TYPE_BATTERY:
2185                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2186                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2187                                         if (single_display)
2188                                                 return ps;
2189                                 } else
2190                                         return ps;
2191                         }
2192                         break;
2193                 case POWER_STATE_TYPE_BALANCED:
2194                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2195                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2196                                         if (single_display)
2197                                                 return ps;
2198                                 } else
2199                                         return ps;
2200                         }
2201                         break;
2202                 case POWER_STATE_TYPE_PERFORMANCE:
2203                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2204                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2205                                         if (single_display)
2206                                                 return ps;
2207                                 } else
2208                                         return ps;
2209                         }
2210                         break;
2211                 /* internal states */
2212                 case POWER_STATE_TYPE_INTERNAL_UVD:
2213                         if (adev->pm.dpm.uvd_ps)
2214                                 return adev->pm.dpm.uvd_ps;
2215                         else
2216                                 break;
2217                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2218                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2219                                 return ps;
2220                         break;
2221                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2222                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2223                                 return ps;
2224                         break;
2225                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2226                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2227                                 return ps;
2228                         break;
2229                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2230                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2231                                 return ps;
2232                         break;
2233                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2234                         return adev->pm.dpm.boot_ps;
2235                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2236                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2237                                 return ps;
2238                         break;
2239                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2240                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2241                                 return ps;
2242                         break;
2243                 case POWER_STATE_TYPE_INTERNAL_ULV:
2244                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2245                                 return ps;
2246                         break;
2247                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2248                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2249                                 return ps;
2250                         break;
2251                 default:
2252                         break;
2253                 }
2254         }
2255         /* use a fallback state if we didn't match */
2256         switch (dpm_state) {
2257         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2258                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2259                 goto restart_search;
2260         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2261         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2262         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2263                 if (adev->pm.dpm.uvd_ps) {
2264                         return adev->pm.dpm.uvd_ps;
2265                 } else {
2266                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2267                         goto restart_search;
2268                 }
2269         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2270                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2271                 goto restart_search;
2272         case POWER_STATE_TYPE_INTERNAL_ACPI:
2273                 dpm_state = POWER_STATE_TYPE_BATTERY;
2274                 goto restart_search;
2275         case POWER_STATE_TYPE_BATTERY:
2276         case POWER_STATE_TYPE_BALANCED:
2277         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2278                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2279                 goto restart_search;
2280         default:
2281                 break;
2282         }
2283
2284         return NULL;
2285 }
2286
2287 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2288 {
2289         struct amdgpu_ps *ps;
2290         enum amd_pm_state_type dpm_state;
2291         int ret;
2292         bool equal = false;
2293
2294         /* if dpm init failed */
2295         if (!adev->pm.dpm_enabled)
2296                 return;
2297
2298         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2299                 /* add other state override checks here */
2300                 if ((!adev->pm.dpm.thermal_active) &&
2301                     (!adev->pm.dpm.uvd_active))
2302                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2303         }
2304         dpm_state = adev->pm.dpm.state;
2305
2306         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2307         if (ps)
2308                 adev->pm.dpm.requested_ps = ps;
2309         else
2310                 return;
2311
2312         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2313                 printk("switching from power state:\n");
2314                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2315                 printk("switching to power state:\n");
2316                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2317         }
2318
2319         /* update whether vce is active */
2320         ps->vce_active = adev->pm.dpm.vce_active;
2321         if (adev->powerplay.pp_funcs->display_configuration_changed)
2322                 amdgpu_dpm_display_configuration_changed(adev);
2323
2324         ret = amdgpu_dpm_pre_set_power_state(adev);
2325         if (ret)
2326                 return;
2327
2328         if (adev->powerplay.pp_funcs->check_state_equal) {
2329                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2330                         equal = false;
2331         }
2332
2333         if (equal)
2334                 return;
2335
2336         amdgpu_dpm_set_power_state(adev);
2337         amdgpu_dpm_post_set_power_state(adev);
2338
2339         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2340         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2341
2342         if (adev->powerplay.pp_funcs->force_performance_level) {
2343                 if (adev->pm.dpm.thermal_active) {
2344                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2345                         /* force low perf level for thermal */
2346                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2347                         /* save the user's level */
2348                         adev->pm.dpm.forced_level = level;
2349                 } else {
2350                         /* otherwise, user selected level */
2351                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2352                 }
2353         }
2354 }
2355
2356 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2357 {
2358         int ret = 0;
2359         if (is_support_sw_smu(adev)) {
2360             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2361             if (ret)
2362                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2363                           enable ? "true" : "false", ret);
2364         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2365                 /* enable/disable UVD */
2366                 mutex_lock(&adev->pm.mutex);
2367                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2368                 mutex_unlock(&adev->pm.mutex);
2369         }
2370         /* enable/disable Low Memory PState for UVD (4k videos) */
2371         if (adev->asic_type == CHIP_STONEY &&
2372                 adev->uvd.decode_image_width >= WIDTH_4K) {
2373                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2374
2375                 if (hwmgr && hwmgr->hwmgr_func &&
2376                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2377                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2378                                                                !enable,
2379                                                                true);
2380         }
2381 }
2382
2383 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2384 {
2385         int ret = 0;
2386         if (is_support_sw_smu(adev)) {
2387             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2388             if (ret)
2389                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2390                           enable ? "true" : "false", ret);
2391         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2392                 /* enable/disable VCE */
2393                 mutex_lock(&adev->pm.mutex);
2394                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2395                 mutex_unlock(&adev->pm.mutex);
2396         }
2397 }
2398
2399 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2400 {
2401         int i;
2402
2403         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2404                 return;
2405
2406         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2407                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2408
2409 }
2410
2411 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2412 {
2413         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2414         int ret;
2415
2416         if (adev->pm.sysfs_initialized)
2417                 return 0;
2418
2419         if (adev->pm.dpm_enabled == 0)
2420                 return 0;
2421
2422         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2423                                                                    DRIVER_NAME, adev,
2424                                                                    hwmon_groups);
2425         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2426                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2427                 dev_err(adev->dev,
2428                         "Unable to register hwmon device: %d\n", ret);
2429                 return ret;
2430         }
2431
2432         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2433         if (ret) {
2434                 DRM_ERROR("failed to create device file for dpm state\n");
2435                 return ret;
2436         }
2437         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2438         if (ret) {
2439                 DRM_ERROR("failed to create device file for dpm state\n");
2440                 return ret;
2441         }
2442
2443
2444         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2445         if (ret) {
2446                 DRM_ERROR("failed to create device file pp_num_states\n");
2447                 return ret;
2448         }
2449         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2450         if (ret) {
2451                 DRM_ERROR("failed to create device file pp_cur_state\n");
2452                 return ret;
2453         }
2454         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2455         if (ret) {
2456                 DRM_ERROR("failed to create device file pp_force_state\n");
2457                 return ret;
2458         }
2459         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2460         if (ret) {
2461                 DRM_ERROR("failed to create device file pp_table\n");
2462                 return ret;
2463         }
2464
2465         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2466         if (ret) {
2467                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2468                 return ret;
2469         }
2470         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2471         if (ret) {
2472                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2473                 return ret;
2474         }
2475         if (adev->asic_type >= CHIP_VEGA10) {
2476                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2477                 if (ret) {
2478                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2479                         return ret;
2480                 }
2481                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2482                 if (ret) {
2483                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2484                         return ret;
2485                 }
2486         }
2487         if (adev->asic_type >= CHIP_VEGA20) {
2488                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2489                 if (ret) {
2490                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2491                         return ret;
2492                 }
2493         }
2494         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2495         if (ret) {
2496                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2497                 return ret;
2498         }
2499         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2500         if (ret) {
2501                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2502                 return ret;
2503         }
2504         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2505         if (ret) {
2506                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2507                 return ret;
2508         }
2509         ret = device_create_file(adev->dev,
2510                         &dev_attr_pp_power_profile_mode);
2511         if (ret) {
2512                 DRM_ERROR("failed to create device file "
2513                                 "pp_power_profile_mode\n");
2514                 return ret;
2515         }
2516         if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
2517                 ret = device_create_file(adev->dev,
2518                                 &dev_attr_pp_od_clk_voltage);
2519                 if (ret) {
2520                         DRM_ERROR("failed to create device file "
2521                                         "pp_od_clk_voltage\n");
2522                         return ret;
2523                 }
2524         }
2525         ret = device_create_file(adev->dev,
2526                         &dev_attr_gpu_busy_percent);
2527         if (ret) {
2528                 DRM_ERROR("failed to create device file "
2529                                 "gpu_busy_level\n");
2530                 return ret;
2531         }
2532         /* PCIe Perf counters won't work on APU nodes */
2533         if (!(adev->flags & AMD_IS_APU)) {
2534                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2535                 if (ret) {
2536                         DRM_ERROR("failed to create device file pcie_bw\n");
2537                         return ret;
2538                 }
2539         }
2540         ret = amdgpu_debugfs_pm_init(adev);
2541         if (ret) {
2542                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2543                 return ret;
2544         }
2545
2546         if ((adev->asic_type >= CHIP_VEGA10) &&
2547             !(adev->flags & AMD_IS_APU)) {
2548                 ret = device_create_file(adev->dev,
2549                                 &dev_attr_ppfeatures);
2550                 if (ret) {
2551                         DRM_ERROR("failed to create device file "
2552                                         "ppfeatures\n");
2553                         return ret;
2554                 }
2555         }
2556
2557         adev->pm.sysfs_initialized = true;
2558
2559         return 0;
2560 }
2561
2562 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2563 {
2564         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2565
2566         if (adev->pm.dpm_enabled == 0)
2567                 return;
2568
2569         if (adev->pm.int_hwmon_dev)
2570                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2571         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2572         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2573
2574         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2575         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2576         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2577         device_remove_file(adev->dev, &dev_attr_pp_table);
2578
2579         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2580         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2581         if (adev->asic_type >= CHIP_VEGA10) {
2582                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2583                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2584         }
2585         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2586         if (adev->asic_type >= CHIP_VEGA20)
2587                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2588         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2589         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2590         device_remove_file(adev->dev,
2591                         &dev_attr_pp_power_profile_mode);
2592         if (hwmgr->od_enabled)
2593                 device_remove_file(adev->dev,
2594                                 &dev_attr_pp_od_clk_voltage);
2595         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2596         if (!(adev->flags & AMD_IS_APU))
2597                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2598         if ((adev->asic_type >= CHIP_VEGA10) &&
2599             !(adev->flags & AMD_IS_APU))
2600                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2601 }
2602
2603 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2604 {
2605         int i = 0;
2606
2607         if (!adev->pm.dpm_enabled)
2608                 return;
2609
2610         if (adev->mode_info.num_crtc)
2611                 amdgpu_display_bandwidth_update(adev);
2612
2613         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2614                 struct amdgpu_ring *ring = adev->rings[i];
2615                 if (ring && ring->sched.ready)
2616                         amdgpu_fence_wait_empty(ring);
2617         }
2618
2619         if (is_support_sw_smu(adev)) {
2620                 struct smu_context *smu = &adev->smu;
2621                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2622                 mutex_lock(&(smu->mutex));
2623                 smu_handle_task(&adev->smu,
2624                                 smu_dpm->dpm_level,
2625                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2626                 mutex_unlock(&(smu->mutex));
2627         } else {
2628                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2629                         if (!amdgpu_device_has_dc_support(adev)) {
2630                                 mutex_lock(&adev->pm.mutex);
2631                                 amdgpu_dpm_get_active_displays(adev);
2632                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2633                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2634                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2635                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2636                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
2637                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
2638                                 if (adev->powerplay.pp_funcs->display_configuration_change)
2639                                         adev->powerplay.pp_funcs->display_configuration_change(
2640                                                                         adev->powerplay.pp_handle,
2641                                                                         &adev->pm.pm_display_cfg);
2642                                 mutex_unlock(&adev->pm.mutex);
2643                         }
2644                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2645                 } else {
2646                         mutex_lock(&adev->pm.mutex);
2647                         amdgpu_dpm_get_active_displays(adev);
2648                         amdgpu_dpm_change_power_state_locked(adev);
2649                         mutex_unlock(&adev->pm.mutex);
2650                 }
2651         }
2652 }
2653
2654 /*
2655  * Debugfs info
2656  */
2657 #if defined(CONFIG_DEBUG_FS)
2658
2659 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2660 {
2661         uint32_t value;
2662         uint64_t value64;
2663         uint32_t query = 0;
2664         int size;
2665
2666         /* GPU Clocks */
2667         size = sizeof(value);
2668         seq_printf(m, "GFX Clocks and Power:\n");
2669         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2670                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2671         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2672                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2673         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2674                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2675         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2676                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2677         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2678                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2679         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2680                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2681         size = sizeof(uint32_t);
2682         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2683                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2684         size = sizeof(value);
2685         seq_printf(m, "\n");
2686
2687         /* GPU Temp */
2688         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2689                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2690
2691         /* GPU Load */
2692         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2693                 seq_printf(m, "GPU Load: %u %%\n", value);
2694         seq_printf(m, "\n");
2695
2696         /* SMC feature mask */
2697         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
2698                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
2699
2700         /* UVD clocks */
2701         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2702                 if (!value) {
2703                         seq_printf(m, "UVD: Disabled\n");
2704                 } else {
2705                         seq_printf(m, "UVD: Enabled\n");
2706                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2707                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2708                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2709                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2710                 }
2711         }
2712         seq_printf(m, "\n");
2713
2714         /* VCE clocks */
2715         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2716                 if (!value) {
2717                         seq_printf(m, "VCE: Disabled\n");
2718                 } else {
2719                         seq_printf(m, "VCE: Enabled\n");
2720                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2721                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2722                 }
2723         }
2724
2725         return 0;
2726 }
2727
2728 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2729 {
2730         int i;
2731
2732         for (i = 0; clocks[i].flag; i++)
2733                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2734                            (flags & clocks[i].flag) ? "On" : "Off");
2735 }
2736
2737 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2738 {
2739         struct drm_info_node *node = (struct drm_info_node *) m->private;
2740         struct drm_device *dev = node->minor->dev;
2741         struct amdgpu_device *adev = dev->dev_private;
2742         struct drm_device *ddev = adev->ddev;
2743         u32 flags = 0;
2744
2745         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2746         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2747         amdgpu_parse_cg_state(m, flags);
2748         seq_printf(m, "\n");
2749
2750         if (!adev->pm.dpm_enabled) {
2751                 seq_printf(m, "dpm not enabled\n");
2752                 return 0;
2753         }
2754         if  ((adev->flags & AMD_IS_PX) &&
2755              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2756                 seq_printf(m, "PX asic powered off\n");
2757         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2758                 mutex_lock(&adev->pm.mutex);
2759                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2760                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2761                 else
2762                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2763                 mutex_unlock(&adev->pm.mutex);
2764         } else {
2765                 return amdgpu_debugfs_pm_info_pp(m, adev);
2766         }
2767
2768         return 0;
2769 }
2770
2771 static const struct drm_info_list amdgpu_pm_info_list[] = {
2772         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2773 };
2774 #endif
2775
2776 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2777 {
2778 #if defined(CONFIG_DEBUG_FS)
2779         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2780 #else
2781         return 0;
2782 #endif
2783 }