drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {0, NULL},
  68 };
  69
  70 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  71 {
  72         if (adev->pm.dpm_enabled) {
  73                 mutex_lock(&adev->pm.mutex);
  74                 if (power_supply_is_system_supplied() > 0)
  75                         adev->pm.ac_power = true;
  76                 else
  77                         adev->pm.ac_power = false;
  78                 if (adev->powerplay.pp_funcs->enable_bapm)
  79                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  80                 mutex_unlock(&adev->pm.mutex);
  81         }
  82 }
  83
  84 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  85                            void *data, uint32_t *size)
  86 {
  87         int ret = 0;
  88
  89         if (!data || !size)
  90                 return -EINVAL;
  91
  92         if (is_support_sw_smu(adev))
  93                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
  94         else {
  95                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
  96                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
  97                                                                     sensor, data, size);
  98                 else
  99                         ret = -EINVAL;
 100         }
 101
 102         return ret;
 103 }
 104
 105 /**
 106  * DOC: power_dpm_state
 107  *
 108  * The power_dpm_state file is a legacy interface and is only provided for
 109  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 110  * certain power related parameters.  The file power_dpm_state is used for this.
 111  * It accepts the following arguments:
 112  *
 113  * - battery
 114  *
 115  * - balanced
 116  *
 117  * - performance
 118  *
 119  * battery
 120  *
 121  * On older GPUs, the vbios provided a special power state for battery
 122  * operation.  Selecting battery switched to this state.  This is no
 123  * longer provided on newer GPUs so the option does nothing in that case.
 124  *
 125  * balanced
 126  *
 127  * On older GPUs, the vbios provided a special power state for balanced
 128  * operation.  Selecting balanced switched to this state.  This is no
 129  * longer provided on newer GPUs so the option does nothing in that case.
 130  *
 131  * performance
 132  *
 133  * On older GPUs, the vbios provided a special power state for performance
 134  * operation.  Selecting performance switched to this state.  This is no
 135  * longer provided on newer GPUs so the option does nothing in that case.
 136  *
 137  */
 138
 139 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 140                                     struct device_attribute *attr,
 141                                     char *buf)
 142 {
 143         struct drm_device *ddev = dev_get_drvdata(dev);
 144         struct amdgpu_device *adev = ddev->dev_private;
 145         enum amd_pm_state_type pm;
 146
 147         if (adev->powerplay.pp_funcs->get_current_power_state)
 148                 pm = amdgpu_dpm_get_current_power_state(adev);
 149         else
 150                 pm = adev->pm.dpm.user_state;
 151
 152         return snprintf(buf, PAGE_SIZE, "%s\n",
 153                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 154                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 155 }
 156
 157 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 158                                     struct device_attribute *attr,
 159                                     const char *buf,
 160                                     size_t count)
 161 {
 162         struct drm_device *ddev = dev_get_drvdata(dev);
 163         struct amdgpu_device *adev = ddev->dev_private;
 164         enum amd_pm_state_type  state;
 165
 166         if (strncmp("battery", buf, strlen("battery")) == 0)
 167                 state = POWER_STATE_TYPE_BATTERY;
 168         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 169                 state = POWER_STATE_TYPE_BALANCED;
 170         else if (strncmp("performance", buf, strlen("performance")) == 0)
 171                 state = POWER_STATE_TYPE_PERFORMANCE;
 172         else {
 173                 count = -EINVAL;
 174                 goto fail;
 175         }
 176
 177         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 178                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 179         } else {
 180                 mutex_lock(&adev->pm.mutex);
 181                 adev->pm.dpm.user_state = state;
 182                 mutex_unlock(&adev->pm.mutex);
 183
 184                 /* Can't set dpm state when the card is off */
 185                 if (!(adev->flags & AMD_IS_PX) ||
 186                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 187                         amdgpu_pm_compute_clocks(adev);
 188         }
 189 fail:
 190         return count;
 191 }
 192
 193
 194 /**
 195  * DOC: power_dpm_force_performance_level
 196  *
 197  * The amdgpu driver provides a sysfs API for adjusting certain power
 198  * related parameters.  The file power_dpm_force_performance_level is
 199  * used for this.  It accepts the following arguments:
 200  *
 201  * - auto
 202  *
 203  * - low
 204  *
 205  * - high
 206  *
 207  * - manual
 208  *
 209  * - profile_standard
 210  *
 211  * - profile_min_sclk
 212  *
 213  * - profile_min_mclk
 214  *
 215  * - profile_peak
 216  *
 217  * auto
 218  *
 219  * When auto is selected, the driver will attempt to dynamically select
 220  * the optimal power profile for current conditions in the driver.
 221  *
 222  * low
 223  *
 224  * When low is selected, the clocks are forced to the lowest power state.
 225  *
 226  * high
 227  *
 228  * When high is selected, the clocks are forced to the highest power state.
 229  *
 230  * manual
 231  *
 232  * When manual is selected, the user can manually adjust which power states
 233  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 234  * and pp_dpm_pcie files and adjust the power state transition heuristics
 235  * via the pp_power_profile_mode sysfs file.
 236  *
 237  * profile_standard
 238  * profile_min_sclk
 239  * profile_min_mclk
 240  * profile_peak
 241  *
 242  * When the profiling modes are selected, clock and power gating are
 243  * disabled and the clocks are set for different profiling cases. This
 244  * mode is recommended for profiling specific work loads where you do
 245  * not want clock or power gating for clock fluctuation to interfere
 246  * with your results. profile_standard sets the clocks to a fixed clock
 247  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 248  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 249  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 250  *
 251  */
 252
 253 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 254                                                 struct device_attribute *attr,
 255                                                                 char *buf)
 256 {
 257         struct drm_device *ddev = dev_get_drvdata(dev);
 258         struct amdgpu_device *adev = ddev->dev_private;
 259         enum amd_dpm_forced_level level = 0xff;
 260
 261         if  ((adev->flags & AMD_IS_PX) &&
 262              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 263                 return snprintf(buf, PAGE_SIZE, "off\n");
 264
 265         if (adev->powerplay.pp_funcs->get_performance_level)
 266                 level = amdgpu_dpm_get_performance_level(adev);
 267         else
 268                 level = adev->pm.dpm.forced_level;
 269
 270         return snprintf(buf, PAGE_SIZE, "%s\n",
 271                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 272                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 273                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 274                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 275                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 276                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 277                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 278                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 279                         "unknown");
 280 }
 281
 282 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 283                                                        struct device_attribute *attr,
 284                                                        const char *buf,
 285                                                        size_t count)
 286 {
 287         struct drm_device *ddev = dev_get_drvdata(dev);
 288         struct amdgpu_device *adev = ddev->dev_private;
 289         enum amd_dpm_forced_level level;
 290         enum amd_dpm_forced_level current_level = 0xff;
 291         int ret = 0;
 292
 293         /* Can't force performance level when the card is off */
 294         if  ((adev->flags & AMD_IS_PX) &&
 295              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 296                 return -EINVAL;
 297
 298         if (adev->powerplay.pp_funcs->get_performance_level)
 299                 current_level = amdgpu_dpm_get_performance_level(adev);
 300
 301         if (strncmp("low", buf, strlen("low")) == 0) {
 302                 level = AMD_DPM_FORCED_LEVEL_LOW;
 303         } else if (strncmp("high", buf, strlen("high")) == 0) {
 304                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 305         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 306                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 307         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 308                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 309         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 310                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 311         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 312                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 313         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 315         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 317         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 319         }  else {
 320                 count = -EINVAL;
 321                 goto fail;
 322         }
 323
 324         if (current_level == level)
 325                 return count;
 326
 327         if (adev->powerplay.pp_funcs->force_performance_level) {
 328                 mutex_lock(&adev->pm.mutex);
 329                 if (adev->pm.dpm.thermal_active) {
 330                         count = -EINVAL;
 331                         mutex_unlock(&adev->pm.mutex);
 332                         goto fail;
 333                 }
 334                 ret = amdgpu_dpm_force_performance_level(adev, level);
 335                 if (ret)
 336                         count = -EINVAL;
 337                 else
 338                         adev->pm.dpm.forced_level = level;
 339                 mutex_unlock(&adev->pm.mutex);
 340         }
 341
 342 fail:
 343         return count;
 344 }
 345
 346 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 347                 struct device_attribute *attr,
 348                 char *buf)
 349 {
 350         struct drm_device *ddev = dev_get_drvdata(dev);
 351         struct amdgpu_device *adev = ddev->dev_private;
 352         struct pp_states_info data;
 353         int i, buf_len;
 354
 355         if (adev->powerplay.pp_funcs->get_pp_num_states)
 356                 amdgpu_dpm_get_pp_num_states(adev, &data);
 357
 358         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 359         for (i = 0; i < data.nums; i++)
 360                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 361                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 362                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 363                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 364                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 365
 366         return buf_len;
 367 }
 368
 369 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 370                 struct device_attribute *attr,
 371                 char *buf)
 372 {
 373         struct drm_device *ddev = dev_get_drvdata(dev);
 374         struct amdgpu_device *adev = ddev->dev_private;
 375         struct pp_states_info data;
 376         enum amd_pm_state_type pm = 0;
 377         int i = 0;
 378
 379         if (adev->powerplay.pp_funcs->get_current_power_state
 380                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 381                 pm = amdgpu_dpm_get_current_power_state(adev);
 382                 amdgpu_dpm_get_pp_num_states(adev, &data);
 383
 384                 for (i = 0; i < data.nums; i++) {
 385                         if (pm == data.states[i])
 386                                 break;
 387                 }
 388
 389                 if (i == data.nums)
 390                         i = -EINVAL;
 391         }
 392
 393         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 394 }
 395
 396 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 397                 struct device_attribute *attr,
 398                 char *buf)
 399 {
 400         struct drm_device *ddev = dev_get_drvdata(dev);
 401         struct amdgpu_device *adev = ddev->dev_private;
 402
 403         if (adev->pp_force_state_enabled)
 404                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 405         else
 406                 return snprintf(buf, PAGE_SIZE, "\n");
 407 }
 408
 409 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 410                 struct device_attribute *attr,
 411                 const char *buf,
 412                 size_t count)
 413 {
 414         struct drm_device *ddev = dev_get_drvdata(dev);
 415         struct amdgpu_device *adev = ddev->dev_private;
 416         enum amd_pm_state_type state = 0;
 417         unsigned long idx;
 418         int ret;
 419
 420         if (strlen(buf) == 1)
 421                 adev->pp_force_state_enabled = false;
 422         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 423                         adev->powerplay.pp_funcs->get_pp_num_states) {
 424                 struct pp_states_info data;
 425
 426                 ret = kstrtoul(buf, 0, &idx);
 427                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 428                         count = -EINVAL;
 429                         goto fail;
 430                 }
 431                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 432
 433                 amdgpu_dpm_get_pp_num_states(adev, &data);
 434                 state = data.states[idx];
 435                 /* only set user selected power states */
 436                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 437                     state != POWER_STATE_TYPE_DEFAULT) {
 438                         amdgpu_dpm_dispatch_task(adev,
 439                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 440                         adev->pp_force_state_enabled = true;
 441                 }
 442         }
 443 fail:
 444         return count;
 445 }
 446
 447 /**
 448  * DOC: pp_table
 449  *
 450  * The amdgpu driver provides a sysfs API for uploading new powerplay
 451  * tables.  The file pp_table is used for this.  Reading the file
 452  * will dump the current power play table.  Writing to the file
 453  * will attempt to upload a new powerplay table and re-initialize
 454  * powerplay using that new table.
 455  *
 456  */
 457
 458 static ssize_t amdgpu_get_pp_table(struct device *dev,
 459                 struct device_attribute *attr,
 460                 char *buf)
 461 {
 462         struct drm_device *ddev = dev_get_drvdata(dev);
 463         struct amdgpu_device *adev = ddev->dev_private;
 464         char *table = NULL;
 465         int size;
 466
 467         if (is_support_sw_smu(adev)) {
 468                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 469                 if (size < 0)
 470                         return size;
 471         }
 472         else if (adev->powerplay.pp_funcs->get_pp_table)
 473                 size = amdgpu_dpm_get_pp_table(adev, &table);
 474         else
 475                 return 0;
 476
 477         if (size >= PAGE_SIZE)
 478                 size = PAGE_SIZE - 1;
 479
 480         memcpy(buf, table, size);
 481
 482         return size;
 483 }
 484
 485 static ssize_t amdgpu_set_pp_table(struct device *dev,
 486                 struct device_attribute *attr,
 487                 const char *buf,
 488                 size_t count)
 489 {
 490         struct drm_device *ddev = dev_get_drvdata(dev);
 491         struct amdgpu_device *adev = ddev->dev_private;
 492         int ret = 0;
 493
 494         if (is_support_sw_smu(adev)) {
 495                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 496                 if (ret)
 497                         return ret;
 498         } else if (adev->powerplay.pp_funcs->set_pp_table)
 499                 amdgpu_dpm_set_pp_table(adev, buf, count);
 500
 501         return count;
 502 }
 503
 504 /**
 505  * DOC: pp_od_clk_voltage
 506  *
 507  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 508  * in each power level within a power state.  The pp_od_clk_voltage is used for
 509  * this.
 510  *
 511  * < For Vega10 and previous ASICs >
 512  *
 513  * Reading the file will display:
 514  *
 515  * - a list of engine clock levels and voltages labeled OD_SCLK
 516  *
 517  * - a list of memory clock levels and voltages labeled OD_MCLK
 518  *
 519  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 520  *
 521  * To manually adjust these settings, first select manual using
 522  * power_dpm_force_performance_level. Enter a new value for each
 523  * level by writing a string that contains "s/m level clock voltage" to
 524  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 525  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 526  * 810 mV.  When you have edited all of the states as needed, write
 527  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 528  * default power levels, write "r" (reset) to the file to reset them.
 529  *
 530  *
 531  * < For Vega20 >
 532  *
 533  * Reading the file will display:
 534  *
 535  * - minimum and maximum engine clock labeled OD_SCLK
 536  *
 537  * - maximum memory clock labeled OD_MCLK
 538  *
 539  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 540  *   They can be used to calibrate the sclk voltage curve.
 541  *
 542  * - a list of valid ranges for sclk, mclk, and voltage curve points
 543  *   labeled OD_RANGE
 544  *
 545  * To manually adjust these settings:
 546  *
 547  * - First select manual using power_dpm_force_performance_level
 548  *
 549  * - For clock frequency setting, enter a new value by writing a
 550  *   string that contains "s/m index clock" to the file. The index
 551  *   should be 0 if to set minimum clock. And 1 if to set maximum
 552  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 553  *   "m 1 800" will update maximum mclk to be 800Mhz.
 554  *
 555  *   For sclk voltage curve, enter the new values by writing a
 556  *   string that contains "vc point clock voltage" to the file. The
 557  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 558  *   update point1 with clock set as 300Mhz and voltage as
 559  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 560  *   as 1000Mhz and voltage 1000mV.
 561  *
 562  * - When you have edited all of the states as needed, write "c" (commit)
 563  *   to the file to commit your changes
 564  *
 565  * - If you want to reset to the default power levels, write "r" (reset)
 566  *   to the file to reset them
 567  *
 568  */
 569
 570 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 571                 struct device_attribute *attr,
 572                 const char *buf,
 573                 size_t count)
 574 {
 575         struct drm_device *ddev = dev_get_drvdata(dev);
 576         struct amdgpu_device *adev = ddev->dev_private;
 577         int ret;
 578         uint32_t parameter_size = 0;
 579         long parameter[64];
 580         char buf_cpy[128];
 581         char *tmp_str;
 582         char *sub_str;
 583         const char delimiter[3] = {' ', '\n', '\0'};
 584         uint32_t type;
 585
 586         if (count > 127)
 587                 return -EINVAL;
 588
 589         if (*buf == 's')
 590                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 591         else if (*buf == 'm')
 592                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 593         else if(*buf == 'r')
 594                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 595         else if (*buf == 'c')
 596                 type = PP_OD_COMMIT_DPM_TABLE;
 597         else if (!strncmp(buf, "vc", 2))
 598                 type = PP_OD_EDIT_VDDC_CURVE;
 599         else
 600                 return -EINVAL;
 601
 602         memcpy(buf_cpy, buf, count+1);
 603
 604         tmp_str = buf_cpy;
 605
 606         if (type == PP_OD_EDIT_VDDC_CURVE)
 607                 tmp_str++;
 608         while (isspace(*++tmp_str));
 609
 610         while (tmp_str[0]) {
 611                 sub_str = strsep(&tmp_str, delimiter);
 612                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 613                 if (ret)
 614                         return -EINVAL;
 615                 parameter_size++;
 616
 617                 while (isspace(*tmp_str))
 618                         tmp_str++;
 619         }
 620
 621         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 622                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 623                                                 parameter, parameter_size);
 624
 625         if (ret)
 626                 return -EINVAL;
 627
 628         if (type == PP_OD_COMMIT_DPM_TABLE) {
 629                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 630                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 631                         return count;
 632                 } else {
 633                         return -EINVAL;
 634                 }
 635         }
 636
 637         return count;
 638 }
 639
 640 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 641                 struct device_attribute *attr,
 642                 char *buf)
 643 {
 644         struct drm_device *ddev = dev_get_drvdata(dev);
 645         struct amdgpu_device *adev = ddev->dev_private;
 646         uint32_t size = 0;
 647
 648         if (adev->powerplay.pp_funcs->print_clock_levels) {
 649                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 650                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 651                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 652                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 653                 return size;
 654         } else {
 655                 return snprintf(buf, PAGE_SIZE, "\n");
 656         }
 657
 658 }
 659
 660 /**
 661  * DOC: ppfeatures
 662  *
 663  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 664  * features to be enabled. The file ppfeatures is used for this. And
 665  * this is only available for Vega10 and later dGPUs.
 666  *
 667  * Reading back the file will show you the followings:
 668  * - Current ppfeature masks
 669  * - List of the all supported powerplay features with their naming,
 670  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 671  *
 672  * To manually enable or disable a specific feature, just set or clear
 673  * the corresponding bit from original ppfeature masks and input the
 674  * new ppfeature masks.
 675  */
 676 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 677                 struct device_attribute *attr,
 678                 const char *buf,
 679                 size_t count)
 680 {
 681         struct drm_device *ddev = dev_get_drvdata(dev);
 682         struct amdgpu_device *adev = ddev->dev_private;
 683         uint64_t featuremask;
 684         int ret;
 685
 686         ret = kstrtou64(buf, 0, &featuremask);
 687         if (ret)
 688                 return -EINVAL;
 689
 690         pr_debug("featuremask = 0x%llx\n", featuremask);
 691
 692         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 693                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 694                 if (ret)
 695                         return -EINVAL;
 696         }
 697
 698         return count;
 699 }
 700
 701 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 702                 struct device_attribute *attr,
 703                 char *buf)
 704 {
 705         struct drm_device *ddev = dev_get_drvdata(dev);
 706         struct amdgpu_device *adev = ddev->dev_private;
 707
 708         if (adev->powerplay.pp_funcs->get_ppfeature_status)
 709                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 710
 711         return snprintf(buf, PAGE_SIZE, "\n");
 712 }
 713
 714 /**
 715  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 716  * pp_dpm_pcie
 717  *
 718  * The amdgpu driver provides a sysfs API for adjusting what power levels
 719  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 720  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 721  * this.
 722  *
 723  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 724  * Vega10 and later ASICs.
 725  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 726  *
 727  * Reading back the files will show you the available power levels within
 728  * the power state and the clock information for those levels.
 729  *
 730  * To manually adjust these states, first select manual using
 731  * power_dpm_force_performance_level.
 732  * Secondly,Enter a new value for each level by inputing a string that
 733  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 734  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 735  *
 736  * NOTE: change to the dcefclk max dpm level is not supported now
 737  */
 738
 739 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 740                 struct device_attribute *attr,
 741                 char *buf)
 742 {
 743         struct drm_device *ddev = dev_get_drvdata(dev);
 744         struct amdgpu_device *adev = ddev->dev_private;
 745
 746         if (is_support_sw_smu(adev))
 747                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 748         else if (adev->powerplay.pp_funcs->print_clock_levels)
 749                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 750         else
 751                 return snprintf(buf, PAGE_SIZE, "\n");
 752 }
 753
 754 /*
 755  * Worst case: 32 bits individually specified, in octal at 12 characters
 756  * per line (+1 for \n).
 757  */
 758 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 759
 760 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 761 {
 762         int ret;
 763         long level;
 764         char *sub_str = NULL;
 765         char *tmp;
 766         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 767         const char delimiter[3] = {' ', '\n', '\0'};
 768         size_t bytes;
 769
 770         *mask = 0;
 771
 772         bytes = min(count, sizeof(buf_cpy) - 1);
 773         memcpy(buf_cpy, buf, bytes);
 774         buf_cpy[bytes] = '\0';
 775         tmp = buf_cpy;
 776         while (tmp[0]) {
 777                 sub_str = strsep(&tmp, delimiter);
 778                 if (strlen(sub_str)) {
 779                         ret = kstrtol(sub_str, 0, &level);
 780                         if (ret)
 781                                 return -EINVAL;
 782                         *mask |= 1 << level;
 783                 } else
 784                         break;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 791                 struct device_attribute *attr,
 792                 const char *buf,
 793                 size_t count)
 794 {
 795         struct drm_device *ddev = dev_get_drvdata(dev);
 796         struct amdgpu_device *adev = ddev->dev_private;
 797         int ret;
 798         uint32_t mask = 0;
 799
 800         ret = amdgpu_read_mask(buf, count, &mask);
 801         if (ret)
 802                 return ret;
 803
 804         if (adev->powerplay.pp_funcs->force_clock_level)
 805                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 806
 807         if (ret)
 808                 return -EINVAL;
 809
 810         return count;
 811 }
 812
 813 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 814                 struct device_attribute *attr,
 815                 char *buf)
 816 {
 817         struct drm_device *ddev = dev_get_drvdata(dev);
 818         struct amdgpu_device *adev = ddev->dev_private;
 819
 820         if (is_support_sw_smu(adev))
 821                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 822         else if (adev->powerplay.pp_funcs->print_clock_levels)
 823                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 824         else
 825                 return snprintf(buf, PAGE_SIZE, "\n");
 826 }
 827
 828 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 829                 struct device_attribute *attr,
 830                 const char *buf,
 831                 size_t count)
 832 {
 833         struct drm_device *ddev = dev_get_drvdata(dev);
 834         struct amdgpu_device *adev = ddev->dev_private;
 835         int ret;
 836         uint32_t mask = 0;
 837
 838         ret = amdgpu_read_mask(buf, count, &mask);
 839         if (ret)
 840                 return ret;
 841
 842         if (adev->powerplay.pp_funcs->force_clock_level)
 843                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 844
 845         if (ret)
 846                 return -EINVAL;
 847
 848         return count;
 849 }
 850
 851 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 852                 struct device_attribute *attr,
 853                 char *buf)
 854 {
 855         struct drm_device *ddev = dev_get_drvdata(dev);
 856         struct amdgpu_device *adev = ddev->dev_private;
 857
 858         if (adev->powerplay.pp_funcs->print_clock_levels)
 859                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 860         else
 861                 return snprintf(buf, PAGE_SIZE, "\n");
 862 }
 863
 864 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 865                 struct device_attribute *attr,
 866                 const char *buf,
 867                 size_t count)
 868 {
 869         struct drm_device *ddev = dev_get_drvdata(dev);
 870         struct amdgpu_device *adev = ddev->dev_private;
 871         int ret;
 872         uint32_t mask = 0;
 873
 874         ret = amdgpu_read_mask(buf, count, &mask);
 875         if (ret)
 876                 return ret;
 877
 878         if (adev->powerplay.pp_funcs->force_clock_level)
 879                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 880
 881         if (ret)
 882                 return -EINVAL;
 883
 884         return count;
 885 }
 886
 887 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 888                 struct device_attribute *attr,
 889                 char *buf)
 890 {
 891         struct drm_device *ddev = dev_get_drvdata(dev);
 892         struct amdgpu_device *adev = ddev->dev_private;
 893
 894         if (adev->powerplay.pp_funcs->print_clock_levels)
 895                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 896         else
 897                 return snprintf(buf, PAGE_SIZE, "\n");
 898 }
 899
 900 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 901                 struct device_attribute *attr,
 902                 const char *buf,
 903                 size_t count)
 904 {
 905         struct drm_device *ddev = dev_get_drvdata(dev);
 906         struct amdgpu_device *adev = ddev->dev_private;
 907         int ret;
 908         uint32_t mask = 0;
 909
 910         ret = amdgpu_read_mask(buf, count, &mask);
 911         if (ret)
 912                 return ret;
 913
 914         if (adev->powerplay.pp_funcs->force_clock_level)
 915                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
 916
 917         if (ret)
 918                 return -EINVAL;
 919
 920         return count;
 921 }
 922
 923 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
 924                 struct device_attribute *attr,
 925                 char *buf)
 926 {
 927         struct drm_device *ddev = dev_get_drvdata(dev);
 928         struct amdgpu_device *adev = ddev->dev_private;
 929
 930         if (adev->powerplay.pp_funcs->print_clock_levels)
 931                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
 932         else
 933                 return snprintf(buf, PAGE_SIZE, "\n");
 934 }
 935
 936 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
 937                 struct device_attribute *attr,
 938                 const char *buf,
 939                 size_t count)
 940 {
 941         struct drm_device *ddev = dev_get_drvdata(dev);
 942         struct amdgpu_device *adev = ddev->dev_private;
 943         int ret;
 944         uint32_t mask = 0;
 945
 946         ret = amdgpu_read_mask(buf, count, &mask);
 947         if (ret)
 948                 return ret;
 949
 950         if (adev->powerplay.pp_funcs->force_clock_level)
 951                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
 952
 953         if (ret)
 954                 return -EINVAL;
 955
 956         return count;
 957 }
 958
 959 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 960                 struct device_attribute *attr,
 961                 char *buf)
 962 {
 963         struct drm_device *ddev = dev_get_drvdata(dev);
 964         struct amdgpu_device *adev = ddev->dev_private;
 965
 966         if (adev->powerplay.pp_funcs->print_clock_levels)
 967                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 968         else
 969                 return snprintf(buf, PAGE_SIZE, "\n");
 970 }
 971
 972 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 973                 struct device_attribute *attr,
 974                 const char *buf,
 975                 size_t count)
 976 {
 977         struct drm_device *ddev = dev_get_drvdata(dev);
 978         struct amdgpu_device *adev = ddev->dev_private;
 979         int ret;
 980         uint32_t mask = 0;
 981
 982         ret = amdgpu_read_mask(buf, count, &mask);
 983         if (ret)
 984                 return ret;
 985
 986         if (adev->powerplay.pp_funcs->force_clock_level)
 987                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 988
 989         if (ret)
 990                 return -EINVAL;
 991
 992         return count;
 993 }
 994
 995 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 996                 struct device_attribute *attr,
 997                 char *buf)
 998 {
 999         struct drm_device *ddev = dev_get_drvdata(dev);
1000         struct amdgpu_device *adev = ddev->dev_private;
1001         uint32_t value = 0;
1002
1003         if (adev->powerplay.pp_funcs->get_sclk_od)
1004                 value = amdgpu_dpm_get_sclk_od(adev);
1005
1006         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1007 }
1008
1009 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1010                 struct device_attribute *attr,
1011                 const char *buf,
1012                 size_t count)
1013 {
1014         struct drm_device *ddev = dev_get_drvdata(dev);
1015         struct amdgpu_device *adev = ddev->dev_private;
1016         int ret;
1017         long int value;
1018
1019         ret = kstrtol(buf, 0, &value);
1020
1021         if (ret) {
1022                 count = -EINVAL;
1023                 goto fail;
1024         }
1025         if (adev->powerplay.pp_funcs->set_sclk_od)
1026                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1027
1028         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1029                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1030         } else {
1031                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1032                 amdgpu_pm_compute_clocks(adev);
1033         }
1034
1035 fail:
1036         return count;
1037 }
1038
1039 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1040                 struct device_attribute *attr,
1041                 char *buf)
1042 {
1043         struct drm_device *ddev = dev_get_drvdata(dev);
1044         struct amdgpu_device *adev = ddev->dev_private;
1045         uint32_t value = 0;
1046
1047         if (adev->powerplay.pp_funcs->get_mclk_od)
1048                 value = amdgpu_dpm_get_mclk_od(adev);
1049
1050         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1051 }
1052
1053 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1054                 struct device_attribute *attr,
1055                 const char *buf,
1056                 size_t count)
1057 {
1058         struct drm_device *ddev = dev_get_drvdata(dev);
1059         struct amdgpu_device *adev = ddev->dev_private;
1060         int ret;
1061         long int value;
1062
1063         ret = kstrtol(buf, 0, &value);
1064
1065         if (ret) {
1066                 count = -EINVAL;
1067                 goto fail;
1068         }
1069         if (adev->powerplay.pp_funcs->set_mclk_od)
1070                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1071
1072         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1073                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1074         } else {
1075                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1076                 amdgpu_pm_compute_clocks(adev);
1077         }
1078
1079 fail:
1080         return count;
1081 }
1082
1083 /**
1084  * DOC: pp_power_profile_mode
1085  *
1086  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1087  * related to switching between power levels in a power state.  The file
1088  * pp_power_profile_mode is used for this.
1089  *
1090  * Reading this file outputs a list of all of the predefined power profiles
1091  * and the relevant heuristics settings for that profile.
1092  *
1093  * To select a profile or create a custom profile, first select manual using
1094  * power_dpm_force_performance_level.  Writing the number of a predefined
1095  * profile to pp_power_profile_mode will enable those heuristics.  To
1096  * create a custom set of heuristics, write a string of numbers to the file
1097  * starting with the number of the custom profile along with a setting
1098  * for each heuristic parameter.  Due to differences across asic families
1099  * the heuristic parameters vary from family to family.
1100  *
1101  */
1102
1103 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1104                 struct device_attribute *attr,
1105                 char *buf)
1106 {
1107         struct drm_device *ddev = dev_get_drvdata(dev);
1108         struct amdgpu_device *adev = ddev->dev_private;
1109
1110         if (adev->powerplay.pp_funcs->get_power_profile_mode)
1111                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1112
1113         return snprintf(buf, PAGE_SIZE, "\n");
1114 }
1115
1116
1117 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1118                 struct device_attribute *attr,
1119                 const char *buf,
1120                 size_t count)
1121 {
1122         int ret = 0xff;
1123         struct drm_device *ddev = dev_get_drvdata(dev);
1124         struct amdgpu_device *adev = ddev->dev_private;
1125         uint32_t parameter_size = 0;
1126         long parameter[64];
1127         char *sub_str, buf_cpy[128];
1128         char *tmp_str;
1129         uint32_t i = 0;
1130         char tmp[2];
1131         long int profile_mode = 0;
1132         const char delimiter[3] = {' ', '\n', '\0'};
1133
1134         tmp[0] = *(buf);
1135         tmp[1] = '\0';
1136         ret = kstrtol(tmp, 0, &profile_mode);
1137         if (ret)
1138                 goto fail;
1139
1140         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1141                 if (count < 2 || count > 127)
1142                         return -EINVAL;
1143                 while (isspace(*++buf))
1144                         i++;
1145                 memcpy(buf_cpy, buf, count-i);
1146                 tmp_str = buf_cpy;
1147                 while (tmp_str[0]) {
1148                         sub_str = strsep(&tmp_str, delimiter);
1149                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1150                         if (ret) {
1151                                 count = -EINVAL;
1152                                 goto fail;
1153                         }
1154                         parameter_size++;
1155                         while (isspace(*tmp_str))
1156                                 tmp_str++;
1157                 }
1158         }
1159         parameter[parameter_size] = profile_mode;
1160         if (adev->powerplay.pp_funcs->set_power_profile_mode)
1161                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1162
1163         if (!ret)
1164                 return count;
1165 fail:
1166         return -EINVAL;
1167 }
1168
1169 /**
1170  * DOC: busy_percent
1171  *
1172  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1173  * is as a percentage.  The file gpu_busy_percent is used for this.
1174  * The SMU firmware computes a percentage of load based on the
1175  * aggregate activity level in the IP cores.
1176  */
1177 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1178                 struct device_attribute *attr,
1179                 char *buf)
1180 {
1181         struct drm_device *ddev = dev_get_drvdata(dev);
1182         struct amdgpu_device *adev = ddev->dev_private;
1183         int r, value, size = sizeof(value);
1184
1185         /* read the IP busy sensor */
1186         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1187                                    (void *)&value, &size);
1188
1189         if (r)
1190                 return r;
1191
1192         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1193 }
1194
1195 /**
1196  * DOC: pcie_bw
1197  *
1198  * The amdgpu driver provides a sysfs API for estimating how much data
1199  * has been received and sent by the GPU in the last second through PCIe.
1200  * The file pcie_bw is used for this.
1201  * The Perf counters count the number of received and sent messages and return
1202  * those values, as well as the maximum payload size of a PCIe packet (mps).
1203  * Note that it is not possible to easily and quickly obtain the size of each
1204  * packet transmitted, so we output the max payload size (mps) to allow for
1205  * quick estimation of the PCIe bandwidth usage
1206  */
1207 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1208                 struct device_attribute *attr,
1209                 char *buf)
1210 {
1211         struct drm_device *ddev = dev_get_drvdata(dev);
1212         struct amdgpu_device *adev = ddev->dev_private;
1213         uint64_t count0, count1;
1214
1215         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1216         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1217                         count0, count1, pcie_get_mps(adev->pdev));
1218 }
1219
1220 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1221 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1222                    amdgpu_get_dpm_forced_performance_level,
1223                    amdgpu_set_dpm_forced_performance_level);
1224 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1225 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1226 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1227                 amdgpu_get_pp_force_state,
1228                 amdgpu_set_pp_force_state);
1229 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1230                 amdgpu_get_pp_table,
1231                 amdgpu_set_pp_table);
1232 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1233                 amdgpu_get_pp_dpm_sclk,
1234                 amdgpu_set_pp_dpm_sclk);
1235 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1236                 amdgpu_get_pp_dpm_mclk,
1237                 amdgpu_set_pp_dpm_mclk);
1238 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1239                 amdgpu_get_pp_dpm_socclk,
1240                 amdgpu_set_pp_dpm_socclk);
1241 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1242                 amdgpu_get_pp_dpm_fclk,
1243                 amdgpu_set_pp_dpm_fclk);
1244 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1245                 amdgpu_get_pp_dpm_dcefclk,
1246                 amdgpu_set_pp_dpm_dcefclk);
1247 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1248                 amdgpu_get_pp_dpm_pcie,
1249                 amdgpu_set_pp_dpm_pcie);
1250 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1251                 amdgpu_get_pp_sclk_od,
1252                 amdgpu_set_pp_sclk_od);
1253 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1254                 amdgpu_get_pp_mclk_od,
1255                 amdgpu_set_pp_mclk_od);
1256 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1257                 amdgpu_get_pp_power_profile_mode,
1258                 amdgpu_set_pp_power_profile_mode);
1259 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1260                 amdgpu_get_pp_od_clk_voltage,
1261                 amdgpu_set_pp_od_clk_voltage);
1262 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1263                 amdgpu_get_busy_percent, NULL);
1264 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1265 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1266                 amdgpu_get_ppfeature_status,
1267                 amdgpu_set_ppfeature_status);
1268
1269 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1270                                       struct device_attribute *attr,
1271                                       char *buf)
1272 {
1273         struct amdgpu_device *adev = dev_get_drvdata(dev);
1274         struct drm_device *ddev = adev->ddev;
1275         int r, temp, size = sizeof(temp);
1276
1277         /* Can't get temperature when the card is off */
1278         if  ((adev->flags & AMD_IS_PX) &&
1279              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1280                 return -EINVAL;
1281
1282         /* get the temperature */
1283         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1284                                    (void *)&temp, &size);
1285         if (r)
1286                 return r;
1287
1288         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1289 }
1290
1291 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1292                                              struct device_attribute *attr,
1293                                              char *buf)
1294 {
1295         struct amdgpu_device *adev = dev_get_drvdata(dev);
1296         int hyst = to_sensor_dev_attr(attr)->index;
1297         int temp;
1298
1299         if (hyst)
1300                 temp = adev->pm.dpm.thermal.min_temp;
1301         else
1302                 temp = adev->pm.dpm.thermal.max_temp;
1303
1304         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1305 }
1306
1307 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1308                                             struct device_attribute *attr,
1309                                             char *buf)
1310 {
1311         struct amdgpu_device *adev = dev_get_drvdata(dev);
1312         u32 pwm_mode = 0;
1313
1314         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1315                 return -EINVAL;
1316
1317         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1318
1319         return sprintf(buf, "%i\n", pwm_mode);
1320 }
1321
1322 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1323                                             struct device_attribute *attr,
1324                                             const char *buf,
1325                                             size_t count)
1326 {
1327         struct amdgpu_device *adev = dev_get_drvdata(dev);
1328         int err;
1329         int value;
1330
1331         /* Can't adjust fan when the card is off */
1332         if  ((adev->flags & AMD_IS_PX) &&
1333              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1334                 return -EINVAL;
1335
1336         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1337                 return -EINVAL;
1338
1339         err = kstrtoint(buf, 10, &value);
1340         if (err)
1341                 return err;
1342
1343         amdgpu_dpm_set_fan_control_mode(adev, value);
1344
1345         return count;
1346 }
1347
1348 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1349                                          struct device_attribute *attr,
1350                                          char *buf)
1351 {
1352         return sprintf(buf, "%i\n", 0);
1353 }
1354
1355 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1356                                          struct device_attribute *attr,
1357                                          char *buf)
1358 {
1359         return sprintf(buf, "%i\n", 255);
1360 }
1361
1362 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1363                                      struct device_attribute *attr,
1364                                      const char *buf, size_t count)
1365 {
1366         struct amdgpu_device *adev = dev_get_drvdata(dev);
1367         int err;
1368         u32 value;
1369         u32 pwm_mode;
1370
1371         /* Can't adjust fan when the card is off */
1372         if  ((adev->flags & AMD_IS_PX) &&
1373              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1374                 return -EINVAL;
1375
1376         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1377         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1378                 pr_info("manual fan speed control should be enabled first\n");
1379                 return -EINVAL;
1380         }
1381
1382         err = kstrtou32(buf, 10, &value);
1383         if (err)
1384                 return err;
1385
1386         value = (value * 100) / 255;
1387
1388         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1389                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1390                 if (err)
1391                         return err;
1392         }
1393
1394         return count;
1395 }
1396
1397 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1398                                      struct device_attribute *attr,
1399                                      char *buf)
1400 {
1401         struct amdgpu_device *adev = dev_get_drvdata(dev);
1402         int err;
1403         u32 speed = 0;
1404
1405         /* Can't adjust fan when the card is off */
1406         if  ((adev->flags & AMD_IS_PX) &&
1407              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1408                 return -EINVAL;
1409
1410         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1411                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1412                 if (err)
1413                         return err;
1414         }
1415
1416         speed = (speed * 255) / 100;
1417
1418         return sprintf(buf, "%i\n", speed);
1419 }
1420
1421 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1422                                            struct device_attribute *attr,
1423                                            char *buf)
1424 {
1425         struct amdgpu_device *adev = dev_get_drvdata(dev);
1426         int err;
1427         u32 speed = 0;
1428
1429         /* Can't adjust fan when the card is off */
1430         if  ((adev->flags & AMD_IS_PX) &&
1431              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1432                 return -EINVAL;
1433
1434         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1435                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1436                 if (err)
1437                         return err;
1438         }
1439
1440         return sprintf(buf, "%i\n", speed);
1441 }
1442
1443 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1444                                          struct device_attribute *attr,
1445                                          char *buf)
1446 {
1447         struct amdgpu_device *adev = dev_get_drvdata(dev);
1448         u32 min_rpm = 0;
1449         u32 size = sizeof(min_rpm);
1450         int r;
1451
1452         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1453                                    (void *)&min_rpm, &size);
1454         if (r)
1455                 return r;
1456
1457         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1458 }
1459
1460 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1461                                          struct device_attribute *attr,
1462                                          char *buf)
1463 {
1464         struct amdgpu_device *adev = dev_get_drvdata(dev);
1465         u32 max_rpm = 0;
1466         u32 size = sizeof(max_rpm);
1467         int r;
1468
1469         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1470                                    (void *)&max_rpm, &size);
1471         if (r)
1472                 return r;
1473
1474         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1475 }
1476
1477 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1478                                            struct device_attribute *attr,
1479                                            char *buf)
1480 {
1481         struct amdgpu_device *adev = dev_get_drvdata(dev);
1482         int err;
1483         u32 rpm = 0;
1484
1485         /* Can't adjust fan when the card is off */
1486         if  ((adev->flags & AMD_IS_PX) &&
1487              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1488                 return -EINVAL;
1489
1490         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1491                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1492                 if (err)
1493                         return err;
1494         }
1495
1496         return sprintf(buf, "%i\n", rpm);
1497 }
1498
1499 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1500                                      struct device_attribute *attr,
1501                                      const char *buf, size_t count)
1502 {
1503         struct amdgpu_device *adev = dev_get_drvdata(dev);
1504         int err;
1505         u32 value;
1506         u32 pwm_mode;
1507
1508         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1509         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1510                 return -ENODATA;
1511
1512         /* Can't adjust fan when the card is off */
1513         if  ((adev->flags & AMD_IS_PX) &&
1514              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1515                 return -EINVAL;
1516
1517         err = kstrtou32(buf, 10, &value);
1518         if (err)
1519                 return err;
1520
1521         if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1522                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1523                 if (err)
1524                         return err;
1525         }
1526
1527         return count;
1528 }
1529
1530 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1531                                             struct device_attribute *attr,
1532                                             char *buf)
1533 {
1534         struct amdgpu_device *adev = dev_get_drvdata(dev);
1535         u32 pwm_mode = 0;
1536
1537         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1538                 return -EINVAL;
1539
1540         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1541
1542         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1543 }
1544
1545 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1546                                             struct device_attribute *attr,
1547                                             const char *buf,
1548                                             size_t count)
1549 {
1550         struct amdgpu_device *adev = dev_get_drvdata(dev);
1551         int err;
1552         int value;
1553         u32 pwm_mode;
1554
1555         /* Can't adjust fan when the card is off */
1556         if  ((adev->flags & AMD_IS_PX) &&
1557              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1558                 return -EINVAL;
1559
1560         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1561                 return -EINVAL;
1562
1563         err = kstrtoint(buf, 10, &value);
1564         if (err)
1565                 return err;
1566
1567         if (value == 0)
1568                 pwm_mode = AMD_FAN_CTRL_AUTO;
1569         else if (value == 1)
1570                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1571         else
1572                 return -EINVAL;
1573
1574         amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1575
1576         return count;
1577 }
1578
1579 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1580                                         struct device_attribute *attr,
1581                                         char *buf)
1582 {
1583         struct amdgpu_device *adev = dev_get_drvdata(dev);
1584         struct drm_device *ddev = adev->ddev;
1585         u32 vddgfx;
1586         int r, size = sizeof(vddgfx);
1587
1588         /* Can't get voltage when the card is off */
1589         if  ((adev->flags & AMD_IS_PX) &&
1590              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1591                 return -EINVAL;
1592
1593         /* get the voltage */
1594         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1595                                    (void *)&vddgfx, &size);
1596         if (r)
1597                 return r;
1598
1599         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1600 }
1601
1602 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1603                                               struct device_attribute *attr,
1604                                               char *buf)
1605 {
1606         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1607 }
1608
1609 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1610                                        struct device_attribute *attr,
1611                                        char *buf)
1612 {
1613         struct amdgpu_device *adev = dev_get_drvdata(dev);
1614         struct drm_device *ddev = adev->ddev;
1615         u32 vddnb;
1616         int r, size = sizeof(vddnb);
1617
1618         /* only APUs have vddnb */
1619         if  (!(adev->flags & AMD_IS_APU))
1620                 return -EINVAL;
1621
1622         /* Can't get voltage when the card is off */
1623         if  ((adev->flags & AMD_IS_PX) &&
1624              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1625                 return -EINVAL;
1626
1627         /* get the voltage */
1628         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1629                                    (void *)&vddnb, &size);
1630         if (r)
1631                 return r;
1632
1633         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1634 }
1635
1636 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1637                                               struct device_attribute *attr,
1638                                               char *buf)
1639 {
1640         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1641 }
1642
1643 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1644                                            struct device_attribute *attr,
1645                                            char *buf)
1646 {
1647         struct amdgpu_device *adev = dev_get_drvdata(dev);
1648         struct drm_device *ddev = adev->ddev;
1649         u32 query = 0;
1650         int r, size = sizeof(u32);
1651         unsigned uw;
1652
1653         /* Can't get power when the card is off */
1654         if  ((adev->flags & AMD_IS_PX) &&
1655              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1656                 return -EINVAL;
1657
1658         /* get the voltage */
1659         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1660                                    (void *)&query, &size);
1661         if (r)
1662                 return r;
1663
1664         /* convert to microwatts */
1665         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1666
1667         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1668 }
1669
1670 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1671                                          struct device_attribute *attr,
1672                                          char *buf)
1673 {
1674         return sprintf(buf, "%i\n", 0);
1675 }
1676
1677 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1678                                          struct device_attribute *attr,
1679                                          char *buf)
1680 {
1681         struct amdgpu_device *adev = dev_get_drvdata(dev);
1682         uint32_t limit = 0;
1683
1684         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1685                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1686                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1687         } else {
1688                 return snprintf(buf, PAGE_SIZE, "\n");
1689         }
1690 }
1691
1692 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1693                                          struct device_attribute *attr,
1694                                          char *buf)
1695 {
1696         struct amdgpu_device *adev = dev_get_drvdata(dev);
1697         uint32_t limit = 0;
1698
1699         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1700                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1701                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1702         } else {
1703                 return snprintf(buf, PAGE_SIZE, "\n");
1704         }
1705 }
1706
1707
1708 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1709                 struct device_attribute *attr,
1710                 const char *buf,
1711                 size_t count)
1712 {
1713         struct amdgpu_device *adev = dev_get_drvdata(dev);
1714         int err;
1715         u32 value;
1716
1717         err = kstrtou32(buf, 10, &value);
1718         if (err)
1719                 return err;
1720
1721         value = value / 1000000; /* convert to Watt */
1722         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1723                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1724                 if (err)
1725                         return err;
1726         } else {
1727                 return -EINVAL;
1728         }
1729
1730         return count;
1731 }
1732
1733 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
1734                                       struct device_attribute *attr,
1735                                       char *buf)
1736 {
1737         struct amdgpu_device *adev = dev_get_drvdata(dev);
1738         struct drm_device *ddev = adev->ddev;
1739         uint32_t sclk;
1740         int r, size = sizeof(sclk);
1741
1742         /* Can't get voltage when the card is off */
1743         if  ((adev->flags & AMD_IS_PX) &&
1744              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1745                 return -EINVAL;
1746
1747         /* sanity check PP is enabled */
1748         if (!(adev->powerplay.pp_funcs &&
1749               adev->powerplay.pp_funcs->read_sensor))
1750               return -EINVAL;
1751
1752         /* get the sclk */
1753         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
1754                                    (void *)&sclk, &size);
1755         if (r)
1756                 return r;
1757
1758         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
1759 }
1760
1761 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
1762                                             struct device_attribute *attr,
1763                                             char *buf)
1764 {
1765         return snprintf(buf, PAGE_SIZE, "sclk\n");
1766 }
1767
1768 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
1769                                       struct device_attribute *attr,
1770                                       char *buf)
1771 {
1772         struct amdgpu_device *adev = dev_get_drvdata(dev);
1773         struct drm_device *ddev = adev->ddev;
1774         uint32_t mclk;
1775         int r, size = sizeof(mclk);
1776
1777         /* Can't get voltage when the card is off */
1778         if  ((adev->flags & AMD_IS_PX) &&
1779              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1780                 return -EINVAL;
1781
1782         /* sanity check PP is enabled */
1783         if (!(adev->powerplay.pp_funcs &&
1784               adev->powerplay.pp_funcs->read_sensor))
1785               return -EINVAL;
1786
1787         /* get the sclk */
1788         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
1789                                    (void *)&mclk, &size);
1790         if (r)
1791                 return r;
1792
1793         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
1794 }
1795
1796 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
1797                                             struct device_attribute *attr,
1798                                             char *buf)
1799 {
1800         return snprintf(buf, PAGE_SIZE, "mclk\n");
1801 }
1802
1803 /**
1804  * DOC: hwmon
1805  *
1806  * The amdgpu driver exposes the following sensor interfaces:
1807  *
1808  * - GPU temperature (via the on-die sensor)
1809  *
1810  * - GPU voltage
1811  *
1812  * - Northbridge voltage (APUs only)
1813  *
1814  * - GPU power
1815  *
1816  * - GPU fan
1817  *
1818  * - GPU gfx/compute engine clock
1819  *
1820  * - GPU memory clock (dGPU only)
1821  *
1822  * hwmon interfaces for GPU temperature:
1823  *
1824  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1825  *
1826  * - temp1_crit: temperature critical max value in millidegrees Celsius
1827  *
1828  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1829  *
1830  * hwmon interfaces for GPU voltage:
1831  *
1832  * - in0_input: the voltage on the GPU in millivolts
1833  *
1834  * - in1_input: the voltage on the Northbridge in millivolts
1835  *
1836  * hwmon interfaces for GPU power:
1837  *
1838  * - power1_average: average power used by the GPU in microWatts
1839  *
1840  * - power1_cap_min: minimum cap supported in microWatts
1841  *
1842  * - power1_cap_max: maximum cap supported in microWatts
1843  *
1844  * - power1_cap: selected power cap in microWatts
1845  *
1846  * hwmon interfaces for GPU fan:
1847  *
1848  * - pwm1: pulse width modulation fan level (0-255)
1849  *
1850  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1851  *
1852  * - pwm1_min: pulse width modulation fan control minimum level (0)
1853  *
1854  * - pwm1_max: pulse width modulation fan control maximum level (255)
1855  *
1856  * - fan1_min: an minimum value Unit: revolution/min (RPM)
1857  *
1858  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
1859  *
1860  * - fan1_input: fan speed in RPM
1861  *
1862  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
1863  *
1864  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
1865  *
1866  * hwmon interfaces for GPU clocks:
1867  *
1868  * - freq1_input: the gfx/compute clock in hertz
1869  *
1870  * - freq2_input: the memory clock in hertz
1871  *
1872  * You can use hwmon tools like sensors to view this information on your system.
1873  *
1874  */
1875
1876 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1877 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1878 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1879 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1880 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1881 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1882 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1883 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1884 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
1885 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
1886 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
1887 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
1888 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1889 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1890 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1891 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1892 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1893 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1894 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1895 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1896 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
1897 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
1898 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
1899 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
1900
1901 static struct attribute *hwmon_attributes[] = {
1902         &sensor_dev_attr_temp1_input.dev_attr.attr,
1903         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1904         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1905         &sensor_dev_attr_pwm1.dev_attr.attr,
1906         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1907         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1908         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1909         &sensor_dev_attr_fan1_input.dev_attr.attr,
1910         &sensor_dev_attr_fan1_min.dev_attr.attr,
1911         &sensor_dev_attr_fan1_max.dev_attr.attr,
1912         &sensor_dev_attr_fan1_target.dev_attr.attr,
1913         &sensor_dev_attr_fan1_enable.dev_attr.attr,
1914         &sensor_dev_attr_in0_input.dev_attr.attr,
1915         &sensor_dev_attr_in0_label.dev_attr.attr,
1916         &sensor_dev_attr_in1_input.dev_attr.attr,
1917         &sensor_dev_attr_in1_label.dev_attr.attr,
1918         &sensor_dev_attr_power1_average.dev_attr.attr,
1919         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1920         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1921         &sensor_dev_attr_power1_cap.dev_attr.attr,
1922         &sensor_dev_attr_freq1_input.dev_attr.attr,
1923         &sensor_dev_attr_freq1_label.dev_attr.attr,
1924         &sensor_dev_attr_freq2_input.dev_attr.attr,
1925         &sensor_dev_attr_freq2_label.dev_attr.attr,
1926         NULL
1927 };
1928
1929 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1930                                         struct attribute *attr, int index)
1931 {
1932         struct device *dev = kobj_to_dev(kobj);
1933         struct amdgpu_device *adev = dev_get_drvdata(dev);
1934         umode_t effective_mode = attr->mode;
1935
1936         /* Skip fan attributes if fan is not present */
1937         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1938             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1939             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1940             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1941             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1942             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1943             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1944             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1945             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1946                 return 0;
1947
1948         /* Skip fan attributes on APU */
1949         if ((adev->flags & AMD_IS_APU) &&
1950             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1951              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1952              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1953              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1954              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1955              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1956              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1957              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1958              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1959                 return 0;
1960
1961         /* Skip limit attributes if DPM is not enabled */
1962         if (!adev->pm.dpm_enabled &&
1963             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1964              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1965              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1966              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1967              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1968              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1969              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1970              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1971              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1972              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1973              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1974                 return 0;
1975
1976         /* mask fan attributes if we have no bindings for this asic to expose */
1977         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1978              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1979             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1980              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1981                 effective_mode &= ~S_IRUGO;
1982
1983         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1984              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1985             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1986              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1987                 effective_mode &= ~S_IWUSR;
1988
1989         if ((adev->flags & AMD_IS_APU) &&
1990             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
1991              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1992              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1993              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1994                 return 0;
1995
1996         /* hide max/min values if we can't both query and manage the fan */
1997         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1998              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1999              (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2000              !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2001             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2002              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2003                 return 0;
2004
2005         if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2006              !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2007             (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2008              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2009                 return 0;
2010
2011         /* only APUs have vddnb */
2012         if (!(adev->flags & AMD_IS_APU) &&
2013             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2014              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2015                 return 0;
2016
2017         /* no mclk on APUs */
2018         if ((adev->flags & AMD_IS_APU) &&
2019             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2020              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2021                 return 0;
2022
2023         return effective_mode;
2024 }
2025
2026 static const struct attribute_group hwmon_attrgroup = {
2027         .attrs = hwmon_attributes,
2028         .is_visible = hwmon_attributes_visible,
2029 };
2030
2031 static const struct attribute_group *hwmon_groups[] = {
2032         &hwmon_attrgroup,
2033         NULL
2034 };
2035
2036 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2037 {
2038         struct amdgpu_device *adev =
2039                 container_of(work, struct amdgpu_device,
2040                              pm.dpm.thermal.work);
2041         /* switch to the thermal state */
2042         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2043         int temp, size = sizeof(temp);
2044
2045         if (!adev->pm.dpm_enabled)
2046                 return;
2047
2048         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2049                                     (void *)&temp, &size)) {
2050                 if (temp < adev->pm.dpm.thermal.min_temp)
2051                         /* switch back the user state */
2052                         dpm_state = adev->pm.dpm.user_state;
2053         } else {
2054                 if (adev->pm.dpm.thermal.high_to_low)
2055                         /* switch back the user state */
2056                         dpm_state = adev->pm.dpm.user_state;
2057         }
2058         mutex_lock(&adev->pm.mutex);
2059         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2060                 adev->pm.dpm.thermal_active = true;
2061         else
2062                 adev->pm.dpm.thermal_active = false;
2063         adev->pm.dpm.state = dpm_state;
2064         mutex_unlock(&adev->pm.mutex);
2065
2066         amdgpu_pm_compute_clocks(adev);
2067 }
2068
2069 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2070                                                      enum amd_pm_state_type dpm_state)
2071 {
2072         int i;
2073         struct amdgpu_ps *ps;
2074         u32 ui_class;
2075         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2076                 true : false;
2077
2078         /* check if the vblank period is too short to adjust the mclk */
2079         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2080                 if (amdgpu_dpm_vblank_too_short(adev))
2081                         single_display = false;
2082         }
2083
2084         /* certain older asics have a separare 3D performance state,
2085          * so try that first if the user selected performance
2086          */
2087         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2088                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2089         /* balanced states don't exist at the moment */
2090         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2091                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2092
2093 restart_search:
2094         /* Pick the best power state based on current conditions */
2095         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2096                 ps = &adev->pm.dpm.ps[i];
2097                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2098                 switch (dpm_state) {
2099                 /* user states */
2100                 case POWER_STATE_TYPE_BATTERY:
2101                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2102                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2103                                         if (single_display)
2104                                                 return ps;
2105                                 } else
2106                                         return ps;
2107                         }
2108                         break;
2109                 case POWER_STATE_TYPE_BALANCED:
2110                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2111                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2112                                         if (single_display)
2113                                                 return ps;
2114                                 } else
2115                                         return ps;
2116                         }
2117                         break;
2118                 case POWER_STATE_TYPE_PERFORMANCE:
2119                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2120                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2121                                         if (single_display)
2122                                                 return ps;
2123                                 } else
2124                                         return ps;
2125                         }
2126                         break;
2127                 /* internal states */
2128                 case POWER_STATE_TYPE_INTERNAL_UVD:
2129                         if (adev->pm.dpm.uvd_ps)
2130                                 return adev->pm.dpm.uvd_ps;
2131                         else
2132                                 break;
2133                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2134                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2135                                 return ps;
2136                         break;
2137                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2138                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2139                                 return ps;
2140                         break;
2141                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2142                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2143                                 return ps;
2144                         break;
2145                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2146                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2147                                 return ps;
2148                         break;
2149                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2150                         return adev->pm.dpm.boot_ps;
2151                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2152                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2153                                 return ps;
2154                         break;
2155                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2156                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2157                                 return ps;
2158                         break;
2159                 case POWER_STATE_TYPE_INTERNAL_ULV:
2160                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2161                                 return ps;
2162                         break;
2163                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2164                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2165                                 return ps;
2166                         break;
2167                 default:
2168                         break;
2169                 }
2170         }
2171         /* use a fallback state if we didn't match */
2172         switch (dpm_state) {
2173         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2174                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2175                 goto restart_search;
2176         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2177         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2178         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2179                 if (adev->pm.dpm.uvd_ps) {
2180                         return adev->pm.dpm.uvd_ps;
2181                 } else {
2182                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2183                         goto restart_search;
2184                 }
2185         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2186                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2187                 goto restart_search;
2188         case POWER_STATE_TYPE_INTERNAL_ACPI:
2189                 dpm_state = POWER_STATE_TYPE_BATTERY;
2190                 goto restart_search;
2191         case POWER_STATE_TYPE_BATTERY:
2192         case POWER_STATE_TYPE_BALANCED:
2193         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2194                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2195                 goto restart_search;
2196         default:
2197                 break;
2198         }
2199
2200         return NULL;
2201 }
2202
2203 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2204 {
2205         struct amdgpu_ps *ps;
2206         enum amd_pm_state_type dpm_state;
2207         int ret;
2208         bool equal = false;
2209
2210         /* if dpm init failed */
2211         if (!adev->pm.dpm_enabled)
2212                 return;
2213
2214         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2215                 /* add other state override checks here */
2216                 if ((!adev->pm.dpm.thermal_active) &&
2217                     (!adev->pm.dpm.uvd_active))
2218                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2219         }
2220         dpm_state = adev->pm.dpm.state;
2221
2222         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2223         if (ps)
2224                 adev->pm.dpm.requested_ps = ps;
2225         else
2226                 return;
2227
2228         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2229                 printk("switching from power state:\n");
2230                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2231                 printk("switching to power state:\n");
2232                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2233         }
2234
2235         /* update whether vce is active */
2236         ps->vce_active = adev->pm.dpm.vce_active;
2237         if (adev->powerplay.pp_funcs->display_configuration_changed)
2238                 amdgpu_dpm_display_configuration_changed(adev);
2239
2240         ret = amdgpu_dpm_pre_set_power_state(adev);
2241         if (ret)
2242                 return;
2243
2244         if (adev->powerplay.pp_funcs->check_state_equal) {
2245                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2246                         equal = false;
2247         }
2248
2249         if (equal)
2250                 return;
2251
2252         amdgpu_dpm_set_power_state(adev);
2253         amdgpu_dpm_post_set_power_state(adev);
2254
2255         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2256         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2257
2258         if (adev->powerplay.pp_funcs->force_performance_level) {
2259                 if (adev->pm.dpm.thermal_active) {
2260                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2261                         /* force low perf level for thermal */
2262                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2263                         /* save the user's level */
2264                         adev->pm.dpm.forced_level = level;
2265                 } else {
2266                         /* otherwise, user selected level */
2267                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2268                 }
2269         }
2270 }
2271
2272 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2273 {
2274         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2275                 /* enable/disable UVD */
2276                 mutex_lock(&adev->pm.mutex);
2277                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2278                 mutex_unlock(&adev->pm.mutex);
2279         }
2280         /* enable/disable Low Memory PState for UVD (4k videos) */
2281         if (adev->asic_type == CHIP_STONEY &&
2282                 adev->uvd.decode_image_width >= WIDTH_4K) {
2283                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2284
2285                 if (hwmgr && hwmgr->hwmgr_func &&
2286                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2287                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2288                                                                !enable,
2289                                                                true);
2290         }
2291 }
2292
2293 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2294 {
2295         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2296                 /* enable/disable VCE */
2297                 mutex_lock(&adev->pm.mutex);
2298                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2299                 mutex_unlock(&adev->pm.mutex);
2300         }
2301 }
2302
2303 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2304 {
2305         int i;
2306
2307         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2308                 return;
2309
2310         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2311                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2312
2313 }
2314
2315 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2316 {
2317         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2318         int ret;
2319
2320         if (adev->pm.sysfs_initialized)
2321                 return 0;
2322
2323         if (adev->pm.dpm_enabled == 0)
2324                 return 0;
2325
2326         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2327                                                                    DRIVER_NAME, adev,
2328                                                                    hwmon_groups);
2329         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2330                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2331                 dev_err(adev->dev,
2332                         "Unable to register hwmon device: %d\n", ret);
2333                 return ret;
2334         }
2335
2336         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2337         if (ret) {
2338                 DRM_ERROR("failed to create device file for dpm state\n");
2339                 return ret;
2340         }
2341         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2342         if (ret) {
2343                 DRM_ERROR("failed to create device file for dpm state\n");
2344                 return ret;
2345         }
2346
2347
2348         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2349         if (ret) {
2350                 DRM_ERROR("failed to create device file pp_num_states\n");
2351                 return ret;
2352         }
2353         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2354         if (ret) {
2355                 DRM_ERROR("failed to create device file pp_cur_state\n");
2356                 return ret;
2357         }
2358         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2359         if (ret) {
2360                 DRM_ERROR("failed to create device file pp_force_state\n");
2361                 return ret;
2362         }
2363         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2364         if (ret) {
2365                 DRM_ERROR("failed to create device file pp_table\n");
2366                 return ret;
2367         }
2368
2369         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2370         if (ret) {
2371                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2372                 return ret;
2373         }
2374         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2375         if (ret) {
2376                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2377                 return ret;
2378         }
2379         if (adev->asic_type >= CHIP_VEGA10) {
2380                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2381                 if (ret) {
2382                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2383                         return ret;
2384                 }
2385                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2386                 if (ret) {
2387                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2388                         return ret;
2389                 }
2390         }
2391         if (adev->asic_type >= CHIP_VEGA20) {
2392                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2393                 if (ret) {
2394                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2395                         return ret;
2396                 }
2397         }
2398         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2399         if (ret) {
2400                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2401                 return ret;
2402         }
2403         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2404         if (ret) {
2405                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2406                 return ret;
2407         }
2408         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2409         if (ret) {
2410                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2411                 return ret;
2412         }
2413         ret = device_create_file(adev->dev,
2414                         &dev_attr_pp_power_profile_mode);
2415         if (ret) {
2416                 DRM_ERROR("failed to create device file "
2417                                 "pp_power_profile_mode\n");
2418                 return ret;
2419         }
2420         if (hwmgr->od_enabled) {
2421                 ret = device_create_file(adev->dev,
2422                                 &dev_attr_pp_od_clk_voltage);
2423                 if (ret) {
2424                         DRM_ERROR("failed to create device file "
2425                                         "pp_od_clk_voltage\n");
2426                         return ret;
2427                 }
2428         }
2429         ret = device_create_file(adev->dev,
2430                         &dev_attr_gpu_busy_percent);
2431         if (ret) {
2432                 DRM_ERROR("failed to create device file "
2433                                 "gpu_busy_level\n");
2434                 return ret;
2435         }
2436         /* PCIe Perf counters won't work on APU nodes */
2437         if (!(adev->flags & AMD_IS_APU)) {
2438                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2439                 if (ret) {
2440                         DRM_ERROR("failed to create device file pcie_bw\n");
2441                         return ret;
2442                 }
2443         }
2444         ret = amdgpu_debugfs_pm_init(adev);
2445         if (ret) {
2446                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2447                 return ret;
2448         }
2449
2450         if ((adev->asic_type >= CHIP_VEGA10) &&
2451             !(adev->flags & AMD_IS_APU)) {
2452                 ret = device_create_file(adev->dev,
2453                                 &dev_attr_ppfeatures);
2454                 if (ret) {
2455                         DRM_ERROR("failed to create device file "
2456                                         "ppfeatures\n");
2457                         return ret;
2458                 }
2459         }
2460
2461         adev->pm.sysfs_initialized = true;
2462
2463         return 0;
2464 }
2465
2466 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2467 {
2468         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2469
2470         if (adev->pm.dpm_enabled == 0)
2471                 return;
2472
2473         if (adev->pm.int_hwmon_dev)
2474                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2475         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2476         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2477
2478         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2479         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2480         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2481         device_remove_file(adev->dev, &dev_attr_pp_table);
2482
2483         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2484         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2485         if (adev->asic_type >= CHIP_VEGA10) {
2486                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2487                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2488         }
2489         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2490         if (adev->asic_type >= CHIP_VEGA20)
2491                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2492         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2493         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2494         device_remove_file(adev->dev,
2495                         &dev_attr_pp_power_profile_mode);
2496         if (hwmgr->od_enabled)
2497                 device_remove_file(adev->dev,
2498                                 &dev_attr_pp_od_clk_voltage);
2499         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2500         if (!(adev->flags & AMD_IS_APU))
2501                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2502         if ((adev->asic_type >= CHIP_VEGA10) &&
2503             !(adev->flags & AMD_IS_APU))
2504                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2505 }
2506
2507 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2508 {
2509         int i = 0;
2510
2511         if (!adev->pm.dpm_enabled)
2512                 return;
2513
2514         if (adev->mode_info.num_crtc)
2515                 amdgpu_display_bandwidth_update(adev);
2516
2517         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2518                 struct amdgpu_ring *ring = adev->rings[i];
2519                 if (ring && ring->sched.ready)
2520                         amdgpu_fence_wait_empty(ring);
2521         }
2522
2523         if (adev->powerplay.pp_funcs->dispatch_tasks) {
2524                 if (!amdgpu_device_has_dc_support(adev)) {
2525                         mutex_lock(&adev->pm.mutex);
2526                         amdgpu_dpm_get_active_displays(adev);
2527                         adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2528                         adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2529                         adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2530                         /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2531                         if (adev->pm.pm_display_cfg.vrefresh > 120)
2532                                 adev->pm.pm_display_cfg.min_vblank_time = 0;
2533                         if (adev->powerplay.pp_funcs->display_configuration_change)
2534                                 adev->powerplay.pp_funcs->display_configuration_change(
2535                                                                 adev->powerplay.pp_handle,
2536                                                                 &adev->pm.pm_display_cfg);
2537                         mutex_unlock(&adev->pm.mutex);
2538                 }
2539                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2540         } else {
2541                 mutex_lock(&adev->pm.mutex);
2542                 amdgpu_dpm_get_active_displays(adev);
2543                 amdgpu_dpm_change_power_state_locked(adev);
2544                 mutex_unlock(&adev->pm.mutex);
2545         }
2546 }
2547
2548 /*
2549  * Debugfs info
2550  */
2551 #if defined(CONFIG_DEBUG_FS)
2552
2553 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2554 {
2555         uint32_t value;
2556         uint64_t value64;
2557         uint32_t query = 0;
2558         int size;
2559
2560         /* GPU Clocks */
2561         size = sizeof(value);
2562         seq_printf(m, "GFX Clocks and Power:\n");
2563         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2564                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2565         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2566                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2567         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2568                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2569         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2570                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2571         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2572                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2573         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2574                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2575         size = sizeof(uint32_t);
2576         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2577                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2578         size = sizeof(value);
2579         seq_printf(m, "\n");
2580
2581         /* GPU Temp */
2582         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2583                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2584
2585         /* GPU Load */
2586         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2587                 seq_printf(m, "GPU Load: %u %%\n", value);
2588         seq_printf(m, "\n");
2589
2590         /* SMC feature mask */
2591         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
2592                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
2593
2594         /* UVD clocks */
2595         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2596                 if (!value) {
2597                         seq_printf(m, "UVD: Disabled\n");
2598                 } else {
2599                         seq_printf(m, "UVD: Enabled\n");
2600                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2601                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2602                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2603                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2604                 }
2605         }
2606         seq_printf(m, "\n");
2607
2608         /* VCE clocks */
2609         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2610                 if (!value) {
2611                         seq_printf(m, "VCE: Disabled\n");
2612                 } else {
2613                         seq_printf(m, "VCE: Enabled\n");
2614                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2615                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2616                 }
2617         }
2618
2619         return 0;
2620 }
2621
2622 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2623 {
2624         int i;
2625
2626         for (i = 0; clocks[i].flag; i++)
2627                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2628                            (flags & clocks[i].flag) ? "On" : "Off");
2629 }
2630
2631 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2632 {
2633         struct drm_info_node *node = (struct drm_info_node *) m->private;
2634         struct drm_device *dev = node->minor->dev;
2635         struct amdgpu_device *adev = dev->dev_private;
2636         struct drm_device *ddev = adev->ddev;
2637         u32 flags = 0;
2638
2639         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2640         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2641         amdgpu_parse_cg_state(m, flags);
2642         seq_printf(m, "\n");
2643
2644         if (!adev->pm.dpm_enabled) {
2645                 seq_printf(m, "dpm not enabled\n");
2646                 return 0;
2647         }
2648         if  ((adev->flags & AMD_IS_PX) &&
2649              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2650                 seq_printf(m, "PX asic powered off\n");
2651         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2652                 mutex_lock(&adev->pm.mutex);
2653                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2654                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2655                 else
2656                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2657                 mutex_unlock(&adev->pm.mutex);
2658         } else {
2659                 return amdgpu_debugfs_pm_info_pp(m, adev);
2660         }
2661
2662         return 0;
2663 }
2664
2665 static const struct drm_info_list amdgpu_pm_info_list[] = {
2666         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2667 };
2668 #endif
2669
2670 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2671 {
2672 #if defined(CONFIG_DEBUG_FS)
2673         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2674 #else
2675         return 0;
2676 #endif
2677 }