drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include <linux/pm_runtime.h>
  41 #include "hwmgr.h"
  42 #define WIDTH_4K 3840
  43
  44 static const struct cg_flag_name clocks[] = {
  45         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  55         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  58         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  61         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  64         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  67         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  69
  70         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  72         {0, NULL},
  73 };
  74
  75 static const struct hwmon_temp_label {
  76         enum PP_HWMON_TEMP channel;
  77         const char *label;
  78 } temp_label[] = {
  79         {PP_TEMP_EDGE, "edge"},
  80         {PP_TEMP_JUNCTION, "junction"},
  81         {PP_TEMP_MEM, "mem"},
  82 };
  83
  84 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  85 {
  86         if (adev->pm.dpm_enabled) {
  87                 mutex_lock(&adev->pm.mutex);
  88                 if (power_supply_is_system_supplied() > 0)
  89                         adev->pm.ac_power = true;
  90                 else
  91                         adev->pm.ac_power = false;
  92                 if (adev->powerplay.pp_funcs &&
  93                     adev->powerplay.pp_funcs->enable_bapm)
  94                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  95                 mutex_unlock(&adev->pm.mutex);
  96
  97                 if (is_support_sw_smu(adev))
  98                         smu_set_ac_dc(&adev->smu);
  99         }
 100 }
 101
 102 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 103                            void *data, uint32_t *size)
 104 {
 105         int ret = 0;
 106
 107         if (!data || !size)
 108                 return -EINVAL;
 109
 110         if (is_support_sw_smu(adev))
 111                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 112         else {
 113                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 114                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 115                                                                     sensor, data, size);
 116                 else
 117                         ret = -EINVAL;
 118         }
 119
 120         return ret;
 121 }
 122
 123 /**
 124  * DOC: power_dpm_state
 125  *
 126  * The power_dpm_state file is a legacy interface and is only provided for
 127  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 128  * certain power related parameters.  The file power_dpm_state is used for this.
 129  * It accepts the following arguments:
 130  *
 131  * - battery
 132  *
 133  * - balanced
 134  *
 135  * - performance
 136  *
 137  * battery
 138  *
 139  * On older GPUs, the vbios provided a special power state for battery
 140  * operation.  Selecting battery switched to this state.  This is no
 141  * longer provided on newer GPUs so the option does nothing in that case.
 142  *
 143  * balanced
 144  *
 145  * On older GPUs, the vbios provided a special power state for balanced
 146  * operation.  Selecting balanced switched to this state.  This is no
 147  * longer provided on newer GPUs so the option does nothing in that case.
 148  *
 149  * performance
 150  *
 151  * On older GPUs, the vbios provided a special power state for performance
 152  * operation.  Selecting performance switched to this state.  This is no
 153  * longer provided on newer GPUs so the option does nothing in that case.
 154  *
 155  */
 156
 157 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 158                                           struct device_attribute *attr,
 159                                           char *buf)
 160 {
 161         struct drm_device *ddev = dev_get_drvdata(dev);
 162         struct amdgpu_device *adev = ddev->dev_private;
 163         enum amd_pm_state_type pm;
 164         int ret;
 165
 166         if (adev->in_gpu_reset)
 167                 return -EPERM;
 168
 169         ret = pm_runtime_get_sync(ddev->dev);
 170         if (ret < 0) {
 171                 pm_runtime_put_autosuspend(ddev->dev);
 172                 return ret;
 173         }
 174
 175         if (is_support_sw_smu(adev)) {
 176                 if (adev->smu.ppt_funcs->get_current_power_state)
 177                         pm = smu_get_current_power_state(&adev->smu);
 178                 else
 179                         pm = adev->pm.dpm.user_state;
 180         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 181                 pm = amdgpu_dpm_get_current_power_state(adev);
 182         } else {
 183                 pm = adev->pm.dpm.user_state;
 184         }
 185
 186         pm_runtime_mark_last_busy(ddev->dev);
 187         pm_runtime_put_autosuspend(ddev->dev);
 188
 189         return snprintf(buf, PAGE_SIZE, "%s\n",
 190                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 191                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 192 }
 193
 194 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 195                                           struct device_attribute *attr,
 196                                           const char *buf,
 197                                           size_t count)
 198 {
 199         struct drm_device *ddev = dev_get_drvdata(dev);
 200         struct amdgpu_device *adev = ddev->dev_private;
 201         enum amd_pm_state_type  state;
 202         int ret;
 203
 204         if (adev->in_gpu_reset)
 205                 return -EPERM;
 206
 207         if (strncmp("battery", buf, strlen("battery")) == 0)
 208                 state = POWER_STATE_TYPE_BATTERY;
 209         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 210                 state = POWER_STATE_TYPE_BALANCED;
 211         else if (strncmp("performance", buf, strlen("performance")) == 0)
 212                 state = POWER_STATE_TYPE_PERFORMANCE;
 213         else
 214                 return -EINVAL;
 215
 216         ret = pm_runtime_get_sync(ddev->dev);
 217         if (ret < 0) {
 218                 pm_runtime_put_autosuspend(ddev->dev);
 219                 return ret;
 220         }
 221
 222         if (is_support_sw_smu(adev)) {
 223                 mutex_lock(&adev->pm.mutex);
 224                 adev->pm.dpm.user_state = state;
 225                 mutex_unlock(&adev->pm.mutex);
 226         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 227                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 228         } else {
 229                 mutex_lock(&adev->pm.mutex);
 230                 adev->pm.dpm.user_state = state;
 231                 mutex_unlock(&adev->pm.mutex);
 232
 233                 amdgpu_pm_compute_clocks(adev);
 234         }
 235         pm_runtime_mark_last_busy(ddev->dev);
 236         pm_runtime_put_autosuspend(ddev->dev);
 237
 238         return count;
 239 }
 240
 241
 242 /**
 243  * DOC: power_dpm_force_performance_level
 244  *
 245  * The amdgpu driver provides a sysfs API for adjusting certain power
 246  * related parameters.  The file power_dpm_force_performance_level is
 247  * used for this.  It accepts the following arguments:
 248  *
 249  * - auto
 250  *
 251  * - low
 252  *
 253  * - high
 254  *
 255  * - manual
 256  *
 257  * - profile_standard
 258  *
 259  * - profile_min_sclk
 260  *
 261  * - profile_min_mclk
 262  *
 263  * - profile_peak
 264  *
 265  * auto
 266  *
 267  * When auto is selected, the driver will attempt to dynamically select
 268  * the optimal power profile for current conditions in the driver.
 269  *
 270  * low
 271  *
 272  * When low is selected, the clocks are forced to the lowest power state.
 273  *
 274  * high
 275  *
 276  * When high is selected, the clocks are forced to the highest power state.
 277  *
 278  * manual
 279  *
 280  * When manual is selected, the user can manually adjust which power states
 281  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 282  * and pp_dpm_pcie files and adjust the power state transition heuristics
 283  * via the pp_power_profile_mode sysfs file.
 284  *
 285  * profile_standard
 286  * profile_min_sclk
 287  * profile_min_mclk
 288  * profile_peak
 289  *
 290  * When the profiling modes are selected, clock and power gating are
 291  * disabled and the clocks are set for different profiling cases. This
 292  * mode is recommended for profiling specific work loads where you do
 293  * not want clock or power gating for clock fluctuation to interfere
 294  * with your results. profile_standard sets the clocks to a fixed clock
 295  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 296  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 297  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 298  *
 299  */
 300
 301 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 302                                                             struct device_attribute *attr,
 303                                                             char *buf)
 304 {
 305         struct drm_device *ddev = dev_get_drvdata(dev);
 306         struct amdgpu_device *adev = ddev->dev_private;
 307         enum amd_dpm_forced_level level = 0xff;
 308         int ret;
 309
 310         if (adev->in_gpu_reset)
 311                 return -EPERM;
 312
 313         ret = pm_runtime_get_sync(ddev->dev);
 314         if (ret < 0) {
 315                 pm_runtime_put_autosuspend(ddev->dev);
 316                 return ret;
 317         }
 318
 319         if (is_support_sw_smu(adev))
 320                 level = smu_get_performance_level(&adev->smu);
 321         else if (adev->powerplay.pp_funcs->get_performance_level)
 322                 level = amdgpu_dpm_get_performance_level(adev);
 323         else
 324                 level = adev->pm.dpm.forced_level;
 325
 326         pm_runtime_mark_last_busy(ddev->dev);
 327         pm_runtime_put_autosuspend(ddev->dev);
 328
 329         return snprintf(buf, PAGE_SIZE, "%s\n",
 330                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 331                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 332                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 333                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 334                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 335                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 336                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 337                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 338                         "unknown");
 339 }
 340
 341 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 342                                                             struct device_attribute *attr,
 343                                                             const char *buf,
 344                                                             size_t count)
 345 {
 346         struct drm_device *ddev = dev_get_drvdata(dev);
 347         struct amdgpu_device *adev = ddev->dev_private;
 348         enum amd_dpm_forced_level level;
 349         enum amd_dpm_forced_level current_level = 0xff;
 350         int ret = 0;
 351
 352         if (adev->in_gpu_reset)
 353                 return -EPERM;
 354
 355         if (strncmp("low", buf, strlen("low")) == 0) {
 356                 level = AMD_DPM_FORCED_LEVEL_LOW;
 357         } else if (strncmp("high", buf, strlen("high")) == 0) {
 358                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 359         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 360                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 361         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 362                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 363         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 364                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 365         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 366                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 367         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 368                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 369         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 370                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 371         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 372                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 373         }  else {
 374                 return -EINVAL;
 375         }
 376
 377         ret = pm_runtime_get_sync(ddev->dev);
 378         if (ret < 0) {
 379                 pm_runtime_put_autosuspend(ddev->dev);
 380                 return ret;
 381         }
 382
 383         if (is_support_sw_smu(adev))
 384                 current_level = smu_get_performance_level(&adev->smu);
 385         else if (adev->powerplay.pp_funcs->get_performance_level)
 386                 current_level = amdgpu_dpm_get_performance_level(adev);
 387
 388         if (current_level == level) {
 389                 pm_runtime_mark_last_busy(ddev->dev);
 390                 pm_runtime_put_autosuspend(ddev->dev);
 391                 return count;
 392         }
 393
 394         if (adev->asic_type == CHIP_RAVEN) {
 395                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 396                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 397                                 amdgpu_gfx_off_ctrl(adev, false);
 398                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 399                                 amdgpu_gfx_off_ctrl(adev, true);
 400                 }
 401         }
 402
 403         /* profile_exit setting is valid only when current mode is in profile mode */
 404         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 405             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 406             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 407             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 408             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 409                 pr_err("Currently not in any profile mode!\n");
 410                 pm_runtime_mark_last_busy(ddev->dev);
 411                 pm_runtime_put_autosuspend(ddev->dev);
 412                 return -EINVAL;
 413         }
 414
 415         if (is_support_sw_smu(adev)) {
 416                 ret = smu_force_performance_level(&adev->smu, level);
 417                 if (ret) {
 418                         pm_runtime_mark_last_busy(ddev->dev);
 419                         pm_runtime_put_autosuspend(ddev->dev);
 420                         return -EINVAL;
 421                 }
 422         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 423                 mutex_lock(&adev->pm.mutex);
 424                 if (adev->pm.dpm.thermal_active) {
 425                         mutex_unlock(&adev->pm.mutex);
 426                         pm_runtime_mark_last_busy(ddev->dev);
 427                         pm_runtime_put_autosuspend(ddev->dev);
 428                         return -EINVAL;
 429                 }
 430                 ret = amdgpu_dpm_force_performance_level(adev, level);
 431                 if (ret) {
 432                         mutex_unlock(&adev->pm.mutex);
 433                         pm_runtime_mark_last_busy(ddev->dev);
 434                         pm_runtime_put_autosuspend(ddev->dev);
 435                         return -EINVAL;
 436                 } else {
 437                         adev->pm.dpm.forced_level = level;
 438                 }
 439                 mutex_unlock(&adev->pm.mutex);
 440         }
 441         pm_runtime_mark_last_busy(ddev->dev);
 442         pm_runtime_put_autosuspend(ddev->dev);
 443
 444         return count;
 445 }
 446
 447 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 448                 struct device_attribute *attr,
 449                 char *buf)
 450 {
 451         struct drm_device *ddev = dev_get_drvdata(dev);
 452         struct amdgpu_device *adev = ddev->dev_private;
 453         struct pp_states_info data;
 454         int i, buf_len, ret;
 455
 456         if (adev->in_gpu_reset)
 457                 return -EPERM;
 458
 459         ret = pm_runtime_get_sync(ddev->dev);
 460         if (ret < 0) {
 461                 pm_runtime_put_autosuspend(ddev->dev);
 462                 return ret;
 463         }
 464
 465         if (is_support_sw_smu(adev)) {
 466                 ret = smu_get_power_num_states(&adev->smu, &data);
 467                 if (ret)
 468                         return ret;
 469         } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
 470                 amdgpu_dpm_get_pp_num_states(adev, &data);
 471         } else {
 472                 memset(&data, 0, sizeof(data));
 473         }
 474
 475         pm_runtime_mark_last_busy(ddev->dev);
 476         pm_runtime_put_autosuspend(ddev->dev);
 477
 478         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 479         for (i = 0; i < data.nums; i++)
 480                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 481                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 482                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 483                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 484                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 485
 486         return buf_len;
 487 }
 488
 489 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 490                 struct device_attribute *attr,
 491                 char *buf)
 492 {
 493         struct drm_device *ddev = dev_get_drvdata(dev);
 494         struct amdgpu_device *adev = ddev->dev_private;
 495         struct pp_states_info data;
 496         struct smu_context *smu = &adev->smu;
 497         enum amd_pm_state_type pm = 0;
 498         int i = 0, ret = 0;
 499
 500         if (adev->in_gpu_reset)
 501                 return -EPERM;
 502
 503         ret = pm_runtime_get_sync(ddev->dev);
 504         if (ret < 0) {
 505                 pm_runtime_put_autosuspend(ddev->dev);
 506                 return ret;
 507         }
 508
 509         if (is_support_sw_smu(adev)) {
 510                 pm = smu_get_current_power_state(smu);
 511                 ret = smu_get_power_num_states(smu, &data);
 512                 if (ret)
 513                         return ret;
 514         } else if (adev->powerplay.pp_funcs->get_current_power_state
 515                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 516                 pm = amdgpu_dpm_get_current_power_state(adev);
 517                 amdgpu_dpm_get_pp_num_states(adev, &data);
 518         }
 519
 520         pm_runtime_mark_last_busy(ddev->dev);
 521         pm_runtime_put_autosuspend(ddev->dev);
 522
 523         for (i = 0; i < data.nums; i++) {
 524                 if (pm == data.states[i])
 525                         break;
 526         }
 527
 528         if (i == data.nums)
 529                 i = -EINVAL;
 530
 531         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 532 }
 533
 534 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 535                 struct device_attribute *attr,
 536                 char *buf)
 537 {
 538         struct drm_device *ddev = dev_get_drvdata(dev);
 539         struct amdgpu_device *adev = ddev->dev_private;
 540
 541         if (adev->in_gpu_reset)
 542                 return -EPERM;
 543
 544         if (adev->pp_force_state_enabled)
 545                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 546         else
 547                 return snprintf(buf, PAGE_SIZE, "\n");
 548 }
 549
 550 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 551                 struct device_attribute *attr,
 552                 const char *buf,
 553                 size_t count)
 554 {
 555         struct drm_device *ddev = dev_get_drvdata(dev);
 556         struct amdgpu_device *adev = ddev->dev_private;
 557         enum amd_pm_state_type state = 0;
 558         unsigned long idx;
 559         int ret;
 560
 561         if (adev->in_gpu_reset)
 562                 return -EPERM;
 563
 564         if (strlen(buf) == 1)
 565                 adev->pp_force_state_enabled = false;
 566         else if (is_support_sw_smu(adev))
 567                 adev->pp_force_state_enabled = false;
 568         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 569                         adev->powerplay.pp_funcs->get_pp_num_states) {
 570                 struct pp_states_info data;
 571
 572                 ret = kstrtoul(buf, 0, &idx);
 573                 if (ret || idx >= ARRAY_SIZE(data.states))
 574                         return -EINVAL;
 575
 576                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 577
 578                 amdgpu_dpm_get_pp_num_states(adev, &data);
 579                 state = data.states[idx];
 580
 581                 ret = pm_runtime_get_sync(ddev->dev);
 582                 if (ret < 0) {
 583                         pm_runtime_put_autosuspend(ddev->dev);
 584                         return ret;
 585                 }
 586
 587                 /* only set user selected power states */
 588                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 589                     state != POWER_STATE_TYPE_DEFAULT) {
 590                         amdgpu_dpm_dispatch_task(adev,
 591                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 592                         adev->pp_force_state_enabled = true;
 593                 }
 594                 pm_runtime_mark_last_busy(ddev->dev);
 595                 pm_runtime_put_autosuspend(ddev->dev);
 596         }
 597
 598         return count;
 599 }
 600
 601 /**
 602  * DOC: pp_table
 603  *
 604  * The amdgpu driver provides a sysfs API for uploading new powerplay
 605  * tables.  The file pp_table is used for this.  Reading the file
 606  * will dump the current power play table.  Writing to the file
 607  * will attempt to upload a new powerplay table and re-initialize
 608  * powerplay using that new table.
 609  *
 610  */
 611
 612 static ssize_t amdgpu_get_pp_table(struct device *dev,
 613                 struct device_attribute *attr,
 614                 char *buf)
 615 {
 616         struct drm_device *ddev = dev_get_drvdata(dev);
 617         struct amdgpu_device *adev = ddev->dev_private;
 618         char *table = NULL;
 619         int size, ret;
 620
 621         if (adev->in_gpu_reset)
 622                 return -EPERM;
 623
 624         ret = pm_runtime_get_sync(ddev->dev);
 625         if (ret < 0) {
 626                 pm_runtime_put_autosuspend(ddev->dev);
 627                 return ret;
 628         }
 629
 630         if (is_support_sw_smu(adev)) {
 631                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 632                 pm_runtime_mark_last_busy(ddev->dev);
 633                 pm_runtime_put_autosuspend(ddev->dev);
 634                 if (size < 0)
 635                         return size;
 636         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 637                 size = amdgpu_dpm_get_pp_table(adev, &table);
 638                 pm_runtime_mark_last_busy(ddev->dev);
 639                 pm_runtime_put_autosuspend(ddev->dev);
 640                 if (size < 0)
 641                         return size;
 642         } else {
 643                 pm_runtime_mark_last_busy(ddev->dev);
 644                 pm_runtime_put_autosuspend(ddev->dev);
 645                 return 0;
 646         }
 647
 648         if (size >= PAGE_SIZE)
 649                 size = PAGE_SIZE - 1;
 650
 651         memcpy(buf, table, size);
 652
 653         return size;
 654 }
 655
 656 static ssize_t amdgpu_set_pp_table(struct device *dev,
 657                 struct device_attribute *attr,
 658                 const char *buf,
 659                 size_t count)
 660 {
 661         struct drm_device *ddev = dev_get_drvdata(dev);
 662         struct amdgpu_device *adev = ddev->dev_private;
 663         int ret = 0;
 664
 665         if (adev->in_gpu_reset)
 666                 return -EPERM;
 667
 668         ret = pm_runtime_get_sync(ddev->dev);
 669         if (ret < 0) {
 670                 pm_runtime_put_autosuspend(ddev->dev);
 671                 return ret;
 672         }
 673
 674         if (is_support_sw_smu(adev)) {
 675                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 676                 if (ret) {
 677                         pm_runtime_mark_last_busy(ddev->dev);
 678                         pm_runtime_put_autosuspend(ddev->dev);
 679                         return ret;
 680                 }
 681         } else if (adev->powerplay.pp_funcs->set_pp_table)
 682                 amdgpu_dpm_set_pp_table(adev, buf, count);
 683
 684         pm_runtime_mark_last_busy(ddev->dev);
 685         pm_runtime_put_autosuspend(ddev->dev);
 686
 687         return count;
 688 }
 689
 690 /**
 691  * DOC: pp_od_clk_voltage
 692  *
 693  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 694  * in each power level within a power state.  The pp_od_clk_voltage is used for
 695  * this.
 696  *
 697  * Note that the actual memory controller clock rate are exposed, not
 698  * the effective memory clock of the DRAMs. To translate it, use the
 699  * following formula:
 700  *
 701  * Clock conversion (Mhz):
 702  *
 703  * HBM: effective_memory_clock = memory_controller_clock * 1
 704  *
 705  * G5: effective_memory_clock = memory_controller_clock * 1
 706  *
 707  * G6: effective_memory_clock = memory_controller_clock * 2
 708  *
 709  * DRAM data rate (MT/s):
 710  *
 711  * HBM: effective_memory_clock * 2 = data_rate
 712  *
 713  * G5: effective_memory_clock * 4 = data_rate
 714  *
 715  * G6: effective_memory_clock * 8 = data_rate
 716  *
 717  * Bandwidth (MB/s):
 718  *
 719  * data_rate * vram_bit_width / 8 = memory_bandwidth
 720  *
 721  * Some examples:
 722  *
 723  * G5 on RX460:
 724  *
 725  * memory_controller_clock = 1750 Mhz
 726  *
 727  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 728  *
 729  * data rate = 1750 * 4 = 7000 MT/s
 730  *
 731  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 732  *
 733  * G6 on RX5700:
 734  *
 735  * memory_controller_clock = 875 Mhz
 736  *
 737  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 738  *
 739  * data rate = 1750 * 8 = 14000 MT/s
 740  *
 741  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 742  *
 743  * < For Vega10 and previous ASICs >
 744  *
 745  * Reading the file will display:
 746  *
 747  * - a list of engine clock levels and voltages labeled OD_SCLK
 748  *
 749  * - a list of memory clock levels and voltages labeled OD_MCLK
 750  *
 751  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 752  *
 753  * To manually adjust these settings, first select manual using
 754  * power_dpm_force_performance_level. Enter a new value for each
 755  * level by writing a string that contains "s/m level clock voltage" to
 756  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 757  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 758  * 810 mV.  When you have edited all of the states as needed, write
 759  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 760  * default power levels, write "r" (reset) to the file to reset them.
 761  *
 762  *
 763  * < For Vega20 and newer ASICs >
 764  *
 765  * Reading the file will display:
 766  *
 767  * - minimum and maximum engine clock labeled OD_SCLK
 768  *
 769  * - maximum memory clock labeled OD_MCLK
 770  *
 771  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 772  *   They can be used to calibrate the sclk voltage curve.
 773  *
 774  * - a list of valid ranges for sclk, mclk, and voltage curve points
 775  *   labeled OD_RANGE
 776  *
 777  * To manually adjust these settings:
 778  *
 779  * - First select manual using power_dpm_force_performance_level
 780  *
 781  * - For clock frequency setting, enter a new value by writing a
 782  *   string that contains "s/m index clock" to the file. The index
 783  *   should be 0 if to set minimum clock. And 1 if to set maximum
 784  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 785  *   "m 1 800" will update maximum mclk to be 800Mhz.
 786  *
 787  *   For sclk voltage curve, enter the new values by writing a
 788  *   string that contains "vc point clock voltage" to the file. The
 789  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 790  *   update point1 with clock set as 300Mhz and voltage as
 791  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 792  *   as 1000Mhz and voltage 1000mV.
 793  *
 794  * - When you have edited all of the states as needed, write "c" (commit)
 795  *   to the file to commit your changes
 796  *
 797  * - If you want to reset to the default power levels, write "r" (reset)
 798  *   to the file to reset them
 799  *
 800  */
 801
 802 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 803                 struct device_attribute *attr,
 804                 const char *buf,
 805                 size_t count)
 806 {
 807         struct drm_device *ddev = dev_get_drvdata(dev);
 808         struct amdgpu_device *adev = ddev->dev_private;
 809         int ret;
 810         uint32_t parameter_size = 0;
 811         long parameter[64];
 812         char buf_cpy[128];
 813         char *tmp_str;
 814         char *sub_str;
 815         const char delimiter[3] = {' ', '\n', '\0'};
 816         uint32_t type;
 817
 818         if (adev->in_gpu_reset)
 819                 return -EPERM;
 820
 821         if (count > 127)
 822                 return -EINVAL;
 823
 824         if (*buf == 's')
 825                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 826         else if (*buf == 'm')
 827                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 828         else if(*buf == 'r')
 829                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 830         else if (*buf == 'c')
 831                 type = PP_OD_COMMIT_DPM_TABLE;
 832         else if (!strncmp(buf, "vc", 2))
 833                 type = PP_OD_EDIT_VDDC_CURVE;
 834         else
 835                 return -EINVAL;
 836
 837         memcpy(buf_cpy, buf, count+1);
 838
 839         tmp_str = buf_cpy;
 840
 841         if (type == PP_OD_EDIT_VDDC_CURVE)
 842                 tmp_str++;
 843         while (isspace(*++tmp_str));
 844
 845         while (tmp_str[0]) {
 846                 sub_str = strsep(&tmp_str, delimiter);
 847                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 848                 if (ret)
 849                         return -EINVAL;
 850                 parameter_size++;
 851
 852                 while (isspace(*tmp_str))
 853                         tmp_str++;
 854         }
 855
 856         ret = pm_runtime_get_sync(ddev->dev);
 857         if (ret < 0) {
 858                 pm_runtime_put_autosuspend(ddev->dev);
 859                 return ret;
 860         }
 861
 862         if (is_support_sw_smu(adev)) {
 863                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 864                                             parameter, parameter_size);
 865
 866                 if (ret) {
 867                         pm_runtime_mark_last_busy(ddev->dev);
 868                         pm_runtime_put_autosuspend(ddev->dev);
 869                         return -EINVAL;
 870                 }
 871         } else {
 872                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 873                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 874                                                 parameter, parameter_size);
 875                         if (ret) {
 876                                 pm_runtime_mark_last_busy(ddev->dev);
 877                                 pm_runtime_put_autosuspend(ddev->dev);
 878                                 return -EINVAL;
 879                         }
 880                 }
 881
 882                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 883                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 884                                 amdgpu_dpm_dispatch_task(adev,
 885                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 886                                                 NULL);
 887                                 pm_runtime_mark_last_busy(ddev->dev);
 888                                 pm_runtime_put_autosuspend(ddev->dev);
 889                                 return count;
 890                         } else {
 891                                 pm_runtime_mark_last_busy(ddev->dev);
 892                                 pm_runtime_put_autosuspend(ddev->dev);
 893                                 return -EINVAL;
 894                         }
 895                 }
 896         }
 897         pm_runtime_mark_last_busy(ddev->dev);
 898         pm_runtime_put_autosuspend(ddev->dev);
 899
 900         return count;
 901 }
 902
 903 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 904                 struct device_attribute *attr,
 905                 char *buf)
 906 {
 907         struct drm_device *ddev = dev_get_drvdata(dev);
 908         struct amdgpu_device *adev = ddev->dev_private;
 909         ssize_t size;
 910         int ret;
 911
 912         if (adev->in_gpu_reset)
 913                 return -EPERM;
 914
 915         ret = pm_runtime_get_sync(ddev->dev);
 916         if (ret < 0) {
 917                 pm_runtime_put_autosuspend(ddev->dev);
 918                 return ret;
 919         }
 920
 921         if (is_support_sw_smu(adev)) {
 922                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 923                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 924                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 925                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 926         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 927                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 928                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 929                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 930                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 931         } else {
 932                 size = snprintf(buf, PAGE_SIZE, "\n");
 933         }
 934         pm_runtime_mark_last_busy(ddev->dev);
 935         pm_runtime_put_autosuspend(ddev->dev);
 936
 937         return size;
 938 }
 939
 940 /**
 941  * DOC: pp_features
 942  *
 943  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 944  * features to be enabled. The file pp_features is used for this. And
 945  * this is only available for Vega10 and later dGPUs.
 946  *
 947  * Reading back the file will show you the followings:
 948  * - Current ppfeature masks
 949  * - List of the all supported powerplay features with their naming,
 950  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 951  *
 952  * To manually enable or disable a specific feature, just set or clear
 953  * the corresponding bit from original ppfeature masks and input the
 954  * new ppfeature masks.
 955  */
 956 static ssize_t amdgpu_set_pp_features(struct device *dev,
 957                                       struct device_attribute *attr,
 958                                       const char *buf,
 959                                       size_t count)
 960 {
 961         struct drm_device *ddev = dev_get_drvdata(dev);
 962         struct amdgpu_device *adev = ddev->dev_private;
 963         uint64_t featuremask;
 964         int ret;
 965
 966         if (adev->in_gpu_reset)
 967                 return -EPERM;
 968
 969         ret = kstrtou64(buf, 0, &featuremask);
 970         if (ret)
 971                 return -EINVAL;
 972
 973         pr_debug("featuremask = 0x%llx\n", featuremask);
 974
 975         ret = pm_runtime_get_sync(ddev->dev);
 976         if (ret < 0) {
 977                 pm_runtime_put_autosuspend(ddev->dev);
 978                 return ret;
 979         }
 980
 981         if (is_support_sw_smu(adev)) {
 982                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 983                 if (ret) {
 984                         pm_runtime_mark_last_busy(ddev->dev);
 985                         pm_runtime_put_autosuspend(ddev->dev);
 986                         return -EINVAL;
 987                 }
 988         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 989                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 990                 if (ret) {
 991                         pm_runtime_mark_last_busy(ddev->dev);
 992                         pm_runtime_put_autosuspend(ddev->dev);
 993                         return -EINVAL;
 994                 }
 995         }
 996         pm_runtime_mark_last_busy(ddev->dev);
 997         pm_runtime_put_autosuspend(ddev->dev);
 998
 999         return count;
1000 }
1001
1002 static ssize_t amdgpu_get_pp_features(struct device *dev,
1003                                       struct device_attribute *attr,
1004                                       char *buf)
1005 {
1006         struct drm_device *ddev = dev_get_drvdata(dev);
1007         struct amdgpu_device *adev = ddev->dev_private;
1008         ssize_t size;
1009         int ret;
1010
1011         if (adev->in_gpu_reset)
1012                 return -EPERM;
1013
1014         ret = pm_runtime_get_sync(ddev->dev);
1015         if (ret < 0) {
1016                 pm_runtime_put_autosuspend(ddev->dev);
1017                 return ret;
1018         }
1019
1020         if (is_support_sw_smu(adev))
1021                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
1022         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
1023                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
1024         else
1025                 size = snprintf(buf, PAGE_SIZE, "\n");
1026
1027         pm_runtime_mark_last_busy(ddev->dev);
1028         pm_runtime_put_autosuspend(ddev->dev);
1029
1030         return size;
1031 }
1032
1033 /**
1034  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
1035  *
1036  * The amdgpu driver provides a sysfs API for adjusting what power levels
1037  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
1038  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
1039  * this.
1040  *
1041  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
1042  * Vega10 and later ASICs.
1043  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
1044  *
1045  * Reading back the files will show you the available power levels within
1046  * the power state and the clock information for those levels.
1047  *
1048  * To manually adjust these states, first select manual using
1049  * power_dpm_force_performance_level.
1050  * Secondly, enter a new value for each level by inputing a string that
1051  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1052  * E.g.,
1053  *
1054  * .. code-block:: bash
1055  *
1056  *      echo "4 5 6" > pp_dpm_sclk
1057  *
1058  * will enable sclk levels 4, 5, and 6.
1059  *
1060  * NOTE: change to the dcefclk max dpm level is not supported now
1061  */
1062
1063 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1064                 struct device_attribute *attr,
1065                 char *buf)
1066 {
1067         struct drm_device *ddev = dev_get_drvdata(dev);
1068         struct amdgpu_device *adev = ddev->dev_private;
1069         ssize_t size;
1070         int ret;
1071
1072         if (adev->in_gpu_reset)
1073                 return -EPERM;
1074
1075         ret = pm_runtime_get_sync(ddev->dev);
1076         if (ret < 0) {
1077                 pm_runtime_put_autosuspend(ddev->dev);
1078                 return ret;
1079         }
1080
1081         if (is_support_sw_smu(adev))
1082                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
1083         else if (adev->powerplay.pp_funcs->print_clock_levels)
1084                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
1085         else
1086                 size = snprintf(buf, PAGE_SIZE, "\n");
1087
1088         pm_runtime_mark_last_busy(ddev->dev);
1089         pm_runtime_put_autosuspend(ddev->dev);
1090
1091         return size;
1092 }
1093
1094 /*
1095  * Worst case: 32 bits individually specified, in octal at 12 characters
1096  * per line (+1 for \n).
1097  */
1098 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1099
1100 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1101 {
1102         int ret;
1103         long level;
1104         char *sub_str = NULL;
1105         char *tmp;
1106         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1107         const char delimiter[3] = {' ', '\n', '\0'};
1108         size_t bytes;
1109
1110         *mask = 0;
1111
1112         bytes = min(count, sizeof(buf_cpy) - 1);
1113         memcpy(buf_cpy, buf, bytes);
1114         buf_cpy[bytes] = '\0';
1115         tmp = buf_cpy;
1116         while (tmp[0]) {
1117                 sub_str = strsep(&tmp, delimiter);
1118                 if (strlen(sub_str)) {
1119                         ret = kstrtol(sub_str, 0, &level);
1120                         if (ret)
1121                                 return -EINVAL;
1122                         *mask |= 1 << level;
1123                 } else
1124                         break;
1125         }
1126
1127         return 0;
1128 }
1129
1130 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1131                 struct device_attribute *attr,
1132                 const char *buf,
1133                 size_t count)
1134 {
1135         struct drm_device *ddev = dev_get_drvdata(dev);
1136         struct amdgpu_device *adev = ddev->dev_private;
1137         int ret;
1138         uint32_t mask = 0;
1139
1140         if (adev->in_gpu_reset)
1141                 return -EPERM;
1142
1143         ret = amdgpu_read_mask(buf, count, &mask);
1144         if (ret)
1145                 return ret;
1146
1147         ret = pm_runtime_get_sync(ddev->dev);
1148         if (ret < 0) {
1149                 pm_runtime_put_autosuspend(ddev->dev);
1150                 return ret;
1151         }
1152
1153         if (is_support_sw_smu(adev))
1154                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
1155         else if (adev->powerplay.pp_funcs->force_clock_level)
1156                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1157
1158         pm_runtime_mark_last_busy(ddev->dev);
1159         pm_runtime_put_autosuspend(ddev->dev);
1160
1161         if (ret)
1162                 return -EINVAL;
1163
1164         return count;
1165 }
1166
1167 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1168                 struct device_attribute *attr,
1169                 char *buf)
1170 {
1171         struct drm_device *ddev = dev_get_drvdata(dev);
1172         struct amdgpu_device *adev = ddev->dev_private;
1173         ssize_t size;
1174         int ret;
1175
1176         if (adev->in_gpu_reset)
1177                 return -EPERM;
1178
1179         ret = pm_runtime_get_sync(ddev->dev);
1180         if (ret < 0) {
1181                 pm_runtime_put_autosuspend(ddev->dev);
1182                 return ret;
1183         }
1184
1185         if (is_support_sw_smu(adev))
1186                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1187         else if (adev->powerplay.pp_funcs->print_clock_levels)
1188                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1189         else
1190                 size = snprintf(buf, PAGE_SIZE, "\n");
1191
1192         pm_runtime_mark_last_busy(ddev->dev);
1193         pm_runtime_put_autosuspend(ddev->dev);
1194
1195         return size;
1196 }
1197
1198 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1199                 struct device_attribute *attr,
1200                 const char *buf,
1201                 size_t count)
1202 {
1203         struct drm_device *ddev = dev_get_drvdata(dev);
1204         struct amdgpu_device *adev = ddev->dev_private;
1205         uint32_t mask = 0;
1206         int ret;
1207
1208         if (adev->in_gpu_reset)
1209                 return -EPERM;
1210
1211         ret = amdgpu_read_mask(buf, count, &mask);
1212         if (ret)
1213                 return ret;
1214
1215         ret = pm_runtime_get_sync(ddev->dev);
1216         if (ret < 0) {
1217                 pm_runtime_put_autosuspend(ddev->dev);
1218                 return ret;
1219         }
1220
1221         if (is_support_sw_smu(adev))
1222                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
1223         else if (adev->powerplay.pp_funcs->force_clock_level)
1224                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1225
1226         pm_runtime_mark_last_busy(ddev->dev);
1227         pm_runtime_put_autosuspend(ddev->dev);
1228
1229         if (ret)
1230                 return -EINVAL;
1231
1232         return count;
1233 }
1234
1235 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1236                 struct device_attribute *attr,
1237                 char *buf)
1238 {
1239         struct drm_device *ddev = dev_get_drvdata(dev);
1240         struct amdgpu_device *adev = ddev->dev_private;
1241         ssize_t size;
1242         int ret;
1243
1244         if (adev->in_gpu_reset)
1245                 return -EPERM;
1246
1247         ret = pm_runtime_get_sync(ddev->dev);
1248         if (ret < 0) {
1249                 pm_runtime_put_autosuspend(ddev->dev);
1250                 return ret;
1251         }
1252
1253         if (is_support_sw_smu(adev))
1254                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1255         else if (adev->powerplay.pp_funcs->print_clock_levels)
1256                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1257         else
1258                 size = snprintf(buf, PAGE_SIZE, "\n");
1259
1260         pm_runtime_mark_last_busy(ddev->dev);
1261         pm_runtime_put_autosuspend(ddev->dev);
1262
1263         return size;
1264 }
1265
1266 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1267                 struct device_attribute *attr,
1268                 const char *buf,
1269                 size_t count)
1270 {
1271         struct drm_device *ddev = dev_get_drvdata(dev);
1272         struct amdgpu_device *adev = ddev->dev_private;
1273         int ret;
1274         uint32_t mask = 0;
1275
1276         if (adev->in_gpu_reset)
1277                 return -EPERM;
1278
1279         ret = amdgpu_read_mask(buf, count, &mask);
1280         if (ret)
1281                 return ret;
1282
1283         ret = pm_runtime_get_sync(ddev->dev);
1284         if (ret < 0) {
1285                 pm_runtime_put_autosuspend(ddev->dev);
1286                 return ret;
1287         }
1288
1289         if (is_support_sw_smu(adev))
1290                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
1291         else if (adev->powerplay.pp_funcs->force_clock_level)
1292                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1293         else
1294                 ret = 0;
1295
1296         pm_runtime_mark_last_busy(ddev->dev);
1297         pm_runtime_put_autosuspend(ddev->dev);
1298
1299         if (ret)
1300                 return -EINVAL;
1301
1302         return count;
1303 }
1304
1305 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1306                 struct device_attribute *attr,
1307                 char *buf)
1308 {
1309         struct drm_device *ddev = dev_get_drvdata(dev);
1310         struct amdgpu_device *adev = ddev->dev_private;
1311         ssize_t size;
1312         int ret;
1313
1314         if (adev->in_gpu_reset)
1315                 return -EPERM;
1316
1317         ret = pm_runtime_get_sync(ddev->dev);
1318         if (ret < 0) {
1319                 pm_runtime_put_autosuspend(ddev->dev);
1320                 return ret;
1321         }
1322
1323         if (is_support_sw_smu(adev))
1324                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1325         else if (adev->powerplay.pp_funcs->print_clock_levels)
1326                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1327         else
1328                 size = snprintf(buf, PAGE_SIZE, "\n");
1329
1330         pm_runtime_mark_last_busy(ddev->dev);
1331         pm_runtime_put_autosuspend(ddev->dev);
1332
1333         return size;
1334 }
1335
1336 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1337                 struct device_attribute *attr,
1338                 const char *buf,
1339                 size_t count)
1340 {
1341         struct drm_device *ddev = dev_get_drvdata(dev);
1342         struct amdgpu_device *adev = ddev->dev_private;
1343         int ret;
1344         uint32_t mask = 0;
1345
1346         if (adev->in_gpu_reset)
1347                 return -EPERM;
1348
1349         ret = amdgpu_read_mask(buf, count, &mask);
1350         if (ret)
1351                 return ret;
1352
1353         ret = pm_runtime_get_sync(ddev->dev);
1354         if (ret < 0) {
1355                 pm_runtime_put_autosuspend(ddev->dev);
1356                 return ret;
1357         }
1358
1359         if (is_support_sw_smu(adev))
1360                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
1361         else if (adev->powerplay.pp_funcs->force_clock_level)
1362                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1363         else
1364                 ret = 0;
1365
1366         pm_runtime_mark_last_busy(ddev->dev);
1367         pm_runtime_put_autosuspend(ddev->dev);
1368
1369         if (ret)
1370                 return -EINVAL;
1371
1372         return count;
1373 }
1374
1375 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1376                 struct device_attribute *attr,
1377                 char *buf)
1378 {
1379         struct drm_device *ddev = dev_get_drvdata(dev);
1380         struct amdgpu_device *adev = ddev->dev_private;
1381         ssize_t size;
1382         int ret;
1383
1384         if (adev->in_gpu_reset)
1385                 return -EPERM;
1386
1387         ret = pm_runtime_get_sync(ddev->dev);
1388         if (ret < 0) {
1389                 pm_runtime_put_autosuspend(ddev->dev);
1390                 return ret;
1391         }
1392
1393         if (is_support_sw_smu(adev))
1394                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1395         else if (adev->powerplay.pp_funcs->print_clock_levels)
1396                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1397         else
1398                 size = snprintf(buf, PAGE_SIZE, "\n");
1399
1400         pm_runtime_mark_last_busy(ddev->dev);
1401         pm_runtime_put_autosuspend(ddev->dev);
1402
1403         return size;
1404 }
1405
1406 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1407                 struct device_attribute *attr,
1408                 const char *buf,
1409                 size_t count)
1410 {
1411         struct drm_device *ddev = dev_get_drvdata(dev);
1412         struct amdgpu_device *adev = ddev->dev_private;
1413         int ret;
1414         uint32_t mask = 0;
1415
1416         if (adev->in_gpu_reset)
1417                 return -EPERM;
1418
1419         ret = amdgpu_read_mask(buf, count, &mask);
1420         if (ret)
1421                 return ret;
1422
1423         ret = pm_runtime_get_sync(ddev->dev);
1424         if (ret < 0) {
1425                 pm_runtime_put_autosuspend(ddev->dev);
1426                 return ret;
1427         }
1428
1429         if (is_support_sw_smu(adev))
1430                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
1431         else if (adev->powerplay.pp_funcs->force_clock_level)
1432                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1433         else
1434                 ret = 0;
1435
1436         pm_runtime_mark_last_busy(ddev->dev);
1437         pm_runtime_put_autosuspend(ddev->dev);
1438
1439         if (ret)
1440                 return -EINVAL;
1441
1442         return count;
1443 }
1444
1445 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1446                 struct device_attribute *attr,
1447                 char *buf)
1448 {
1449         struct drm_device *ddev = dev_get_drvdata(dev);
1450         struct amdgpu_device *adev = ddev->dev_private;
1451         ssize_t size;
1452         int ret;
1453
1454         if (adev->in_gpu_reset)
1455                 return -EPERM;
1456
1457         ret = pm_runtime_get_sync(ddev->dev);
1458         if (ret < 0) {
1459                 pm_runtime_put_autosuspend(ddev->dev);
1460                 return ret;
1461         }
1462
1463         if (is_support_sw_smu(adev))
1464                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1465         else if (adev->powerplay.pp_funcs->print_clock_levels)
1466                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1467         else
1468                 size = snprintf(buf, PAGE_SIZE, "\n");
1469
1470         pm_runtime_mark_last_busy(ddev->dev);
1471         pm_runtime_put_autosuspend(ddev->dev);
1472
1473         return size;
1474 }
1475
1476 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1477                 struct device_attribute *attr,
1478                 const char *buf,
1479                 size_t count)
1480 {
1481         struct drm_device *ddev = dev_get_drvdata(dev);
1482         struct amdgpu_device *adev = ddev->dev_private;
1483         int ret;
1484         uint32_t mask = 0;
1485
1486         if (adev->in_gpu_reset)
1487                 return -EPERM;
1488
1489         ret = amdgpu_read_mask(buf, count, &mask);
1490         if (ret)
1491                 return ret;
1492
1493         ret = pm_runtime_get_sync(ddev->dev);
1494         if (ret < 0) {
1495                 pm_runtime_put_autosuspend(ddev->dev);
1496                 return ret;
1497         }
1498
1499         if (is_support_sw_smu(adev))
1500                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
1501         else if (adev->powerplay.pp_funcs->force_clock_level)
1502                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1503         else
1504                 ret = 0;
1505
1506         pm_runtime_mark_last_busy(ddev->dev);
1507         pm_runtime_put_autosuspend(ddev->dev);
1508
1509         if (ret)
1510                 return -EINVAL;
1511
1512         return count;
1513 }
1514
1515 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1516                 struct device_attribute *attr,
1517                 char *buf)
1518 {
1519         struct drm_device *ddev = dev_get_drvdata(dev);
1520         struct amdgpu_device *adev = ddev->dev_private;
1521         uint32_t value = 0;
1522         int ret;
1523
1524         if (adev->in_gpu_reset)
1525                 return -EPERM;
1526
1527         ret = pm_runtime_get_sync(ddev->dev);
1528         if (ret < 0) {
1529                 pm_runtime_put_autosuspend(ddev->dev);
1530                 return ret;
1531         }
1532
1533         if (is_support_sw_smu(adev))
1534                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1535         else if (adev->powerplay.pp_funcs->get_sclk_od)
1536                 value = amdgpu_dpm_get_sclk_od(adev);
1537
1538         pm_runtime_mark_last_busy(ddev->dev);
1539         pm_runtime_put_autosuspend(ddev->dev);
1540
1541         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1542 }
1543
1544 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1545                 struct device_attribute *attr,
1546                 const char *buf,
1547                 size_t count)
1548 {
1549         struct drm_device *ddev = dev_get_drvdata(dev);
1550         struct amdgpu_device *adev = ddev->dev_private;
1551         int ret;
1552         long int value;
1553
1554         if (adev->in_gpu_reset)
1555                 return -EPERM;
1556
1557         ret = kstrtol(buf, 0, &value);
1558
1559         if (ret)
1560                 return -EINVAL;
1561
1562         ret = pm_runtime_get_sync(ddev->dev);
1563         if (ret < 0) {
1564                 pm_runtime_put_autosuspend(ddev->dev);
1565                 return ret;
1566         }
1567
1568         if (is_support_sw_smu(adev)) {
1569                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1570         } else {
1571                 if (adev->powerplay.pp_funcs->set_sclk_od)
1572                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1573
1574                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1575                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1576                 } else {
1577                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1578                         amdgpu_pm_compute_clocks(adev);
1579                 }
1580         }
1581
1582         pm_runtime_mark_last_busy(ddev->dev);
1583         pm_runtime_put_autosuspend(ddev->dev);
1584
1585         return count;
1586 }
1587
1588 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1589                 struct device_attribute *attr,
1590                 char *buf)
1591 {
1592         struct drm_device *ddev = dev_get_drvdata(dev);
1593         struct amdgpu_device *adev = ddev->dev_private;
1594         uint32_t value = 0;
1595         int ret;
1596
1597         if (adev->in_gpu_reset)
1598                 return -EPERM;
1599
1600         ret = pm_runtime_get_sync(ddev->dev);
1601         if (ret < 0) {
1602                 pm_runtime_put_autosuspend(ddev->dev);
1603                 return ret;
1604         }
1605
1606         if (is_support_sw_smu(adev))
1607                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1608         else if (adev->powerplay.pp_funcs->get_mclk_od)
1609                 value = amdgpu_dpm_get_mclk_od(adev);
1610
1611         pm_runtime_mark_last_busy(ddev->dev);
1612         pm_runtime_put_autosuspend(ddev->dev);
1613
1614         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1615 }
1616
1617 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1618                 struct device_attribute *attr,
1619                 const char *buf,
1620                 size_t count)
1621 {
1622         struct drm_device *ddev = dev_get_drvdata(dev);
1623         struct amdgpu_device *adev = ddev->dev_private;
1624         int ret;
1625         long int value;
1626
1627         if (adev->in_gpu_reset)
1628                 return -EPERM;
1629
1630         ret = kstrtol(buf, 0, &value);
1631
1632         if (ret)
1633                 return -EINVAL;
1634
1635         ret = pm_runtime_get_sync(ddev->dev);
1636         if (ret < 0) {
1637                 pm_runtime_put_autosuspend(ddev->dev);
1638                 return ret;
1639         }
1640
1641         if (is_support_sw_smu(adev)) {
1642                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1643         } else {
1644                 if (adev->powerplay.pp_funcs->set_mclk_od)
1645                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1646
1647                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1648                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1649                 } else {
1650                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1651                         amdgpu_pm_compute_clocks(adev);
1652                 }
1653         }
1654
1655         pm_runtime_mark_last_busy(ddev->dev);
1656         pm_runtime_put_autosuspend(ddev->dev);
1657
1658         return count;
1659 }
1660
1661 /**
1662  * DOC: pp_power_profile_mode
1663  *
1664  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1665  * related to switching between power levels in a power state.  The file
1666  * pp_power_profile_mode is used for this.
1667  *
1668  * Reading this file outputs a list of all of the predefined power profiles
1669  * and the relevant heuristics settings for that profile.
1670  *
1671  * To select a profile or create a custom profile, first select manual using
1672  * power_dpm_force_performance_level.  Writing the number of a predefined
1673  * profile to pp_power_profile_mode will enable those heuristics.  To
1674  * create a custom set of heuristics, write a string of numbers to the file
1675  * starting with the number of the custom profile along with a setting
1676  * for each heuristic parameter.  Due to differences across asic families
1677  * the heuristic parameters vary from family to family.
1678  *
1679  */
1680
1681 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1682                 struct device_attribute *attr,
1683                 char *buf)
1684 {
1685         struct drm_device *ddev = dev_get_drvdata(dev);
1686         struct amdgpu_device *adev = ddev->dev_private;
1687         ssize_t size;
1688         int ret;
1689
1690         if (adev->in_gpu_reset)
1691                 return -EPERM;
1692
1693         ret = pm_runtime_get_sync(ddev->dev);
1694         if (ret < 0) {
1695                 pm_runtime_put_autosuspend(ddev->dev);
1696                 return ret;
1697         }
1698
1699         if (is_support_sw_smu(adev))
1700                 size = smu_get_power_profile_mode(&adev->smu, buf);
1701         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1702                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1703         else
1704                 size = snprintf(buf, PAGE_SIZE, "\n");
1705
1706         pm_runtime_mark_last_busy(ddev->dev);
1707         pm_runtime_put_autosuspend(ddev->dev);
1708
1709         return size;
1710 }
1711
1712
1713 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1714                 struct device_attribute *attr,
1715                 const char *buf,
1716                 size_t count)
1717 {
1718         int ret;
1719         struct drm_device *ddev = dev_get_drvdata(dev);
1720         struct amdgpu_device *adev = ddev->dev_private;
1721         uint32_t parameter_size = 0;
1722         long parameter[64];
1723         char *sub_str, buf_cpy[128];
1724         char *tmp_str;
1725         uint32_t i = 0;
1726         char tmp[2];
1727         long int profile_mode = 0;
1728         const char delimiter[3] = {' ', '\n', '\0'};
1729
1730         if (adev->in_gpu_reset)
1731                 return -EPERM;
1732
1733         tmp[0] = *(buf);
1734         tmp[1] = '\0';
1735         ret = kstrtol(tmp, 0, &profile_mode);
1736         if (ret)
1737                 return -EINVAL;
1738
1739         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1740                 if (count < 2 || count > 127)
1741                         return -EINVAL;
1742                 while (isspace(*++buf))
1743                         i++;
1744                 memcpy(buf_cpy, buf, count-i);
1745                 tmp_str = buf_cpy;
1746                 while (tmp_str[0]) {
1747                         sub_str = strsep(&tmp_str, delimiter);
1748                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1749                         if (ret)
1750                                 return -EINVAL;
1751                         parameter_size++;
1752                         while (isspace(*tmp_str))
1753                                 tmp_str++;
1754                 }
1755         }
1756         parameter[parameter_size] = profile_mode;
1757
1758         ret = pm_runtime_get_sync(ddev->dev);
1759         if (ret < 0) {
1760                 pm_runtime_put_autosuspend(ddev->dev);
1761                 return ret;
1762         }
1763
1764         if (is_support_sw_smu(adev))
1765                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1766         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1767                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1768
1769         pm_runtime_mark_last_busy(ddev->dev);
1770         pm_runtime_put_autosuspend(ddev->dev);
1771
1772         if (!ret)
1773                 return count;
1774
1775         return -EINVAL;
1776 }
1777
1778 /**
1779  * DOC: gpu_busy_percent
1780  *
1781  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1782  * is as a percentage.  The file gpu_busy_percent is used for this.
1783  * The SMU firmware computes a percentage of load based on the
1784  * aggregate activity level in the IP cores.
1785  */
1786 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1787                                            struct device_attribute *attr,
1788                                            char *buf)
1789 {
1790         struct drm_device *ddev = dev_get_drvdata(dev);
1791         struct amdgpu_device *adev = ddev->dev_private;
1792         int r, value, size = sizeof(value);
1793
1794         if (adev->in_gpu_reset)
1795                 return -EPERM;
1796
1797         r = pm_runtime_get_sync(ddev->dev);
1798         if (r < 0) {
1799                 pm_runtime_put_autosuspend(ddev->dev);
1800                 return r;
1801         }
1802
1803         /* read the IP busy sensor */
1804         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1805                                    (void *)&value, &size);
1806
1807         pm_runtime_mark_last_busy(ddev->dev);
1808         pm_runtime_put_autosuspend(ddev->dev);
1809
1810         if (r)
1811                 return r;
1812
1813         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1814 }
1815
1816 /**
1817  * DOC: mem_busy_percent
1818  *
1819  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1820  * is as a percentage.  The file mem_busy_percent is used for this.
1821  * The SMU firmware computes a percentage of load based on the
1822  * aggregate activity level in the IP cores.
1823  */
1824 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1825                                            struct device_attribute *attr,
1826                                            char *buf)
1827 {
1828         struct drm_device *ddev = dev_get_drvdata(dev);
1829         struct amdgpu_device *adev = ddev->dev_private;
1830         int r, value, size = sizeof(value);
1831
1832         if (adev->in_gpu_reset)
1833                 return -EPERM;
1834
1835         r = pm_runtime_get_sync(ddev->dev);
1836         if (r < 0) {
1837                 pm_runtime_put_autosuspend(ddev->dev);
1838                 return r;
1839         }
1840
1841         /* read the IP busy sensor */
1842         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1843                                    (void *)&value, &size);
1844
1845         pm_runtime_mark_last_busy(ddev->dev);
1846         pm_runtime_put_autosuspend(ddev->dev);
1847
1848         if (r)
1849                 return r;
1850
1851         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1852 }
1853
1854 /**
1855  * DOC: pcie_bw
1856  *
1857  * The amdgpu driver provides a sysfs API for estimating how much data
1858  * has been received and sent by the GPU in the last second through PCIe.
1859  * The file pcie_bw is used for this.
1860  * The Perf counters count the number of received and sent messages and return
1861  * those values, as well as the maximum payload size of a PCIe packet (mps).
1862  * Note that it is not possible to easily and quickly obtain the size of each
1863  * packet transmitted, so we output the max payload size (mps) to allow for
1864  * quick estimation of the PCIe bandwidth usage
1865  */
1866 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1867                 struct device_attribute *attr,
1868                 char *buf)
1869 {
1870         struct drm_device *ddev = dev_get_drvdata(dev);
1871         struct amdgpu_device *adev = ddev->dev_private;
1872         uint64_t count0 = 0, count1 = 0;
1873         int ret;
1874
1875         if (adev->in_gpu_reset)
1876                 return -EPERM;
1877
1878         if (adev->flags & AMD_IS_APU)
1879                 return -ENODATA;
1880
1881         if (!adev->asic_funcs->get_pcie_usage)
1882                 return -ENODATA;
1883
1884         ret = pm_runtime_get_sync(ddev->dev);
1885         if (ret < 0) {
1886                 pm_runtime_put_autosuspend(ddev->dev);
1887                 return ret;
1888         }
1889
1890         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1891
1892         pm_runtime_mark_last_busy(ddev->dev);
1893         pm_runtime_put_autosuspend(ddev->dev);
1894
1895         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1896                         count0, count1, pcie_get_mps(adev->pdev));
1897 }
1898
1899 /**
1900  * DOC: unique_id
1901  *
1902  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1903  * The file unique_id is used for this.
1904  * This will provide a Unique ID that will persist from machine to machine
1905  *
1906  * NOTE: This will only work for GFX9 and newer. This file will be absent
1907  * on unsupported ASICs (GFX8 and older)
1908  */
1909 static ssize_t amdgpu_get_unique_id(struct device *dev,
1910                 struct device_attribute *attr,
1911                 char *buf)
1912 {
1913         struct drm_device *ddev = dev_get_drvdata(dev);
1914         struct amdgpu_device *adev = ddev->dev_private;
1915
1916         if (adev->in_gpu_reset)
1917                 return -EPERM;
1918
1919         if (adev->unique_id)
1920                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1921
1922         return 0;
1923 }
1924
1925 /**
1926  * DOC: thermal_throttling_logging
1927  *
1928  * Thermal throttling pulls down the clock frequency and thus the performance.
1929  * It's an useful mechanism to protect the chip from overheating. Since it
1930  * impacts performance, the user controls whether it is enabled and if so,
1931  * the log frequency.
1932  *
1933  * Reading back the file shows you the status(enabled or disabled) and
1934  * the interval(in seconds) between each thermal logging.
1935  *
1936  * Writing an integer to the file, sets a new logging interval, in seconds.
1937  * The value should be between 1 and 3600. If the value is less than 1,
1938  * thermal logging is disabled. Values greater than 3600 are ignored.
1939  */
1940 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1941                                                      struct device_attribute *attr,
1942                                                      char *buf)
1943 {
1944         struct drm_device *ddev = dev_get_drvdata(dev);
1945         struct amdgpu_device *adev = ddev->dev_private;
1946
1947         return snprintf(buf, PAGE_SIZE, "%s: thermal throttling logging %s, with interval %d seconds\n",
1948                         adev->ddev->unique,
1949                         atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1950                         adev->throttling_logging_rs.interval / HZ + 1);
1951 }
1952
1953 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1954                                                      struct device_attribute *attr,
1955                                                      const char *buf,
1956                                                      size_t count)
1957 {
1958         struct drm_device *ddev = dev_get_drvdata(dev);
1959         struct amdgpu_device *adev = ddev->dev_private;
1960         long throttling_logging_interval;
1961         unsigned long flags;
1962         int ret = 0;
1963
1964         ret = kstrtol(buf, 0, &throttling_logging_interval);
1965         if (ret)
1966                 return ret;
1967
1968         if (throttling_logging_interval > 3600)
1969                 return -EINVAL;
1970
1971         if (throttling_logging_interval > 0) {
1972                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1973                 /*
1974                  * Reset the ratelimit timer internals.
1975                  * This can effectively restart the timer.
1976                  */
1977                 adev->throttling_logging_rs.interval =
1978                         (throttling_logging_interval - 1) * HZ;
1979                 adev->throttling_logging_rs.begin = 0;
1980                 adev->throttling_logging_rs.printed = 0;
1981                 adev->throttling_logging_rs.missed = 0;
1982                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1983
1984                 atomic_set(&adev->throttling_logging_enabled, 1);
1985         } else {
1986                 atomic_set(&adev->throttling_logging_enabled, 0);
1987         }
1988
1989         return count;
1990 }
1991
1992 /**
1993  * DOC: gpu_metrics
1994  *
1995  * The amdgpu driver provides a sysfs API for retrieving current gpu
1996  * metrics data. The file gpu_metrics is used for this. Reading the
1997  * file will dump all the current gpu metrics data.
1998  *
1999  * These data include temperature, frequency, engines utilization,
2000  * power consume, throttler status, fan speed and cpu core statistics(
2001  * available for APU only). That's it will give a snapshot of all sensors
2002  * at the same time.
2003  */
2004 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
2005                                       struct device_attribute *attr,
2006                                       char *buf)
2007 {
2008         struct drm_device *ddev = dev_get_drvdata(dev);
2009         struct amdgpu_device *adev = ddev->dev_private;
2010         void *gpu_metrics;
2011         ssize_t size = 0;
2012         int ret;
2013
2014         if (adev->in_gpu_reset)
2015                 return -EPERM;
2016
2017         ret = pm_runtime_get_sync(ddev->dev);
2018         if (ret < 0) {
2019                 pm_runtime_put_autosuspend(ddev->dev);
2020                 return ret;
2021         }
2022
2023         if (is_support_sw_smu(adev))
2024                 size = smu_sys_get_gpu_metrics(&adev->smu, &gpu_metrics);
2025         else if (adev->powerplay.pp_funcs->get_gpu_metrics)
2026                 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
2027
2028         if (size <= 0)
2029                 goto out;
2030
2031         if (size >= PAGE_SIZE)
2032                 size = PAGE_SIZE - 1;
2033
2034         memcpy(buf, gpu_metrics, size);
2035
2036 out:
2037         pm_runtime_mark_last_busy(ddev->dev);
2038         pm_runtime_put_autosuspend(ddev->dev);
2039
2040         return size;
2041 }
2042
2043 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2044         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2045         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC),
2046         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
2047         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
2048         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
2049         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
2050         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2051         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2052         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2053         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2054         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
2055         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
2056         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2057         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2058         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
2059         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2060         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
2061         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
2062         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2063         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
2064         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
2065         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC),
2066         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC),
2067 };
2068
2069 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2070                                uint32_t mask, enum amdgpu_device_attr_states *states)
2071 {
2072         struct device_attribute *dev_attr = &attr->dev_attr;
2073         const char *attr_name = dev_attr->attr.name;
2074         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2075         enum amd_asic_type asic_type = adev->asic_type;
2076
2077         if (!(attr->flags & mask)) {
2078                 *states = ATTR_STATE_UNSUPPORTED;
2079                 return 0;
2080         }
2081
2082 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2083
2084         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2085                 if (asic_type < CHIP_VEGA10)
2086                         *states = ATTR_STATE_UNSUPPORTED;
2087         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2088                 if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
2089                         *states = ATTR_STATE_UNSUPPORTED;
2090         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2091                 if (asic_type < CHIP_VEGA20)
2092                         *states = ATTR_STATE_UNSUPPORTED;
2093         } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
2094                 if (asic_type == CHIP_ARCTURUS)
2095                         *states = ATTR_STATE_UNSUPPORTED;
2096         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2097                 *states = ATTR_STATE_UNSUPPORTED;
2098                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2099                     (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2100                         *states = ATTR_STATE_SUPPORTED;
2101         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2102                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
2103                         *states = ATTR_STATE_UNSUPPORTED;
2104         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2105                 /* PCIe Perf counters won't work on APU nodes */
2106                 if (adev->flags & AMD_IS_APU)
2107                         *states = ATTR_STATE_UNSUPPORTED;
2108         } else if (DEVICE_ATTR_IS(unique_id)) {
2109                 if (asic_type != CHIP_VEGA10 &&
2110                     asic_type != CHIP_VEGA20 &&
2111                     asic_type != CHIP_ARCTURUS)
2112                         *states = ATTR_STATE_UNSUPPORTED;
2113         } else if (DEVICE_ATTR_IS(pp_features)) {
2114                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
2115                         *states = ATTR_STATE_UNSUPPORTED;
2116         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2117                 if (asic_type < CHIP_VEGA12)
2118                         *states = ATTR_STATE_UNSUPPORTED;
2119         }
2120
2121         if (asic_type == CHIP_ARCTURUS) {
2122                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
2123                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2124                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2125                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2126                         dev_attr->attr.mode &= ~S_IWUGO;
2127                         dev_attr->store = NULL;
2128                 }
2129         }
2130
2131 #undef DEVICE_ATTR_IS
2132
2133         return 0;
2134 }
2135
2136
2137 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2138                                      struct amdgpu_device_attr *attr,
2139                                      uint32_t mask, struct list_head *attr_list)
2140 {
2141         int ret = 0;
2142         struct device_attribute *dev_attr = &attr->dev_attr;
2143         const char *name = dev_attr->attr.name;
2144         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2145         struct amdgpu_device_attr_entry *attr_entry;
2146
2147         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2148                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2149
2150         BUG_ON(!attr);
2151
2152         attr_update = attr->attr_update ? attr_update : default_attr_update;
2153
2154         ret = attr_update(adev, attr, mask, &attr_states);
2155         if (ret) {
2156                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2157                         name, ret);
2158                 return ret;
2159         }
2160
2161         if (attr_states == ATTR_STATE_UNSUPPORTED)
2162                 return 0;
2163
2164         ret = device_create_file(adev->dev, dev_attr);
2165         if (ret) {
2166                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2167                         name, ret);
2168         }
2169
2170         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2171         if (!attr_entry)
2172                 return -ENOMEM;
2173
2174         attr_entry->attr = attr;
2175         INIT_LIST_HEAD(&attr_entry->entry);
2176
2177         list_add_tail(&attr_entry->entry, attr_list);
2178
2179         return ret;
2180 }
2181
2182 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2183 {
2184         struct device_attribute *dev_attr = &attr->dev_attr;
2185
2186         device_remove_file(adev->dev, dev_attr);
2187 }
2188
2189 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2190                                              struct list_head *attr_list);
2191
2192 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2193                                             struct amdgpu_device_attr *attrs,
2194                                             uint32_t counts,
2195                                             uint32_t mask,
2196                                             struct list_head *attr_list)
2197 {
2198         int ret = 0;
2199         uint32_t i = 0;
2200
2201         for (i = 0; i < counts; i++) {
2202                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2203                 if (ret)
2204                         goto failed;
2205         }
2206
2207         return 0;
2208
2209 failed:
2210         amdgpu_device_attr_remove_groups(adev, attr_list);
2211
2212         return ret;
2213 }
2214
2215 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2216                                              struct list_head *attr_list)
2217 {
2218         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2219
2220         if (list_empty(attr_list))
2221                 return ;
2222
2223         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2224                 amdgpu_device_attr_remove(adev, entry->attr);
2225                 list_del(&entry->entry);
2226                 kfree(entry);
2227         }
2228 }
2229
2230 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2231                                       struct device_attribute *attr,
2232                                       char *buf)
2233 {
2234         struct amdgpu_device *adev = dev_get_drvdata(dev);
2235         int channel = to_sensor_dev_attr(attr)->index;
2236         int r, temp = 0, size = sizeof(temp);
2237
2238         if (adev->in_gpu_reset)
2239                 return -EPERM;
2240
2241         if (channel >= PP_TEMP_MAX)
2242                 return -EINVAL;
2243
2244         r = pm_runtime_get_sync(adev->ddev->dev);
2245         if (r < 0) {
2246                 pm_runtime_put_autosuspend(adev->ddev->dev);
2247                 return r;
2248         }
2249
2250         switch (channel) {
2251         case PP_TEMP_JUNCTION:
2252                 /* get current junction temperature */
2253                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2254                                            (void *)&temp, &size);
2255                 break;
2256         case PP_TEMP_EDGE:
2257                 /* get current edge temperature */
2258                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2259                                            (void *)&temp, &size);
2260                 break;
2261         case PP_TEMP_MEM:
2262                 /* get current memory temperature */
2263                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2264                                            (void *)&temp, &size);
2265                 break;
2266         default:
2267                 r = -EINVAL;
2268                 break;
2269         }
2270
2271         pm_runtime_mark_last_busy(adev->ddev->dev);
2272         pm_runtime_put_autosuspend(adev->ddev->dev);
2273
2274         if (r)
2275                 return r;
2276
2277         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2278 }
2279
2280 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2281                                              struct device_attribute *attr,
2282                                              char *buf)
2283 {
2284         struct amdgpu_device *adev = dev_get_drvdata(dev);
2285         int hyst = to_sensor_dev_attr(attr)->index;
2286         int temp;
2287
2288         if (hyst)
2289                 temp = adev->pm.dpm.thermal.min_temp;
2290         else
2291                 temp = adev->pm.dpm.thermal.max_temp;
2292
2293         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2294 }
2295
2296 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2297                                              struct device_attribute *attr,
2298                                              char *buf)
2299 {
2300         struct amdgpu_device *adev = dev_get_drvdata(dev);
2301         int hyst = to_sensor_dev_attr(attr)->index;
2302         int temp;
2303
2304         if (hyst)
2305                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2306         else
2307                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2308
2309         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2310 }
2311
2312 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2313                                              struct device_attribute *attr,
2314                                              char *buf)
2315 {
2316         struct amdgpu_device *adev = dev_get_drvdata(dev);
2317         int hyst = to_sensor_dev_attr(attr)->index;
2318         int temp;
2319
2320         if (hyst)
2321                 temp = adev->pm.dpm.thermal.min_mem_temp;
2322         else
2323                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2324
2325         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2326 }
2327
2328 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2329                                              struct device_attribute *attr,
2330                                              char *buf)
2331 {
2332         int channel = to_sensor_dev_attr(attr)->index;
2333
2334         if (channel >= PP_TEMP_MAX)
2335                 return -EINVAL;
2336
2337         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
2338 }
2339
2340 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2341                                              struct device_attribute *attr,
2342                                              char *buf)
2343 {
2344         struct amdgpu_device *adev = dev_get_drvdata(dev);
2345         int channel = to_sensor_dev_attr(attr)->index;
2346         int temp = 0;
2347
2348         if (channel >= PP_TEMP_MAX)
2349                 return -EINVAL;
2350
2351         switch (channel) {
2352         case PP_TEMP_JUNCTION:
2353                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2354                 break;
2355         case PP_TEMP_EDGE:
2356                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2357                 break;
2358         case PP_TEMP_MEM:
2359                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2360                 break;
2361         }
2362
2363         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2364 }
2365
2366 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2367                                             struct device_attribute *attr,
2368                                             char *buf)
2369 {
2370         struct amdgpu_device *adev = dev_get_drvdata(dev);
2371         u32 pwm_mode = 0;
2372         int ret;
2373
2374         if (adev->in_gpu_reset)
2375                 return -EPERM;
2376
2377         ret = pm_runtime_get_sync(adev->ddev->dev);
2378         if (ret < 0) {
2379                 pm_runtime_put_autosuspend(adev->ddev->dev);
2380                 return ret;
2381         }
2382
2383         if (is_support_sw_smu(adev)) {
2384                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2385         } else {
2386                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2387                         pm_runtime_mark_last_busy(adev->ddev->dev);
2388                         pm_runtime_put_autosuspend(adev->ddev->dev);
2389                         return -EINVAL;
2390                 }
2391
2392                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2393         }
2394
2395         pm_runtime_mark_last_busy(adev->ddev->dev);
2396         pm_runtime_put_autosuspend(adev->ddev->dev);
2397
2398         return sprintf(buf, "%i\n", pwm_mode);
2399 }
2400
2401 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2402                                             struct device_attribute *attr,
2403                                             const char *buf,
2404                                             size_t count)
2405 {
2406         struct amdgpu_device *adev = dev_get_drvdata(dev);
2407         int err, ret;
2408         int value;
2409
2410         if (adev->in_gpu_reset)
2411                 return -EPERM;
2412
2413         err = kstrtoint(buf, 10, &value);
2414         if (err)
2415                 return err;
2416
2417         ret = pm_runtime_get_sync(adev->ddev->dev);
2418         if (ret < 0) {
2419                 pm_runtime_put_autosuspend(adev->ddev->dev);
2420                 return ret;
2421         }
2422
2423         if (is_support_sw_smu(adev)) {
2424                 smu_set_fan_control_mode(&adev->smu, value);
2425         } else {
2426                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2427                         pm_runtime_mark_last_busy(adev->ddev->dev);
2428                         pm_runtime_put_autosuspend(adev->ddev->dev);
2429                         return -EINVAL;
2430                 }
2431
2432                 amdgpu_dpm_set_fan_control_mode(adev, value);
2433         }
2434
2435         pm_runtime_mark_last_busy(adev->ddev->dev);
2436         pm_runtime_put_autosuspend(adev->ddev->dev);
2437
2438         return count;
2439 }
2440
2441 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2442                                          struct device_attribute *attr,
2443                                          char *buf)
2444 {
2445         return sprintf(buf, "%i\n", 0);
2446 }
2447
2448 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2449                                          struct device_attribute *attr,
2450                                          char *buf)
2451 {
2452         return sprintf(buf, "%i\n", 255);
2453 }
2454
2455 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2456                                      struct device_attribute *attr,
2457                                      const char *buf, size_t count)
2458 {
2459         struct amdgpu_device *adev = dev_get_drvdata(dev);
2460         int err;
2461         u32 value;
2462         u32 pwm_mode;
2463
2464         if (adev->in_gpu_reset)
2465                 return -EPERM;
2466
2467         err = pm_runtime_get_sync(adev->ddev->dev);
2468         if (err < 0) {
2469                 pm_runtime_put_autosuspend(adev->ddev->dev);
2470                 return err;
2471         }
2472
2473         if (is_support_sw_smu(adev))
2474                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2475         else
2476                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2477
2478         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2479                 pr_info("manual fan speed control should be enabled first\n");
2480                 pm_runtime_mark_last_busy(adev->ddev->dev);
2481                 pm_runtime_put_autosuspend(adev->ddev->dev);
2482                 return -EINVAL;
2483         }
2484
2485         err = kstrtou32(buf, 10, &value);
2486         if (err) {
2487                 pm_runtime_mark_last_busy(adev->ddev->dev);
2488                 pm_runtime_put_autosuspend(adev->ddev->dev);
2489                 return err;
2490         }
2491
2492         value = (value * 100) / 255;
2493
2494         if (is_support_sw_smu(adev))
2495                 err = smu_set_fan_speed_percent(&adev->smu, value);
2496         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2497                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2498         else
2499                 err = -EINVAL;
2500
2501         pm_runtime_mark_last_busy(adev->ddev->dev);
2502         pm_runtime_put_autosuspend(adev->ddev->dev);
2503
2504         if (err)
2505                 return err;
2506
2507         return count;
2508 }
2509
2510 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2511                                      struct device_attribute *attr,
2512                                      char *buf)
2513 {
2514         struct amdgpu_device *adev = dev_get_drvdata(dev);
2515         int err;
2516         u32 speed = 0;
2517
2518         if (adev->in_gpu_reset)
2519                 return -EPERM;
2520
2521         err = pm_runtime_get_sync(adev->ddev->dev);
2522         if (err < 0) {
2523                 pm_runtime_put_autosuspend(adev->ddev->dev);
2524                 return err;
2525         }
2526
2527         if (is_support_sw_smu(adev))
2528                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2529         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2530                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2531         else
2532                 err = -EINVAL;
2533
2534         pm_runtime_mark_last_busy(adev->ddev->dev);
2535         pm_runtime_put_autosuspend(adev->ddev->dev);
2536
2537         if (err)
2538                 return err;
2539
2540         speed = (speed * 255) / 100;
2541
2542         return sprintf(buf, "%i\n", speed);
2543 }
2544
2545 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2546                                            struct device_attribute *attr,
2547                                            char *buf)
2548 {
2549         struct amdgpu_device *adev = dev_get_drvdata(dev);
2550         int err;
2551         u32 speed = 0;
2552
2553         if (adev->in_gpu_reset)
2554                 return -EPERM;
2555
2556         err = pm_runtime_get_sync(adev->ddev->dev);
2557         if (err < 0) {
2558                 pm_runtime_put_autosuspend(adev->ddev->dev);
2559                 return err;
2560         }
2561
2562         if (is_support_sw_smu(adev))
2563                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2564         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2565                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2566         else
2567                 err = -EINVAL;
2568
2569         pm_runtime_mark_last_busy(adev->ddev->dev);
2570         pm_runtime_put_autosuspend(adev->ddev->dev);
2571
2572         if (err)
2573                 return err;
2574
2575         return sprintf(buf, "%i\n", speed);
2576 }
2577
2578 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2579                                          struct device_attribute *attr,
2580                                          char *buf)
2581 {
2582         struct amdgpu_device *adev = dev_get_drvdata(dev);
2583         u32 min_rpm = 0;
2584         u32 size = sizeof(min_rpm);
2585         int r;
2586
2587         if (adev->in_gpu_reset)
2588                 return -EPERM;
2589
2590         r = pm_runtime_get_sync(adev->ddev->dev);
2591         if (r < 0) {
2592                 pm_runtime_put_autosuspend(adev->ddev->dev);
2593                 return r;
2594         }
2595
2596         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2597                                    (void *)&min_rpm, &size);
2598
2599         pm_runtime_mark_last_busy(adev->ddev->dev);
2600         pm_runtime_put_autosuspend(adev->ddev->dev);
2601
2602         if (r)
2603                 return r;
2604
2605         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2606 }
2607
2608 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2609                                          struct device_attribute *attr,
2610                                          char *buf)
2611 {
2612         struct amdgpu_device *adev = dev_get_drvdata(dev);
2613         u32 max_rpm = 0;
2614         u32 size = sizeof(max_rpm);
2615         int r;
2616
2617         if (adev->in_gpu_reset)
2618                 return -EPERM;
2619
2620         r = pm_runtime_get_sync(adev->ddev->dev);
2621         if (r < 0) {
2622                 pm_runtime_put_autosuspend(adev->ddev->dev);
2623                 return r;
2624         }
2625
2626         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2627                                    (void *)&max_rpm, &size);
2628
2629         pm_runtime_mark_last_busy(adev->ddev->dev);
2630         pm_runtime_put_autosuspend(adev->ddev->dev);
2631
2632         if (r)
2633                 return r;
2634
2635         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2636 }
2637
2638 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2639                                            struct device_attribute *attr,
2640                                            char *buf)
2641 {
2642         struct amdgpu_device *adev = dev_get_drvdata(dev);
2643         int err;
2644         u32 rpm = 0;
2645
2646         if (adev->in_gpu_reset)
2647                 return -EPERM;
2648
2649         err = pm_runtime_get_sync(adev->ddev->dev);
2650         if (err < 0) {
2651                 pm_runtime_put_autosuspend(adev->ddev->dev);
2652                 return err;
2653         }
2654
2655         if (is_support_sw_smu(adev))
2656                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2657         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2658                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2659         else
2660                 err = -EINVAL;
2661
2662         pm_runtime_mark_last_busy(adev->ddev->dev);
2663         pm_runtime_put_autosuspend(adev->ddev->dev);
2664
2665         if (err)
2666                 return err;
2667
2668         return sprintf(buf, "%i\n", rpm);
2669 }
2670
2671 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2672                                      struct device_attribute *attr,
2673                                      const char *buf, size_t count)
2674 {
2675         struct amdgpu_device *adev = dev_get_drvdata(dev);
2676         int err;
2677         u32 value;
2678         u32 pwm_mode;
2679
2680         if (adev->in_gpu_reset)
2681                 return -EPERM;
2682
2683         err = pm_runtime_get_sync(adev->ddev->dev);
2684         if (err < 0) {
2685                 pm_runtime_put_autosuspend(adev->ddev->dev);
2686                 return err;
2687         }
2688
2689         if (is_support_sw_smu(adev))
2690                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2691         else
2692                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2693
2694         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2695                 pm_runtime_mark_last_busy(adev->ddev->dev);
2696                 pm_runtime_put_autosuspend(adev->ddev->dev);
2697                 return -ENODATA;
2698         }
2699
2700         err = kstrtou32(buf, 10, &value);
2701         if (err) {
2702                 pm_runtime_mark_last_busy(adev->ddev->dev);
2703                 pm_runtime_put_autosuspend(adev->ddev->dev);
2704                 return err;
2705         }
2706
2707         if (is_support_sw_smu(adev))
2708                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2709         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2710                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2711         else
2712                 err = -EINVAL;
2713
2714         pm_runtime_mark_last_busy(adev->ddev->dev);
2715         pm_runtime_put_autosuspend(adev->ddev->dev);
2716
2717         if (err)
2718                 return err;
2719
2720         return count;
2721 }
2722
2723 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2724                                             struct device_attribute *attr,
2725                                             char *buf)
2726 {
2727         struct amdgpu_device *adev = dev_get_drvdata(dev);
2728         u32 pwm_mode = 0;
2729         int ret;
2730
2731         if (adev->in_gpu_reset)
2732                 return -EPERM;
2733
2734         ret = pm_runtime_get_sync(adev->ddev->dev);
2735         if (ret < 0) {
2736                 pm_runtime_put_autosuspend(adev->ddev->dev);
2737                 return ret;
2738         }
2739
2740         if (is_support_sw_smu(adev)) {
2741                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2742         } else {
2743                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2744                         pm_runtime_mark_last_busy(adev->ddev->dev);
2745                         pm_runtime_put_autosuspend(adev->ddev->dev);
2746                         return -EINVAL;
2747                 }
2748
2749                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2750         }
2751
2752         pm_runtime_mark_last_busy(adev->ddev->dev);
2753         pm_runtime_put_autosuspend(adev->ddev->dev);
2754
2755         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2756 }
2757
2758 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2759                                             struct device_attribute *attr,
2760                                             const char *buf,
2761                                             size_t count)
2762 {
2763         struct amdgpu_device *adev = dev_get_drvdata(dev);
2764         int err;
2765         int value;
2766         u32 pwm_mode;
2767
2768         if (adev->in_gpu_reset)
2769                 return -EPERM;
2770
2771         err = kstrtoint(buf, 10, &value);
2772         if (err)
2773                 return err;
2774
2775         if (value == 0)
2776                 pwm_mode = AMD_FAN_CTRL_AUTO;
2777         else if (value == 1)
2778                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2779         else
2780                 return -EINVAL;
2781
2782         err = pm_runtime_get_sync(adev->ddev->dev);
2783         if (err < 0) {
2784                 pm_runtime_put_autosuspend(adev->ddev->dev);
2785                 return err;
2786         }
2787
2788         if (is_support_sw_smu(adev)) {
2789                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2790         } else {
2791                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2792                         pm_runtime_mark_last_busy(adev->ddev->dev);
2793                         pm_runtime_put_autosuspend(adev->ddev->dev);
2794                         return -EINVAL;
2795                 }
2796                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2797         }
2798
2799         pm_runtime_mark_last_busy(adev->ddev->dev);
2800         pm_runtime_put_autosuspend(adev->ddev->dev);
2801
2802         return count;
2803 }
2804
2805 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2806                                         struct device_attribute *attr,
2807                                         char *buf)
2808 {
2809         struct amdgpu_device *adev = dev_get_drvdata(dev);
2810         u32 vddgfx;
2811         int r, size = sizeof(vddgfx);
2812
2813         if (adev->in_gpu_reset)
2814                 return -EPERM;
2815
2816         r = pm_runtime_get_sync(adev->ddev->dev);
2817         if (r < 0) {
2818                 pm_runtime_put_autosuspend(adev->ddev->dev);
2819                 return r;
2820         }
2821
2822         /* get the voltage */
2823         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2824                                    (void *)&vddgfx, &size);
2825
2826         pm_runtime_mark_last_busy(adev->ddev->dev);
2827         pm_runtime_put_autosuspend(adev->ddev->dev);
2828
2829         if (r)
2830                 return r;
2831
2832         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2833 }
2834
2835 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2836                                               struct device_attribute *attr,
2837                                               char *buf)
2838 {
2839         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2840 }
2841
2842 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2843                                        struct device_attribute *attr,
2844                                        char *buf)
2845 {
2846         struct amdgpu_device *adev = dev_get_drvdata(dev);
2847         u32 vddnb;
2848         int r, size = sizeof(vddnb);
2849
2850         if (adev->in_gpu_reset)
2851                 return -EPERM;
2852
2853         /* only APUs have vddnb */
2854         if  (!(adev->flags & AMD_IS_APU))
2855                 return -EINVAL;
2856
2857         r = pm_runtime_get_sync(adev->ddev->dev);
2858         if (r < 0) {
2859                 pm_runtime_put_autosuspend(adev->ddev->dev);
2860                 return r;
2861         }
2862
2863         /* get the voltage */
2864         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2865                                    (void *)&vddnb, &size);
2866
2867         pm_runtime_mark_last_busy(adev->ddev->dev);
2868         pm_runtime_put_autosuspend(adev->ddev->dev);
2869
2870         if (r)
2871                 return r;
2872
2873         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
2874 }
2875
2876 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2877                                               struct device_attribute *attr,
2878                                               char *buf)
2879 {
2880         return snprintf(buf, PAGE_SIZE, "vddnb\n");
2881 }
2882
2883 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2884                                            struct device_attribute *attr,
2885                                            char *buf)
2886 {
2887         struct amdgpu_device *adev = dev_get_drvdata(dev);
2888         u32 query = 0;
2889         int r, size = sizeof(u32);
2890         unsigned uw;
2891
2892         if (adev->in_gpu_reset)
2893                 return -EPERM;
2894
2895         r = pm_runtime_get_sync(adev->ddev->dev);
2896         if (r < 0) {
2897                 pm_runtime_put_autosuspend(adev->ddev->dev);
2898                 return r;
2899         }
2900
2901         /* get the voltage */
2902         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2903                                    (void *)&query, &size);
2904
2905         pm_runtime_mark_last_busy(adev->ddev->dev);
2906         pm_runtime_put_autosuspend(adev->ddev->dev);
2907
2908         if (r)
2909                 return r;
2910
2911         /* convert to microwatts */
2912         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2913
2914         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2915 }
2916
2917 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2918                                          struct device_attribute *attr,
2919                                          char *buf)
2920 {
2921         return sprintf(buf, "%i\n", 0);
2922 }
2923
2924 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2925                                          struct device_attribute *attr,
2926                                          char *buf)
2927 {
2928         struct amdgpu_device *adev = dev_get_drvdata(dev);
2929         uint32_t limit = 0;
2930         ssize_t size;
2931         int r;
2932
2933         if (adev->in_gpu_reset)
2934                 return -EPERM;
2935
2936         r = pm_runtime_get_sync(adev->ddev->dev);
2937         if (r < 0) {
2938                 pm_runtime_put_autosuspend(adev->ddev->dev);
2939                 return r;
2940         }
2941
2942         if (is_support_sw_smu(adev)) {
2943                 smu_get_power_limit(&adev->smu, &limit, true);
2944                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2945         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2946                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2947                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2948         } else {
2949                 size = snprintf(buf, PAGE_SIZE, "\n");
2950         }
2951
2952         pm_runtime_mark_last_busy(adev->ddev->dev);
2953         pm_runtime_put_autosuspend(adev->ddev->dev);
2954
2955         return size;
2956 }
2957
2958 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2959                                          struct device_attribute *attr,
2960                                          char *buf)
2961 {
2962         struct amdgpu_device *adev = dev_get_drvdata(dev);
2963         uint32_t limit = 0;
2964         ssize_t size;
2965         int r;
2966
2967         if (adev->in_gpu_reset)
2968                 return -EPERM;
2969
2970         r = pm_runtime_get_sync(adev->ddev->dev);
2971         if (r < 0) {
2972                 pm_runtime_put_autosuspend(adev->ddev->dev);
2973                 return r;
2974         }
2975
2976         if (is_support_sw_smu(adev)) {
2977                 smu_get_power_limit(&adev->smu, &limit, false);
2978                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2979         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2980                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2981                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2982         } else {
2983                 size = snprintf(buf, PAGE_SIZE, "\n");
2984         }
2985
2986         pm_runtime_mark_last_busy(adev->ddev->dev);
2987         pm_runtime_put_autosuspend(adev->ddev->dev);
2988
2989         return size;
2990 }
2991
2992
2993 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2994                 struct device_attribute *attr,
2995                 const char *buf,
2996                 size_t count)
2997 {
2998         struct amdgpu_device *adev = dev_get_drvdata(dev);
2999         int err;
3000         u32 value;
3001
3002         if (adev->in_gpu_reset)
3003                 return -EPERM;
3004
3005         if (amdgpu_sriov_vf(adev))
3006                 return -EINVAL;
3007
3008         err = kstrtou32(buf, 10, &value);
3009         if (err)
3010                 return err;
3011
3012         value = value / 1000000; /* convert to Watt */
3013
3014
3015         err = pm_runtime_get_sync(adev->ddev->dev);
3016         if (err < 0) {
3017                 pm_runtime_put_autosuspend(adev->ddev->dev);
3018                 return err;
3019         }
3020
3021         if (is_support_sw_smu(adev))
3022                 err = smu_set_power_limit(&adev->smu, value);
3023         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
3024                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
3025         else
3026                 err = -EINVAL;
3027
3028         pm_runtime_mark_last_busy(adev->ddev->dev);
3029         pm_runtime_put_autosuspend(adev->ddev->dev);
3030
3031         if (err)
3032                 return err;
3033
3034         return count;
3035 }
3036
3037 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3038                                       struct device_attribute *attr,
3039                                       char *buf)
3040 {
3041         struct amdgpu_device *adev = dev_get_drvdata(dev);
3042         uint32_t sclk;
3043         int r, size = sizeof(sclk);
3044
3045         if (adev->in_gpu_reset)
3046                 return -EPERM;
3047
3048         r = pm_runtime_get_sync(adev->ddev->dev);
3049         if (r < 0) {
3050                 pm_runtime_put_autosuspend(adev->ddev->dev);
3051                 return r;
3052         }
3053
3054         /* get the sclk */
3055         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3056                                    (void *)&sclk, &size);
3057
3058         pm_runtime_mark_last_busy(adev->ddev->dev);
3059         pm_runtime_put_autosuspend(adev->ddev->dev);
3060
3061         if (r)
3062                 return r;
3063
3064         return snprintf(buf, PAGE_SIZE, "%u\n", sclk * 10 * 1000);
3065 }
3066
3067 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3068                                             struct device_attribute *attr,
3069                                             char *buf)
3070 {
3071         return snprintf(buf, PAGE_SIZE, "sclk\n");
3072 }
3073
3074 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3075                                       struct device_attribute *attr,
3076                                       char *buf)
3077 {
3078         struct amdgpu_device *adev = dev_get_drvdata(dev);
3079         uint32_t mclk;
3080         int r, size = sizeof(mclk);
3081
3082         if (adev->in_gpu_reset)
3083                 return -EPERM;
3084
3085         r = pm_runtime_get_sync(adev->ddev->dev);
3086         if (r < 0) {
3087                 pm_runtime_put_autosuspend(adev->ddev->dev);
3088                 return r;
3089         }
3090
3091         /* get the sclk */
3092         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3093                                    (void *)&mclk, &size);
3094
3095         pm_runtime_mark_last_busy(adev->ddev->dev);
3096         pm_runtime_put_autosuspend(adev->ddev->dev);
3097
3098         if (r)
3099                 return r;
3100
3101         return snprintf(buf, PAGE_SIZE, "%u\n", mclk * 10 * 1000);
3102 }
3103
3104 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3105                                             struct device_attribute *attr,
3106                                             char *buf)
3107 {
3108         return snprintf(buf, PAGE_SIZE, "mclk\n");
3109 }
3110
3111 /**
3112  * DOC: hwmon
3113  *
3114  * The amdgpu driver exposes the following sensor interfaces:
3115  *
3116  * - GPU temperature (via the on-die sensor)
3117  *
3118  * - GPU voltage
3119  *
3120  * - Northbridge voltage (APUs only)
3121  *
3122  * - GPU power
3123  *
3124  * - GPU fan
3125  *
3126  * - GPU gfx/compute engine clock
3127  *
3128  * - GPU memory clock (dGPU only)
3129  *
3130  * hwmon interfaces for GPU temperature:
3131  *
3132  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3133  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3134  *
3135  * - temp[1-3]_label: temperature channel label
3136  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3137  *
3138  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3139  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3140  *
3141  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3142  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3143  *
3144  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3145  *   - these are supported on SOC15 dGPUs only
3146  *
3147  * hwmon interfaces for GPU voltage:
3148  *
3149  * - in0_input: the voltage on the GPU in millivolts
3150  *
3151  * - in1_input: the voltage on the Northbridge in millivolts
3152  *
3153  * hwmon interfaces for GPU power:
3154  *
3155  * - power1_average: average power used by the GPU in microWatts
3156  *
3157  * - power1_cap_min: minimum cap supported in microWatts
3158  *
3159  * - power1_cap_max: maximum cap supported in microWatts
3160  *
3161  * - power1_cap: selected power cap in microWatts
3162  *
3163  * hwmon interfaces for GPU fan:
3164  *
3165  * - pwm1: pulse width modulation fan level (0-255)
3166  *
3167  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3168  *
3169  * - pwm1_min: pulse width modulation fan control minimum level (0)
3170  *
3171  * - pwm1_max: pulse width modulation fan control maximum level (255)
3172  *
3173  * - fan1_min: an minimum value Unit: revolution/min (RPM)
3174  *
3175  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
3176  *
3177  * - fan1_input: fan speed in RPM
3178  *
3179  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3180  *
3181  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3182  *
3183  * hwmon interfaces for GPU clocks:
3184  *
3185  * - freq1_input: the gfx/compute clock in hertz
3186  *
3187  * - freq2_input: the memory clock in hertz
3188  *
3189  * You can use hwmon tools like sensors to view this information on your system.
3190  *
3191  */
3192
3193 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3194 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3195 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3196 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3197 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3198 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3199 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3200 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3201 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3202 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3203 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3204 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3205 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3206 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3207 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3208 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3209 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3210 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3211 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3212 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3213 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3214 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3215 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3216 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3217 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3218 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3219 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3220 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3221 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3222 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3223 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3224 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3225 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3226 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3227 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3228 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3229
3230 static struct attribute *hwmon_attributes[] = {
3231         &sensor_dev_attr_temp1_input.dev_attr.attr,
3232         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3233         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3234         &sensor_dev_attr_temp2_input.dev_attr.attr,
3235         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3236         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3237         &sensor_dev_attr_temp3_input.dev_attr.attr,
3238         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3239         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3240         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3241         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3242         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3243         &sensor_dev_attr_temp1_label.dev_attr.attr,
3244         &sensor_dev_attr_temp2_label.dev_attr.attr,
3245         &sensor_dev_attr_temp3_label.dev_attr.attr,
3246         &sensor_dev_attr_pwm1.dev_attr.attr,
3247         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3248         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3249         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3250         &sensor_dev_attr_fan1_input.dev_attr.attr,
3251         &sensor_dev_attr_fan1_min.dev_attr.attr,
3252         &sensor_dev_attr_fan1_max.dev_attr.attr,
3253         &sensor_dev_attr_fan1_target.dev_attr.attr,
3254         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3255         &sensor_dev_attr_in0_input.dev_attr.attr,
3256         &sensor_dev_attr_in0_label.dev_attr.attr,
3257         &sensor_dev_attr_in1_input.dev_attr.attr,
3258         &sensor_dev_attr_in1_label.dev_attr.attr,
3259         &sensor_dev_attr_power1_average.dev_attr.attr,
3260         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3261         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3262         &sensor_dev_attr_power1_cap.dev_attr.attr,
3263         &sensor_dev_attr_freq1_input.dev_attr.attr,
3264         &sensor_dev_attr_freq1_label.dev_attr.attr,
3265         &sensor_dev_attr_freq2_input.dev_attr.attr,
3266         &sensor_dev_attr_freq2_label.dev_attr.attr,
3267         NULL
3268 };
3269
3270 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3271                                         struct attribute *attr, int index)
3272 {
3273         struct device *dev = kobj_to_dev(kobj);
3274         struct amdgpu_device *adev = dev_get_drvdata(dev);
3275         umode_t effective_mode = attr->mode;
3276
3277         /* under multi-vf mode, the hwmon attributes are all not supported */
3278         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3279                 return 0;
3280
3281         /* there is no fan under pp one vf mode */
3282         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3283             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3284              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3285              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3286              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3287              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3288              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3289              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3290              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3291              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3292                 return 0;
3293
3294         /* Skip fan attributes if fan is not present */
3295         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3296             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3297             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3298             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3299             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3300             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3301             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3302             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3303             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3304                 return 0;
3305
3306         /* Skip fan attributes on APU */
3307         if ((adev->flags & AMD_IS_APU) &&
3308             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3309              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3310              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3311              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3312              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3313              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3314              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3315              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3316              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3317                 return 0;
3318
3319         /* Skip crit temp on APU */
3320         if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3321             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3322              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3323                 return 0;
3324
3325         /* Skip limit attributes if DPM is not enabled */
3326         if (!adev->pm.dpm_enabled &&
3327             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3328              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3329              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3330              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3331              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3332              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3333              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3334              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3335              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3336              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3337              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3338                 return 0;
3339
3340         if (!is_support_sw_smu(adev)) {
3341                 /* mask fan attributes if we have no bindings for this asic to expose */
3342                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3343                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3344                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3345                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3346                         effective_mode &= ~S_IRUGO;
3347
3348                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3349                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3350                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3351                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3352                         effective_mode &= ~S_IWUSR;
3353         }
3354
3355         if (((adev->flags & AMD_IS_APU) ||
3356              adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3357              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3358             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
3359              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3360              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3361              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
3362                 return 0;
3363
3364         if (!is_support_sw_smu(adev)) {
3365                 /* hide max/min values if we can't both query and manage the fan */
3366                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3367                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3368                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3369                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3370                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3371                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3372                         return 0;
3373
3374                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3375                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3376                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3377                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3378                         return 0;
3379         }
3380
3381         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3382              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3383             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3384              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3385                 return 0;
3386
3387         /* only APUs have vddnb */
3388         if (!(adev->flags & AMD_IS_APU) &&
3389             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3390              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3391                 return 0;
3392
3393         /* no mclk on APUs */
3394         if ((adev->flags & AMD_IS_APU) &&
3395             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3396              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3397                 return 0;
3398
3399         /* only SOC15 dGPUs support hotspot and mem temperatures */
3400         if (((adev->flags & AMD_IS_APU) ||
3401              adev->asic_type < CHIP_VEGA10) &&
3402             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3403              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3404              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3405              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3406              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3407              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3408              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3409              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3410              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3411              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3412              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3413                 return 0;
3414
3415         return effective_mode;
3416 }
3417
3418 static const struct attribute_group hwmon_attrgroup = {
3419         .attrs = hwmon_attributes,
3420         .is_visible = hwmon_attributes_visible,
3421 };
3422
3423 static const struct attribute_group *hwmon_groups[] = {
3424         &hwmon_attrgroup,
3425         NULL
3426 };
3427
3428 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
3429 {
3430         struct amdgpu_device *adev =
3431                 container_of(work, struct amdgpu_device,
3432                              pm.dpm.thermal.work);
3433         /* switch to the thermal state */
3434         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
3435         int temp, size = sizeof(temp);
3436
3437         if (!adev->pm.dpm_enabled)
3438                 return;
3439
3440         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
3441                                     (void *)&temp, &size)) {
3442                 if (temp < adev->pm.dpm.thermal.min_temp)
3443                         /* switch back the user state */
3444                         dpm_state = adev->pm.dpm.user_state;
3445         } else {
3446                 if (adev->pm.dpm.thermal.high_to_low)
3447                         /* switch back the user state */
3448                         dpm_state = adev->pm.dpm.user_state;
3449         }
3450         mutex_lock(&adev->pm.mutex);
3451         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
3452                 adev->pm.dpm.thermal_active = true;
3453         else
3454                 adev->pm.dpm.thermal_active = false;
3455         adev->pm.dpm.state = dpm_state;
3456         mutex_unlock(&adev->pm.mutex);
3457
3458         amdgpu_pm_compute_clocks(adev);
3459 }
3460
3461 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
3462                                                      enum amd_pm_state_type dpm_state)
3463 {
3464         int i;
3465         struct amdgpu_ps *ps;
3466         u32 ui_class;
3467         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
3468                 true : false;
3469
3470         /* check if the vblank period is too short to adjust the mclk */
3471         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
3472                 if (amdgpu_dpm_vblank_too_short(adev))
3473                         single_display = false;
3474         }
3475
3476         /* certain older asics have a separare 3D performance state,
3477          * so try that first if the user selected performance
3478          */
3479         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
3480                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
3481         /* balanced states don't exist at the moment */
3482         if (dpm_state == POWER_STATE_TYPE_BALANCED)
3483                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3484
3485 restart_search:
3486         /* Pick the best power state based on current conditions */
3487         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
3488                 ps = &adev->pm.dpm.ps[i];
3489                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
3490                 switch (dpm_state) {
3491                 /* user states */
3492                 case POWER_STATE_TYPE_BATTERY:
3493                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
3494                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3495                                         if (single_display)
3496                                                 return ps;
3497                                 } else
3498                                         return ps;
3499                         }
3500                         break;
3501                 case POWER_STATE_TYPE_BALANCED:
3502                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
3503                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3504                                         if (single_display)
3505                                                 return ps;
3506                                 } else
3507                                         return ps;
3508                         }
3509                         break;
3510                 case POWER_STATE_TYPE_PERFORMANCE:
3511                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3512                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3513                                         if (single_display)
3514                                                 return ps;
3515                                 } else
3516                                         return ps;
3517                         }
3518                         break;
3519                 /* internal states */
3520                 case POWER_STATE_TYPE_INTERNAL_UVD:
3521                         if (adev->pm.dpm.uvd_ps)
3522                                 return adev->pm.dpm.uvd_ps;
3523                         else
3524                                 break;
3525                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3526                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3527                                 return ps;
3528                         break;
3529                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3530                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3531                                 return ps;
3532                         break;
3533                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3534                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3535                                 return ps;
3536                         break;
3537                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3538                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3539                                 return ps;
3540                         break;
3541                 case POWER_STATE_TYPE_INTERNAL_BOOT:
3542                         return adev->pm.dpm.boot_ps;
3543                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
3544                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
3545                                 return ps;
3546                         break;
3547                 case POWER_STATE_TYPE_INTERNAL_ACPI:
3548                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
3549                                 return ps;
3550                         break;
3551                 case POWER_STATE_TYPE_INTERNAL_ULV:
3552                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
3553                                 return ps;
3554                         break;
3555                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
3556                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
3557                                 return ps;
3558                         break;
3559                 default:
3560                         break;
3561                 }
3562         }
3563         /* use a fallback state if we didn't match */
3564         switch (dpm_state) {
3565         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3566                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
3567                 goto restart_search;
3568         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3569         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3570         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3571                 if (adev->pm.dpm.uvd_ps) {
3572                         return adev->pm.dpm.uvd_ps;
3573                 } else {
3574                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3575                         goto restart_search;
3576                 }
3577         case POWER_STATE_TYPE_INTERNAL_THERMAL:
3578                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
3579                 goto restart_search;
3580         case POWER_STATE_TYPE_INTERNAL_ACPI:
3581                 dpm_state = POWER_STATE_TYPE_BATTERY;
3582                 goto restart_search;
3583         case POWER_STATE_TYPE_BATTERY:
3584         case POWER_STATE_TYPE_BALANCED:
3585         case POWER_STATE_TYPE_INTERNAL_3DPERF:
3586                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3587                 goto restart_search;
3588         default:
3589                 break;
3590         }
3591
3592         return NULL;
3593 }
3594
3595 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
3596 {
3597         struct amdgpu_ps *ps;
3598         enum amd_pm_state_type dpm_state;
3599         int ret;
3600         bool equal = false;
3601
3602         /* if dpm init failed */
3603         if (!adev->pm.dpm_enabled)
3604                 return;
3605
3606         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
3607                 /* add other state override checks here */
3608                 if ((!adev->pm.dpm.thermal_active) &&
3609                     (!adev->pm.dpm.uvd_active))
3610                         adev->pm.dpm.state = adev->pm.dpm.user_state;
3611         }
3612         dpm_state = adev->pm.dpm.state;
3613
3614         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
3615         if (ps)
3616                 adev->pm.dpm.requested_ps = ps;
3617         else
3618                 return;
3619
3620         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
3621                 printk("switching from power state:\n");
3622                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
3623                 printk("switching to power state:\n");
3624                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
3625         }
3626
3627         /* update whether vce is active */
3628         ps->vce_active = adev->pm.dpm.vce_active;
3629         if (adev->powerplay.pp_funcs->display_configuration_changed)
3630                 amdgpu_dpm_display_configuration_changed(adev);
3631
3632         ret = amdgpu_dpm_pre_set_power_state(adev);
3633         if (ret)
3634                 return;
3635
3636         if (adev->powerplay.pp_funcs->check_state_equal) {
3637                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
3638                         equal = false;
3639         }
3640
3641         if (equal)
3642                 return;
3643
3644         amdgpu_dpm_set_power_state(adev);
3645         amdgpu_dpm_post_set_power_state(adev);
3646
3647         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
3648         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
3649
3650         if (adev->powerplay.pp_funcs->force_performance_level) {
3651                 if (adev->pm.dpm.thermal_active) {
3652                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
3653                         /* force low perf level for thermal */
3654                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
3655                         /* save the user's level */
3656                         adev->pm.dpm.forced_level = level;
3657                 } else {
3658                         /* otherwise, user selected level */
3659                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
3660                 }
3661         }
3662 }
3663
3664 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
3665 {
3666         int ret = 0;
3667
3668         if (adev->family == AMDGPU_FAMILY_SI) {
3669                 mutex_lock(&adev->pm.mutex);
3670                 if (enable) {
3671                         adev->pm.dpm.uvd_active = true;
3672                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
3673                 } else {
3674                         adev->pm.dpm.uvd_active = false;
3675                 }
3676                 mutex_unlock(&adev->pm.mutex);
3677
3678                 amdgpu_pm_compute_clocks(adev);
3679         } else {
3680                 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
3681                 if (ret)
3682                         DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
3683                                   enable ? "enable" : "disable", ret);
3684
3685                 /* enable/disable Low Memory PState for UVD (4k videos) */
3686                 if (adev->asic_type == CHIP_STONEY &&
3687                         adev->uvd.decode_image_width >= WIDTH_4K) {
3688                         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3689
3690                         if (hwmgr && hwmgr->hwmgr_func &&
3691                             hwmgr->hwmgr_func->update_nbdpm_pstate)
3692                                 hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
3693                                                                        !enable,
3694                                                                        true);
3695                 }
3696         }
3697 }
3698
3699 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
3700 {
3701         int ret = 0;
3702
3703         if (adev->family == AMDGPU_FAMILY_SI) {
3704                 mutex_lock(&adev->pm.mutex);
3705                 if (enable) {
3706                         adev->pm.dpm.vce_active = true;
3707                         /* XXX select vce level based on ring/task */
3708                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
3709                 } else {
3710                         adev->pm.dpm.vce_active = false;
3711                 }
3712                 mutex_unlock(&adev->pm.mutex);
3713
3714                 amdgpu_pm_compute_clocks(adev);
3715         } else {
3716                 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
3717                 if (ret)
3718                         DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
3719                                   enable ? "enable" : "disable", ret);
3720         }
3721 }
3722
3723 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
3724 {
3725         int i;
3726
3727         if (adev->powerplay.pp_funcs->print_power_state == NULL)
3728                 return;
3729
3730         for (i = 0; i < adev->pm.dpm.num_ps; i++)
3731                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
3732
3733 }
3734
3735 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
3736 {
3737         int ret = 0;
3738
3739         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
3740         if (ret)
3741                 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
3742                           enable ? "enable" : "disable", ret);
3743 }
3744
3745 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
3746 {
3747         int r;
3748
3749         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
3750                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
3751                 if (r) {
3752                         pr_err("smu firmware loading failed\n");
3753                         return r;
3754                 }
3755                 *smu_version = adev->pm.fw_version;
3756         }
3757         return 0;
3758 }
3759
3760 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3761 {
3762         int ret;
3763         uint32_t mask = 0;
3764
3765         if (adev->pm.sysfs_initialized)
3766                 return 0;
3767
3768         if (adev->pm.dpm_enabled == 0)
3769                 return 0;
3770
3771         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3772
3773         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3774                                                                    DRIVER_NAME, adev,
3775                                                                    hwmon_groups);
3776         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3777                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3778                 dev_err(adev->dev,
3779                         "Unable to register hwmon device: %d\n", ret);
3780                 return ret;
3781         }
3782
3783         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3784         case SRIOV_VF_MODE_ONE_VF:
3785                 mask = ATTR_FLAG_ONEVF;
3786                 break;
3787         case SRIOV_VF_MODE_MULTI_VF:
3788                 mask = 0;
3789                 break;
3790         case SRIOV_VF_MODE_BARE_METAL:
3791         default:
3792                 mask = ATTR_FLAG_MASK_ALL;
3793                 break;
3794         }
3795
3796         ret = amdgpu_device_attr_create_groups(adev,
3797                                                amdgpu_device_attrs,
3798                                                ARRAY_SIZE(amdgpu_device_attrs),
3799                                                mask,
3800                                                &adev->pm.pm_attr_list);
3801         if (ret)
3802                 return ret;
3803
3804         adev->pm.sysfs_initialized = true;
3805
3806         return 0;
3807 }
3808
3809 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3810 {
3811         if (adev->pm.dpm_enabled == 0)
3812                 return;
3813
3814         if (adev->pm.int_hwmon_dev)
3815                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3816
3817         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3818 }
3819
3820 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
3821 {
3822         int i = 0;
3823
3824         if (!adev->pm.dpm_enabled)
3825                 return;
3826
3827         if (adev->mode_info.num_crtc)
3828                 amdgpu_display_bandwidth_update(adev);
3829
3830         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3831                 struct amdgpu_ring *ring = adev->rings[i];
3832                 if (ring && ring->sched.ready)
3833                         amdgpu_fence_wait_empty(ring);
3834         }
3835
3836         if (is_support_sw_smu(adev)) {
3837                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3838                 smu_handle_task(&adev->smu,
3839                                 smu_dpm->dpm_level,
3840                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
3841                                 true);
3842         } else {
3843                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3844                         if (!amdgpu_device_has_dc_support(adev)) {
3845                                 mutex_lock(&adev->pm.mutex);
3846                                 amdgpu_dpm_get_active_displays(adev);
3847                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3848                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3849                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3850                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3851                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3852                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3853                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3854                                         adev->powerplay.pp_funcs->display_configuration_change(
3855                                                                         adev->powerplay.pp_handle,
3856                                                                         &adev->pm.pm_display_cfg);
3857                                 mutex_unlock(&adev->pm.mutex);
3858                         }
3859                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3860                 } else {
3861                         mutex_lock(&adev->pm.mutex);
3862                         amdgpu_dpm_get_active_displays(adev);
3863                         amdgpu_dpm_change_power_state_locked(adev);
3864                         mutex_unlock(&adev->pm.mutex);
3865                 }
3866         }
3867 }
3868
3869 /*
3870  * Debugfs info
3871  */
3872 #if defined(CONFIG_DEBUG_FS)
3873
3874 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3875 {
3876         uint32_t value;
3877         uint64_t value64;
3878         uint32_t query = 0;
3879         int size;
3880
3881         /* GPU Clocks */
3882         size = sizeof(value);
3883         seq_printf(m, "GFX Clocks and Power:\n");
3884         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3885                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3886         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3887                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3888         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3889                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3890         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3891                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3892         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3893                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3894         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3895                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3896         size = sizeof(uint32_t);
3897         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3898                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3899         size = sizeof(value);
3900         seq_printf(m, "\n");
3901
3902         /* GPU Temp */
3903         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3904                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3905
3906         /* GPU Load */
3907         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3908                 seq_printf(m, "GPU Load: %u %%\n", value);
3909         /* MEM Load */
3910         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3911                 seq_printf(m, "MEM Load: %u %%\n", value);
3912
3913         seq_printf(m, "\n");
3914
3915         /* SMC feature mask */
3916         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3917                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3918
3919         if (adev->asic_type > CHIP_VEGA20) {
3920                 /* VCN clocks */
3921                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3922                         if (!value) {
3923                                 seq_printf(m, "VCN: Disabled\n");
3924                         } else {
3925                                 seq_printf(m, "VCN: Enabled\n");
3926                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3927                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3928                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3929                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3930                         }
3931                 }
3932                 seq_printf(m, "\n");
3933         } else {
3934                 /* UVD clocks */
3935                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3936                         if (!value) {
3937                                 seq_printf(m, "UVD: Disabled\n");
3938                         } else {
3939                                 seq_printf(m, "UVD: Enabled\n");
3940                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3941                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3942                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3943                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3944                         }
3945                 }
3946                 seq_printf(m, "\n");
3947
3948                 /* VCE clocks */
3949                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3950                         if (!value) {
3951                                 seq_printf(m, "VCE: Disabled\n");
3952                         } else {
3953                                 seq_printf(m, "VCE: Enabled\n");
3954                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3955                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3956                         }
3957                 }
3958         }
3959
3960         return 0;
3961 }
3962
3963 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3964 {
3965         int i;
3966
3967         for (i = 0; clocks[i].flag; i++)
3968                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3969                            (flags & clocks[i].flag) ? "On" : "Off");
3970 }
3971
3972 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3973 {
3974         struct drm_info_node *node = (struct drm_info_node *) m->private;
3975         struct drm_device *dev = node->minor->dev;
3976         struct amdgpu_device *adev = dev->dev_private;
3977         u32 flags = 0;
3978         int r;
3979
3980         if (adev->in_gpu_reset)
3981                 return -EPERM;
3982
3983         r = pm_runtime_get_sync(dev->dev);
3984         if (r < 0) {
3985                 pm_runtime_put_autosuspend(dev->dev);
3986                 return r;
3987         }
3988
3989         if (!adev->pm.dpm_enabled) {
3990                 seq_printf(m, "dpm not enabled\n");
3991                 pm_runtime_mark_last_busy(dev->dev);
3992                 pm_runtime_put_autosuspend(dev->dev);
3993                 return 0;
3994         }
3995
3996         if (!is_support_sw_smu(adev) &&
3997             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3998                 mutex_lock(&adev->pm.mutex);
3999                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
4000                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
4001                 else
4002                         seq_printf(m, "Debugfs support not implemented for this asic\n");
4003                 mutex_unlock(&adev->pm.mutex);
4004                 r = 0;
4005         } else {
4006                 r = amdgpu_debugfs_pm_info_pp(m, adev);
4007         }
4008         if (r)
4009                 goto out;
4010
4011         amdgpu_device_ip_get_clockgating_state(adev, &flags);
4012
4013         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
4014         amdgpu_parse_cg_state(m, flags);
4015         seq_printf(m, "\n");
4016
4017 out:
4018         pm_runtime_mark_last_busy(dev->dev);
4019         pm_runtime_put_autosuspend(dev->dev);
4020
4021         return r;
4022 }
4023
4024 static const struct drm_info_list amdgpu_pm_info_list[] = {
4025         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
4026 };
4027 #endif
4028
4029 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
4030 {
4031 #if defined(CONFIG_DEBUG_FS)
4032         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
4033 #else
4034         return 0;
4035 #endif
4036 }