2 * Copyright 2014 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <drm/amdgpu_drm.h>
27 #include "atombios_encoders.h"
28 #include "amdgpu_pll.h"
29 #include <asm/div64.h>
30 #include <linux/gcd.h>
33 * amdgpu_pll_reduce_ratio - fractional number reduction
37 * @nom_min: minimum value for nominator
38 * @den_min: minimum value for denominator
40 * Find the greatest common divisor and apply it on both nominator and
41 * denominator, but make nominator and denominator are at least as large
42 * as their minimum values.
44 static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den,
45 unsigned nom_min, unsigned den_min)
49 /* reduce the numbers to a simpler ratio */
50 tmp = gcd(*nom, *den);
54 /* make sure nominator is large enough */
56 tmp = DIV_ROUND_UP(nom_min, *nom);
61 /* make sure the denominator is large enough */
63 tmp = DIV_ROUND_UP(den_min, *den);
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
74 * @post_div: post divider
75 * @fb_div_max: feedback divider maximum
76 * @ref_div_max: reference divider maximum
77 * @fb_div: resulting feedback divider
78 * @ref_div: resulting reference divider
80 * Calculate feedback and reference divider for a given post divider. Makes
81 * sure we stay within the limits.
83 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
84 unsigned fb_div_max, unsigned ref_div_max,
85 unsigned *fb_div, unsigned *ref_div)
87 /* limit reference * post divider to a maximum */
88 ref_div_max = min(128 / post_div, ref_div_max);
90 /* get matching reference and feedback divider */
91 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
92 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
94 /* limit fb divider to its maximum */
95 if (*fb_div > fb_div_max) {
96 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
102 * amdgpu_pll_compute - compute PLL paramaters
104 * @pll: information about the PLL
105 * @freq: requested frequency
106 * @dot_clock_p: resulting pixel clock
107 * @fb_div_p: resulting feedback divider
108 * @frac_fb_div_p: fractional part of the feedback divider
109 * @ref_div_p: resulting reference divider
110 * @post_div_p: resulting reference divider
112 * Try to calculate the PLL parameters to generate the given frequency:
113 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
115 void amdgpu_pll_compute(struct amdgpu_pll *pll,
123 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
126 unsigned fb_div_min, fb_div_max, fb_div;
127 unsigned post_div_min, post_div_max, post_div;
128 unsigned ref_div_min, ref_div_max, ref_div;
129 unsigned post_div_best, diff_best;
132 /* determine allowed feedback divider range */
133 fb_div_min = pll->min_feedback_div;
134 fb_div_max = pll->max_feedback_div;
136 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
141 /* determine allowed ref divider range */
142 if (pll->flags & AMDGPU_PLL_USE_REF_DIV)
143 ref_div_min = pll->reference_div;
145 ref_div_min = pll->min_ref_div;
147 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&
148 pll->flags & AMDGPU_PLL_USE_REF_DIV)
149 ref_div_max = pll->reference_div;
151 ref_div_max = pll->max_ref_div;
153 /* determine allowed post divider range */
154 if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {
155 post_div_min = pll->post_div;
156 post_div_max = pll->post_div;
158 unsigned vco_min, vco_max;
160 if (pll->flags & AMDGPU_PLL_IS_LCD) {
161 vco_min = pll->lcd_pll_out_min;
162 vco_max = pll->lcd_pll_out_max;
164 vco_min = pll->pll_out_min;
165 vco_max = pll->pll_out_max;
168 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
173 post_div_min = vco_min / target_clock;
174 if ((target_clock * post_div_min) < vco_min)
176 if (post_div_min < pll->min_post_div)
177 post_div_min = pll->min_post_div;
179 post_div_max = vco_max / target_clock;
180 if ((target_clock * post_div_max) > vco_max)
182 if (post_div_max > pll->max_post_div)
183 post_div_max = pll->max_post_div;
186 /* represent the searched ratio as fractional number */
188 den = pll->reference_freq;
190 /* reduce the numbers to a simpler ratio */
191 amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
193 /* now search for a post divider */
194 if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)
195 post_div_best = post_div_min;
197 post_div_best = post_div_max;
200 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
202 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max,
203 ref_div_max, &fb_div, &ref_div);
204 diff = abs(target_clock - (pll->reference_freq * fb_div) /
205 (ref_div * post_div));
207 if (diff < diff_best || (diff == diff_best &&
208 !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {
210 post_div_best = post_div;
214 post_div = post_div_best;
216 /* get the feedback and reference divider for the optimal value */
217 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
220 /* reduce the numbers to a simpler ratio once more */
221 /* this also makes sure that the reference divider is large enough */
222 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
224 /* avoid high jitter with small fractional dividers */
225 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
226 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
227 if (fb_div < fb_div_min) {
228 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
234 /* and finally save the result */
235 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
236 *fb_div_p = fb_div / 10;
237 *frac_fb_div_p = fb_div % 10;
243 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
244 (pll->reference_freq * *frac_fb_div_p)) /
245 (ref_div * post_div * 10);
246 *ref_div_p = ref_div;
247 *post_div_p = post_div;
249 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
250 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
255 * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use
259 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
261 u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc)
263 struct drm_device *dev = crtc->dev;
264 struct drm_crtc *test_crtc;
265 struct amdgpu_crtc *test_amdgpu_crtc;
268 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
269 if (crtc == test_crtc)
272 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
273 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
274 pll_in_use |= (1 << test_amdgpu_crtc->pll_id);
280 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
284 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
285 * also in DP mode. For DP, a single PPLL can be used for all DP
288 int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc)
290 struct drm_device *dev = crtc->dev;
291 struct drm_crtc *test_crtc;
292 struct amdgpu_crtc *test_amdgpu_crtc;
294 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
295 if (crtc == test_crtc)
297 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
298 if (test_amdgpu_crtc->encoder &&
299 ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
300 /* for DP use the same PLL for all */
301 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
302 return test_amdgpu_crtc->pll_id;
305 return ATOM_PPLL_INVALID;
309 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
313 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
314 * be shared (i.e., same clock).
316 int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc)
318 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
319 struct drm_device *dev = crtc->dev;
320 struct drm_crtc *test_crtc;
321 struct amdgpu_crtc *test_amdgpu_crtc;
322 u32 adjusted_clock, test_adjusted_clock;
324 adjusted_clock = amdgpu_crtc->adjusted_clock;
326 if (adjusted_clock == 0)
327 return ATOM_PPLL_INVALID;
329 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
330 if (crtc == test_crtc)
332 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
333 if (test_amdgpu_crtc->encoder &&
334 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
335 /* check if we are already driving this connector with another crtc */
336 if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {
337 /* if we are, return that pll */
338 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
339 return test_amdgpu_crtc->pll_id;
341 /* for non-DP check the clock */
342 test_adjusted_clock = test_amdgpu_crtc->adjusted_clock;
343 if ((crtc->mode.clock == test_crtc->mode.clock) &&
344 (adjusted_clock == test_adjusted_clock) &&
345 (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&
346 (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))
347 return test_amdgpu_crtc->pll_id;
350 return ATOM_PPLL_INVALID;