2 * Copyright 2014 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <drm/amdgpu_drm.h>
27 #include "atombios_encoders.h"
28 #include "amdgpu_pll.h"
29 #include <asm/div64.h>
30 #include <linux/gcd.h>
33 * amdgpu_pll_reduce_ratio - fractional number reduction
37 * @nom_min: minimum value for nominator
38 * @den_min: minimum value for denominator
40 * Find the greatest common divisor and apply it on both nominator and
41 * denominator, but make nominator and denominator are at least as large
42 * as their minimum values.
44 static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den,
45 unsigned nom_min, unsigned den_min)
49 /* reduce the numbers to a simpler ratio */
50 tmp = gcd(*nom, *den);
54 /* make sure nominator is large enough */
56 tmp = DIV_ROUND_UP(nom_min, *nom);
61 /* make sure the denominator is large enough */
63 tmp = DIV_ROUND_UP(den_min, *den);
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
74 * @post_div: post divider
75 * @fb_div_max: feedback divider maximum
76 * @ref_div_max: reference divider maximum
77 * @fb_div: resulting feedback divider
78 * @ref_div: resulting reference divider
80 * Calculate feedback and reference divider for a given post divider. Makes
81 * sure we stay within the limits.
83 static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom,
84 unsigned int den, unsigned int post_div,
85 unsigned int fb_div_max, unsigned int ref_div_max,
86 unsigned int *fb_div, unsigned int *ref_div)
89 /* limit reference * post divider to a maximum */
90 if (adev->family == AMDGPU_FAMILY_SI)
91 ref_div_max = min(100 / post_div, ref_div_max);
93 ref_div_max = min(128 / post_div, ref_div_max);
95 /* get matching reference and feedback divider */
96 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
97 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
99 /* limit fb divider to its maximum */
100 if (*fb_div > fb_div_max) {
101 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
102 *fb_div = fb_div_max;
107 * amdgpu_pll_compute - compute PLL paramaters
109 * @pll: information about the PLL
110 * @freq: requested frequency
111 * @dot_clock_p: resulting pixel clock
112 * @fb_div_p: resulting feedback divider
113 * @frac_fb_div_p: fractional part of the feedback divider
114 * @ref_div_p: resulting reference divider
115 * @post_div_p: resulting reference divider
117 * Try to calculate the PLL parameters to generate the given frequency:
118 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
120 void amdgpu_pll_compute(struct amdgpu_device *adev,
121 struct amdgpu_pll *pll,
129 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
132 unsigned fb_div_min, fb_div_max, fb_div;
133 unsigned post_div_min, post_div_max, post_div;
134 unsigned ref_div_min, ref_div_max, ref_div;
135 unsigned post_div_best, diff_best;
138 /* determine allowed feedback divider range */
139 fb_div_min = pll->min_feedback_div;
140 fb_div_max = pll->max_feedback_div;
142 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
147 /* determine allowed ref divider range */
148 if (pll->flags & AMDGPU_PLL_USE_REF_DIV)
149 ref_div_min = pll->reference_div;
151 ref_div_min = pll->min_ref_div;
153 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&
154 pll->flags & AMDGPU_PLL_USE_REF_DIV)
155 ref_div_max = pll->reference_div;
157 ref_div_max = pll->max_ref_div;
159 /* determine allowed post divider range */
160 if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {
161 post_div_min = pll->post_div;
162 post_div_max = pll->post_div;
164 unsigned vco_min, vco_max;
166 if (pll->flags & AMDGPU_PLL_IS_LCD) {
167 vco_min = pll->lcd_pll_out_min;
168 vco_max = pll->lcd_pll_out_max;
170 vco_min = pll->pll_out_min;
171 vco_max = pll->pll_out_max;
174 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
179 post_div_min = vco_min / target_clock;
180 if ((target_clock * post_div_min) < vco_min)
182 if (post_div_min < pll->min_post_div)
183 post_div_min = pll->min_post_div;
185 post_div_max = vco_max / target_clock;
186 if ((target_clock * post_div_max) > vco_max)
188 if (post_div_max > pll->max_post_div)
189 post_div_max = pll->max_post_div;
192 /* represent the searched ratio as fractional number */
194 den = pll->reference_freq;
196 /* reduce the numbers to a simpler ratio */
197 amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
199 /* now search for a post divider */
200 if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)
201 post_div_best = post_div_min;
203 post_div_best = post_div_max;
206 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
208 amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max,
209 ref_div_max, &fb_div, &ref_div);
210 diff = abs(target_clock - (pll->reference_freq * fb_div) /
211 (ref_div * post_div));
213 if (diff < diff_best || (diff == diff_best &&
214 !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {
216 post_div_best = post_div;
220 post_div = post_div_best;
222 /* get the feedback and reference divider for the optimal value */
223 amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max, ref_div_max,
226 /* reduce the numbers to a simpler ratio once more */
227 /* this also makes sure that the reference divider is large enough */
228 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
230 /* avoid high jitter with small fractional dividers */
231 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
232 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
233 if (fb_div < fb_div_min) {
234 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
240 /* and finally save the result */
241 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
242 *fb_div_p = fb_div / 10;
243 *frac_fb_div_p = fb_div % 10;
249 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
250 (pll->reference_freq * *frac_fb_div_p)) /
251 (ref_div * post_div * 10);
252 *ref_div_p = ref_div;
253 *post_div_p = post_div;
255 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
256 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
261 * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use
265 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
267 u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc)
269 struct drm_device *dev = crtc->dev;
270 struct drm_crtc *test_crtc;
271 struct amdgpu_crtc *test_amdgpu_crtc;
274 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
275 if (crtc == test_crtc)
278 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
279 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
280 pll_in_use |= (1 << test_amdgpu_crtc->pll_id);
286 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
290 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
291 * also in DP mode. For DP, a single PPLL can be used for all DP
294 int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc)
296 struct drm_device *dev = crtc->dev;
297 struct drm_crtc *test_crtc;
298 struct amdgpu_crtc *test_amdgpu_crtc;
300 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
301 if (crtc == test_crtc)
303 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
304 if (test_amdgpu_crtc->encoder &&
305 ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
306 /* for DP use the same PLL for all */
307 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
308 return test_amdgpu_crtc->pll_id;
311 return ATOM_PPLL_INVALID;
315 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
319 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
320 * be shared (i.e., same clock).
322 int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc)
324 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
325 struct drm_device *dev = crtc->dev;
326 struct drm_crtc *test_crtc;
327 struct amdgpu_crtc *test_amdgpu_crtc;
328 u32 adjusted_clock, test_adjusted_clock;
330 adjusted_clock = amdgpu_crtc->adjusted_clock;
332 if (adjusted_clock == 0)
333 return ATOM_PPLL_INVALID;
335 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
336 if (crtc == test_crtc)
338 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
339 if (test_amdgpu_crtc->encoder &&
340 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
341 /* check if we are already driving this connector with another crtc */
342 if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {
343 /* if we are, return that pll */
344 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
345 return test_amdgpu_crtc->pll_id;
347 /* for non-DP check the clock */
348 test_adjusted_clock = test_amdgpu_crtc->adjusted_clock;
349 if ((crtc->mode.clock == test_crtc->mode.clock) &&
350 (adjusted_clock == test_adjusted_clock) &&
351 (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&
352 (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))
353 return test_amdgpu_crtc->pll_id;
356 return ATOM_PPLL_INVALID;