2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
36 #include <drm/amdgpu_drm.h>
37 #include <drm/drm_cache.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
46 * represents memory used by driver (VRAM, system memory, etc.). The driver
47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
48 * to create/destroy/set buffer object which are then managed by the kernel TTM
50 * The interfaces are also used internally by kernel clients, including gfx,
51 * uvd, etc. for kernel managed allocations used by the GPU.
55 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
57 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
61 if (bo->tbo.base.import_attach)
62 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
63 drm_gem_object_release(&bo->tbo.base);
64 amdgpu_bo_unref(&bo->parent);
68 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
70 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
71 struct amdgpu_bo_user *ubo;
73 ubo = to_amdgpu_bo_user(bo);
75 amdgpu_bo_destroy(tbo);
78 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
80 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
81 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
83 /* in case amdgpu_device_recover_vram got NULL of bo->parent */
84 if (!list_empty(&bo->shadow_list)) {
85 mutex_lock(&adev->shadow_list_lock);
86 list_del_init(&bo->shadow_list);
87 mutex_unlock(&adev->shadow_list_lock);
90 amdgpu_bo_destroy(tbo);
94 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
95 * @bo: buffer object to be checked
97 * Uses destroy function associated with the object to determine if this is
101 * true if the object belongs to &amdgpu_bo, false if not.
103 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
105 if (bo->destroy == &amdgpu_bo_destroy ||
106 bo->destroy == &amdgpu_bo_user_destroy ||
107 bo->destroy == &amdgpu_bo_vm_destroy)
114 * amdgpu_bo_placement_from_domain - set buffer's placement
115 * @abo: &amdgpu_bo buffer object whose placement is to be set
116 * @domain: requested domain
118 * Sets buffer's placement according to requested domain and the buffer's
121 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
123 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
124 struct ttm_placement *placement = &abo->placement;
125 struct ttm_place *places = abo->placements;
126 u64 flags = abo->flags;
129 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
130 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
134 places[c].mem_type = TTM_PL_VRAM;
137 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
138 places[c].lpfn = visible_pfn;
140 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
142 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
143 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
147 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
151 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
152 AMDGPU_PL_PREEMPT : TTM_PL_TT;
157 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
160 places[c].mem_type = TTM_PL_SYSTEM;
165 if (domain & AMDGPU_GEM_DOMAIN_GDS) {
168 places[c].mem_type = AMDGPU_PL_GDS;
173 if (domain & AMDGPU_GEM_DOMAIN_GWS) {
176 places[c].mem_type = AMDGPU_PL_GWS;
181 if (domain & AMDGPU_GEM_DOMAIN_OA) {
184 places[c].mem_type = AMDGPU_PL_OA;
192 places[c].mem_type = TTM_PL_SYSTEM;
197 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS);
199 placement->num_placement = c;
200 placement->placement = places;
202 placement->num_busy_placement = c;
203 placement->busy_placement = places;
207 * amdgpu_bo_create_reserved - create reserved BO for kernel use
209 * @adev: amdgpu device object
210 * @size: size for the new BO
211 * @align: alignment for the new BO
212 * @domain: where to place it
213 * @bo_ptr: used to initialize BOs in structures
214 * @gpu_addr: GPU addr of the pinned BO
215 * @cpu_addr: optional CPU address mapping
217 * Allocates and pins a BO for kernel internal use, and returns it still
220 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
223 * 0 on success, negative error code otherwise.
225 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
226 unsigned long size, int align,
227 u32 domain, struct amdgpu_bo **bo_ptr,
228 u64 *gpu_addr, void **cpu_addr)
230 struct amdgpu_bo_param bp;
235 amdgpu_bo_unref(bo_ptr);
239 memset(&bp, 0, sizeof(bp));
241 bp.byte_align = align;
243 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
244 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
245 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
246 bp.type = ttm_bo_type_kernel;
248 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
251 r = amdgpu_bo_create(adev, &bp, bo_ptr);
253 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
260 r = amdgpu_bo_reserve(*bo_ptr, false);
262 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
266 r = amdgpu_bo_pin(*bo_ptr, domain);
268 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
269 goto error_unreserve;
272 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
274 dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
279 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
282 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
284 dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
292 amdgpu_bo_unpin(*bo_ptr);
294 amdgpu_bo_unreserve(*bo_ptr);
298 amdgpu_bo_unref(bo_ptr);
304 * amdgpu_bo_create_kernel - create BO for kernel use
306 * @adev: amdgpu device object
307 * @size: size for the new BO
308 * @align: alignment for the new BO
309 * @domain: where to place it
310 * @bo_ptr: used to initialize BOs in structures
311 * @gpu_addr: GPU addr of the pinned BO
312 * @cpu_addr: optional CPU address mapping
314 * Allocates and pins a BO for kernel internal use.
316 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
319 * 0 on success, negative error code otherwise.
321 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
322 unsigned long size, int align,
323 u32 domain, struct amdgpu_bo **bo_ptr,
324 u64 *gpu_addr, void **cpu_addr)
328 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
335 amdgpu_bo_unreserve(*bo_ptr);
341 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
343 * @adev: amdgpu device object
344 * @offset: offset of the BO
345 * @size: size of the BO
346 * @domain: where to place it
347 * @bo_ptr: used to initialize BOs in structures
348 * @cpu_addr: optional CPU address mapping
350 * Creates a kernel BO at a specific offset in the address space of the domain.
353 * 0 on success, negative error code otherwise.
355 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
356 uint64_t offset, uint64_t size, uint32_t domain,
357 struct amdgpu_bo **bo_ptr, void **cpu_addr)
359 struct ttm_operation_ctx ctx = { false, false };
364 size = ALIGN(size, PAGE_SIZE);
366 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
371 if ((*bo_ptr) == NULL)
375 * Remove the original mem node and create a new one at the request
379 amdgpu_bo_kunmap(*bo_ptr);
381 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
383 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
384 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
385 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
387 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
388 &(*bo_ptr)->tbo.resource, &ctx);
393 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
398 amdgpu_bo_unreserve(*bo_ptr);
402 amdgpu_bo_unreserve(*bo_ptr);
403 amdgpu_bo_unref(bo_ptr);
408 * amdgpu_bo_free_kernel - free BO for kernel use
410 * @bo: amdgpu BO to free
411 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
412 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
414 * unmaps and unpin a BO for kernel internal use.
416 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
422 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
424 amdgpu_bo_kunmap(*bo);
426 amdgpu_bo_unpin(*bo);
427 amdgpu_bo_unreserve(*bo);
438 /* Validate bo size is bit bigger then the request domain */
439 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
440 unsigned long size, u32 domain)
442 struct ttm_resource_manager *man = NULL;
445 * If GTT is part of requested domains the check must succeed to
446 * allow fall back to GTT
448 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
449 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
451 if (size < (man->size << PAGE_SHIFT))
457 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
458 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
460 if (size < (man->size << PAGE_SHIFT))
467 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
471 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
472 man->size << PAGE_SHIFT);
476 bool amdgpu_bo_support_uswc(u64 bo_flags)
480 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
481 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
484 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
485 /* Don't try to enable write-combining when it can't work, or things
487 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
490 #ifndef CONFIG_COMPILE_TEST
491 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
492 thanks to write-combining
495 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
496 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
497 "better performance thanks to write-combining\n");
500 /* For architectures that don't support WC memory,
501 * mask out the WC flag from the BO
503 if (!drm_arch_can_wc_memory())
511 * amdgpu_bo_create - create an &amdgpu_bo buffer object
512 * @adev: amdgpu device object
513 * @bp: parameters to be used for the buffer object
514 * @bo_ptr: pointer to the buffer object pointer
516 * Creates an &amdgpu_bo buffer object.
519 * 0 for success or a negative error code on failure.
521 int amdgpu_bo_create(struct amdgpu_device *adev,
522 struct amdgpu_bo_param *bp,
523 struct amdgpu_bo **bo_ptr)
525 struct ttm_operation_ctx ctx = {
526 .interruptible = (bp->type != ttm_bo_type_kernel),
527 .no_wait_gpu = bp->no_wait_gpu,
528 /* We opt to avoid OOM on system pages allocations */
529 .gfp_retry_mayfail = true,
530 .allow_res_evict = bp->type != ttm_bo_type_kernel,
533 struct amdgpu_bo *bo;
534 unsigned long page_align, size = bp->size;
537 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
538 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
539 /* GWS and OA don't need any alignment. */
540 page_align = bp->byte_align;
542 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
543 /* Both size and alignment must be a multiple of 4. */
544 page_align = ALIGN(bp->byte_align, 4);
545 size = ALIGN(size, 4) << PAGE_SHIFT;
547 /* Memory should be aligned at least to a page size. */
548 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
549 size = ALIGN(size, PAGE_SIZE);
552 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
555 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
558 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
561 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
562 INIT_LIST_HEAD(&bo->shadow_list);
564 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
566 bo->allowed_domains = bo->preferred_domains;
567 if (bp->type != ttm_bo_type_kernel &&
568 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
569 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
571 bo->flags = bp->flags;
573 if (!amdgpu_bo_support_uswc(bo->flags))
574 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
576 bo->tbo.bdev = &adev->mman.bdev;
577 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
578 AMDGPU_GEM_DOMAIN_GDS))
579 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
581 amdgpu_bo_placement_from_domain(bo, bp->domain);
582 if (bp->type == ttm_bo_type_kernel)
583 bo->tbo.priority = 1;
586 bp->destroy = &amdgpu_bo_destroy;
588 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
589 &bo->placement, page_align, &ctx, NULL,
590 bp->resv, bp->destroy);
591 if (unlikely(r != 0))
594 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
595 bo->tbo.resource->mem_type == TTM_PL_VRAM &&
596 bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
597 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
600 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
602 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
603 bo->tbo.resource->mem_type == TTM_PL_VRAM) {
604 struct dma_fence *fence;
606 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
610 amdgpu_bo_fence(bo, fence, false);
611 dma_fence_put(bo->tbo.moving);
612 bo->tbo.moving = dma_fence_get(fence);
613 dma_fence_put(fence);
616 amdgpu_bo_unreserve(bo);
619 trace_amdgpu_bo_create(bo);
621 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
622 if (bp->type == ttm_bo_type_device)
623 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
629 dma_resv_unlock(bo->tbo.base.resv);
630 amdgpu_bo_unref(&bo);
635 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
636 * @adev: amdgpu device object
637 * @bp: parameters to be used for the buffer object
638 * @ubo_ptr: pointer to the buffer object pointer
640 * Create a BO to be used by user application;
643 * 0 for success or a negative error code on failure.
646 int amdgpu_bo_create_user(struct amdgpu_device *adev,
647 struct amdgpu_bo_param *bp,
648 struct amdgpu_bo_user **ubo_ptr)
650 struct amdgpu_bo *bo_ptr;
653 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
654 bp->destroy = &amdgpu_bo_user_destroy;
655 r = amdgpu_bo_create(adev, bp, &bo_ptr);
659 *ubo_ptr = to_amdgpu_bo_user(bo_ptr);
664 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
665 * @adev: amdgpu device object
666 * @bp: parameters to be used for the buffer object
667 * @vmbo_ptr: pointer to the buffer object pointer
669 * Create a BO to be for GPUVM.
672 * 0 for success or a negative error code on failure.
675 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
676 struct amdgpu_bo_param *bp,
677 struct amdgpu_bo_vm **vmbo_ptr)
679 struct amdgpu_bo *bo_ptr;
682 /* bo_ptr_size will be determined by the caller and it depends on
683 * num of amdgpu_vm_pt entries.
685 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
686 bp->destroy = &amdgpu_bo_vm_destroy;
687 r = amdgpu_bo_create(adev, bp, &bo_ptr);
691 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
696 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
697 * @bo: pointer to the buffer object
699 * Sets placement according to domain; and changes placement and caching
700 * policy of the buffer object according to the placement.
701 * This is used for validating shadow bos. It calls ttm_bo_validate() to
702 * make sure the buffer is resident where it needs to be.
705 * 0 for success or a negative error code on failure.
707 int amdgpu_bo_validate(struct amdgpu_bo *bo)
709 struct ttm_operation_ctx ctx = { false, false };
713 if (bo->tbo.pin_count)
716 domain = bo->preferred_domains;
719 amdgpu_bo_placement_from_domain(bo, domain);
720 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
721 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
722 domain = bo->allowed_domains;
730 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
732 * @bo: BO that will be inserted into the shadow list
734 * Insert a BO to the shadow list.
736 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo *bo)
738 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
740 mutex_lock(&adev->shadow_list_lock);
741 list_add_tail(&bo->shadow_list, &adev->shadow_list);
742 mutex_unlock(&adev->shadow_list_lock);
746 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
748 * @shadow: &amdgpu_bo shadow to be restored
749 * @fence: dma_fence associated with the operation
751 * Copies a buffer object's shadow content back to the object.
752 * This is used for recovering a buffer from its shadow in case of a gpu
753 * reset where vram context may be lost.
756 * 0 for success or a negative error code on failure.
758 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
761 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
762 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
763 uint64_t shadow_addr, parent_addr;
765 shadow_addr = amdgpu_bo_gpu_offset(shadow);
766 parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
768 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
769 amdgpu_bo_size(shadow), NULL, fence,
774 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
775 * @bo: &amdgpu_bo buffer object to be mapped
776 * @ptr: kernel virtual address to be returned
778 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
779 * amdgpu_bo_kptr() to get the kernel virtual address.
782 * 0 for success or a negative error code on failure.
784 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
789 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
792 kptr = amdgpu_bo_kptr(bo);
799 r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false,
800 MAX_SCHEDULE_TIMEOUT);
804 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);
809 *ptr = amdgpu_bo_kptr(bo);
815 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
816 * @bo: &amdgpu_bo buffer object
818 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
821 * the virtual address of a buffer object area.
823 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
827 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
831 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
832 * @bo: &amdgpu_bo buffer object to be unmapped
834 * Unmaps a kernel map set up by amdgpu_bo_kmap().
836 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
839 ttm_bo_kunmap(&bo->kmap);
843 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
844 * @bo: &amdgpu_bo buffer object
846 * References the contained &ttm_buffer_object.
849 * a refcounted pointer to the &amdgpu_bo buffer object.
851 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
856 ttm_bo_get(&bo->tbo);
861 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
862 * @bo: &amdgpu_bo buffer object
864 * Unreferences the contained &ttm_buffer_object and clear the pointer
866 void amdgpu_bo_unref(struct amdgpu_bo **bo)
868 struct ttm_buffer_object *tbo;
879 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
880 * @bo: &amdgpu_bo buffer object to be pinned
881 * @domain: domain to be pinned to
882 * @min_offset: the start of requested address range
883 * @max_offset: the end of requested address range
885 * Pins the buffer object according to requested domain and address range. If
886 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
887 * pin_count and pin_size accordingly.
889 * Pinning means to lock pages in memory along with keeping them at a fixed
890 * offset. It is required when a buffer can not be moved, for example, when
891 * a display buffer is being scanned out.
893 * Compared with amdgpu_bo_pin(), this function gives more flexibility on
894 * where to pin a buffer if there are specific restrictions on where a buffer
898 * 0 for success or a negative error code on failure.
900 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
901 u64 min_offset, u64 max_offset)
903 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
904 struct ttm_operation_ctx ctx = { false, false };
907 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
910 if (WARN_ON_ONCE(min_offset > max_offset))
913 /* A shared bo cannot be migrated to VRAM */
914 if (bo->prime_shared_count || bo->tbo.base.import_attach) {
915 if (domain & AMDGPU_GEM_DOMAIN_GTT)
916 domain = AMDGPU_GEM_DOMAIN_GTT;
921 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
922 * See function amdgpu_display_supported_domains()
924 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
926 if (bo->tbo.pin_count) {
927 uint32_t mem_type = bo->tbo.resource->mem_type;
928 uint32_t mem_flags = bo->tbo.resource->placement;
930 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
933 if ((mem_type == TTM_PL_VRAM) &&
934 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
935 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
938 ttm_bo_pin(&bo->tbo);
940 if (max_offset != 0) {
941 u64 domain_start = amdgpu_ttm_domain_start(adev,
943 WARN_ON_ONCE(max_offset <
944 (amdgpu_bo_gpu_offset(bo) - domain_start));
950 if (bo->tbo.base.import_attach)
951 dma_buf_pin(bo->tbo.base.import_attach);
953 /* force to pin into visible video ram */
954 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
955 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
956 amdgpu_bo_placement_from_domain(bo, domain);
957 for (i = 0; i < bo->placement.num_placement; i++) {
960 fpfn = min_offset >> PAGE_SHIFT;
961 lpfn = max_offset >> PAGE_SHIFT;
963 if (fpfn > bo->placements[i].fpfn)
964 bo->placements[i].fpfn = fpfn;
965 if (!bo->placements[i].lpfn ||
966 (lpfn && lpfn < bo->placements[i].lpfn))
967 bo->placements[i].lpfn = lpfn;
970 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
972 dev_err(adev->dev, "%p pin failed\n", bo);
976 ttm_bo_pin(&bo->tbo);
978 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
979 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
980 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
981 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
982 &adev->visible_pin_size);
983 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
984 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
992 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
993 * @bo: &amdgpu_bo buffer object to be pinned
994 * @domain: domain to be pinned to
996 * A simple wrapper to amdgpu_bo_pin_restricted().
997 * Provides a simpler API for buffers that do not have any strict restrictions
998 * on where a buffer must be located.
1001 * 0 for success or a negative error code on failure.
1003 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
1005 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1006 return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1010 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
1011 * @bo: &amdgpu_bo buffer object to be unpinned
1013 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
1014 * Changes placement and pin size accordingly.
1017 * 0 for success or a negative error code on failure.
1019 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
1021 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1023 ttm_bo_unpin(&bo->tbo);
1024 if (bo->tbo.pin_count)
1027 if (bo->tbo.base.import_attach)
1028 dma_buf_unpin(bo->tbo.base.import_attach);
1030 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
1031 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
1032 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
1033 &adev->visible_pin_size);
1034 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1035 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
1040 * amdgpu_bo_evict_vram - evict VRAM buffers
1041 * @adev: amdgpu device object
1043 * Evicts all VRAM buffers on the lru list of the memory type.
1044 * Mainly used for evicting vram at suspend time.
1047 * 0 for success or a negative error code on failure.
1049 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
1051 struct ttm_resource_manager *man;
1053 if (adev->in_s3 && (adev->flags & AMD_IS_APU)) {
1054 /* No need to evict vram on APUs for suspend to ram */
1058 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1059 return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
1062 static const char *amdgpu_vram_names[] = {
1077 * amdgpu_bo_init - initialize memory manager
1078 * @adev: amdgpu device object
1080 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1083 * 0 for success or a negative error code on failure.
1085 int amdgpu_bo_init(struct amdgpu_device *adev)
1087 /* On A+A platform, VRAM can be mapped as WB */
1088 if (!adev->gmc.xgmi.connected_to_cpu) {
1089 /* reserve PAT memory space to WC for VRAM */
1090 arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1091 adev->gmc.aper_size);
1093 /* Add an MTRR for the VRAM */
1094 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1095 adev->gmc.aper_size);
1098 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1099 adev->gmc.mc_vram_size >> 20,
1100 (unsigned long long)adev->gmc.aper_size >> 20);
1101 DRM_INFO("RAM width %dbits %s\n",
1102 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1103 return amdgpu_ttm_init(adev);
1107 * amdgpu_bo_fini - tear down memory manager
1108 * @adev: amdgpu device object
1110 * Reverses amdgpu_bo_init() to tear down memory manager.
1112 void amdgpu_bo_fini(struct amdgpu_device *adev)
1114 amdgpu_ttm_fini(adev);
1118 * amdgpu_bo_set_tiling_flags - set tiling flags
1119 * @bo: &amdgpu_bo buffer object
1120 * @tiling_flags: new flags
1122 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1123 * kernel driver to set the tiling flags on a buffer.
1126 * 0 for success or a negative error code on failure.
1128 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1130 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1131 struct amdgpu_bo_user *ubo;
1133 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1134 if (adev->family <= AMDGPU_FAMILY_CZ &&
1135 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1138 ubo = to_amdgpu_bo_user(bo);
1139 ubo->tiling_flags = tiling_flags;
1144 * amdgpu_bo_get_tiling_flags - get tiling flags
1145 * @bo: &amdgpu_bo buffer object
1146 * @tiling_flags: returned flags
1148 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1149 * set the tiling flags on a buffer.
1151 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1153 struct amdgpu_bo_user *ubo;
1155 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1156 dma_resv_assert_held(bo->tbo.base.resv);
1157 ubo = to_amdgpu_bo_user(bo);
1160 *tiling_flags = ubo->tiling_flags;
1164 * amdgpu_bo_set_metadata - set metadata
1165 * @bo: &amdgpu_bo buffer object
1166 * @metadata: new metadata
1167 * @metadata_size: size of the new metadata
1168 * @flags: flags of the new metadata
1170 * Sets buffer object's metadata, its size and flags.
1171 * Used via GEM ioctl.
1174 * 0 for success or a negative error code on failure.
1176 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
1177 uint32_t metadata_size, uint64_t flags)
1179 struct amdgpu_bo_user *ubo;
1182 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1183 ubo = to_amdgpu_bo_user(bo);
1184 if (!metadata_size) {
1185 if (ubo->metadata_size) {
1186 kfree(ubo->metadata);
1187 ubo->metadata = NULL;
1188 ubo->metadata_size = 0;
1193 if (metadata == NULL)
1196 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1200 kfree(ubo->metadata);
1201 ubo->metadata_flags = flags;
1202 ubo->metadata = buffer;
1203 ubo->metadata_size = metadata_size;
1209 * amdgpu_bo_get_metadata - get metadata
1210 * @bo: &amdgpu_bo buffer object
1211 * @buffer: returned metadata
1212 * @buffer_size: size of the buffer
1213 * @metadata_size: size of the returned metadata
1214 * @flags: flags of the returned metadata
1216 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1217 * less than metadata_size.
1218 * Used via GEM ioctl.
1221 * 0 for success or a negative error code on failure.
1223 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1224 size_t buffer_size, uint32_t *metadata_size,
1227 struct amdgpu_bo_user *ubo;
1229 if (!buffer && !metadata_size)
1232 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1233 ubo = to_amdgpu_bo_user(bo);
1235 *metadata_size = ubo->metadata_size;
1238 if (buffer_size < ubo->metadata_size)
1241 if (ubo->metadata_size)
1242 memcpy(buffer, ubo->metadata, ubo->metadata_size);
1246 *flags = ubo->metadata_flags;
1252 * amdgpu_bo_move_notify - notification about a memory move
1253 * @bo: pointer to a buffer object
1254 * @evict: if this move is evicting the buffer from the graphics address space
1255 * @new_mem: new information of the bufer object
1257 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1259 * TTM driver callback which is called when ttm moves a buffer.
1261 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1263 struct ttm_resource *new_mem)
1265 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1266 struct amdgpu_bo *abo;
1267 struct ttm_resource *old_mem = bo->resource;
1269 if (!amdgpu_bo_is_amdgpu_bo(bo))
1272 abo = ttm_to_amdgpu_bo(bo);
1273 amdgpu_vm_bo_invalidate(adev, abo, evict);
1275 amdgpu_bo_kunmap(abo);
1277 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1278 bo->resource->mem_type != TTM_PL_SYSTEM)
1279 dma_buf_move_notify(abo->tbo.base.dma_buf);
1281 /* remember the eviction */
1283 atomic64_inc(&adev->num_evictions);
1285 /* update statistics */
1289 /* move_notify is called before move happens */
1290 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
1293 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
1294 uint64_t *gtt_mem, uint64_t *cpu_mem)
1296 unsigned int domain;
1298 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1300 case AMDGPU_GEM_DOMAIN_VRAM:
1301 *vram_mem += amdgpu_bo_size(bo);
1303 case AMDGPU_GEM_DOMAIN_GTT:
1304 *gtt_mem += amdgpu_bo_size(bo);
1306 case AMDGPU_GEM_DOMAIN_CPU:
1308 *cpu_mem += amdgpu_bo_size(bo);
1314 * amdgpu_bo_release_notify - notification about a BO being released
1315 * @bo: pointer to a buffer object
1317 * Wipes VRAM buffers whose contents should not be leaked before the
1318 * memory is released.
1320 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1322 struct dma_fence *fence = NULL;
1323 struct amdgpu_bo *abo;
1326 if (!amdgpu_bo_is_amdgpu_bo(bo))
1329 abo = ttm_to_amdgpu_bo(bo);
1332 amdgpu_amdkfd_unreserve_memory_limit(abo);
1334 /* We only remove the fence if the resv has individualized. */
1335 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1336 && bo->base.resv != &bo->base._resv);
1337 if (bo->base.resv == &bo->base._resv)
1338 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1340 if (bo->resource->mem_type != TTM_PL_VRAM ||
1341 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
1344 dma_resv_lock(bo->base.resv, NULL);
1346 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);
1348 amdgpu_bo_fence(abo, fence, false);
1349 dma_fence_put(fence);
1352 dma_resv_unlock(bo->base.resv);
1356 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1357 * @bo: pointer to a buffer object
1359 * Notifies the driver we are taking a fault on this BO and have reserved it,
1360 * also performs bookkeeping.
1361 * TTM driver callback for dealing with vm faults.
1364 * 0 for success or a negative error code on failure.
1366 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1368 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1369 struct ttm_operation_ctx ctx = { false, false };
1370 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1371 unsigned long offset;
1374 /* Remember that this BO was accessed by the CPU */
1375 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1377 if (bo->resource->mem_type != TTM_PL_VRAM)
1380 offset = bo->resource->start << PAGE_SHIFT;
1381 if ((offset + bo->base.size) <= adev->gmc.visible_vram_size)
1384 /* Can't move a pinned BO to visible VRAM */
1385 if (abo->tbo.pin_count > 0)
1386 return VM_FAULT_SIGBUS;
1388 /* hurrah the memory is not visible ! */
1389 atomic64_inc(&adev->num_vram_cpu_page_faults);
1390 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1391 AMDGPU_GEM_DOMAIN_GTT);
1393 /* Avoid costly evictions; only set GTT as a busy placement */
1394 abo->placement.num_busy_placement = 1;
1395 abo->placement.busy_placement = &abo->placements[1];
1397 r = ttm_bo_validate(bo, &abo->placement, &ctx);
1398 if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1399 return VM_FAULT_NOPAGE;
1400 else if (unlikely(r))
1401 return VM_FAULT_SIGBUS;
1403 offset = bo->resource->start << PAGE_SHIFT;
1404 /* this should never happen */
1405 if (bo->resource->mem_type == TTM_PL_VRAM &&
1406 (offset + bo->base.size) > adev->gmc.visible_vram_size)
1407 return VM_FAULT_SIGBUS;
1409 ttm_bo_move_to_lru_tail_unlocked(bo);
1414 * amdgpu_bo_fence - add fence to buffer object
1416 * @bo: buffer object in question
1417 * @fence: fence to add
1418 * @shared: true if fence should be added shared
1421 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1424 struct dma_resv *resv = bo->tbo.base.resv;
1427 dma_resv_add_shared_fence(resv, fence);
1429 dma_resv_add_excl_fence(resv, fence);
1433 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1435 * @adev: amdgpu device pointer
1436 * @resv: reservation object to sync to
1437 * @sync_mode: synchronization mode
1438 * @owner: fence owner
1439 * @intr: Whether the wait is interruptible
1441 * Extract the fences from the reservation object and waits for them to finish.
1444 * 0 on success, errno otherwise.
1446 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1447 enum amdgpu_sync_mode sync_mode, void *owner,
1450 struct amdgpu_sync sync;
1453 amdgpu_sync_create(&sync);
1454 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1455 r = amdgpu_sync_wait(&sync, intr);
1456 amdgpu_sync_free(&sync);
1461 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1462 * @bo: buffer object to wait for
1463 * @owner: fence owner
1464 * @intr: Whether the wait is interruptible
1466 * Wrapper to wait for fences in a BO.
1468 * 0 on success, errno otherwise.
1470 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1472 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1474 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1475 AMDGPU_SYNC_NE_OWNER, owner, intr);
1479 * amdgpu_bo_gpu_offset - return GPU offset of bo
1480 * @bo: amdgpu object for which we query the offset
1482 * Note: object should either be pinned or reserved when calling this
1483 * function, it might be useful to add check for this for debugging.
1486 * current GPU offset of the object.
1488 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1490 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
1491 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1492 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1493 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
1494 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
1495 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1497 return amdgpu_bo_gpu_offset_no_check(bo);
1501 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1502 * @bo: amdgpu object for which we query the offset
1505 * current GPU offset of the object without raising warnings.
1507 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1509 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1512 offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1513 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1515 return amdgpu_gmc_sign_extend(offset);
1519 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout
1520 * @adev: amdgpu device object
1521 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1524 * Which of the allowed domains is preferred for pinning the BO for scanout.
1526 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
1529 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
1530 domain = AMDGPU_GEM_DOMAIN_VRAM;
1531 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1532 domain = AMDGPU_GEM_DOMAIN_GTT;
1537 #if defined(CONFIG_DEBUG_FS)
1538 #define amdgpu_bo_print_flag(m, bo, flag) \
1540 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
1541 seq_printf((m), " " #flag); \
1546 * amdgpu_bo_print_info - print BO info in debugfs file
1548 * @id: Index or Id of the BO
1549 * @bo: Requested BO for printing info
1552 * Print BO information in debugfs file
1555 * Size of the BO in bytes.
1557 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1559 struct dma_buf_attachment *attachment;
1560 struct dma_buf *dma_buf;
1561 unsigned int domain;
1562 const char *placement;
1563 unsigned int pin_count;
1566 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1568 case AMDGPU_GEM_DOMAIN_VRAM:
1571 case AMDGPU_GEM_DOMAIN_GTT:
1574 case AMDGPU_GEM_DOMAIN_CPU:
1580 size = amdgpu_bo_size(bo);
1581 seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1582 id, size, placement);
1584 pin_count = READ_ONCE(bo->tbo.pin_count);
1586 seq_printf(m, " pin count %d", pin_count);
1588 dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1589 attachment = READ_ONCE(bo->tbo.base.import_attach);
1592 seq_printf(m, " imported from %p", dma_buf);
1594 seq_printf(m, " exported as %p", dma_buf);
1596 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1597 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1598 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1599 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1600 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1601 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1602 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);