2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __AMDGPU_NBIO_H__
24 #define __AMDGPU_NBIO_H__
27 * amdgpu nbio functions
29 struct nbio_hdp_flush_reg {
40 u32 ref_and_mask_sdma0;
41 u32 ref_and_mask_sdma1;
42 u32 ref_and_mask_sdma2;
43 u32 ref_and_mask_sdma3;
44 u32 ref_and_mask_sdma4;
45 u32 ref_and_mask_sdma5;
46 u32 ref_and_mask_sdma6;
47 u32 ref_and_mask_sdma7;
50 struct amdgpu_nbio_ras_funcs {
51 void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
52 void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
53 int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
54 int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
55 void (*query_ras_error_count)(struct amdgpu_device *adev,
56 void *ras_error_status);
57 int (*ras_late_init)(struct amdgpu_device *adev);
58 void (*ras_fini)(struct amdgpu_device *adev);
61 struct amdgpu_nbio_funcs {
62 const struct nbio_hdp_flush_reg *hdp_flush_reg;
63 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
64 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
65 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
66 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
67 u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
68 u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
69 u32 (*get_rev_id)(struct amdgpu_device *adev);
70 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
71 u32 (*get_memsize)(struct amdgpu_device *adev);
72 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
73 bool use_doorbell, int doorbell_index, int doorbell_size);
74 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
75 int doorbell_index, int instance);
76 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
78 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
80 void (*ih_doorbell_range)(struct amdgpu_device *adev,
81 bool use_doorbell, int doorbell_index);
82 void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
84 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
86 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
88 void (*get_clockgating_state)(struct amdgpu_device *adev,
90 void (*ih_control)(struct amdgpu_device *adev);
91 void (*init_registers)(struct amdgpu_device *adev);
92 void (*remap_hdp_registers)(struct amdgpu_device *adev);
93 void (*enable_aspm)(struct amdgpu_device *adev,
95 void (*program_aspm)(struct amdgpu_device *adev);
99 const struct nbio_hdp_flush_reg *hdp_flush_reg;
100 struct amdgpu_irq_src ras_controller_irq;
101 struct amdgpu_irq_src ras_err_event_athub_irq;
102 struct ras_common_if *ras_if;
103 const struct amdgpu_nbio_funcs *funcs;
104 const struct amdgpu_nbio_ras_funcs *ras_funcs;
107 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);
108 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);