2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/display/drm_dp_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_framebuffer.h>
38 #include <drm/drm_probe_helper.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <linux/hrtimer.h>
42 #include "amdgpu_irq.h"
44 #include <drm/display/drm_dp_mst_helper.h>
45 #include "modules/inc/mod_freesync.h"
46 #include "amdgpu_dm_irq_params.h"
50 struct amdgpu_encoder;
55 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
56 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
57 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
58 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
60 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base)
62 #define AMDGPU_MAX_HPD_PINS 6
63 #define AMDGPU_MAX_CRTCS 6
64 #define AMDGPU_MAX_PLANES 6
65 #define AMDGPU_MAX_AFMT_BLOCKS 9
67 enum amdgpu_rmx_type {
74 enum amdgpu_underscan_type {
80 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
81 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
90 AMDGPU_HPD_NONE = 0xff,
93 enum amdgpu_crtc_irq {
94 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
95 AMDGPU_CRTC_IRQ_VBLANK2,
96 AMDGPU_CRTC_IRQ_VBLANK3,
97 AMDGPU_CRTC_IRQ_VBLANK4,
98 AMDGPU_CRTC_IRQ_VBLANK5,
99 AMDGPU_CRTC_IRQ_VBLANK6,
100 AMDGPU_CRTC_IRQ_VLINE1,
101 AMDGPU_CRTC_IRQ_VLINE2,
102 AMDGPU_CRTC_IRQ_VLINE3,
103 AMDGPU_CRTC_IRQ_VLINE4,
104 AMDGPU_CRTC_IRQ_VLINE5,
105 AMDGPU_CRTC_IRQ_VLINE6,
106 AMDGPU_CRTC_IRQ_NONE = 0xff
109 enum amdgpu_pageflip_irq {
110 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
111 AMDGPU_PAGEFLIP_IRQ_D2,
112 AMDGPU_PAGEFLIP_IRQ_D3,
113 AMDGPU_PAGEFLIP_IRQ_D4,
114 AMDGPU_PAGEFLIP_IRQ_D5,
115 AMDGPU_PAGEFLIP_IRQ_D6,
116 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
119 enum amdgpu_flip_status {
122 AMDGPU_FLIP_SUBMITTED
125 #define AMDGPU_MAX_I2C_BUS 16
127 /* amdgpu gpio-based i2c
128 * 1. "mask" reg and bits
129 * grabs the gpio pins for software use
131 * 2. "a" reg and bits
134 * 3. "en" reg and bits
135 * sets the pin direction
137 * 4. "y" reg and bits
141 struct amdgpu_i2c_bus_rec {
143 /* id used by atom */
145 /* id used by atom */
146 enum amdgpu_hpd_id hpd;
147 /* can be used with hw i2c engine */
149 /* uses multi-media i2c engine */
152 uint32_t mask_clk_reg;
153 uint32_t mask_data_reg;
157 uint32_t en_data_reg;
160 uint32_t mask_clk_mask;
161 uint32_t mask_data_mask;
163 uint32_t a_data_mask;
164 uint32_t en_clk_mask;
165 uint32_t en_data_mask;
167 uint32_t y_data_mask;
170 #define AMDGPU_MAX_BIOS_CONNECTOR 16
173 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
174 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
175 #define AMDGPU_PLL_USE_REF_DIV (1 << 2)
176 #define AMDGPU_PLL_LEGACY (1 << 3)
177 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
178 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
179 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
180 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
181 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
182 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
183 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
184 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
185 #define AMDGPU_PLL_USE_POST_DIV (1 << 12)
186 #define AMDGPU_PLL_IS_LCD (1 << 13)
187 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
190 /* reference frequency */
191 uint32_t reference_freq;
194 uint32_t reference_div;
197 /* pll in/out limits */
200 uint32_t pll_out_min;
201 uint32_t pll_out_max;
202 uint32_t lcd_pll_out_min;
203 uint32_t lcd_pll_out_max;
207 uint32_t min_ref_div;
208 uint32_t max_ref_div;
209 uint32_t min_post_div;
210 uint32_t max_post_div;
211 uint32_t min_feedback_div;
212 uint32_t max_feedback_div;
213 uint32_t min_frac_feedback_div;
214 uint32_t max_frac_feedback_div;
216 /* flags for the current clock */
223 struct amdgpu_i2c_chan {
224 struct i2c_adapter adapter;
225 struct drm_device *dev;
226 struct i2c_algo_bit_data bit;
227 struct amdgpu_i2c_bus_rec rec;
228 struct drm_dp_aux aux;
236 bool last_buffer_filled_status;
238 struct amdgpu_audio_pin *pin;
244 struct amdgpu_audio_pin {
255 struct amdgpu_audio {
257 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
261 struct amdgpu_display_funcs {
262 /* display watermarks */
263 void (*bandwidth_update)(struct amdgpu_device *adev);
264 /* get frame count */
265 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
266 /* set backlight level */
267 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
269 /* get backlight level */
270 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
272 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
273 void (*hpd_set_polarity)(struct amdgpu_device *adev,
274 enum amdgpu_hpd_id hpd);
275 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
277 void (*page_flip)(struct amdgpu_device *adev,
278 int crtc_id, u64 crtc_base, bool async);
279 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
280 u32 *vbl, u32 *position);
281 /* display topology setup */
282 void (*add_encoder)(struct amdgpu_device *adev,
283 uint32_t encoder_enum,
284 uint32_t supported_device,
286 void (*add_connector)(struct amdgpu_device *adev,
287 uint32_t connector_id,
288 uint32_t supported_device,
290 struct amdgpu_i2c_bus_rec *i2c_bus,
291 uint16_t connector_object_id,
292 struct amdgpu_hpd *hpd,
293 struct amdgpu_router *router);
298 struct amdgpu_framebuffer {
299 struct drm_framebuffer base;
301 uint64_t tiling_flags;
304 /* caching for later use */
308 struct amdgpu_mode_info {
309 struct atom_context *atom_context;
310 struct card_info *atom_card_info;
311 bool mode_config_initialized;
312 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
313 struct drm_plane *planes[AMDGPU_MAX_PLANES];
314 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
315 /* DVI-I properties */
316 struct drm_property *coherent_mode_property;
317 /* DAC enable load detect */
318 struct drm_property *load_detect_property;
320 struct drm_property *underscan_property;
321 struct drm_property *underscan_hborder_property;
322 struct drm_property *underscan_vborder_property;
324 struct drm_property *audio_property;
326 struct drm_property *dither_property;
327 /* Adaptive Backlight Modulation (power feature) */
328 struct drm_property *abm_level_property;
329 /* hardcoded DFP edid from BIOS */
330 struct edid *bios_hardcoded_edid;
331 int bios_hardcoded_edid_size;
335 /* pointer to backlight encoder */
336 struct amdgpu_encoder *bl_encoder;
337 u8 bl_level; /* saved backlight level */
338 struct amdgpu_audio audio; /* audio stuff */
339 int num_crtc; /* number of crtcs */
340 int num_hpd; /* number of hpd pins */
341 int num_dig; /* number of dig blocks */
342 bool gpu_vm_support; /* supports display from GTT */
344 const struct amdgpu_display_funcs *funcs;
345 const enum drm_plane_type *plane_type;
347 /* Driver-private color mgmt props */
349 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to
350 * convert encoded values to light linear values before sampling or
353 struct drm_property *plane_degamma_lut_property;
354 /* @plane_degamma_lut_size_property: Plane property to define the max
355 * size of degamma LUT as supported by the driver (read-only).
357 struct drm_property *plane_degamma_lut_size_property;
359 * @plane_degamma_tf_property: Plane pre-defined transfer function to
360 * to go from scanout/encoded values to linear values.
362 struct drm_property *plane_degamma_tf_property;
364 * @plane_hdr_mult_property:
366 struct drm_property *plane_hdr_mult_property;
368 struct drm_property *plane_ctm_property;
370 * @shaper_lut_property: Plane property to set pre-blending shaper LUT
371 * that converts color content before 3D LUT. If
372 * plane_shaper_tf_property != Identity TF, AMD color module will
373 * combine the user LUT values with pre-defined TF into the LUT
374 * parameters to be programmed.
376 struct drm_property *plane_shaper_lut_property;
378 * @shaper_lut_size_property: Plane property for the size of
379 * pre-blending shaper LUT as supported by the driver (read-only).
381 struct drm_property *plane_shaper_lut_size_property;
383 * @plane_shaper_tf_property: Plane property to set a predefined
384 * transfer function for pre-blending shaper (before applying 3D LUT)
385 * with or without LUT. There is no shaper ROM, but we can use AMD
386 * color modules to program LUT parameters from predefined TF (or
387 * from a combination of pre-defined TF and the custom 1D LUT).
389 struct drm_property *plane_shaper_tf_property;
391 * @plane_lut3d_property: Plane property for color transformation using
392 * a 3D LUT (pre-blending), a three-dimensional array where each
393 * element is an RGB triplet. Each dimension has the size of
394 * lut3d_size. The array contains samples from the approximated
395 * function. On AMD, values between samples are estimated by
396 * tetrahedral interpolation. The array is accessed with three indices,
397 * one for each input dimension (color channel), blue being the
398 * outermost dimension, red the innermost.
400 struct drm_property *plane_lut3d_property;
402 * @plane_degamma_lut_size_property: Plane property to define the max
403 * size of 3D LUT as supported by the driver (read-only). The max size
404 * is the max size of one dimension and, therefore, the max number of
405 * entries for 3D LUT array is the 3D LUT size cubed;
407 struct drm_property *plane_lut3d_size_property;
409 * @plane_blend_lut_property: Plane property for output gamma before
410 * blending. Userspace set a blend LUT to convert colors after 3D LUT
411 * conversion. It works as a post-3DLUT 1D LUT. With shaper LUT, they
412 * are sandwiching 3D LUT with two 1D LUT. If plane_blend_tf_property
413 * != Identity TF, AMD color module will combine the user LUT values
414 * with pre-defined TF into the LUT parameters to be programmed.
416 struct drm_property *plane_blend_lut_property;
418 * @plane_blend_lut_size_property: Plane property to define the max
419 * size of blend LUT as supported by the driver (read-only).
421 struct drm_property *plane_blend_lut_size_property;
423 * @plane_blend_tf_property: Plane property to set a predefined
424 * transfer function for pre-blending blend/out_gamma (after applying
425 * 3D LUT) with or without LUT. There is no blend ROM, but we can use
426 * AMD color modules to program LUT parameters from predefined TF (or
427 * from a combination of pre-defined TF and the custom 1D LUT).
429 struct drm_property *plane_blend_tf_property;
430 /* @regamma_tf_property: Transfer function for CRTC regamma
431 * (post-blending). Possible values are defined by `enum
432 * amdgpu_transfer_function`. There is no regamma ROM, but we can use
433 * AMD color modules to program LUT parameters from predefined TF (or
434 * from a combination of pre-defined TF and the custom 1D LUT).
436 struct drm_property *regamma_tf_property;
439 #define AMDGPU_MAX_BL_LEVEL 0xFF
441 struct amdgpu_backlight_privdata {
442 struct amdgpu_encoder *encoder;
446 struct amdgpu_atom_ss {
448 uint16_t percentage_divider;
460 struct drm_crtc base;
464 uint32_t crtc_offset;
465 struct drm_gem_object *cursor_bo;
466 uint64_t cursor_addr;
473 int max_cursor_width;
474 int max_cursor_height;
475 enum amdgpu_rmx_type rmx_type;
480 struct drm_display_mode native_mode;
483 struct amdgpu_flip_work *pflip_works;
484 enum amdgpu_flip_status pflip_status;
485 int deferred_flip_completion;
486 /* parameters access from DM IRQ handler */
487 struct dm_irq_params dm_irq_params;
489 struct amdgpu_atom_ss ss;
493 u32 pll_reference_div;
496 struct drm_encoder *encoder;
497 struct drm_connector *connector;
502 u32 lb_vblank_lead_lines;
503 struct drm_display_mode hw_mode;
504 /* for virtual dce */
505 struct hrtimer vblank_timer;
506 enum amdgpu_interrupt_state vsync_timer_enabled;
509 struct drm_pending_vblank_event *event;
513 struct drm_writeback_connector *wb_conn;
516 struct amdgpu_encoder_atom_dig {
520 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
523 uint16_t panel_pwr_delay;
526 struct drm_display_mode native_mode;
527 struct backlight_device *bl_dev;
529 uint8_t backlight_level;
531 struct amdgpu_afmt *afmt;
534 struct amdgpu_encoder {
535 struct drm_encoder base;
536 uint32_t encoder_enum;
539 uint32_t active_device;
541 uint32_t pixel_clock;
542 enum amdgpu_rmx_type rmx_type;
543 enum amdgpu_underscan_type underscan_type;
544 uint32_t underscan_hborder;
545 uint32_t underscan_vborder;
546 struct drm_display_mode native_mode;
548 int audio_polling_active;
553 struct amdgpu_connector_atom_dig {
555 u8 dpcd[DP_RECEIVER_CAP_SIZE];
556 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
563 struct amdgpu_gpio_rec {
572 enum amdgpu_hpd_id hpd;
574 struct amdgpu_gpio_rec gpio;
577 struct amdgpu_router {
579 struct amdgpu_i2c_bus_rec i2c_info;
584 u8 ddc_mux_control_pin;
589 u8 cd_mux_control_pin;
593 enum amdgpu_connector_audio {
594 AMDGPU_AUDIO_DISABLE = 0,
595 AMDGPU_AUDIO_ENABLE = 1,
596 AMDGPU_AUDIO_AUTO = 2
599 enum amdgpu_connector_dither {
600 AMDGPU_FMT_DITHER_DISABLE = 0,
601 AMDGPU_FMT_DITHER_ENABLE = 1,
604 struct amdgpu_dm_dp_aux {
605 struct drm_dp_aux aux;
606 struct ddc_service *ddc_service;
609 struct amdgpu_i2c_adapter {
610 struct i2c_adapter base;
612 struct ddc_service *ddc_service;
615 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
617 struct amdgpu_connector {
618 struct drm_connector base;
619 uint32_t connector_id;
621 struct amdgpu_i2c_chan *ddc_bus;
622 /* some systems have an hdmi and vga port with a shared ddc line */
625 /* we need to mind the EDID between detect
626 and get modes due to analog/digital/tvencoder */
629 bool dac_load_detect;
630 bool detected_by_load; /* if the connection status was determined by load */
631 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
632 uint16_t connector_object_id;
633 struct amdgpu_hpd hpd;
634 struct amdgpu_router router;
635 struct amdgpu_i2c_chan *router_bus;
636 enum amdgpu_connector_audio audio;
637 enum amdgpu_connector_dither dither;
638 unsigned pixelclock_for_modeset;
641 /* TODO: start to use this struct and remove same field from base one */
642 struct amdgpu_mst_connector {
643 struct amdgpu_connector base;
645 struct drm_dp_mst_topology_mgr mst_mgr;
646 struct amdgpu_dm_dp_aux dm_dp_aux;
647 struct drm_dp_mst_port *mst_output_port;
648 struct amdgpu_connector *mst_root;
649 bool is_mst_connector;
650 struct amdgpu_encoder *mst_encoder;
653 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
654 ((em) == ATOM_ENCODER_MODE_DP_MST))
656 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
657 #define DRM_SCANOUTPOS_VALID (1 << 0)
658 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
659 #define DRM_SCANOUTPOS_ACCURATE (1 << 2)
660 #define USE_REAL_VBLANKSTART (1 << 30)
661 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
663 void amdgpu_link_encoder_connector(struct drm_device *dev);
665 struct drm_connector *
666 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
667 struct drm_connector *
668 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
669 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
672 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
673 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
675 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
678 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
680 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
681 unsigned int pipe, unsigned int flags, int *vpos,
682 int *hpos, ktime_t *stime, ktime_t *etime,
683 const struct drm_display_mode *mode);
685 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
687 void amdgpu_enc_destroy(struct drm_encoder *encoder);
688 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
689 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
690 const struct drm_display_mode *mode,
691 struct drm_display_mode *adjusted_mode);
692 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
693 struct drm_display_mode *adjusted_mode);
694 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
696 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
697 bool in_vblank_irq, int *vpos,
698 int *hpos, ktime_t *stime, ktime_t *etime,
699 const struct drm_display_mode *mode);
701 /* amdgpu_display.c */
702 void amdgpu_display_print_display_setup(struct drm_device *dev);
703 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
704 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
705 struct drm_modeset_acquire_ctx *ctx);
706 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
707 struct drm_framebuffer *fb,
708 struct drm_pending_vblank_event *event,
709 uint32_t page_flip_flags, uint32_t target,
710 struct drm_modeset_acquire_ctx *ctx);
711 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;