2 * Copyright (C) 2021 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef __AMDGPU_MCA_H__
22 #define __AMDGPU_MCA_H__
24 #include "amdgpu_ras.h"
26 #define MCA_MAX_REGS_COUNT (16)
28 #define MCA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)
29 #define MCA_REG__STATUS__VAL(x) MCA_REG_FIELD(x, 63, 63)
30 #define MCA_REG__STATUS__OVERFLOW(x) MCA_REG_FIELD(x, 62, 62)
31 #define MCA_REG__STATUS__UC(x) MCA_REG_FIELD(x, 61, 61)
32 #define MCA_REG__STATUS__EN(x) MCA_REG_FIELD(x, 60, 60)
33 #define MCA_REG__STATUS__MISCV(x) MCA_REG_FIELD(x, 59, 59)
34 #define MCA_REG__STATUS__ADDRV(x) MCA_REG_FIELD(x, 58, 58)
35 #define MCA_REG__STATUS__PCC(x) MCA_REG_FIELD(x, 57, 57)
36 #define MCA_REG__STATUS__ERRCOREIDVAL(x) MCA_REG_FIELD(x, 56, 56)
37 #define MCA_REG__STATUS__TCC(x) MCA_REG_FIELD(x, 55, 55)
38 #define MCA_REG__STATUS__SYNDV(x) MCA_REG_FIELD(x, 53, 53)
39 #define MCA_REG__STATUS__CECC(x) MCA_REG_FIELD(x, 46, 46)
40 #define MCA_REG__STATUS__UECC(x) MCA_REG_FIELD(x, 45, 45)
41 #define MCA_REG__STATUS__DEFERRED(x) MCA_REG_FIELD(x, 44, 44)
42 #define MCA_REG__STATUS__POISON(x) MCA_REG_FIELD(x, 43, 43)
43 #define MCA_REG__STATUS__SCRUB(x) MCA_REG_FIELD(x, 40, 40)
44 #define MCA_REG__STATUS__ERRCOREID(x) MCA_REG_FIELD(x, 37, 32)
45 #define MCA_REG__STATUS__ADDRLSB(x) MCA_REG_FIELD(x, 29, 24)
46 #define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16)
47 #define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0)
49 #define MCA_REG__SYND__ERRORINFORMATION(x) MCA_REG_FIELD(x, 17, 0)
52 AMDGPU_MCA_IP_UNKNOW = -1,
53 AMDGPU_MCA_IP_PSP = 0,
59 AMDGPU_MCA_IP_PCS_XGMI,
63 enum amdgpu_mca_error_type {
64 AMDGPU_MCA_ERROR_TYPE_UE = 0,
65 AMDGPU_MCA_ERROR_TYPE_CE,
68 struct amdgpu_mca_ras_block {
69 struct amdgpu_ras_block_object ras_block;
72 struct amdgpu_mca_ras {
73 struct ras_common_if *ras_if;
74 struct amdgpu_mca_ras_block *ras;
78 struct amdgpu_mca_ras mp0;
79 struct amdgpu_mca_ras mp1;
80 struct amdgpu_mca_ras mpio;
81 const struct amdgpu_mca_smu_funcs *mca_funcs;
85 MCA_REG_IDX_STATUS = 1,
87 MCA_REG_IDX_MISC0 = 3,
90 MCA_REG_IDX_COUNT = 16,
93 struct mca_bank_info {
100 struct mca_bank_entry {
102 enum amdgpu_mca_error_type type;
103 enum amdgpu_mca_ip ip;
104 struct mca_bank_info info;
105 uint64_t regs[MCA_MAX_REGS_COUNT];
108 struct mca_bank_node {
109 struct mca_bank_entry entry;
110 struct list_head node;
113 struct mca_bank_set {
115 struct list_head list;
118 struct amdgpu_mca_smu_funcs {
121 int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable);
122 int (*mca_get_ras_mca_set)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
123 struct mca_bank_set *mca_set);
124 int (*mca_parse_mca_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
125 struct mca_bank_entry *entry, uint32_t *count);
126 int (*mca_get_valid_mca_count)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
128 int (*mca_get_mca_entry)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
129 int idx, struct mca_bank_entry *entry);
132 void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
133 uint64_t mc_status_addr,
134 unsigned long *error_count);
136 void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
137 uint64_t mc_status_addr,
138 unsigned long *error_count);
140 void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
141 uint64_t mc_status_addr);
143 void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
144 uint64_t mc_status_addr,
145 void *ras_error_status);
146 int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev);
147 int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);
148 int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev);
150 void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs);
151 int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable);
152 int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count);
153 int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
154 enum amdgpu_mca_error_type type, uint32_t *total);
155 int amdgpu_mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
156 enum amdgpu_mca_error_type type, uint32_t *count);
157 int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
158 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
159 int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
160 enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set);
161 int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
162 int idx, struct mca_bank_entry *entry);
164 void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);
166 void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set);
167 int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry);
168 void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set);
169 int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data);