2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/drm_debugfs.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_uvd.h"
33 #include "amdgpu_vce.h"
36 #include <linux/vga_switcheroo.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pci.h>
40 #include <linux/pm_runtime.h>
41 #include "amdgpu_amdkfd.h"
42 #include "amdgpu_gem.h"
43 #include "amdgpu_display.h"
44 #include "amdgpu_ras.h"
46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
48 struct amdgpu_gpu_instance *gpu_instance;
51 mutex_lock(&mgpu_info.mutex);
53 for (i = 0; i < mgpu_info.num_gpu; i++) {
54 gpu_instance = &(mgpu_info.gpu_ins[i]);
55 if (gpu_instance->adev == adev) {
56 mgpu_info.gpu_ins[i] =
57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
59 if (adev->flags & AMD_IS_APU)
67 mutex_unlock(&mgpu_info.mutex);
71 * amdgpu_driver_unload_kms - Main unload function for KMS.
73 * @dev: drm dev pointer
75 * This is the main unload function for KMS (all asics).
76 * Returns 0 on success.
78 void amdgpu_driver_unload_kms(struct drm_device *dev)
80 struct amdgpu_device *adev = drm_to_adev(dev);
85 amdgpu_unregister_gpu_instance(adev);
87 if (adev->rmmio == NULL)
91 pm_runtime_get_sync(dev->dev);
92 pm_runtime_forbid(dev->dev);
95 amdgpu_acpi_fini(adev);
96 amdgpu_device_fini(adev);
99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
101 struct amdgpu_gpu_instance *gpu_instance;
103 mutex_lock(&mgpu_info.mutex);
105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
106 DRM_ERROR("Cannot register more gpu instance\n");
107 mutex_unlock(&mgpu_info.mutex);
111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
112 gpu_instance->adev = adev;
113 gpu_instance->mgpu_fan_enabled = 0;
116 if (adev->flags & AMD_IS_APU)
119 mgpu_info.num_dgpu++;
121 mutex_unlock(&mgpu_info.mutex);
125 * amdgpu_driver_load_kms - Main load function for KMS.
127 * @adev: pointer to struct amdgpu_device
128 * @flags: device flags
130 * This is the main load function for KMS (all asics).
131 * Returns 0 on success, error on failure.
133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
135 struct drm_device *dev;
138 dev = adev_to_drm(adev);
140 if (amdgpu_has_atpx() &&
141 (amdgpu_is_atpx_hybrid() ||
142 amdgpu_has_atpx_dgpu_power_cntl()) &&
143 ((flags & AMD_IS_APU) == 0) &&
144 !pci_is_thunderbolt_attached(dev->pdev))
147 /* amdgpu_device_init should report only fatal error
148 * like memory allocation failure or iomapping failure,
149 * or memory manager initialization failure, it must
150 * properly initialize the GPU MC controller and permit
153 r = amdgpu_device_init(adev, flags);
155 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
159 if (amdgpu_device_supports_boco(dev) &&
160 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
162 } else if (amdgpu_device_supports_baco(dev) &&
163 (amdgpu_runtime_pm != 0)) {
164 switch (adev->asic_type) {
167 case CHIP_SIENNA_CICHLID:
168 case CHIP_NAVY_FLOUNDER:
169 /* enable runpm if runpm=1 */
170 if (amdgpu_runtime_pm > 0)
174 /* turn runpm on if noretry=0 */
175 if (!adev->gmc.noretry)
179 /* enable runpm on CI+ */
185 /* Call ACPI methods: require modeset init
186 * but failure is not fatal
189 acpi_status = amdgpu_acpi_init(adev);
191 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
194 /* only need to skip on ATPX */
195 if (amdgpu_device_supports_boco(dev) &&
196 !amdgpu_is_atpx_hybrid())
197 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
198 pm_runtime_use_autosuspend(dev->dev);
199 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
200 pm_runtime_allow(dev->dev);
201 pm_runtime_mark_last_busy(dev->dev);
202 pm_runtime_put_autosuspend(dev->dev);
207 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
208 if (adev->rmmio && adev->runpm)
209 pm_runtime_put_noidle(dev->dev);
210 amdgpu_driver_unload_kms(dev);
216 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
217 struct drm_amdgpu_query_fw *query_fw,
218 struct amdgpu_device *adev)
220 switch (query_fw->fw_type) {
221 case AMDGPU_INFO_FW_VCE:
222 fw_info->ver = adev->vce.fw_version;
223 fw_info->feature = adev->vce.fb_version;
225 case AMDGPU_INFO_FW_UVD:
226 fw_info->ver = adev->uvd.fw_version;
227 fw_info->feature = 0;
229 case AMDGPU_INFO_FW_VCN:
230 fw_info->ver = adev->vcn.fw_version;
231 fw_info->feature = 0;
233 case AMDGPU_INFO_FW_GMC:
234 fw_info->ver = adev->gmc.fw_version;
235 fw_info->feature = 0;
237 case AMDGPU_INFO_FW_GFX_ME:
238 fw_info->ver = adev->gfx.me_fw_version;
239 fw_info->feature = adev->gfx.me_feature_version;
241 case AMDGPU_INFO_FW_GFX_PFP:
242 fw_info->ver = adev->gfx.pfp_fw_version;
243 fw_info->feature = adev->gfx.pfp_feature_version;
245 case AMDGPU_INFO_FW_GFX_CE:
246 fw_info->ver = adev->gfx.ce_fw_version;
247 fw_info->feature = adev->gfx.ce_feature_version;
249 case AMDGPU_INFO_FW_GFX_RLC:
250 fw_info->ver = adev->gfx.rlc_fw_version;
251 fw_info->feature = adev->gfx.rlc_feature_version;
253 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
254 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
255 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
258 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
259 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
261 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
262 fw_info->ver = adev->gfx.rlc_srls_fw_version;
263 fw_info->feature = adev->gfx.rlc_srls_feature_version;
265 case AMDGPU_INFO_FW_GFX_MEC:
266 if (query_fw->index == 0) {
267 fw_info->ver = adev->gfx.mec_fw_version;
268 fw_info->feature = adev->gfx.mec_feature_version;
269 } else if (query_fw->index == 1) {
270 fw_info->ver = adev->gfx.mec2_fw_version;
271 fw_info->feature = adev->gfx.mec2_feature_version;
275 case AMDGPU_INFO_FW_SMC:
276 fw_info->ver = adev->pm.fw_version;
277 fw_info->feature = 0;
279 case AMDGPU_INFO_FW_TA:
280 switch (query_fw->index) {
282 fw_info->ver = adev->psp.ta_fw_version;
283 fw_info->feature = adev->psp.ta_xgmi_ucode_version;
286 fw_info->ver = adev->psp.ta_fw_version;
287 fw_info->feature = adev->psp.ta_ras_ucode_version;
290 fw_info->ver = adev->psp.ta_fw_version;
291 fw_info->feature = adev->psp.ta_hdcp_ucode_version;
294 fw_info->ver = adev->psp.ta_fw_version;
295 fw_info->feature = adev->psp.ta_dtm_ucode_version;
301 case AMDGPU_INFO_FW_SDMA:
302 if (query_fw->index >= adev->sdma.num_instances)
304 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
305 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
307 case AMDGPU_INFO_FW_SOS:
308 fw_info->ver = adev->psp.sos_fw_version;
309 fw_info->feature = adev->psp.sos_feature_version;
311 case AMDGPU_INFO_FW_ASD:
312 fw_info->ver = adev->psp.asd_fw_version;
313 fw_info->feature = adev->psp.asd_feature_version;
315 case AMDGPU_INFO_FW_DMCU:
316 fw_info->ver = adev->dm.dmcu_fw_version;
317 fw_info->feature = 0;
319 case AMDGPU_INFO_FW_DMCUB:
320 fw_info->ver = adev->dm.dmcub_fw_version;
321 fw_info->feature = 0;
323 case AMDGPU_INFO_FW_TOC:
324 fw_info->ver = adev->psp.toc_fw_version;
325 fw_info->feature = adev->psp.toc_feature_version;
333 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
334 struct drm_amdgpu_info *info,
335 struct drm_amdgpu_info_hw_ip *result)
337 uint32_t ib_start_alignment = 0;
338 uint32_t ib_size_alignment = 0;
339 enum amd_ip_block_type type;
340 unsigned int num_rings = 0;
343 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
346 switch (info->query_hw_ip.type) {
347 case AMDGPU_HW_IP_GFX:
348 type = AMD_IP_BLOCK_TYPE_GFX;
349 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
350 if (adev->gfx.gfx_ring[i].sched.ready)
352 ib_start_alignment = 32;
353 ib_size_alignment = 32;
355 case AMDGPU_HW_IP_COMPUTE:
356 type = AMD_IP_BLOCK_TYPE_GFX;
357 for (i = 0; i < adev->gfx.num_compute_rings; i++)
358 if (adev->gfx.compute_ring[i].sched.ready)
360 ib_start_alignment = 32;
361 ib_size_alignment = 32;
363 case AMDGPU_HW_IP_DMA:
364 type = AMD_IP_BLOCK_TYPE_SDMA;
365 for (i = 0; i < adev->sdma.num_instances; i++)
366 if (adev->sdma.instance[i].ring.sched.ready)
368 ib_start_alignment = 256;
369 ib_size_alignment = 4;
371 case AMDGPU_HW_IP_UVD:
372 type = AMD_IP_BLOCK_TYPE_UVD;
373 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
374 if (adev->uvd.harvest_config & (1 << i))
377 if (adev->uvd.inst[i].ring.sched.ready)
380 ib_start_alignment = 64;
381 ib_size_alignment = 64;
383 case AMDGPU_HW_IP_VCE:
384 type = AMD_IP_BLOCK_TYPE_VCE;
385 for (i = 0; i < adev->vce.num_rings; i++)
386 if (adev->vce.ring[i].sched.ready)
388 ib_start_alignment = 4;
389 ib_size_alignment = 1;
391 case AMDGPU_HW_IP_UVD_ENC:
392 type = AMD_IP_BLOCK_TYPE_UVD;
393 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
394 if (adev->uvd.harvest_config & (1 << i))
397 for (j = 0; j < adev->uvd.num_enc_rings; j++)
398 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
401 ib_start_alignment = 64;
402 ib_size_alignment = 64;
404 case AMDGPU_HW_IP_VCN_DEC:
405 type = AMD_IP_BLOCK_TYPE_VCN;
406 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
407 if (adev->uvd.harvest_config & (1 << i))
410 if (adev->vcn.inst[i].ring_dec.sched.ready)
413 ib_start_alignment = 16;
414 ib_size_alignment = 16;
416 case AMDGPU_HW_IP_VCN_ENC:
417 type = AMD_IP_BLOCK_TYPE_VCN;
418 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
419 if (adev->uvd.harvest_config & (1 << i))
422 for (j = 0; j < adev->vcn.num_enc_rings; j++)
423 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
426 ib_start_alignment = 64;
427 ib_size_alignment = 1;
429 case AMDGPU_HW_IP_VCN_JPEG:
430 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
431 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
433 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
434 if (adev->jpeg.harvest_config & (1 << i))
437 if (adev->jpeg.inst[i].ring_dec.sched.ready)
440 ib_start_alignment = 16;
441 ib_size_alignment = 16;
447 for (i = 0; i < adev->num_ip_blocks; i++)
448 if (adev->ip_blocks[i].version->type == type &&
449 adev->ip_blocks[i].status.valid)
452 if (i == adev->num_ip_blocks)
455 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
458 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
459 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
460 result->capabilities_flags = 0;
461 result->available_rings = (1 << num_rings) - 1;
462 result->ib_start_alignment = ib_start_alignment;
463 result->ib_size_alignment = ib_size_alignment;
468 * Userspace get information ioctl
471 * amdgpu_info_ioctl - answer a device specific request.
473 * @dev: drm device pointer
474 * @data: request object
477 * This function is used to pass device specific parameters to the userspace
478 * drivers. Examples include: pci device id, pipeline parms, tiling params,
480 * Returns 0 on success, -EINVAL on failure.
482 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
484 struct amdgpu_device *adev = drm_to_adev(dev);
485 struct drm_amdgpu_info *info = data;
486 struct amdgpu_mode_info *minfo = &adev->mode_info;
487 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
488 uint32_t size = info->return_size;
489 struct drm_crtc *crtc;
493 int ui32_size = sizeof(ui32);
495 if (!info->return_size || !info->return_pointer)
498 switch (info->query) {
499 case AMDGPU_INFO_ACCEL_WORKING:
500 ui32 = adev->accel_working;
501 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
502 case AMDGPU_INFO_CRTC_FROM_ID:
503 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
504 crtc = (struct drm_crtc *)minfo->crtcs[i];
505 if (crtc && crtc->base.id == info->mode_crtc.id) {
506 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
507 ui32 = amdgpu_crtc->crtc_id;
513 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
516 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
517 case AMDGPU_INFO_HW_IP_INFO: {
518 struct drm_amdgpu_info_hw_ip ip = {};
521 ret = amdgpu_hw_ip_info(adev, info, &ip);
525 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
526 return ret ? -EFAULT : 0;
528 case AMDGPU_INFO_HW_IP_COUNT: {
529 enum amd_ip_block_type type;
532 switch (info->query_hw_ip.type) {
533 case AMDGPU_HW_IP_GFX:
534 type = AMD_IP_BLOCK_TYPE_GFX;
536 case AMDGPU_HW_IP_COMPUTE:
537 type = AMD_IP_BLOCK_TYPE_GFX;
539 case AMDGPU_HW_IP_DMA:
540 type = AMD_IP_BLOCK_TYPE_SDMA;
542 case AMDGPU_HW_IP_UVD:
543 type = AMD_IP_BLOCK_TYPE_UVD;
545 case AMDGPU_HW_IP_VCE:
546 type = AMD_IP_BLOCK_TYPE_VCE;
548 case AMDGPU_HW_IP_UVD_ENC:
549 type = AMD_IP_BLOCK_TYPE_UVD;
551 case AMDGPU_HW_IP_VCN_DEC:
552 case AMDGPU_HW_IP_VCN_ENC:
553 type = AMD_IP_BLOCK_TYPE_VCN;
555 case AMDGPU_HW_IP_VCN_JPEG:
556 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
557 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
563 for (i = 0; i < adev->num_ip_blocks; i++)
564 if (adev->ip_blocks[i].version->type == type &&
565 adev->ip_blocks[i].status.valid &&
566 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
569 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
571 case AMDGPU_INFO_TIMESTAMP:
572 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
573 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
574 case AMDGPU_INFO_FW_VERSION: {
575 struct drm_amdgpu_info_firmware fw_info;
578 /* We only support one instance of each IP block right now. */
579 if (info->query_fw.ip_instance != 0)
582 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
586 return copy_to_user(out, &fw_info,
587 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
589 case AMDGPU_INFO_NUM_BYTES_MOVED:
590 ui64 = atomic64_read(&adev->num_bytes_moved);
591 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
592 case AMDGPU_INFO_NUM_EVICTIONS:
593 ui64 = atomic64_read(&adev->num_evictions);
594 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
595 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
596 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
597 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
598 case AMDGPU_INFO_VRAM_USAGE:
599 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
600 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
601 case AMDGPU_INFO_VIS_VRAM_USAGE:
602 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
603 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
604 case AMDGPU_INFO_GTT_USAGE:
605 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
606 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
607 case AMDGPU_INFO_GDS_CONFIG: {
608 struct drm_amdgpu_info_gds gds_info;
610 memset(&gds_info, 0, sizeof(gds_info));
611 gds_info.compute_partition_size = adev->gds.gds_size;
612 gds_info.gds_total_size = adev->gds.gds_size;
613 gds_info.gws_per_compute_partition = adev->gds.gws_size;
614 gds_info.oa_per_compute_partition = adev->gds.oa_size;
615 return copy_to_user(out, &gds_info,
616 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
618 case AMDGPU_INFO_VRAM_GTT: {
619 struct drm_amdgpu_info_vram_gtt vram_gtt;
621 vram_gtt.vram_size = adev->gmc.real_vram_size -
622 atomic64_read(&adev->vram_pin_size) -
623 AMDGPU_VM_RESERVED_VRAM;
624 vram_gtt.vram_cpu_accessible_size =
625 min(adev->gmc.visible_vram_size -
626 atomic64_read(&adev->visible_pin_size),
628 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
629 vram_gtt.gtt_size *= PAGE_SIZE;
630 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
631 return copy_to_user(out, &vram_gtt,
632 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
634 case AMDGPU_INFO_MEMORY: {
635 struct drm_amdgpu_memory_info mem;
636 struct ttm_resource_manager *vram_man =
637 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
638 struct ttm_resource_manager *gtt_man =
639 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
640 memset(&mem, 0, sizeof(mem));
641 mem.vram.total_heap_size = adev->gmc.real_vram_size;
642 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
643 atomic64_read(&adev->vram_pin_size) -
644 AMDGPU_VM_RESERVED_VRAM;
645 mem.vram.heap_usage =
646 amdgpu_vram_mgr_usage(vram_man);
647 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
649 mem.cpu_accessible_vram.total_heap_size =
650 adev->gmc.visible_vram_size;
651 mem.cpu_accessible_vram.usable_heap_size =
652 min(adev->gmc.visible_vram_size -
653 atomic64_read(&adev->visible_pin_size),
654 mem.vram.usable_heap_size);
655 mem.cpu_accessible_vram.heap_usage =
656 amdgpu_vram_mgr_vis_usage(vram_man);
657 mem.cpu_accessible_vram.max_allocation =
658 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
660 mem.gtt.total_heap_size = gtt_man->size;
661 mem.gtt.total_heap_size *= PAGE_SIZE;
662 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
663 atomic64_read(&adev->gart_pin_size);
665 amdgpu_gtt_mgr_usage(gtt_man);
666 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
668 return copy_to_user(out, &mem,
669 min((size_t)size, sizeof(mem)))
672 case AMDGPU_INFO_READ_MMR_REG: {
673 unsigned n, alloc_size;
675 unsigned se_num = (info->read_mmr_reg.instance >>
676 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
677 AMDGPU_INFO_MMR_SE_INDEX_MASK;
678 unsigned sh_num = (info->read_mmr_reg.instance >>
679 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
680 AMDGPU_INFO_MMR_SH_INDEX_MASK;
682 /* set full masks if the userspace set all bits
683 * in the bitfields */
684 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
686 else if (se_num >= AMDGPU_GFX_MAX_SE)
688 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
690 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
693 if (info->read_mmr_reg.count > 128)
696 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
699 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
701 amdgpu_gfx_off_ctrl(adev, false);
702 for (i = 0; i < info->read_mmr_reg.count; i++) {
703 if (amdgpu_asic_read_register(adev, se_num, sh_num,
704 info->read_mmr_reg.dword_offset + i,
706 DRM_DEBUG_KMS("unallowed offset %#x\n",
707 info->read_mmr_reg.dword_offset + i);
709 amdgpu_gfx_off_ctrl(adev, true);
713 amdgpu_gfx_off_ctrl(adev, true);
714 n = copy_to_user(out, regs, min(size, alloc_size));
716 return n ? -EFAULT : 0;
718 case AMDGPU_INFO_DEV_INFO: {
719 struct drm_amdgpu_info_device *dev_info;
723 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
727 dev_info->device_id = dev->pdev->device;
728 dev_info->chip_rev = adev->rev_id;
729 dev_info->external_rev = adev->external_rev_id;
730 dev_info->pci_rev = dev->pdev->revision;
731 dev_info->family = adev->family;
732 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
733 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
734 /* return all clocks in KHz */
735 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
736 if (adev->pm.dpm_enabled) {
737 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
738 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
740 dev_info->max_engine_clock = adev->clock.default_sclk * 10;
741 dev_info->max_memory_clock = adev->clock.default_mclk * 10;
743 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
744 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
745 adev->gfx.config.max_shader_engines;
746 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
748 dev_info->ids_flags = 0;
749 if (adev->flags & AMD_IS_APU)
750 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
751 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
752 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
753 if (amdgpu_is_tmz(adev))
754 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
756 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
757 vm_size -= AMDGPU_VA_RESERVED_SIZE;
759 /* Older VCE FW versions are buggy and can handle only 40bits */
760 if (adev->vce.fw_version &&
761 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
762 vm_size = min(vm_size, 1ULL << 40);
764 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
765 dev_info->virtual_address_max =
766 min(vm_size, AMDGPU_GMC_HOLE_START);
768 if (vm_size > AMDGPU_GMC_HOLE_START) {
769 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
770 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
772 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
773 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
774 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE;
775 dev_info->cu_active_number = adev->gfx.cu_info.number;
776 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
777 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
778 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
779 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
780 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
781 sizeof(adev->gfx.cu_info.bitmap));
782 dev_info->vram_type = adev->gmc.vram_type;
783 dev_info->vram_bit_width = adev->gmc.vram_width;
784 dev_info->vce_harvest_config = adev->vce.harvest_config;
785 dev_info->gc_double_offchip_lds_buf =
786 adev->gfx.config.double_offchip_lds_buf;
787 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
788 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
789 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
790 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
791 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
792 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
793 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
795 if (adev->family >= AMDGPU_FAMILY_NV)
796 dev_info->pa_sc_tile_steering_override =
797 adev->gfx.config.pa_sc_tile_steering_override;
799 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
801 ret = copy_to_user(out, dev_info,
802 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
806 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
808 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
809 struct amd_vce_state *vce_state;
811 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
812 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
814 vce_clk_table.entries[i].sclk = vce_state->sclk;
815 vce_clk_table.entries[i].mclk = vce_state->mclk;
816 vce_clk_table.entries[i].eclk = vce_state->evclk;
817 vce_clk_table.num_valid_entries++;
821 return copy_to_user(out, &vce_clk_table,
822 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
824 case AMDGPU_INFO_VBIOS: {
825 uint32_t bios_size = adev->bios_size;
827 switch (info->vbios_info.type) {
828 case AMDGPU_INFO_VBIOS_SIZE:
829 return copy_to_user(out, &bios_size,
830 min((size_t)size, sizeof(bios_size)))
832 case AMDGPU_INFO_VBIOS_IMAGE: {
834 uint32_t bios_offset = info->vbios_info.offset;
836 if (bios_offset >= bios_size)
839 bios = adev->bios + bios_offset;
840 return copy_to_user(out, bios,
841 min((size_t)size, (size_t)(bios_size - bios_offset)))
845 DRM_DEBUG_KMS("Invalid request %d\n",
846 info->vbios_info.type);
850 case AMDGPU_INFO_NUM_HANDLES: {
851 struct drm_amdgpu_info_num_handles handle;
853 switch (info->query_hw_ip.type) {
854 case AMDGPU_HW_IP_UVD:
855 /* Starting Polaris, we support unlimited UVD handles */
856 if (adev->asic_type < CHIP_POLARIS10) {
857 handle.uvd_max_handles = adev->uvd.max_handles;
858 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
860 return copy_to_user(out, &handle,
861 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
871 case AMDGPU_INFO_SENSOR: {
872 if (!adev->pm.dpm_enabled)
875 switch (info->sensor_info.type) {
876 case AMDGPU_INFO_SENSOR_GFX_SCLK:
877 /* get sclk in Mhz */
878 if (amdgpu_dpm_read_sensor(adev,
879 AMDGPU_PP_SENSOR_GFX_SCLK,
880 (void *)&ui32, &ui32_size)) {
885 case AMDGPU_INFO_SENSOR_GFX_MCLK:
886 /* get mclk in Mhz */
887 if (amdgpu_dpm_read_sensor(adev,
888 AMDGPU_PP_SENSOR_GFX_MCLK,
889 (void *)&ui32, &ui32_size)) {
894 case AMDGPU_INFO_SENSOR_GPU_TEMP:
895 /* get temperature in millidegrees C */
896 if (amdgpu_dpm_read_sensor(adev,
897 AMDGPU_PP_SENSOR_GPU_TEMP,
898 (void *)&ui32, &ui32_size)) {
902 case AMDGPU_INFO_SENSOR_GPU_LOAD:
904 if (amdgpu_dpm_read_sensor(adev,
905 AMDGPU_PP_SENSOR_GPU_LOAD,
906 (void *)&ui32, &ui32_size)) {
910 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
911 /* get average GPU power */
912 if (amdgpu_dpm_read_sensor(adev,
913 AMDGPU_PP_SENSOR_GPU_POWER,
914 (void *)&ui32, &ui32_size)) {
919 case AMDGPU_INFO_SENSOR_VDDNB:
920 /* get VDDNB in millivolts */
921 if (amdgpu_dpm_read_sensor(adev,
922 AMDGPU_PP_SENSOR_VDDNB,
923 (void *)&ui32, &ui32_size)) {
927 case AMDGPU_INFO_SENSOR_VDDGFX:
928 /* get VDDGFX in millivolts */
929 if (amdgpu_dpm_read_sensor(adev,
930 AMDGPU_PP_SENSOR_VDDGFX,
931 (void *)&ui32, &ui32_size)) {
935 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
936 /* get stable pstate sclk in Mhz */
937 if (amdgpu_dpm_read_sensor(adev,
938 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
939 (void *)&ui32, &ui32_size)) {
944 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
945 /* get stable pstate mclk in Mhz */
946 if (amdgpu_dpm_read_sensor(adev,
947 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
948 (void *)&ui32, &ui32_size)) {
954 DRM_DEBUG_KMS("Invalid request %d\n",
955 info->sensor_info.type);
958 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
960 case AMDGPU_INFO_VRAM_LOST_COUNTER:
961 ui32 = atomic_read(&adev->vram_lost_counter);
962 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
963 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
964 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
969 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
971 return copy_to_user(out, &ras_mask,
972 min_t(u64, size, sizeof(ras_mask))) ?
976 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
984 * Outdated mess for old drm with Xorg being in charge (void function now).
987 * amdgpu_driver_lastclose_kms - drm callback for last close
989 * @dev: drm dev pointer
991 * Switch vga_switcheroo state after last close (all asics).
993 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
995 drm_fb_helper_lastclose(dev);
996 vga_switcheroo_process_delayed_switch();
1000 * amdgpu_driver_open_kms - drm callback for open
1002 * @dev: drm dev pointer
1003 * @file_priv: drm file
1005 * On device open, init vm on cayman+ (all asics).
1006 * Returns 0 on success, error on failure.
1008 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1010 struct amdgpu_device *adev = drm_to_adev(dev);
1011 struct amdgpu_fpriv *fpriv;
1014 /* Ensure IB tests are run on ring */
1015 flush_delayed_work(&adev->delayed_init_work);
1018 if (amdgpu_ras_intr_triggered()) {
1019 DRM_ERROR("RAS Intr triggered, device disabled!!");
1023 file_priv->driver_priv = NULL;
1025 r = pm_runtime_get_sync(dev->dev);
1029 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1030 if (unlikely(!fpriv)) {
1035 pasid = amdgpu_pasid_alloc(16);
1037 dev_warn(adev->dev, "No more PASIDs available!");
1040 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1044 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1045 if (!fpriv->prt_va) {
1050 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1051 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1053 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1054 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1059 mutex_init(&fpriv->bo_list_lock);
1060 idr_init(&fpriv->bo_list_handles);
1062 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1064 file_priv->driver_priv = fpriv;
1068 amdgpu_vm_fini(adev, &fpriv->vm);
1072 amdgpu_pasid_free(pasid);
1077 pm_runtime_mark_last_busy(dev->dev);
1079 pm_runtime_put_autosuspend(dev->dev);
1085 * amdgpu_driver_postclose_kms - drm callback for post close
1087 * @dev: drm dev pointer
1088 * @file_priv: drm file
1090 * On device post close, tear down vm on cayman+ (all asics).
1092 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1093 struct drm_file *file_priv)
1095 struct amdgpu_device *adev = drm_to_adev(dev);
1096 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1097 struct amdgpu_bo_list *list;
1098 struct amdgpu_bo *pd;
1105 pm_runtime_get_sync(dev->dev);
1107 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1108 amdgpu_uvd_free_handles(adev, file_priv);
1109 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1110 amdgpu_vce_free_handles(adev, file_priv);
1112 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1114 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1115 /* TODO: how to handle reserve failure */
1116 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1117 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1118 fpriv->csa_va = NULL;
1119 amdgpu_bo_unreserve(adev->virt.csa_obj);
1122 pasid = fpriv->vm.pasid;
1123 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1125 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1126 amdgpu_vm_fini(adev, &fpriv->vm);
1129 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1130 amdgpu_bo_unref(&pd);
1132 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1133 amdgpu_bo_list_put(list);
1135 idr_destroy(&fpriv->bo_list_handles);
1136 mutex_destroy(&fpriv->bo_list_lock);
1139 file_priv->driver_priv = NULL;
1141 pm_runtime_mark_last_busy(dev->dev);
1142 pm_runtime_put_autosuspend(dev->dev);
1146 * VBlank related functions.
1149 * amdgpu_get_vblank_counter_kms - get frame count
1151 * @crtc: crtc to get the frame count from
1153 * Gets the frame count on the requested crtc (all asics).
1154 * Returns frame count on success, -EINVAL on failure.
1156 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1158 struct drm_device *dev = crtc->dev;
1159 unsigned int pipe = crtc->index;
1160 struct amdgpu_device *adev = drm_to_adev(dev);
1161 int vpos, hpos, stat;
1164 if (pipe >= adev->mode_info.num_crtc) {
1165 DRM_ERROR("Invalid crtc %u\n", pipe);
1169 /* The hw increments its frame counter at start of vsync, not at start
1170 * of vblank, as is required by DRM core vblank counter handling.
1171 * Cook the hw count here to make it appear to the caller as if it
1172 * incremented at start of vblank. We measure distance to start of
1173 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1174 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1175 * result by 1 to give the proper appearance to caller.
1177 if (adev->mode_info.crtcs[pipe]) {
1178 /* Repeat readout if needed to provide stable result if
1179 * we cross start of vsync during the queries.
1182 count = amdgpu_display_vblank_get_counter(adev, pipe);
1183 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1184 * vpos as distance to start of vblank, instead of
1185 * regular vertical scanout pos.
1187 stat = amdgpu_display_get_crtc_scanoutpos(
1188 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1189 &vpos, &hpos, NULL, NULL,
1190 &adev->mode_info.crtcs[pipe]->base.hwmode);
1191 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1193 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1194 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1195 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1197 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1200 /* Bump counter if we are at >= leading edge of vblank,
1201 * but before vsync where vpos would turn negative and
1202 * the hw counter really increments.
1208 /* Fallback to use value as is. */
1209 count = amdgpu_display_vblank_get_counter(adev, pipe);
1210 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1217 * amdgpu_enable_vblank_kms - enable vblank interrupt
1219 * @crtc: crtc to enable vblank interrupt for
1221 * Enable the interrupt on the requested crtc (all asics).
1222 * Returns 0 on success, -EINVAL on failure.
1224 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1226 struct drm_device *dev = crtc->dev;
1227 unsigned int pipe = crtc->index;
1228 struct amdgpu_device *adev = drm_to_adev(dev);
1229 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1231 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1235 * amdgpu_disable_vblank_kms - disable vblank interrupt
1237 * @crtc: crtc to disable vblank interrupt for
1239 * Disable the interrupt on the requested crtc (all asics).
1241 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1243 struct drm_device *dev = crtc->dev;
1244 unsigned int pipe = crtc->index;
1245 struct amdgpu_device *adev = drm_to_adev(dev);
1246 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1248 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1254 #if defined(CONFIG_DEBUG_FS)
1256 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1258 struct drm_info_node *node = (struct drm_info_node *) m->private;
1259 struct drm_device *dev = node->minor->dev;
1260 struct amdgpu_device *adev = drm_to_adev(dev);
1261 struct drm_amdgpu_info_firmware fw_info;
1262 struct drm_amdgpu_query_fw query_fw;
1263 struct atom_context *ctx = adev->mode_info.atom_context;
1267 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1268 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1271 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1272 fw_info.feature, fw_info.ver);
1275 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1276 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1279 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1280 fw_info.feature, fw_info.ver);
1283 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1284 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1287 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1288 fw_info.feature, fw_info.ver);
1291 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1292 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1295 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1296 fw_info.feature, fw_info.ver);
1299 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1300 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1303 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1304 fw_info.feature, fw_info.ver);
1307 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1308 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1311 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1312 fw_info.feature, fw_info.ver);
1315 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1316 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1319 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1320 fw_info.feature, fw_info.ver);
1322 /* RLC SAVE RESTORE LIST CNTL */
1323 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1324 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1327 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1328 fw_info.feature, fw_info.ver);
1330 /* RLC SAVE RESTORE LIST GPM MEM */
1331 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1332 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1335 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1336 fw_info.feature, fw_info.ver);
1338 /* RLC SAVE RESTORE LIST SRM MEM */
1339 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1340 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1343 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1344 fw_info.feature, fw_info.ver);
1347 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1349 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1352 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1353 fw_info.feature, fw_info.ver);
1356 if (adev->gfx.mec2_fw) {
1358 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1361 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1362 fw_info.feature, fw_info.ver);
1366 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1367 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1370 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1371 fw_info.feature, fw_info.ver);
1375 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1376 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1379 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1380 fw_info.feature, fw_info.ver);
1382 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1383 for (i = 0; i < 4; i++) {
1385 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1388 switch (query_fw.index) {
1390 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1391 "RAS", fw_info.feature, fw_info.ver);
1394 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1395 "XGMI", fw_info.feature, fw_info.ver);
1398 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1399 "HDCP", fw_info.feature, fw_info.ver);
1402 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1403 "DTM", fw_info.feature, fw_info.ver);
1411 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1412 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1415 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1416 fw_info.feature, fw_info.ver);
1419 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1420 for (i = 0; i < adev->sdma.num_instances; i++) {
1422 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1425 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1426 i, fw_info.feature, fw_info.ver);
1430 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1431 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1434 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1435 fw_info.feature, fw_info.ver);
1438 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1439 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1442 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1443 fw_info.feature, fw_info.ver);
1446 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1447 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1450 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1451 fw_info.feature, fw_info.ver);
1454 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1455 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1458 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1459 fw_info.feature, fw_info.ver);
1461 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1466 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1467 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1471 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1473 #if defined(CONFIG_DEBUG_FS)
1474 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1475 ARRAY_SIZE(amdgpu_firmware_info_list));