drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (adev->runpm) {
  91                 pm_runtime_get_sync(dev->dev);
  92                 pm_runtime_forbid(dev->dev);
  93         }
  94
  95         amdgpu_acpi_fini(adev);
  96         amdgpu_device_fini(adev);
  97 }
  98
  99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 100 {
 101         struct amdgpu_gpu_instance *gpu_instance;
 102
 103         mutex_lock(&mgpu_info.mutex);
 104
 105         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 106                 DRM_ERROR("Cannot register more gpu instance\n");
 107                 mutex_unlock(&mgpu_info.mutex);
 108                 return;
 109         }
 110
 111         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 112         gpu_instance->adev = adev;
 113         gpu_instance->mgpu_fan_enabled = 0;
 114
 115         mgpu_info.num_gpu++;
 116         if (adev->flags & AMD_IS_APU)
 117                 mgpu_info.num_apu++;
 118         else
 119                 mgpu_info.num_dgpu++;
 120
 121         mutex_unlock(&mgpu_info.mutex);
 122 }
 123
 124 /**
 125  * amdgpu_driver_load_kms - Main load function for KMS.
 126  *
 127  * @adev: pointer to struct amdgpu_device
 128  * @flags: device flags
 129  *
 130  * This is the main load function for KMS (all asics).
 131  * Returns 0 on success, error on failure.
 132  */
 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 134 {
 135         struct drm_device *dev;
 136         struct pci_dev *parent;
 137         int r, acpi_status;
 138
 139         dev = adev_to_drm(adev);
 140
 141         if (amdgpu_has_atpx() &&
 142             (amdgpu_is_atpx_hybrid() ||
 143              amdgpu_has_atpx_dgpu_power_cntl()) &&
 144             ((flags & AMD_IS_APU) == 0) &&
 145             !pci_is_thunderbolt_attached(dev->pdev))
 146                 flags |= AMD_IS_PX;
 147
 148         parent = pci_upstream_bridge(adev->pdev);
 149         adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
 150
 151         /* amdgpu_device_init should report only fatal error
 152          * like memory allocation failure or iomapping failure,
 153          * or memory manager initialization failure, it must
 154          * properly initialize the GPU MC controller and permit
 155          * VRAM allocation
 156          */
 157         r = amdgpu_device_init(adev, flags);
 158         if (r) {
 159                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 160                 goto out;
 161         }
 162
 163         if (amdgpu_device_supports_atpx(dev) &&
 164             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 165                 adev->runpm = true;
 166         } else if (amdgpu_device_supports_baco(dev) &&
 167                    (amdgpu_runtime_pm != 0)) {
 168                 switch (adev->asic_type) {
 169                 case CHIP_VEGA20:
 170                 case CHIP_ARCTURUS:
 171                 case CHIP_SIENNA_CICHLID:
 172                 case CHIP_NAVY_FLOUNDER:
 173                         /* enable runpm if runpm=1 */
 174                         if (amdgpu_runtime_pm > 0)
 175                                 adev->runpm = true;
 176                         break;
 177                 case CHIP_VEGA10:
 178                         /* turn runpm on if noretry=0 */
 179                         if (!adev->gmc.noretry)
 180                                 adev->runpm = true;
 181                         break;
 182                 default:
 183                         /* enable runpm on CI+ */
 184                         adev->runpm = true;
 185                         break;
 186                 }
 187         }
 188
 189         /* Call ACPI methods: require modeset init
 190          * but failure is not fatal
 191          */
 192
 193         acpi_status = amdgpu_acpi_init(adev);
 194         if (acpi_status)
 195                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
 196
 197         if (adev->runpm) {
 198                 /* only need to skip on ATPX */
 199                 if (amdgpu_device_supports_atpx(dev) &&
 200                     !amdgpu_is_atpx_hybrid())
 201                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 202                 pm_runtime_use_autosuspend(dev->dev);
 203                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 204                 pm_runtime_allow(dev->dev);
 205                 pm_runtime_mark_last_busy(dev->dev);
 206                 pm_runtime_put_autosuspend(dev->dev);
 207         }
 208
 209 out:
 210         if (r) {
 211                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 212                 if (adev->rmmio && adev->runpm)
 213                         pm_runtime_put_noidle(dev->dev);
 214                 amdgpu_driver_unload_kms(dev);
 215         }
 216
 217         return r;
 218 }
 219
 220 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 221                                 struct drm_amdgpu_query_fw *query_fw,
 222                                 struct amdgpu_device *adev)
 223 {
 224         switch (query_fw->fw_type) {
 225         case AMDGPU_INFO_FW_VCE:
 226                 fw_info->ver = adev->vce.fw_version;
 227                 fw_info->feature = adev->vce.fb_version;
 228                 break;
 229         case AMDGPU_INFO_FW_UVD:
 230                 fw_info->ver = adev->uvd.fw_version;
 231                 fw_info->feature = 0;
 232                 break;
 233         case AMDGPU_INFO_FW_VCN:
 234                 fw_info->ver = adev->vcn.fw_version;
 235                 fw_info->feature = 0;
 236                 break;
 237         case AMDGPU_INFO_FW_GMC:
 238                 fw_info->ver = adev->gmc.fw_version;
 239                 fw_info->feature = 0;
 240                 break;
 241         case AMDGPU_INFO_FW_GFX_ME:
 242                 fw_info->ver = adev->gfx.me_fw_version;
 243                 fw_info->feature = adev->gfx.me_feature_version;
 244                 break;
 245         case AMDGPU_INFO_FW_GFX_PFP:
 246                 fw_info->ver = adev->gfx.pfp_fw_version;
 247                 fw_info->feature = adev->gfx.pfp_feature_version;
 248                 break;
 249         case AMDGPU_INFO_FW_GFX_CE:
 250                 fw_info->ver = adev->gfx.ce_fw_version;
 251                 fw_info->feature = adev->gfx.ce_feature_version;
 252                 break;
 253         case AMDGPU_INFO_FW_GFX_RLC:
 254                 fw_info->ver = adev->gfx.rlc_fw_version;
 255                 fw_info->feature = adev->gfx.rlc_feature_version;
 256                 break;
 257         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 258                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 259                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 260                 break;
 261         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 262                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 263                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 264                 break;
 265         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 266                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 267                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 268                 break;
 269         case AMDGPU_INFO_FW_GFX_MEC:
 270                 if (query_fw->index == 0) {
 271                         fw_info->ver = adev->gfx.mec_fw_version;
 272                         fw_info->feature = adev->gfx.mec_feature_version;
 273                 } else if (query_fw->index == 1) {
 274                         fw_info->ver = adev->gfx.mec2_fw_version;
 275                         fw_info->feature = adev->gfx.mec2_feature_version;
 276                 } else
 277                         return -EINVAL;
 278                 break;
 279         case AMDGPU_INFO_FW_SMC:
 280                 fw_info->ver = adev->pm.fw_version;
 281                 fw_info->feature = 0;
 282                 break;
 283         case AMDGPU_INFO_FW_TA:
 284                 switch (query_fw->index) {
 285                 case 0:
 286                         fw_info->ver = adev->psp.ta_fw_version;
 287                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 288                         break;
 289                 case 1:
 290                         fw_info->ver = adev->psp.ta_fw_version;
 291                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 292                         break;
 293                 case 2:
 294                         fw_info->ver = adev->psp.ta_fw_version;
 295                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 296                         break;
 297                 case 3:
 298                         fw_info->ver = adev->psp.ta_fw_version;
 299                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 300                         break;
 301                 default:
 302                         return -EINVAL;
 303                 }
 304                 break;
 305         case AMDGPU_INFO_FW_SDMA:
 306                 if (query_fw->index >= adev->sdma.num_instances)
 307                         return -EINVAL;
 308                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 309                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 310                 break;
 311         case AMDGPU_INFO_FW_SOS:
 312                 fw_info->ver = adev->psp.sos_fw_version;
 313                 fw_info->feature = adev->psp.sos_feature_version;
 314                 break;
 315         case AMDGPU_INFO_FW_ASD:
 316                 fw_info->ver = adev->psp.asd_fw_version;
 317                 fw_info->feature = adev->psp.asd_feature_version;
 318                 break;
 319         case AMDGPU_INFO_FW_DMCU:
 320                 fw_info->ver = adev->dm.dmcu_fw_version;
 321                 fw_info->feature = 0;
 322                 break;
 323         case AMDGPU_INFO_FW_DMCUB:
 324                 fw_info->ver = adev->dm.dmcub_fw_version;
 325                 fw_info->feature = 0;
 326                 break;
 327         case AMDGPU_INFO_FW_TOC:
 328                 fw_info->ver = adev->psp.toc_fw_version;
 329                 fw_info->feature = adev->psp.toc_feature_version;
 330                 break;
 331         default:
 332                 return -EINVAL;
 333         }
 334         return 0;
 335 }
 336
 337 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 338                              struct drm_amdgpu_info *info,
 339                              struct drm_amdgpu_info_hw_ip *result)
 340 {
 341         uint32_t ib_start_alignment = 0;
 342         uint32_t ib_size_alignment = 0;
 343         enum amd_ip_block_type type;
 344         unsigned int num_rings = 0;
 345         unsigned int i, j;
 346
 347         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 348                 return -EINVAL;
 349
 350         switch (info->query_hw_ip.type) {
 351         case AMDGPU_HW_IP_GFX:
 352                 type = AMD_IP_BLOCK_TYPE_GFX;
 353                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 354                         if (adev->gfx.gfx_ring[i].sched.ready)
 355                                 ++num_rings;
 356                 ib_start_alignment = 32;
 357                 ib_size_alignment = 32;
 358                 break;
 359         case AMDGPU_HW_IP_COMPUTE:
 360                 type = AMD_IP_BLOCK_TYPE_GFX;
 361                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 362                         if (adev->gfx.compute_ring[i].sched.ready)
 363                                 ++num_rings;
 364                 ib_start_alignment = 32;
 365                 ib_size_alignment = 32;
 366                 break;
 367         case AMDGPU_HW_IP_DMA:
 368                 type = AMD_IP_BLOCK_TYPE_SDMA;
 369                 for (i = 0; i < adev->sdma.num_instances; i++)
 370                         if (adev->sdma.instance[i].ring.sched.ready)
 371                                 ++num_rings;
 372                 ib_start_alignment = 256;
 373                 ib_size_alignment = 4;
 374                 break;
 375         case AMDGPU_HW_IP_UVD:
 376                 type = AMD_IP_BLOCK_TYPE_UVD;
 377                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 378                         if (adev->uvd.harvest_config & (1 << i))
 379                                 continue;
 380
 381                         if (adev->uvd.inst[i].ring.sched.ready)
 382                                 ++num_rings;
 383                 }
 384                 ib_start_alignment = 64;
 385                 ib_size_alignment = 64;
 386                 break;
 387         case AMDGPU_HW_IP_VCE:
 388                 type = AMD_IP_BLOCK_TYPE_VCE;
 389                 for (i = 0; i < adev->vce.num_rings; i++)
 390                         if (adev->vce.ring[i].sched.ready)
 391                                 ++num_rings;
 392                 ib_start_alignment = 4;
 393                 ib_size_alignment = 1;
 394                 break;
 395         case AMDGPU_HW_IP_UVD_ENC:
 396                 type = AMD_IP_BLOCK_TYPE_UVD;
 397                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 398                         if (adev->uvd.harvest_config & (1 << i))
 399                                 continue;
 400
 401                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 402                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 403                                         ++num_rings;
 404                 }
 405                 ib_start_alignment = 64;
 406                 ib_size_alignment = 64;
 407                 break;
 408         case AMDGPU_HW_IP_VCN_DEC:
 409                 type = AMD_IP_BLOCK_TYPE_VCN;
 410                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 411                         if (adev->uvd.harvest_config & (1 << i))
 412                                 continue;
 413
 414                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 415                                 ++num_rings;
 416                 }
 417                 ib_start_alignment = 16;
 418                 ib_size_alignment = 16;
 419                 break;
 420         case AMDGPU_HW_IP_VCN_ENC:
 421                 type = AMD_IP_BLOCK_TYPE_VCN;
 422                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 423                         if (adev->uvd.harvest_config & (1 << i))
 424                                 continue;
 425
 426                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 427                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 428                                         ++num_rings;
 429                 }
 430                 ib_start_alignment = 64;
 431                 ib_size_alignment = 1;
 432                 break;
 433         case AMDGPU_HW_IP_VCN_JPEG:
 434                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 435                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 436
 437                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 438                         if (adev->jpeg.harvest_config & (1 << i))
 439                                 continue;
 440
 441                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 442                                 ++num_rings;
 443                 }
 444                 ib_start_alignment = 16;
 445                 ib_size_alignment = 16;
 446                 break;
 447         default:
 448                 return -EINVAL;
 449         }
 450
 451         for (i = 0; i < adev->num_ip_blocks; i++)
 452                 if (adev->ip_blocks[i].version->type == type &&
 453                     adev->ip_blocks[i].status.valid)
 454                         break;
 455
 456         if (i == adev->num_ip_blocks)
 457                 return 0;
 458
 459         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 460                         num_rings);
 461
 462         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 463         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 464         result->capabilities_flags = 0;
 465         result->available_rings = (1 << num_rings) - 1;
 466         result->ib_start_alignment = ib_start_alignment;
 467         result->ib_size_alignment = ib_size_alignment;
 468         return 0;
 469 }
 470
 471 /*
 472  * Userspace get information ioctl
 473  */
 474 /**
 475  * amdgpu_info_ioctl - answer a device specific request.
 476  *
 477  * @dev: drm device pointer
 478  * @data: request object
 479  * @filp: drm filp
 480  *
 481  * This function is used to pass device specific parameters to the userspace
 482  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 483  * etc. (all asics).
 484  * Returns 0 on success, -EINVAL on failure.
 485  */
 486 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 487 {
 488         struct amdgpu_device *adev = drm_to_adev(dev);
 489         struct drm_amdgpu_info *info = data;
 490         struct amdgpu_mode_info *minfo = &adev->mode_info;
 491         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 492         uint32_t size = info->return_size;
 493         struct drm_crtc *crtc;
 494         uint32_t ui32 = 0;
 495         uint64_t ui64 = 0;
 496         int i, found;
 497         int ui32_size = sizeof(ui32);
 498
 499         if (!info->return_size || !info->return_pointer)
 500                 return -EINVAL;
 501
 502         switch (info->query) {
 503         case AMDGPU_INFO_ACCEL_WORKING:
 504                 ui32 = adev->accel_working;
 505                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 506         case AMDGPU_INFO_CRTC_FROM_ID:
 507                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 508                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 509                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 510                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 511                                 ui32 = amdgpu_crtc->crtc_id;
 512                                 found = 1;
 513                                 break;
 514                         }
 515                 }
 516                 if (!found) {
 517                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 518                         return -EINVAL;
 519                 }
 520                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 521         case AMDGPU_INFO_HW_IP_INFO: {
 522                 struct drm_amdgpu_info_hw_ip ip = {};
 523                 int ret;
 524
 525                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 526                 if (ret)
 527                         return ret;
 528
 529                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 530                 return ret ? -EFAULT : 0;
 531         }
 532         case AMDGPU_INFO_HW_IP_COUNT: {
 533                 enum amd_ip_block_type type;
 534                 uint32_t count = 0;
 535
 536                 switch (info->query_hw_ip.type) {
 537                 case AMDGPU_HW_IP_GFX:
 538                         type = AMD_IP_BLOCK_TYPE_GFX;
 539                         break;
 540                 case AMDGPU_HW_IP_COMPUTE:
 541                         type = AMD_IP_BLOCK_TYPE_GFX;
 542                         break;
 543                 case AMDGPU_HW_IP_DMA:
 544                         type = AMD_IP_BLOCK_TYPE_SDMA;
 545                         break;
 546                 case AMDGPU_HW_IP_UVD:
 547                         type = AMD_IP_BLOCK_TYPE_UVD;
 548                         break;
 549                 case AMDGPU_HW_IP_VCE:
 550                         type = AMD_IP_BLOCK_TYPE_VCE;
 551                         break;
 552                 case AMDGPU_HW_IP_UVD_ENC:
 553                         type = AMD_IP_BLOCK_TYPE_UVD;
 554                         break;
 555                 case AMDGPU_HW_IP_VCN_DEC:
 556                 case AMDGPU_HW_IP_VCN_ENC:
 557                         type = AMD_IP_BLOCK_TYPE_VCN;
 558                         break;
 559                 case AMDGPU_HW_IP_VCN_JPEG:
 560                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 561                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 562                         break;
 563                 default:
 564                         return -EINVAL;
 565                 }
 566
 567                 for (i = 0; i < adev->num_ip_blocks; i++)
 568                         if (adev->ip_blocks[i].version->type == type &&
 569                             adev->ip_blocks[i].status.valid &&
 570                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 571                                 count++;
 572
 573                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 574         }
 575         case AMDGPU_INFO_TIMESTAMP:
 576                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 577                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 578         case AMDGPU_INFO_FW_VERSION: {
 579                 struct drm_amdgpu_info_firmware fw_info;
 580                 int ret;
 581
 582                 /* We only support one instance of each IP block right now. */
 583                 if (info->query_fw.ip_instance != 0)
 584                         return -EINVAL;
 585
 586                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 587                 if (ret)
 588                         return ret;
 589
 590                 return copy_to_user(out, &fw_info,
 591                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 592         }
 593         case AMDGPU_INFO_NUM_BYTES_MOVED:
 594                 ui64 = atomic64_read(&adev->num_bytes_moved);
 595                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 596         case AMDGPU_INFO_NUM_EVICTIONS:
 597                 ui64 = atomic64_read(&adev->num_evictions);
 598                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 599         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 600                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 601                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 602         case AMDGPU_INFO_VRAM_USAGE:
 603                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 604                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 605         case AMDGPU_INFO_VIS_VRAM_USAGE:
 606                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 607                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 608         case AMDGPU_INFO_GTT_USAGE:
 609                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 610                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 611         case AMDGPU_INFO_GDS_CONFIG: {
 612                 struct drm_amdgpu_info_gds gds_info;
 613
 614                 memset(&gds_info, 0, sizeof(gds_info));
 615                 gds_info.compute_partition_size = adev->gds.gds_size;
 616                 gds_info.gds_total_size = adev->gds.gds_size;
 617                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 618                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 619                 return copy_to_user(out, &gds_info,
 620                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 621         }
 622         case AMDGPU_INFO_VRAM_GTT: {
 623                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 624
 625                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 626                         atomic64_read(&adev->vram_pin_size) -
 627                         AMDGPU_VM_RESERVED_VRAM;
 628                 vram_gtt.vram_cpu_accessible_size =
 629                         min(adev->gmc.visible_vram_size -
 630                             atomic64_read(&adev->visible_pin_size),
 631                             vram_gtt.vram_size);
 632                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 633                 vram_gtt.gtt_size *= PAGE_SIZE;
 634                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 635                 return copy_to_user(out, &vram_gtt,
 636                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 637         }
 638         case AMDGPU_INFO_MEMORY: {
 639                 struct drm_amdgpu_memory_info mem;
 640                 struct ttm_resource_manager *vram_man =
 641                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 642                 struct ttm_resource_manager *gtt_man =
 643                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 644                 memset(&mem, 0, sizeof(mem));
 645                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 646                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 647                         atomic64_read(&adev->vram_pin_size) -
 648                         AMDGPU_VM_RESERVED_VRAM;
 649                 mem.vram.heap_usage =
 650                         amdgpu_vram_mgr_usage(vram_man);
 651                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 652
 653                 mem.cpu_accessible_vram.total_heap_size =
 654                         adev->gmc.visible_vram_size;
 655                 mem.cpu_accessible_vram.usable_heap_size =
 656                         min(adev->gmc.visible_vram_size -
 657                             atomic64_read(&adev->visible_pin_size),
 658                             mem.vram.usable_heap_size);
 659                 mem.cpu_accessible_vram.heap_usage =
 660                         amdgpu_vram_mgr_vis_usage(vram_man);
 661                 mem.cpu_accessible_vram.max_allocation =
 662                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 663
 664                 mem.gtt.total_heap_size = gtt_man->size;
 665                 mem.gtt.total_heap_size *= PAGE_SIZE;
 666                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 667                         atomic64_read(&adev->gart_pin_size);
 668                 mem.gtt.heap_usage =
 669                         amdgpu_gtt_mgr_usage(gtt_man);
 670                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 671
 672                 return copy_to_user(out, &mem,
 673                                     min((size_t)size, sizeof(mem)))
 674                                     ? -EFAULT : 0;
 675         }
 676         case AMDGPU_INFO_READ_MMR_REG: {
 677                 unsigned n, alloc_size;
 678                 uint32_t *regs;
 679                 unsigned se_num = (info->read_mmr_reg.instance >>
 680                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 681                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 682                 unsigned sh_num = (info->read_mmr_reg.instance >>
 683                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 684                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 685
 686                 /* set full masks if the userspace set all bits
 687                  * in the bitfields */
 688                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 689                         se_num = 0xffffffff;
 690                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 691                         return -EINVAL;
 692                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 693                         sh_num = 0xffffffff;
 694                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 695                         return -EINVAL;
 696
 697                 if (info->read_mmr_reg.count > 128)
 698                         return -EINVAL;
 699
 700                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 701                 if (!regs)
 702                         return -ENOMEM;
 703                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 704
 705                 amdgpu_gfx_off_ctrl(adev, false);
 706                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 707                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 708                                                       info->read_mmr_reg.dword_offset + i,
 709                                                       &regs[i])) {
 710                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 711                                               info->read_mmr_reg.dword_offset + i);
 712                                 kfree(regs);
 713                                 amdgpu_gfx_off_ctrl(adev, true);
 714                                 return -EFAULT;
 715                         }
 716                 }
 717                 amdgpu_gfx_off_ctrl(adev, true);
 718                 n = copy_to_user(out, regs, min(size, alloc_size));
 719                 kfree(regs);
 720                 return n ? -EFAULT : 0;
 721         }
 722         case AMDGPU_INFO_DEV_INFO: {
 723                 struct drm_amdgpu_info_device *dev_info;
 724                 uint64_t vm_size;
 725                 int ret;
 726
 727                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 728                 if (!dev_info)
 729                         return -ENOMEM;
 730
 731                 dev_info->device_id = dev->pdev->device;
 732                 dev_info->chip_rev = adev->rev_id;
 733                 dev_info->external_rev = adev->external_rev_id;
 734                 dev_info->pci_rev = dev->pdev->revision;
 735                 dev_info->family = adev->family;
 736                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 737                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 738                 /* return all clocks in KHz */
 739                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 740                 if (adev->pm.dpm_enabled) {
 741                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 742                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 743                 } else {
 744                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 745                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 746                 }
 747                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 748                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 749                         adev->gfx.config.max_shader_engines;
 750                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 751                 dev_info->_pad = 0;
 752                 dev_info->ids_flags = 0;
 753                 if (adev->flags & AMD_IS_APU)
 754                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 755                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 756                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 757                 if (amdgpu_is_tmz(adev))
 758                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 759
 760                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 761                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 762
 763                 /* Older VCE FW versions are buggy and can handle only 40bits */
 764                 if (adev->vce.fw_version &&
 765                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 766                         vm_size = min(vm_size, 1ULL << 40);
 767
 768                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 769                 dev_info->virtual_address_max =
 770                         min(vm_size, AMDGPU_GMC_HOLE_START);
 771
 772                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 773                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 774                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 775                 }
 776                 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 777                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 778                 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 779                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 780                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 781                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 782                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 783                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 784                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 785                        sizeof(adev->gfx.cu_info.bitmap));
 786                 dev_info->vram_type = adev->gmc.vram_type;
 787                 dev_info->vram_bit_width = adev->gmc.vram_width;
 788                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 789                 dev_info->gc_double_offchip_lds_buf =
 790                         adev->gfx.config.double_offchip_lds_buf;
 791                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 792                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 793                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 794                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 795                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 796                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 797                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 798
 799                 if (adev->family >= AMDGPU_FAMILY_NV)
 800                         dev_info->pa_sc_tile_steering_override =
 801                                 adev->gfx.config.pa_sc_tile_steering_override;
 802
 803                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 804
 805                 ret = copy_to_user(out, dev_info,
 806                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 807                 kfree(dev_info);
 808                 return ret;
 809         }
 810         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 811                 unsigned i;
 812                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 813                 struct amd_vce_state *vce_state;
 814
 815                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 816                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 817                         if (vce_state) {
 818                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 819                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 820                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 821                                 vce_clk_table.num_valid_entries++;
 822                         }
 823                 }
 824
 825                 return copy_to_user(out, &vce_clk_table,
 826                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 827         }
 828         case AMDGPU_INFO_VBIOS: {
 829                 uint32_t bios_size = adev->bios_size;
 830
 831                 switch (info->vbios_info.type) {
 832                 case AMDGPU_INFO_VBIOS_SIZE:
 833                         return copy_to_user(out, &bios_size,
 834                                         min((size_t)size, sizeof(bios_size)))
 835                                         ? -EFAULT : 0;
 836                 case AMDGPU_INFO_VBIOS_IMAGE: {
 837                         uint8_t *bios;
 838                         uint32_t bios_offset = info->vbios_info.offset;
 839
 840                         if (bios_offset >= bios_size)
 841                                 return -EINVAL;
 842
 843                         bios = adev->bios + bios_offset;
 844                         return copy_to_user(out, bios,
 845                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 846                                         ? -EFAULT : 0;
 847                 }
 848                 default:
 849                         DRM_DEBUG_KMS("Invalid request %d\n",
 850                                         info->vbios_info.type);
 851                         return -EINVAL;
 852                 }
 853         }
 854         case AMDGPU_INFO_NUM_HANDLES: {
 855                 struct drm_amdgpu_info_num_handles handle;
 856
 857                 switch (info->query_hw_ip.type) {
 858                 case AMDGPU_HW_IP_UVD:
 859                         /* Starting Polaris, we support unlimited UVD handles */
 860                         if (adev->asic_type < CHIP_POLARIS10) {
 861                                 handle.uvd_max_handles = adev->uvd.max_handles;
 862                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 863
 864                                 return copy_to_user(out, &handle,
 865                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 866                         } else {
 867                                 return -ENODATA;
 868                         }
 869
 870                         break;
 871                 default:
 872                         return -EINVAL;
 873                 }
 874         }
 875         case AMDGPU_INFO_SENSOR: {
 876                 if (!adev->pm.dpm_enabled)
 877                         return -ENOENT;
 878
 879                 switch (info->sensor_info.type) {
 880                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 881                         /* get sclk in Mhz */
 882                         if (amdgpu_dpm_read_sensor(adev,
 883                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 884                                                    (void *)&ui32, &ui32_size)) {
 885                                 return -EINVAL;
 886                         }
 887                         ui32 /= 100;
 888                         break;
 889                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 890                         /* get mclk in Mhz */
 891                         if (amdgpu_dpm_read_sensor(adev,
 892                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 893                                                    (void *)&ui32, &ui32_size)) {
 894                                 return -EINVAL;
 895                         }
 896                         ui32 /= 100;
 897                         break;
 898                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 899                         /* get temperature in millidegrees C */
 900                         if (amdgpu_dpm_read_sensor(adev,
 901                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 902                                                    (void *)&ui32, &ui32_size)) {
 903                                 return -EINVAL;
 904                         }
 905                         break;
 906                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 907                         /* get GPU load */
 908                         if (amdgpu_dpm_read_sensor(adev,
 909                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 910                                                    (void *)&ui32, &ui32_size)) {
 911                                 return -EINVAL;
 912                         }
 913                         break;
 914                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 915                         /* get average GPU power */
 916                         if (amdgpu_dpm_read_sensor(adev,
 917                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 918                                                    (void *)&ui32, &ui32_size)) {
 919                                 return -EINVAL;
 920                         }
 921                         ui32 >>= 8;
 922                         break;
 923                 case AMDGPU_INFO_SENSOR_VDDNB:
 924                         /* get VDDNB in millivolts */
 925                         if (amdgpu_dpm_read_sensor(adev,
 926                                                    AMDGPU_PP_SENSOR_VDDNB,
 927                                                    (void *)&ui32, &ui32_size)) {
 928                                 return -EINVAL;
 929                         }
 930                         break;
 931                 case AMDGPU_INFO_SENSOR_VDDGFX:
 932                         /* get VDDGFX in millivolts */
 933                         if (amdgpu_dpm_read_sensor(adev,
 934                                                    AMDGPU_PP_SENSOR_VDDGFX,
 935                                                    (void *)&ui32, &ui32_size)) {
 936                                 return -EINVAL;
 937                         }
 938                         break;
 939                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 940                         /* get stable pstate sclk in Mhz */
 941                         if (amdgpu_dpm_read_sensor(adev,
 942                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 943                                                    (void *)&ui32, &ui32_size)) {
 944                                 return -EINVAL;
 945                         }
 946                         ui32 /= 100;
 947                         break;
 948                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 949                         /* get stable pstate mclk in Mhz */
 950                         if (amdgpu_dpm_read_sensor(adev,
 951                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 952                                                    (void *)&ui32, &ui32_size)) {
 953                                 return -EINVAL;
 954                         }
 955                         ui32 /= 100;
 956                         break;
 957                 default:
 958                         DRM_DEBUG_KMS("Invalid request %d\n",
 959                                       info->sensor_info.type);
 960                         return -EINVAL;
 961                 }
 962                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 963         }
 964         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 965                 ui32 = atomic_read(&adev->vram_lost_counter);
 966                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 967         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 968                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 969                 uint64_t ras_mask;
 970
 971                 if (!ras)
 972                         return -EINVAL;
 973                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 974
 975                 return copy_to_user(out, &ras_mask,
 976                                 min_t(u64, size, sizeof(ras_mask))) ?
 977                         -EFAULT : 0;
 978         }
 979         default:
 980                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 981                 return -EINVAL;
 982         }
 983         return 0;
 984 }
 985
 986
 987 /*
 988  * Outdated mess for old drm with Xorg being in charge (void function now).
 989  */
 990 /**
 991  * amdgpu_driver_lastclose_kms - drm callback for last close
 992  *
 993  * @dev: drm dev pointer
 994  *
 995  * Switch vga_switcheroo state after last close (all asics).
 996  */
 997 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 998 {
 999         drm_fb_helper_lastclose(dev);
1000         vga_switcheroo_process_delayed_switch();
1001 }
1002
1003 /**
1004  * amdgpu_driver_open_kms - drm callback for open
1005  *
1006  * @dev: drm dev pointer
1007  * @file_priv: drm file
1008  *
1009  * On device open, init vm on cayman+ (all asics).
1010  * Returns 0 on success, error on failure.
1011  */
1012 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1013 {
1014         struct amdgpu_device *adev = drm_to_adev(dev);
1015         struct amdgpu_fpriv *fpriv;
1016         int r, pasid;
1017
1018         /* Ensure IB tests are run on ring */
1019         flush_delayed_work(&adev->delayed_init_work);
1020
1021
1022         if (amdgpu_ras_intr_triggered()) {
1023                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1024                 return -EHWPOISON;
1025         }
1026
1027         file_priv->driver_priv = NULL;
1028
1029         r = pm_runtime_get_sync(dev->dev);
1030         if (r < 0)
1031                 goto pm_put;
1032
1033         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1034         if (unlikely(!fpriv)) {
1035                 r = -ENOMEM;
1036                 goto out_suspend;
1037         }
1038
1039         pasid = amdgpu_pasid_alloc(16);
1040         if (pasid < 0) {
1041                 dev_warn(adev->dev, "No more PASIDs available!");
1042                 pasid = 0;
1043         }
1044         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1045         if (r)
1046                 goto error_pasid;
1047
1048         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1049         if (!fpriv->prt_va) {
1050                 r = -ENOMEM;
1051                 goto error_vm;
1052         }
1053
1054         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1055                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1056
1057                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1058                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1059                 if (r)
1060                         goto error_vm;
1061         }
1062
1063         mutex_init(&fpriv->bo_list_lock);
1064         idr_init(&fpriv->bo_list_handles);
1065
1066         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1067
1068         file_priv->driver_priv = fpriv;
1069         goto out_suspend;
1070
1071 error_vm:
1072         amdgpu_vm_fini(adev, &fpriv->vm);
1073
1074 error_pasid:
1075         if (pasid)
1076                 amdgpu_pasid_free(pasid);
1077
1078         kfree(fpriv);
1079
1080 out_suspend:
1081         pm_runtime_mark_last_busy(dev->dev);
1082 pm_put:
1083         pm_runtime_put_autosuspend(dev->dev);
1084
1085         return r;
1086 }
1087
1088 /**
1089  * amdgpu_driver_postclose_kms - drm callback for post close
1090  *
1091  * @dev: drm dev pointer
1092  * @file_priv: drm file
1093  *
1094  * On device post close, tear down vm on cayman+ (all asics).
1095  */
1096 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1097                                  struct drm_file *file_priv)
1098 {
1099         struct amdgpu_device *adev = drm_to_adev(dev);
1100         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1101         struct amdgpu_bo_list *list;
1102         struct amdgpu_bo *pd;
1103         u32 pasid;
1104         int handle;
1105
1106         if (!fpriv)
1107                 return;
1108
1109         pm_runtime_get_sync(dev->dev);
1110
1111         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1112                 amdgpu_uvd_free_handles(adev, file_priv);
1113         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1114                 amdgpu_vce_free_handles(adev, file_priv);
1115
1116         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1117
1118         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1119                 /* TODO: how to handle reserve failure */
1120                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1121                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1122                 fpriv->csa_va = NULL;
1123                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1124         }
1125
1126         pasid = fpriv->vm.pasid;
1127         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1128
1129         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1130         amdgpu_vm_fini(adev, &fpriv->vm);
1131
1132         if (pasid)
1133                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1134         amdgpu_bo_unref(&pd);
1135
1136         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1137                 amdgpu_bo_list_put(list);
1138
1139         idr_destroy(&fpriv->bo_list_handles);
1140         mutex_destroy(&fpriv->bo_list_lock);
1141
1142         kfree(fpriv);
1143         file_priv->driver_priv = NULL;
1144
1145         pm_runtime_mark_last_busy(dev->dev);
1146         pm_runtime_put_autosuspend(dev->dev);
1147 }
1148
1149 /*
1150  * VBlank related functions.
1151  */
1152 /**
1153  * amdgpu_get_vblank_counter_kms - get frame count
1154  *
1155  * @crtc: crtc to get the frame count from
1156  *
1157  * Gets the frame count on the requested crtc (all asics).
1158  * Returns frame count on success, -EINVAL on failure.
1159  */
1160 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1161 {
1162         struct drm_device *dev = crtc->dev;
1163         unsigned int pipe = crtc->index;
1164         struct amdgpu_device *adev = drm_to_adev(dev);
1165         int vpos, hpos, stat;
1166         u32 count;
1167
1168         if (pipe >= adev->mode_info.num_crtc) {
1169                 DRM_ERROR("Invalid crtc %u\n", pipe);
1170                 return -EINVAL;
1171         }
1172
1173         /* The hw increments its frame counter at start of vsync, not at start
1174          * of vblank, as is required by DRM core vblank counter handling.
1175          * Cook the hw count here to make it appear to the caller as if it
1176          * incremented at start of vblank. We measure distance to start of
1177          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1178          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1179          * result by 1 to give the proper appearance to caller.
1180          */
1181         if (adev->mode_info.crtcs[pipe]) {
1182                 /* Repeat readout if needed to provide stable result if
1183                  * we cross start of vsync during the queries.
1184                  */
1185                 do {
1186                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1187                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1188                          * vpos as distance to start of vblank, instead of
1189                          * regular vertical scanout pos.
1190                          */
1191                         stat = amdgpu_display_get_crtc_scanoutpos(
1192                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1193                                 &vpos, &hpos, NULL, NULL,
1194                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1195                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1196
1197                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1198                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1199                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1200                 } else {
1201                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1202                                       pipe, vpos);
1203
1204                         /* Bump counter if we are at >= leading edge of vblank,
1205                          * but before vsync where vpos would turn negative and
1206                          * the hw counter really increments.
1207                          */
1208                         if (vpos >= 0)
1209                                 count++;
1210                 }
1211         } else {
1212                 /* Fallback to use value as is. */
1213                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1214                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1215         }
1216
1217         return count;
1218 }
1219
1220 /**
1221  * amdgpu_enable_vblank_kms - enable vblank interrupt
1222  *
1223  * @crtc: crtc to enable vblank interrupt for
1224  *
1225  * Enable the interrupt on the requested crtc (all asics).
1226  * Returns 0 on success, -EINVAL on failure.
1227  */
1228 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1229 {
1230         struct drm_device *dev = crtc->dev;
1231         unsigned int pipe = crtc->index;
1232         struct amdgpu_device *adev = drm_to_adev(dev);
1233         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1234
1235         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1236 }
1237
1238 /**
1239  * amdgpu_disable_vblank_kms - disable vblank interrupt
1240  *
1241  * @crtc: crtc to disable vblank interrupt for
1242  *
1243  * Disable the interrupt on the requested crtc (all asics).
1244  */
1245 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1246 {
1247         struct drm_device *dev = crtc->dev;
1248         unsigned int pipe = crtc->index;
1249         struct amdgpu_device *adev = drm_to_adev(dev);
1250         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1251
1252         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1253 }
1254
1255 /*
1256  * Debugfs info
1257  */
1258 #if defined(CONFIG_DEBUG_FS)
1259
1260 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1261 {
1262         struct drm_info_node *node = (struct drm_info_node *) m->private;
1263         struct drm_device *dev = node->minor->dev;
1264         struct amdgpu_device *adev = drm_to_adev(dev);
1265         struct drm_amdgpu_info_firmware fw_info;
1266         struct drm_amdgpu_query_fw query_fw;
1267         struct atom_context *ctx = adev->mode_info.atom_context;
1268         int ret, i;
1269
1270         /* VCE */
1271         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1272         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1273         if (ret)
1274                 return ret;
1275         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1276                    fw_info.feature, fw_info.ver);
1277
1278         /* UVD */
1279         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1280         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1281         if (ret)
1282                 return ret;
1283         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1284                    fw_info.feature, fw_info.ver);
1285
1286         /* GMC */
1287         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1288         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1289         if (ret)
1290                 return ret;
1291         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1292                    fw_info.feature, fw_info.ver);
1293
1294         /* ME */
1295         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1296         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1297         if (ret)
1298                 return ret;
1299         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1300                    fw_info.feature, fw_info.ver);
1301
1302         /* PFP */
1303         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1304         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1305         if (ret)
1306                 return ret;
1307         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1308                    fw_info.feature, fw_info.ver);
1309
1310         /* CE */
1311         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1312         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1313         if (ret)
1314                 return ret;
1315         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1316                    fw_info.feature, fw_info.ver);
1317
1318         /* RLC */
1319         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1320         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1321         if (ret)
1322                 return ret;
1323         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1324                    fw_info.feature, fw_info.ver);
1325
1326         /* RLC SAVE RESTORE LIST CNTL */
1327         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1328         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1329         if (ret)
1330                 return ret;
1331         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1332                    fw_info.feature, fw_info.ver);
1333
1334         /* RLC SAVE RESTORE LIST GPM MEM */
1335         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1336         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1337         if (ret)
1338                 return ret;
1339         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1340                    fw_info.feature, fw_info.ver);
1341
1342         /* RLC SAVE RESTORE LIST SRM MEM */
1343         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1344         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1345         if (ret)
1346                 return ret;
1347         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1348                    fw_info.feature, fw_info.ver);
1349
1350         /* MEC */
1351         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1352         query_fw.index = 0;
1353         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1354         if (ret)
1355                 return ret;
1356         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1357                    fw_info.feature, fw_info.ver);
1358
1359         /* MEC2 */
1360         if (adev->gfx.mec2_fw) {
1361                 query_fw.index = 1;
1362                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1363                 if (ret)
1364                         return ret;
1365                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1366                            fw_info.feature, fw_info.ver);
1367         }
1368
1369         /* PSP SOS */
1370         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1371         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1372         if (ret)
1373                 return ret;
1374         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1375                    fw_info.feature, fw_info.ver);
1376
1377
1378         /* PSP ASD */
1379         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1380         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1381         if (ret)
1382                 return ret;
1383         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1384                    fw_info.feature, fw_info.ver);
1385
1386         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1387         for (i = 0; i < 4; i++) {
1388                 query_fw.index = i;
1389                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1390                 if (ret)
1391                         continue;
1392                 switch (query_fw.index) {
1393                 case 0:
1394                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1395                                         "RAS", fw_info.feature, fw_info.ver);
1396                         break;
1397                 case 1:
1398                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1399                                         "XGMI", fw_info.feature, fw_info.ver);
1400                         break;
1401                 case 2:
1402                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1403                                         "HDCP", fw_info.feature, fw_info.ver);
1404                         break;
1405                 case 3:
1406                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1407                                         "DTM", fw_info.feature, fw_info.ver);
1408                         break;
1409                 default:
1410                         return -EINVAL;
1411                 }
1412         }
1413
1414         /* SMC */
1415         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1416         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1417         if (ret)
1418                 return ret;
1419         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1420                    fw_info.feature, fw_info.ver);
1421
1422         /* SDMA */
1423         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1424         for (i = 0; i < adev->sdma.num_instances; i++) {
1425                 query_fw.index = i;
1426                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1427                 if (ret)
1428                         return ret;
1429                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1430                            i, fw_info.feature, fw_info.ver);
1431         }
1432
1433         /* VCN */
1434         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1435         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1436         if (ret)
1437                 return ret;
1438         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1439                    fw_info.feature, fw_info.ver);
1440
1441         /* DMCU */
1442         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1443         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1444         if (ret)
1445                 return ret;
1446         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1447                    fw_info.feature, fw_info.ver);
1448
1449         /* DMCUB */
1450         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1451         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1452         if (ret)
1453                 return ret;
1454         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1455                    fw_info.feature, fw_info.ver);
1456
1457         /* TOC */
1458         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1459         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1460         if (ret)
1461                 return ret;
1462         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1463                    fw_info.feature, fw_info.ver);
1464
1465         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1466
1467         return 0;
1468 }
1469
1470 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1471         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1472 };
1473 #endif
1474
1475 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1476 {
1477 #if defined(CONFIG_DEBUG_FS)
1478         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1479                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1480 #else
1481         return 0;
1482 #endif
1483 }