drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (adev->runpm) {
  91                 pm_runtime_get_sync(dev->dev);
  92                 pm_runtime_forbid(dev->dev);
  93         }
  94
  95         amdgpu_acpi_fini(adev);
  96         amdgpu_device_fini(adev);
  97 }
  98
  99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 100 {
 101         struct amdgpu_gpu_instance *gpu_instance;
 102
 103         mutex_lock(&mgpu_info.mutex);
 104
 105         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 106                 DRM_ERROR("Cannot register more gpu instance\n");
 107                 mutex_unlock(&mgpu_info.mutex);
 108                 return;
 109         }
 110
 111         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 112         gpu_instance->adev = adev;
 113         gpu_instance->mgpu_fan_enabled = 0;
 114
 115         mgpu_info.num_gpu++;
 116         if (adev->flags & AMD_IS_APU)
 117                 mgpu_info.num_apu++;
 118         else
 119                 mgpu_info.num_dgpu++;
 120
 121         mutex_unlock(&mgpu_info.mutex);
 122 }
 123
 124 /**
 125  * amdgpu_driver_load_kms - Main load function for KMS.
 126  *
 127  * @adev: pointer to struct amdgpu_device
 128  * @flags: device flags
 129  *
 130  * This is the main load function for KMS (all asics).
 131  * Returns 0 on success, error on failure.
 132  */
 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 134 {
 135         struct drm_device *dev;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         if (amdgpu_has_atpx() &&
 141             (amdgpu_is_atpx_hybrid() ||
 142              amdgpu_has_atpx_dgpu_power_cntl()) &&
 143             ((flags & AMD_IS_APU) == 0) &&
 144             !pci_is_thunderbolt_attached(dev->pdev))
 145                 flags |= AMD_IS_PX;
 146
 147         /* amdgpu_device_init should report only fatal error
 148          * like memory allocation failure or iomapping failure,
 149          * or memory manager initialization failure, it must
 150          * properly initialize the GPU MC controller and permit
 151          * VRAM allocation
 152          */
 153         r = amdgpu_device_init(adev, flags);
 154         if (r) {
 155                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 156                 goto out;
 157         }
 158
 159         if (amdgpu_device_supports_boco(dev) &&
 160             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 161                 adev->runpm = true;
 162         } else if (amdgpu_device_supports_baco(dev) &&
 163                    (amdgpu_runtime_pm != 0)) {
 164                 switch (adev->asic_type) {
 165                 case CHIP_VEGA20:
 166                 case CHIP_ARCTURUS:
 167                 case CHIP_SIENNA_CICHLID:
 168                 case CHIP_NAVY_FLOUNDER:
 169                         /* enable runpm if runpm=1 */
 170                         if (amdgpu_runtime_pm > 0)
 171                                 adev->runpm = true;
 172                         break;
 173                 case CHIP_VEGA10:
 174                         /* turn runpm on if noretry=0 */
 175                         if (!adev->gmc.noretry)
 176                                 adev->runpm = true;
 177                         break;
 178                 default:
 179                         /* enable runpm on CI+ */
 180                         adev->runpm = true;
 181                         break;
 182                 }
 183         }
 184
 185         /* Call ACPI methods: require modeset init
 186          * but failure is not fatal
 187          */
 188
 189         acpi_status = amdgpu_acpi_init(adev);
 190         if (acpi_status)
 191                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
 192
 193         if (adev->runpm) {
 194                 /* only need to skip on ATPX */
 195                 if (amdgpu_device_supports_boco(dev) &&
 196                     !amdgpu_is_atpx_hybrid())
 197                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 198                 pm_runtime_use_autosuspend(dev->dev);
 199                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 200                 pm_runtime_allow(dev->dev);
 201                 pm_runtime_mark_last_busy(dev->dev);
 202                 pm_runtime_put_autosuspend(dev->dev);
 203         }
 204
 205 out:
 206         if (r) {
 207                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 208                 if (adev->rmmio && adev->runpm)
 209                         pm_runtime_put_noidle(dev->dev);
 210                 amdgpu_driver_unload_kms(dev);
 211         }
 212
 213         return r;
 214 }
 215
 216 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 217                                 struct drm_amdgpu_query_fw *query_fw,
 218                                 struct amdgpu_device *adev)
 219 {
 220         switch (query_fw->fw_type) {
 221         case AMDGPU_INFO_FW_VCE:
 222                 fw_info->ver = adev->vce.fw_version;
 223                 fw_info->feature = adev->vce.fb_version;
 224                 break;
 225         case AMDGPU_INFO_FW_UVD:
 226                 fw_info->ver = adev->uvd.fw_version;
 227                 fw_info->feature = 0;
 228                 break;
 229         case AMDGPU_INFO_FW_VCN:
 230                 fw_info->ver = adev->vcn.fw_version;
 231                 fw_info->feature = 0;
 232                 break;
 233         case AMDGPU_INFO_FW_GMC:
 234                 fw_info->ver = adev->gmc.fw_version;
 235                 fw_info->feature = 0;
 236                 break;
 237         case AMDGPU_INFO_FW_GFX_ME:
 238                 fw_info->ver = adev->gfx.me_fw_version;
 239                 fw_info->feature = adev->gfx.me_feature_version;
 240                 break;
 241         case AMDGPU_INFO_FW_GFX_PFP:
 242                 fw_info->ver = adev->gfx.pfp_fw_version;
 243                 fw_info->feature = adev->gfx.pfp_feature_version;
 244                 break;
 245         case AMDGPU_INFO_FW_GFX_CE:
 246                 fw_info->ver = adev->gfx.ce_fw_version;
 247                 fw_info->feature = adev->gfx.ce_feature_version;
 248                 break;
 249         case AMDGPU_INFO_FW_GFX_RLC:
 250                 fw_info->ver = adev->gfx.rlc_fw_version;
 251                 fw_info->feature = adev->gfx.rlc_feature_version;
 252                 break;
 253         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 254                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 255                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 256                 break;
 257         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 258                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 259                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 260                 break;
 261         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 262                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 263                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 264                 break;
 265         case AMDGPU_INFO_FW_GFX_MEC:
 266                 if (query_fw->index == 0) {
 267                         fw_info->ver = adev->gfx.mec_fw_version;
 268                         fw_info->feature = adev->gfx.mec_feature_version;
 269                 } else if (query_fw->index == 1) {
 270                         fw_info->ver = adev->gfx.mec2_fw_version;
 271                         fw_info->feature = adev->gfx.mec2_feature_version;
 272                 } else
 273                         return -EINVAL;
 274                 break;
 275         case AMDGPU_INFO_FW_SMC:
 276                 fw_info->ver = adev->pm.fw_version;
 277                 fw_info->feature = 0;
 278                 break;
 279         case AMDGPU_INFO_FW_TA:
 280                 switch (query_fw->index) {
 281                 case 0:
 282                         fw_info->ver = adev->psp.ta_fw_version;
 283                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 284                         break;
 285                 case 1:
 286                         fw_info->ver = adev->psp.ta_fw_version;
 287                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 288                         break;
 289                 case 2:
 290                         fw_info->ver = adev->psp.ta_fw_version;
 291                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 292                         break;
 293                 case 3:
 294                         fw_info->ver = adev->psp.ta_fw_version;
 295                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 296                         break;
 297                 default:
 298                         return -EINVAL;
 299                 }
 300                 break;
 301         case AMDGPU_INFO_FW_SDMA:
 302                 if (query_fw->index >= adev->sdma.num_instances)
 303                         return -EINVAL;
 304                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 305                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 306                 break;
 307         case AMDGPU_INFO_FW_SOS:
 308                 fw_info->ver = adev->psp.sos_fw_version;
 309                 fw_info->feature = adev->psp.sos_feature_version;
 310                 break;
 311         case AMDGPU_INFO_FW_ASD:
 312                 fw_info->ver = adev->psp.asd_fw_version;
 313                 fw_info->feature = adev->psp.asd_feature_version;
 314                 break;
 315         case AMDGPU_INFO_FW_DMCU:
 316                 fw_info->ver = adev->dm.dmcu_fw_version;
 317                 fw_info->feature = 0;
 318                 break;
 319         case AMDGPU_INFO_FW_DMCUB:
 320                 fw_info->ver = adev->dm.dmcub_fw_version;
 321                 fw_info->feature = 0;
 322                 break;
 323         case AMDGPU_INFO_FW_TOC:
 324                 fw_info->ver = adev->psp.toc_fw_version;
 325                 fw_info->feature = adev->psp.toc_feature_version;
 326                 break;
 327         default:
 328                 return -EINVAL;
 329         }
 330         return 0;
 331 }
 332
 333 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 334                              struct drm_amdgpu_info *info,
 335                              struct drm_amdgpu_info_hw_ip *result)
 336 {
 337         uint32_t ib_start_alignment = 0;
 338         uint32_t ib_size_alignment = 0;
 339         enum amd_ip_block_type type;
 340         unsigned int num_rings = 0;
 341         unsigned int i, j;
 342
 343         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 344                 return -EINVAL;
 345
 346         switch (info->query_hw_ip.type) {
 347         case AMDGPU_HW_IP_GFX:
 348                 type = AMD_IP_BLOCK_TYPE_GFX;
 349                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 350                         if (adev->gfx.gfx_ring[i].sched.ready)
 351                                 ++num_rings;
 352                 ib_start_alignment = 32;
 353                 ib_size_alignment = 32;
 354                 break;
 355         case AMDGPU_HW_IP_COMPUTE:
 356                 type = AMD_IP_BLOCK_TYPE_GFX;
 357                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 358                         if (adev->gfx.compute_ring[i].sched.ready)
 359                                 ++num_rings;
 360                 ib_start_alignment = 32;
 361                 ib_size_alignment = 32;
 362                 break;
 363         case AMDGPU_HW_IP_DMA:
 364                 type = AMD_IP_BLOCK_TYPE_SDMA;
 365                 for (i = 0; i < adev->sdma.num_instances; i++)
 366                         if (adev->sdma.instance[i].ring.sched.ready)
 367                                 ++num_rings;
 368                 ib_start_alignment = 256;
 369                 ib_size_alignment = 4;
 370                 break;
 371         case AMDGPU_HW_IP_UVD:
 372                 type = AMD_IP_BLOCK_TYPE_UVD;
 373                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 374                         if (adev->uvd.harvest_config & (1 << i))
 375                                 continue;
 376
 377                         if (adev->uvd.inst[i].ring.sched.ready)
 378                                 ++num_rings;
 379                 }
 380                 ib_start_alignment = 64;
 381                 ib_size_alignment = 64;
 382                 break;
 383         case AMDGPU_HW_IP_VCE:
 384                 type = AMD_IP_BLOCK_TYPE_VCE;
 385                 for (i = 0; i < adev->vce.num_rings; i++)
 386                         if (adev->vce.ring[i].sched.ready)
 387                                 ++num_rings;
 388                 ib_start_alignment = 4;
 389                 ib_size_alignment = 1;
 390                 break;
 391         case AMDGPU_HW_IP_UVD_ENC:
 392                 type = AMD_IP_BLOCK_TYPE_UVD;
 393                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 394                         if (adev->uvd.harvest_config & (1 << i))
 395                                 continue;
 396
 397                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 398                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 399                                         ++num_rings;
 400                 }
 401                 ib_start_alignment = 64;
 402                 ib_size_alignment = 64;
 403                 break;
 404         case AMDGPU_HW_IP_VCN_DEC:
 405                 type = AMD_IP_BLOCK_TYPE_VCN;
 406                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 407                         if (adev->uvd.harvest_config & (1 << i))
 408                                 continue;
 409
 410                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 411                                 ++num_rings;
 412                 }
 413                 ib_start_alignment = 16;
 414                 ib_size_alignment = 16;
 415                 break;
 416         case AMDGPU_HW_IP_VCN_ENC:
 417                 type = AMD_IP_BLOCK_TYPE_VCN;
 418                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 419                         if (adev->uvd.harvest_config & (1 << i))
 420                                 continue;
 421
 422                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 423                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 424                                         ++num_rings;
 425                 }
 426                 ib_start_alignment = 64;
 427                 ib_size_alignment = 1;
 428                 break;
 429         case AMDGPU_HW_IP_VCN_JPEG:
 430                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 431                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 432
 433                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 434                         if (adev->jpeg.harvest_config & (1 << i))
 435                                 continue;
 436
 437                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 438                                 ++num_rings;
 439                 }
 440                 ib_start_alignment = 16;
 441                 ib_size_alignment = 16;
 442                 break;
 443         default:
 444                 return -EINVAL;
 445         }
 446
 447         for (i = 0; i < adev->num_ip_blocks; i++)
 448                 if (adev->ip_blocks[i].version->type == type &&
 449                     adev->ip_blocks[i].status.valid)
 450                         break;
 451
 452         if (i == adev->num_ip_blocks)
 453                 return 0;
 454
 455         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 456                         num_rings);
 457
 458         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 459         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 460         result->capabilities_flags = 0;
 461         result->available_rings = (1 << num_rings) - 1;
 462         result->ib_start_alignment = ib_start_alignment;
 463         result->ib_size_alignment = ib_size_alignment;
 464         return 0;
 465 }
 466
 467 /*
 468  * Userspace get information ioctl
 469  */
 470 /**
 471  * amdgpu_info_ioctl - answer a device specific request.
 472  *
 473  * @dev: drm device pointer
 474  * @data: request object
 475  * @filp: drm filp
 476  *
 477  * This function is used to pass device specific parameters to the userspace
 478  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 479  * etc. (all asics).
 480  * Returns 0 on success, -EINVAL on failure.
 481  */
 482 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 483 {
 484         struct amdgpu_device *adev = drm_to_adev(dev);
 485         struct drm_amdgpu_info *info = data;
 486         struct amdgpu_mode_info *minfo = &adev->mode_info;
 487         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 488         uint32_t size = info->return_size;
 489         struct drm_crtc *crtc;
 490         uint32_t ui32 = 0;
 491         uint64_t ui64 = 0;
 492         int i, found;
 493         int ui32_size = sizeof(ui32);
 494
 495         if (!info->return_size || !info->return_pointer)
 496                 return -EINVAL;
 497
 498         switch (info->query) {
 499         case AMDGPU_INFO_ACCEL_WORKING:
 500                 ui32 = adev->accel_working;
 501                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 502         case AMDGPU_INFO_CRTC_FROM_ID:
 503                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 504                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 505                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 506                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 507                                 ui32 = amdgpu_crtc->crtc_id;
 508                                 found = 1;
 509                                 break;
 510                         }
 511                 }
 512                 if (!found) {
 513                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 514                         return -EINVAL;
 515                 }
 516                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 517         case AMDGPU_INFO_HW_IP_INFO: {
 518                 struct drm_amdgpu_info_hw_ip ip = {};
 519                 int ret;
 520
 521                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 522                 if (ret)
 523                         return ret;
 524
 525                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 526                 return ret ? -EFAULT : 0;
 527         }
 528         case AMDGPU_INFO_HW_IP_COUNT: {
 529                 enum amd_ip_block_type type;
 530                 uint32_t count = 0;
 531
 532                 switch (info->query_hw_ip.type) {
 533                 case AMDGPU_HW_IP_GFX:
 534                         type = AMD_IP_BLOCK_TYPE_GFX;
 535                         break;
 536                 case AMDGPU_HW_IP_COMPUTE:
 537                         type = AMD_IP_BLOCK_TYPE_GFX;
 538                         break;
 539                 case AMDGPU_HW_IP_DMA:
 540                         type = AMD_IP_BLOCK_TYPE_SDMA;
 541                         break;
 542                 case AMDGPU_HW_IP_UVD:
 543                         type = AMD_IP_BLOCK_TYPE_UVD;
 544                         break;
 545                 case AMDGPU_HW_IP_VCE:
 546                         type = AMD_IP_BLOCK_TYPE_VCE;
 547                         break;
 548                 case AMDGPU_HW_IP_UVD_ENC:
 549                         type = AMD_IP_BLOCK_TYPE_UVD;
 550                         break;
 551                 case AMDGPU_HW_IP_VCN_DEC:
 552                 case AMDGPU_HW_IP_VCN_ENC:
 553                         type = AMD_IP_BLOCK_TYPE_VCN;
 554                         break;
 555                 case AMDGPU_HW_IP_VCN_JPEG:
 556                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 557                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 558                         break;
 559                 default:
 560                         return -EINVAL;
 561                 }
 562
 563                 for (i = 0; i < adev->num_ip_blocks; i++)
 564                         if (adev->ip_blocks[i].version->type == type &&
 565                             adev->ip_blocks[i].status.valid &&
 566                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 567                                 count++;
 568
 569                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 570         }
 571         case AMDGPU_INFO_TIMESTAMP:
 572                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 573                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 574         case AMDGPU_INFO_FW_VERSION: {
 575                 struct drm_amdgpu_info_firmware fw_info;
 576                 int ret;
 577
 578                 /* We only support one instance of each IP block right now. */
 579                 if (info->query_fw.ip_instance != 0)
 580                         return -EINVAL;
 581
 582                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 583                 if (ret)
 584                         return ret;
 585
 586                 return copy_to_user(out, &fw_info,
 587                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 588         }
 589         case AMDGPU_INFO_NUM_BYTES_MOVED:
 590                 ui64 = atomic64_read(&adev->num_bytes_moved);
 591                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 592         case AMDGPU_INFO_NUM_EVICTIONS:
 593                 ui64 = atomic64_read(&adev->num_evictions);
 594                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 595         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 596                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 597                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 598         case AMDGPU_INFO_VRAM_USAGE:
 599                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 600                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 601         case AMDGPU_INFO_VIS_VRAM_USAGE:
 602                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 603                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 604         case AMDGPU_INFO_GTT_USAGE:
 605                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 606                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 607         case AMDGPU_INFO_GDS_CONFIG: {
 608                 struct drm_amdgpu_info_gds gds_info;
 609
 610                 memset(&gds_info, 0, sizeof(gds_info));
 611                 gds_info.compute_partition_size = adev->gds.gds_size;
 612                 gds_info.gds_total_size = adev->gds.gds_size;
 613                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 614                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 615                 return copy_to_user(out, &gds_info,
 616                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 617         }
 618         case AMDGPU_INFO_VRAM_GTT: {
 619                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 620
 621                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 622                         atomic64_read(&adev->vram_pin_size) -
 623                         AMDGPU_VM_RESERVED_VRAM;
 624                 vram_gtt.vram_cpu_accessible_size =
 625                         min(adev->gmc.visible_vram_size -
 626                             atomic64_read(&adev->visible_pin_size),
 627                             vram_gtt.vram_size);
 628                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 629                 vram_gtt.gtt_size *= PAGE_SIZE;
 630                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 631                 return copy_to_user(out, &vram_gtt,
 632                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 633         }
 634         case AMDGPU_INFO_MEMORY: {
 635                 struct drm_amdgpu_memory_info mem;
 636                 struct ttm_resource_manager *vram_man =
 637                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 638                 struct ttm_resource_manager *gtt_man =
 639                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 640                 memset(&mem, 0, sizeof(mem));
 641                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 642                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 643                         atomic64_read(&adev->vram_pin_size) -
 644                         AMDGPU_VM_RESERVED_VRAM;
 645                 mem.vram.heap_usage =
 646                         amdgpu_vram_mgr_usage(vram_man);
 647                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 648
 649                 mem.cpu_accessible_vram.total_heap_size =
 650                         adev->gmc.visible_vram_size;
 651                 mem.cpu_accessible_vram.usable_heap_size =
 652                         min(adev->gmc.visible_vram_size -
 653                             atomic64_read(&adev->visible_pin_size),
 654                             mem.vram.usable_heap_size);
 655                 mem.cpu_accessible_vram.heap_usage =
 656                         amdgpu_vram_mgr_vis_usage(vram_man);
 657                 mem.cpu_accessible_vram.max_allocation =
 658                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 659
 660                 mem.gtt.total_heap_size = gtt_man->size;
 661                 mem.gtt.total_heap_size *= PAGE_SIZE;
 662                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 663                         atomic64_read(&adev->gart_pin_size);
 664                 mem.gtt.heap_usage =
 665                         amdgpu_gtt_mgr_usage(gtt_man);
 666                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 667
 668                 return copy_to_user(out, &mem,
 669                                     min((size_t)size, sizeof(mem)))
 670                                     ? -EFAULT : 0;
 671         }
 672         case AMDGPU_INFO_READ_MMR_REG: {
 673                 unsigned n, alloc_size;
 674                 uint32_t *regs;
 675                 unsigned se_num = (info->read_mmr_reg.instance >>
 676                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 677                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 678                 unsigned sh_num = (info->read_mmr_reg.instance >>
 679                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 680                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 681
 682                 /* set full masks if the userspace set all bits
 683                  * in the bitfields */
 684                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 685                         se_num = 0xffffffff;
 686                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 687                         return -EINVAL;
 688                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 689                         sh_num = 0xffffffff;
 690                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 691                         return -EINVAL;
 692
 693                 if (info->read_mmr_reg.count > 128)
 694                         return -EINVAL;
 695
 696                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 697                 if (!regs)
 698                         return -ENOMEM;
 699                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 700
 701                 amdgpu_gfx_off_ctrl(adev, false);
 702                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 703                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 704                                                       info->read_mmr_reg.dword_offset + i,
 705                                                       &regs[i])) {
 706                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 707                                               info->read_mmr_reg.dword_offset + i);
 708                                 kfree(regs);
 709                                 amdgpu_gfx_off_ctrl(adev, true);
 710                                 return -EFAULT;
 711                         }
 712                 }
 713                 amdgpu_gfx_off_ctrl(adev, true);
 714                 n = copy_to_user(out, regs, min(size, alloc_size));
 715                 kfree(regs);
 716                 return n ? -EFAULT : 0;
 717         }
 718         case AMDGPU_INFO_DEV_INFO: {
 719                 struct drm_amdgpu_info_device *dev_info;
 720                 uint64_t vm_size;
 721                 int ret;
 722
 723                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 724                 if (!dev_info)
 725                         return -ENOMEM;
 726
 727                 dev_info->device_id = dev->pdev->device;
 728                 dev_info->chip_rev = adev->rev_id;
 729                 dev_info->external_rev = adev->external_rev_id;
 730                 dev_info->pci_rev = dev->pdev->revision;
 731                 dev_info->family = adev->family;
 732                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 733                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 734                 /* return all clocks in KHz */
 735                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 736                 if (adev->pm.dpm_enabled) {
 737                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 738                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 739                 } else {
 740                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 741                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 742                 }
 743                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 744                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 745                         adev->gfx.config.max_shader_engines;
 746                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 747                 dev_info->_pad = 0;
 748                 dev_info->ids_flags = 0;
 749                 if (adev->flags & AMD_IS_APU)
 750                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 751                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 752                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 753                 if (amdgpu_is_tmz(adev))
 754                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 755
 756                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 757                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 758
 759                 /* Older VCE FW versions are buggy and can handle only 40bits */
 760                 if (adev->vce.fw_version &&
 761                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 762                         vm_size = min(vm_size, 1ULL << 40);
 763
 764                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 765                 dev_info->virtual_address_max =
 766                         min(vm_size, AMDGPU_GMC_HOLE_START);
 767
 768                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 769                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 770                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 771                 }
 772                 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 773                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 774                 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 775                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 776                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 777                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 778                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 779                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 780                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 781                        sizeof(adev->gfx.cu_info.bitmap));
 782                 dev_info->vram_type = adev->gmc.vram_type;
 783                 dev_info->vram_bit_width = adev->gmc.vram_width;
 784                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 785                 dev_info->gc_double_offchip_lds_buf =
 786                         adev->gfx.config.double_offchip_lds_buf;
 787                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 788                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 789                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 790                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 791                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 792                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 793                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 794
 795                 if (adev->family >= AMDGPU_FAMILY_NV)
 796                         dev_info->pa_sc_tile_steering_override =
 797                                 adev->gfx.config.pa_sc_tile_steering_override;
 798
 799                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 800
 801                 ret = copy_to_user(out, dev_info,
 802                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 803                 kfree(dev_info);
 804                 return ret;
 805         }
 806         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 807                 unsigned i;
 808                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 809                 struct amd_vce_state *vce_state;
 810
 811                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 812                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 813                         if (vce_state) {
 814                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 815                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 816                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 817                                 vce_clk_table.num_valid_entries++;
 818                         }
 819                 }
 820
 821                 return copy_to_user(out, &vce_clk_table,
 822                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 823         }
 824         case AMDGPU_INFO_VBIOS: {
 825                 uint32_t bios_size = adev->bios_size;
 826
 827                 switch (info->vbios_info.type) {
 828                 case AMDGPU_INFO_VBIOS_SIZE:
 829                         return copy_to_user(out, &bios_size,
 830                                         min((size_t)size, sizeof(bios_size)))
 831                                         ? -EFAULT : 0;
 832                 case AMDGPU_INFO_VBIOS_IMAGE: {
 833                         uint8_t *bios;
 834                         uint32_t bios_offset = info->vbios_info.offset;
 835
 836                         if (bios_offset >= bios_size)
 837                                 return -EINVAL;
 838
 839                         bios = adev->bios + bios_offset;
 840                         return copy_to_user(out, bios,
 841                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 842                                         ? -EFAULT : 0;
 843                 }
 844                 default:
 845                         DRM_DEBUG_KMS("Invalid request %d\n",
 846                                         info->vbios_info.type);
 847                         return -EINVAL;
 848                 }
 849         }
 850         case AMDGPU_INFO_NUM_HANDLES: {
 851                 struct drm_amdgpu_info_num_handles handle;
 852
 853                 switch (info->query_hw_ip.type) {
 854                 case AMDGPU_HW_IP_UVD:
 855                         /* Starting Polaris, we support unlimited UVD handles */
 856                         if (adev->asic_type < CHIP_POLARIS10) {
 857                                 handle.uvd_max_handles = adev->uvd.max_handles;
 858                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 859
 860                                 return copy_to_user(out, &handle,
 861                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 862                         } else {
 863                                 return -ENODATA;
 864                         }
 865
 866                         break;
 867                 default:
 868                         return -EINVAL;
 869                 }
 870         }
 871         case AMDGPU_INFO_SENSOR: {
 872                 if (!adev->pm.dpm_enabled)
 873                         return -ENOENT;
 874
 875                 switch (info->sensor_info.type) {
 876                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 877                         /* get sclk in Mhz */
 878                         if (amdgpu_dpm_read_sensor(adev,
 879                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 880                                                    (void *)&ui32, &ui32_size)) {
 881                                 return -EINVAL;
 882                         }
 883                         ui32 /= 100;
 884                         break;
 885                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 886                         /* get mclk in Mhz */
 887                         if (amdgpu_dpm_read_sensor(adev,
 888                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 889                                                    (void *)&ui32, &ui32_size)) {
 890                                 return -EINVAL;
 891                         }
 892                         ui32 /= 100;
 893                         break;
 894                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 895                         /* get temperature in millidegrees C */
 896                         if (amdgpu_dpm_read_sensor(adev,
 897                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 898                                                    (void *)&ui32, &ui32_size)) {
 899                                 return -EINVAL;
 900                         }
 901                         break;
 902                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 903                         /* get GPU load */
 904                         if (amdgpu_dpm_read_sensor(adev,
 905                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 906                                                    (void *)&ui32, &ui32_size)) {
 907                                 return -EINVAL;
 908                         }
 909                         break;
 910                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 911                         /* get average GPU power */
 912                         if (amdgpu_dpm_read_sensor(adev,
 913                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 914                                                    (void *)&ui32, &ui32_size)) {
 915                                 return -EINVAL;
 916                         }
 917                         ui32 >>= 8;
 918                         break;
 919                 case AMDGPU_INFO_SENSOR_VDDNB:
 920                         /* get VDDNB in millivolts */
 921                         if (amdgpu_dpm_read_sensor(adev,
 922                                                    AMDGPU_PP_SENSOR_VDDNB,
 923                                                    (void *)&ui32, &ui32_size)) {
 924                                 return -EINVAL;
 925                         }
 926                         break;
 927                 case AMDGPU_INFO_SENSOR_VDDGFX:
 928                         /* get VDDGFX in millivolts */
 929                         if (amdgpu_dpm_read_sensor(adev,
 930                                                    AMDGPU_PP_SENSOR_VDDGFX,
 931                                                    (void *)&ui32, &ui32_size)) {
 932                                 return -EINVAL;
 933                         }
 934                         break;
 935                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 936                         /* get stable pstate sclk in Mhz */
 937                         if (amdgpu_dpm_read_sensor(adev,
 938                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 939                                                    (void *)&ui32, &ui32_size)) {
 940                                 return -EINVAL;
 941                         }
 942                         ui32 /= 100;
 943                         break;
 944                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 945                         /* get stable pstate mclk in Mhz */
 946                         if (amdgpu_dpm_read_sensor(adev,
 947                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 948                                                    (void *)&ui32, &ui32_size)) {
 949                                 return -EINVAL;
 950                         }
 951                         ui32 /= 100;
 952                         break;
 953                 default:
 954                         DRM_DEBUG_KMS("Invalid request %d\n",
 955                                       info->sensor_info.type);
 956                         return -EINVAL;
 957                 }
 958                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 959         }
 960         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 961                 ui32 = atomic_read(&adev->vram_lost_counter);
 962                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 963         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 964                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 965                 uint64_t ras_mask;
 966
 967                 if (!ras)
 968                         return -EINVAL;
 969                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 970
 971                 return copy_to_user(out, &ras_mask,
 972                                 min_t(u64, size, sizeof(ras_mask))) ?
 973                         -EFAULT : 0;
 974         }
 975         default:
 976                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 977                 return -EINVAL;
 978         }
 979         return 0;
 980 }
 981
 982
 983 /*
 984  * Outdated mess for old drm with Xorg being in charge (void function now).
 985  */
 986 /**
 987  * amdgpu_driver_lastclose_kms - drm callback for last close
 988  *
 989  * @dev: drm dev pointer
 990  *
 991  * Switch vga_switcheroo state after last close (all asics).
 992  */
 993 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 994 {
 995         drm_fb_helper_lastclose(dev);
 996         vga_switcheroo_process_delayed_switch();
 997 }
 998
 999 /**
1000  * amdgpu_driver_open_kms - drm callback for open
1001  *
1002  * @dev: drm dev pointer
1003  * @file_priv: drm file
1004  *
1005  * On device open, init vm on cayman+ (all asics).
1006  * Returns 0 on success, error on failure.
1007  */
1008 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1009 {
1010         struct amdgpu_device *adev = drm_to_adev(dev);
1011         struct amdgpu_fpriv *fpriv;
1012         int r, pasid;
1013
1014         /* Ensure IB tests are run on ring */
1015         flush_delayed_work(&adev->delayed_init_work);
1016
1017
1018         if (amdgpu_ras_intr_triggered()) {
1019                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1020                 return -EHWPOISON;
1021         }
1022
1023         file_priv->driver_priv = NULL;
1024
1025         r = pm_runtime_get_sync(dev->dev);
1026         if (r < 0)
1027                 goto pm_put;
1028
1029         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1030         if (unlikely(!fpriv)) {
1031                 r = -ENOMEM;
1032                 goto out_suspend;
1033         }
1034
1035         pasid = amdgpu_pasid_alloc(16);
1036         if (pasid < 0) {
1037                 dev_warn(adev->dev, "No more PASIDs available!");
1038                 pasid = 0;
1039         }
1040         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1041         if (r)
1042                 goto error_pasid;
1043
1044         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1045         if (!fpriv->prt_va) {
1046                 r = -ENOMEM;
1047                 goto error_vm;
1048         }
1049
1050         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1051                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1052
1053                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1054                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1055                 if (r)
1056                         goto error_vm;
1057         }
1058
1059         mutex_init(&fpriv->bo_list_lock);
1060         idr_init(&fpriv->bo_list_handles);
1061
1062         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1063
1064         file_priv->driver_priv = fpriv;
1065         goto out_suspend;
1066
1067 error_vm:
1068         amdgpu_vm_fini(adev, &fpriv->vm);
1069
1070 error_pasid:
1071         if (pasid)
1072                 amdgpu_pasid_free(pasid);
1073
1074         kfree(fpriv);
1075
1076 out_suspend:
1077         pm_runtime_mark_last_busy(dev->dev);
1078 pm_put:
1079         pm_runtime_put_autosuspend(dev->dev);
1080
1081         return r;
1082 }
1083
1084 /**
1085  * amdgpu_driver_postclose_kms - drm callback for post close
1086  *
1087  * @dev: drm dev pointer
1088  * @file_priv: drm file
1089  *
1090  * On device post close, tear down vm on cayman+ (all asics).
1091  */
1092 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1093                                  struct drm_file *file_priv)
1094 {
1095         struct amdgpu_device *adev = drm_to_adev(dev);
1096         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1097         struct amdgpu_bo_list *list;
1098         struct amdgpu_bo *pd;
1099         u32 pasid;
1100         int handle;
1101
1102         if (!fpriv)
1103                 return;
1104
1105         pm_runtime_get_sync(dev->dev);
1106
1107         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1108                 amdgpu_uvd_free_handles(adev, file_priv);
1109         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1110                 amdgpu_vce_free_handles(adev, file_priv);
1111
1112         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1113
1114         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1115                 /* TODO: how to handle reserve failure */
1116                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1117                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1118                 fpriv->csa_va = NULL;
1119                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1120         }
1121
1122         pasid = fpriv->vm.pasid;
1123         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1124
1125         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1126         amdgpu_vm_fini(adev, &fpriv->vm);
1127
1128         if (pasid)
1129                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1130         amdgpu_bo_unref(&pd);
1131
1132         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1133                 amdgpu_bo_list_put(list);
1134
1135         idr_destroy(&fpriv->bo_list_handles);
1136         mutex_destroy(&fpriv->bo_list_lock);
1137
1138         kfree(fpriv);
1139         file_priv->driver_priv = NULL;
1140
1141         pm_runtime_mark_last_busy(dev->dev);
1142         pm_runtime_put_autosuspend(dev->dev);
1143 }
1144
1145 /*
1146  * VBlank related functions.
1147  */
1148 /**
1149  * amdgpu_get_vblank_counter_kms - get frame count
1150  *
1151  * @crtc: crtc to get the frame count from
1152  *
1153  * Gets the frame count on the requested crtc (all asics).
1154  * Returns frame count on success, -EINVAL on failure.
1155  */
1156 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1157 {
1158         struct drm_device *dev = crtc->dev;
1159         unsigned int pipe = crtc->index;
1160         struct amdgpu_device *adev = drm_to_adev(dev);
1161         int vpos, hpos, stat;
1162         u32 count;
1163
1164         if (pipe >= adev->mode_info.num_crtc) {
1165                 DRM_ERROR("Invalid crtc %u\n", pipe);
1166                 return -EINVAL;
1167         }
1168
1169         /* The hw increments its frame counter at start of vsync, not at start
1170          * of vblank, as is required by DRM core vblank counter handling.
1171          * Cook the hw count here to make it appear to the caller as if it
1172          * incremented at start of vblank. We measure distance to start of
1173          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1174          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1175          * result by 1 to give the proper appearance to caller.
1176          */
1177         if (adev->mode_info.crtcs[pipe]) {
1178                 /* Repeat readout if needed to provide stable result if
1179                  * we cross start of vsync during the queries.
1180                  */
1181                 do {
1182                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1183                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1184                          * vpos as distance to start of vblank, instead of
1185                          * regular vertical scanout pos.
1186                          */
1187                         stat = amdgpu_display_get_crtc_scanoutpos(
1188                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1189                                 &vpos, &hpos, NULL, NULL,
1190                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1191                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1192
1193                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1194                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1195                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1196                 } else {
1197                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1198                                       pipe, vpos);
1199
1200                         /* Bump counter if we are at >= leading edge of vblank,
1201                          * but before vsync where vpos would turn negative and
1202                          * the hw counter really increments.
1203                          */
1204                         if (vpos >= 0)
1205                                 count++;
1206                 }
1207         } else {
1208                 /* Fallback to use value as is. */
1209                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1210                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1211         }
1212
1213         return count;
1214 }
1215
1216 /**
1217  * amdgpu_enable_vblank_kms - enable vblank interrupt
1218  *
1219  * @crtc: crtc to enable vblank interrupt for
1220  *
1221  * Enable the interrupt on the requested crtc (all asics).
1222  * Returns 0 on success, -EINVAL on failure.
1223  */
1224 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1225 {
1226         struct drm_device *dev = crtc->dev;
1227         unsigned int pipe = crtc->index;
1228         struct amdgpu_device *adev = drm_to_adev(dev);
1229         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1230
1231         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1232 }
1233
1234 /**
1235  * amdgpu_disable_vblank_kms - disable vblank interrupt
1236  *
1237  * @crtc: crtc to disable vblank interrupt for
1238  *
1239  * Disable the interrupt on the requested crtc (all asics).
1240  */
1241 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1242 {
1243         struct drm_device *dev = crtc->dev;
1244         unsigned int pipe = crtc->index;
1245         struct amdgpu_device *adev = drm_to_adev(dev);
1246         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1247
1248         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1249 }
1250
1251 /*
1252  * Debugfs info
1253  */
1254 #if defined(CONFIG_DEBUG_FS)
1255
1256 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1257 {
1258         struct drm_info_node *node = (struct drm_info_node *) m->private;
1259         struct drm_device *dev = node->minor->dev;
1260         struct amdgpu_device *adev = drm_to_adev(dev);
1261         struct drm_amdgpu_info_firmware fw_info;
1262         struct drm_amdgpu_query_fw query_fw;
1263         struct atom_context *ctx = adev->mode_info.atom_context;
1264         int ret, i;
1265
1266         /* VCE */
1267         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1268         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1269         if (ret)
1270                 return ret;
1271         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1272                    fw_info.feature, fw_info.ver);
1273
1274         /* UVD */
1275         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1276         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1277         if (ret)
1278                 return ret;
1279         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1280                    fw_info.feature, fw_info.ver);
1281
1282         /* GMC */
1283         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1284         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1285         if (ret)
1286                 return ret;
1287         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1288                    fw_info.feature, fw_info.ver);
1289
1290         /* ME */
1291         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1292         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1293         if (ret)
1294                 return ret;
1295         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1296                    fw_info.feature, fw_info.ver);
1297
1298         /* PFP */
1299         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1300         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1301         if (ret)
1302                 return ret;
1303         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1304                    fw_info.feature, fw_info.ver);
1305
1306         /* CE */
1307         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1308         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1309         if (ret)
1310                 return ret;
1311         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1312                    fw_info.feature, fw_info.ver);
1313
1314         /* RLC */
1315         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1316         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1317         if (ret)
1318                 return ret;
1319         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1320                    fw_info.feature, fw_info.ver);
1321
1322         /* RLC SAVE RESTORE LIST CNTL */
1323         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1324         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1325         if (ret)
1326                 return ret;
1327         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1328                    fw_info.feature, fw_info.ver);
1329
1330         /* RLC SAVE RESTORE LIST GPM MEM */
1331         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1332         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1333         if (ret)
1334                 return ret;
1335         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1336                    fw_info.feature, fw_info.ver);
1337
1338         /* RLC SAVE RESTORE LIST SRM MEM */
1339         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1340         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1341         if (ret)
1342                 return ret;
1343         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1344                    fw_info.feature, fw_info.ver);
1345
1346         /* MEC */
1347         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1348         query_fw.index = 0;
1349         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1350         if (ret)
1351                 return ret;
1352         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1353                    fw_info.feature, fw_info.ver);
1354
1355         /* MEC2 */
1356         if (adev->gfx.mec2_fw) {
1357                 query_fw.index = 1;
1358                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1359                 if (ret)
1360                         return ret;
1361                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1362                            fw_info.feature, fw_info.ver);
1363         }
1364
1365         /* PSP SOS */
1366         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1367         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1368         if (ret)
1369                 return ret;
1370         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1371                    fw_info.feature, fw_info.ver);
1372
1373
1374         /* PSP ASD */
1375         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1376         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1377         if (ret)
1378                 return ret;
1379         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1380                    fw_info.feature, fw_info.ver);
1381
1382         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1383         for (i = 0; i < 4; i++) {
1384                 query_fw.index = i;
1385                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1386                 if (ret)
1387                         continue;
1388                 switch (query_fw.index) {
1389                 case 0:
1390                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1391                                         "RAS", fw_info.feature, fw_info.ver);
1392                         break;
1393                 case 1:
1394                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1395                                         "XGMI", fw_info.feature, fw_info.ver);
1396                         break;
1397                 case 2:
1398                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1399                                         "HDCP", fw_info.feature, fw_info.ver);
1400                         break;
1401                 case 3:
1402                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1403                                         "DTM", fw_info.feature, fw_info.ver);
1404                         break;
1405                 default:
1406                         return -EINVAL;
1407                 }
1408         }
1409
1410         /* SMC */
1411         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1412         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1413         if (ret)
1414                 return ret;
1415         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1416                    fw_info.feature, fw_info.ver);
1417
1418         /* SDMA */
1419         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1420         for (i = 0; i < adev->sdma.num_instances; i++) {
1421                 query_fw.index = i;
1422                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1423                 if (ret)
1424                         return ret;
1425                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1426                            i, fw_info.feature, fw_info.ver);
1427         }
1428
1429         /* VCN */
1430         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1431         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1432         if (ret)
1433                 return ret;
1434         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1435                    fw_info.feature, fw_info.ver);
1436
1437         /* DMCU */
1438         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1439         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1440         if (ret)
1441                 return ret;
1442         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1443                    fw_info.feature, fw_info.ver);
1444
1445         /* DMCUB */
1446         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1447         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1448         if (ret)
1449                 return ret;
1450         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1451                    fw_info.feature, fw_info.ver);
1452
1453         /* TOC */
1454         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1455         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1456         if (ret)
1457                 return ret;
1458         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1459                    fw_info.feature, fw_info.ver);
1460
1461         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1462
1463         return 0;
1464 }
1465
1466 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1467         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1468 };
1469 #endif
1470
1471 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1472 {
1473 #if defined(CONFIG_DEBUG_FS)
1474         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1475                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1476 #else
1477         return 0;
1478 #endif
1479 }