drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (adev->runpm) {
  91                 pm_runtime_get_sync(dev->dev);
  92                 pm_runtime_forbid(dev->dev);
  93         }
  94
  95         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  96                 DRM_WARN("smart shift update failed\n");
  97
  98         amdgpu_acpi_fini(adev);
  99         amdgpu_device_fini_hw(adev);
 100 }
 101
 102 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 103 {
 104         struct amdgpu_gpu_instance *gpu_instance;
 105
 106         mutex_lock(&mgpu_info.mutex);
 107
 108         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 109                 DRM_ERROR("Cannot register more gpu instance\n");
 110                 mutex_unlock(&mgpu_info.mutex);
 111                 return;
 112         }
 113
 114         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 115         gpu_instance->adev = adev;
 116         gpu_instance->mgpu_fan_enabled = 0;
 117
 118         mgpu_info.num_gpu++;
 119         if (adev->flags & AMD_IS_APU)
 120                 mgpu_info.num_apu++;
 121         else
 122                 mgpu_info.num_dgpu++;
 123
 124         mutex_unlock(&mgpu_info.mutex);
 125 }
 126
 127 /**
 128  * amdgpu_driver_load_kms - Main load function for KMS.
 129  *
 130  * @adev: pointer to struct amdgpu_device
 131  * @flags: device flags
 132  *
 133  * This is the main load function for KMS (all asics).
 134  * Returns 0 on success, error on failure.
 135  */
 136 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 137 {
 138         struct drm_device *dev;
 139         struct pci_dev *parent;
 140         int r, acpi_status;
 141
 142         dev = adev_to_drm(adev);
 143
 144         if (amdgpu_has_atpx() &&
 145             (amdgpu_is_atpx_hybrid() ||
 146              amdgpu_has_atpx_dgpu_power_cntl()) &&
 147             ((flags & AMD_IS_APU) == 0) &&
 148             !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
 149                 flags |= AMD_IS_PX;
 150
 151         parent = pci_upstream_bridge(adev->pdev);
 152         adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
 153
 154         /* amdgpu_device_init should report only fatal error
 155          * like memory allocation failure or iomapping failure,
 156          * or memory manager initialization failure, it must
 157          * properly initialize the GPU MC controller and permit
 158          * VRAM allocation
 159          */
 160         r = amdgpu_device_init(adev, flags);
 161         if (r) {
 162                 dev_err(dev->dev, "Fatal error during GPU init\n");
 163                 goto out;
 164         }
 165
 166         if (amdgpu_device_supports_px(dev) &&
 167             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 168                 adev->runpm = true;
 169                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 170         } else if (amdgpu_device_supports_boco(dev) &&
 171                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 172                 adev->runpm = true;
 173                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 174         } else if (amdgpu_device_supports_baco(dev) &&
 175                    (amdgpu_runtime_pm != 0)) {
 176                 switch (adev->asic_type) {
 177                 case CHIP_VEGA20:
 178                 case CHIP_ARCTURUS:
 179                         /* enable runpm if runpm=1 */
 180                         if (amdgpu_runtime_pm > 0)
 181                                 adev->runpm = true;
 182                         break;
 183                 case CHIP_VEGA10:
 184                         /* turn runpm on if noretry=0 */
 185                         if (!adev->gmc.noretry)
 186                                 adev->runpm = true;
 187                         break;
 188                 default:
 189                         /* enable runpm on CI+ */
 190                         adev->runpm = true;
 191                         break;
 192                 }
 193                 if (adev->runpm)
 194                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 195         }
 196
 197         /* Call ACPI methods: require modeset init
 198          * but failure is not fatal
 199          */
 200
 201         acpi_status = amdgpu_acpi_init(adev);
 202         if (acpi_status)
 203                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 204
 205         if (adev->runpm) {
 206                 /* only need to skip on ATPX */
 207                 if (amdgpu_device_supports_px(dev))
 208                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 209                 /* we want direct complete for BOCO */
 210                 if (amdgpu_device_supports_boco(dev))
 211                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
 212                                                 DPM_FLAG_SMART_SUSPEND |
 213                                                 DPM_FLAG_MAY_SKIP_RESUME);
 214                 pm_runtime_use_autosuspend(dev->dev);
 215                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 216                 pm_runtime_allow(dev->dev);
 217                 pm_runtime_mark_last_busy(dev->dev);
 218                 pm_runtime_put_autosuspend(dev->dev);
 219         }
 220
 221         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 222                 DRM_WARN("smart shift update failed\n");
 223
 224 out:
 225         if (r) {
 226                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 227                 if (adev->rmmio && adev->runpm)
 228                         pm_runtime_put_noidle(dev->dev);
 229                 amdgpu_driver_unload_kms(dev);
 230         }
 231
 232         return r;
 233 }
 234
 235 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 236                                 struct drm_amdgpu_query_fw *query_fw,
 237                                 struct amdgpu_device *adev)
 238 {
 239         switch (query_fw->fw_type) {
 240         case AMDGPU_INFO_FW_VCE:
 241                 fw_info->ver = adev->vce.fw_version;
 242                 fw_info->feature = adev->vce.fb_version;
 243                 break;
 244         case AMDGPU_INFO_FW_UVD:
 245                 fw_info->ver = adev->uvd.fw_version;
 246                 fw_info->feature = 0;
 247                 break;
 248         case AMDGPU_INFO_FW_VCN:
 249                 fw_info->ver = adev->vcn.fw_version;
 250                 fw_info->feature = 0;
 251                 break;
 252         case AMDGPU_INFO_FW_GMC:
 253                 fw_info->ver = adev->gmc.fw_version;
 254                 fw_info->feature = 0;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_ME:
 257                 fw_info->ver = adev->gfx.me_fw_version;
 258                 fw_info->feature = adev->gfx.me_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_PFP:
 261                 fw_info->ver = adev->gfx.pfp_fw_version;
 262                 fw_info->feature = adev->gfx.pfp_feature_version;
 263                 break;
 264         case AMDGPU_INFO_FW_GFX_CE:
 265                 fw_info->ver = adev->gfx.ce_fw_version;
 266                 fw_info->feature = adev->gfx.ce_feature_version;
 267                 break;
 268         case AMDGPU_INFO_FW_GFX_RLC:
 269                 fw_info->ver = adev->gfx.rlc_fw_version;
 270                 fw_info->feature = adev->gfx.rlc_feature_version;
 271                 break;
 272         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 273                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 274                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 275                 break;
 276         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 277                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 278                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 279                 break;
 280         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 281                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 282                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 283                 break;
 284         case AMDGPU_INFO_FW_GFX_MEC:
 285                 if (query_fw->index == 0) {
 286                         fw_info->ver = adev->gfx.mec_fw_version;
 287                         fw_info->feature = adev->gfx.mec_feature_version;
 288                 } else if (query_fw->index == 1) {
 289                         fw_info->ver = adev->gfx.mec2_fw_version;
 290                         fw_info->feature = adev->gfx.mec2_feature_version;
 291                 } else
 292                         return -EINVAL;
 293                 break;
 294         case AMDGPU_INFO_FW_SMC:
 295                 fw_info->ver = adev->pm.fw_version;
 296                 fw_info->feature = 0;
 297                 break;
 298         case AMDGPU_INFO_FW_TA:
 299                 switch (query_fw->index) {
 300                 case TA_FW_TYPE_PSP_XGMI:
 301                         fw_info->ver = adev->psp.ta_fw_version;
 302                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 303                         break;
 304                 case TA_FW_TYPE_PSP_RAS:
 305                         fw_info->ver = adev->psp.ta_fw_version;
 306                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 307                         break;
 308                 case TA_FW_TYPE_PSP_HDCP:
 309                         fw_info->ver = adev->psp.ta_fw_version;
 310                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 311                         break;
 312                 case TA_FW_TYPE_PSP_DTM:
 313                         fw_info->ver = adev->psp.ta_fw_version;
 314                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 315                         break;
 316                 case TA_FW_TYPE_PSP_RAP:
 317                         fw_info->ver = adev->psp.ta_fw_version;
 318                         fw_info->feature = adev->psp.ta_rap_ucode_version;
 319                         break;
 320                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 321                         fw_info->ver = adev->psp.ta_fw_version;
 322                         fw_info->feature = adev->psp.ta_securedisplay_ucode_version;
 323                         break;
 324                 default:
 325                         return -EINVAL;
 326                 }
 327                 break;
 328         case AMDGPU_INFO_FW_SDMA:
 329                 if (query_fw->index >= adev->sdma.num_instances)
 330                         return -EINVAL;
 331                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 332                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 333                 break;
 334         case AMDGPU_INFO_FW_SOS:
 335                 fw_info->ver = adev->psp.sos_fw_version;
 336                 fw_info->feature = adev->psp.sos_feature_version;
 337                 break;
 338         case AMDGPU_INFO_FW_ASD:
 339                 fw_info->ver = adev->psp.asd_fw_version;
 340                 fw_info->feature = adev->psp.asd_feature_version;
 341                 break;
 342         case AMDGPU_INFO_FW_DMCU:
 343                 fw_info->ver = adev->dm.dmcu_fw_version;
 344                 fw_info->feature = 0;
 345                 break;
 346         case AMDGPU_INFO_FW_DMCUB:
 347                 fw_info->ver = adev->dm.dmcub_fw_version;
 348                 fw_info->feature = 0;
 349                 break;
 350         case AMDGPU_INFO_FW_TOC:
 351                 fw_info->ver = adev->psp.toc_fw_version;
 352                 fw_info->feature = adev->psp.toc_feature_version;
 353                 break;
 354         default:
 355                 return -EINVAL;
 356         }
 357         return 0;
 358 }
 359
 360 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 361                              struct drm_amdgpu_info *info,
 362                              struct drm_amdgpu_info_hw_ip *result)
 363 {
 364         uint32_t ib_start_alignment = 0;
 365         uint32_t ib_size_alignment = 0;
 366         enum amd_ip_block_type type;
 367         unsigned int num_rings = 0;
 368         unsigned int i, j;
 369
 370         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 371                 return -EINVAL;
 372
 373         switch (info->query_hw_ip.type) {
 374         case AMDGPU_HW_IP_GFX:
 375                 type = AMD_IP_BLOCK_TYPE_GFX;
 376                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 377                         if (adev->gfx.gfx_ring[i].sched.ready)
 378                                 ++num_rings;
 379                 ib_start_alignment = 32;
 380                 ib_size_alignment = 32;
 381                 break;
 382         case AMDGPU_HW_IP_COMPUTE:
 383                 type = AMD_IP_BLOCK_TYPE_GFX;
 384                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 385                         if (adev->gfx.compute_ring[i].sched.ready)
 386                                 ++num_rings;
 387                 ib_start_alignment = 32;
 388                 ib_size_alignment = 32;
 389                 break;
 390         case AMDGPU_HW_IP_DMA:
 391                 type = AMD_IP_BLOCK_TYPE_SDMA;
 392                 for (i = 0; i < adev->sdma.num_instances; i++)
 393                         if (adev->sdma.instance[i].ring.sched.ready)
 394                                 ++num_rings;
 395                 ib_start_alignment = 256;
 396                 ib_size_alignment = 4;
 397                 break;
 398         case AMDGPU_HW_IP_UVD:
 399                 type = AMD_IP_BLOCK_TYPE_UVD;
 400                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 401                         if (adev->uvd.harvest_config & (1 << i))
 402                                 continue;
 403
 404                         if (adev->uvd.inst[i].ring.sched.ready)
 405                                 ++num_rings;
 406                 }
 407                 ib_start_alignment = 64;
 408                 ib_size_alignment = 64;
 409                 break;
 410         case AMDGPU_HW_IP_VCE:
 411                 type = AMD_IP_BLOCK_TYPE_VCE;
 412                 for (i = 0; i < adev->vce.num_rings; i++)
 413                         if (adev->vce.ring[i].sched.ready)
 414                                 ++num_rings;
 415                 ib_start_alignment = 4;
 416                 ib_size_alignment = 1;
 417                 break;
 418         case AMDGPU_HW_IP_UVD_ENC:
 419                 type = AMD_IP_BLOCK_TYPE_UVD;
 420                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 421                         if (adev->uvd.harvest_config & (1 << i))
 422                                 continue;
 423
 424                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 425                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 426                                         ++num_rings;
 427                 }
 428                 ib_start_alignment = 64;
 429                 ib_size_alignment = 64;
 430                 break;
 431         case AMDGPU_HW_IP_VCN_DEC:
 432                 type = AMD_IP_BLOCK_TYPE_VCN;
 433                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 434                         if (adev->uvd.harvest_config & (1 << i))
 435                                 continue;
 436
 437                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 438                                 ++num_rings;
 439                 }
 440                 ib_start_alignment = 16;
 441                 ib_size_alignment = 16;
 442                 break;
 443         case AMDGPU_HW_IP_VCN_ENC:
 444                 type = AMD_IP_BLOCK_TYPE_VCN;
 445                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 446                         if (adev->uvd.harvest_config & (1 << i))
 447                                 continue;
 448
 449                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 450                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 451                                         ++num_rings;
 452                 }
 453                 ib_start_alignment = 64;
 454                 ib_size_alignment = 1;
 455                 break;
 456         case AMDGPU_HW_IP_VCN_JPEG:
 457                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 458                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 459
 460                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 461                         if (adev->jpeg.harvest_config & (1 << i))
 462                                 continue;
 463
 464                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 465                                 ++num_rings;
 466                 }
 467                 ib_start_alignment = 16;
 468                 ib_size_alignment = 16;
 469                 break;
 470         default:
 471                 return -EINVAL;
 472         }
 473
 474         for (i = 0; i < adev->num_ip_blocks; i++)
 475                 if (adev->ip_blocks[i].version->type == type &&
 476                     adev->ip_blocks[i].status.valid)
 477                         break;
 478
 479         if (i == adev->num_ip_blocks)
 480                 return 0;
 481
 482         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 483                         num_rings);
 484
 485         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 486         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 487         result->capabilities_flags = 0;
 488         result->available_rings = (1 << num_rings) - 1;
 489         result->ib_start_alignment = ib_start_alignment;
 490         result->ib_size_alignment = ib_size_alignment;
 491         return 0;
 492 }
 493
 494 /*
 495  * Userspace get information ioctl
 496  */
 497 /**
 498  * amdgpu_info_ioctl - answer a device specific request.
 499  *
 500  * @dev: drm device pointer
 501  * @data: request object
 502  * @filp: drm filp
 503  *
 504  * This function is used to pass device specific parameters to the userspace
 505  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 506  * etc. (all asics).
 507  * Returns 0 on success, -EINVAL on failure.
 508  */
 509 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 510 {
 511         struct amdgpu_device *adev = drm_to_adev(dev);
 512         struct drm_amdgpu_info *info = data;
 513         struct amdgpu_mode_info *minfo = &adev->mode_info;
 514         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 515         uint32_t size = info->return_size;
 516         struct drm_crtc *crtc;
 517         uint32_t ui32 = 0;
 518         uint64_t ui64 = 0;
 519         int i, found;
 520         int ui32_size = sizeof(ui32);
 521
 522         if (!info->return_size || !info->return_pointer)
 523                 return -EINVAL;
 524
 525         switch (info->query) {
 526         case AMDGPU_INFO_ACCEL_WORKING:
 527                 ui32 = adev->accel_working;
 528                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 529         case AMDGPU_INFO_CRTC_FROM_ID:
 530                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 531                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 532                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 533                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 534                                 ui32 = amdgpu_crtc->crtc_id;
 535                                 found = 1;
 536                                 break;
 537                         }
 538                 }
 539                 if (!found) {
 540                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 541                         return -EINVAL;
 542                 }
 543                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 544         case AMDGPU_INFO_HW_IP_INFO: {
 545                 struct drm_amdgpu_info_hw_ip ip = {};
 546                 int ret;
 547
 548                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 549                 if (ret)
 550                         return ret;
 551
 552                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 553                 return ret ? -EFAULT : 0;
 554         }
 555         case AMDGPU_INFO_HW_IP_COUNT: {
 556                 enum amd_ip_block_type type;
 557                 uint32_t count = 0;
 558
 559                 switch (info->query_hw_ip.type) {
 560                 case AMDGPU_HW_IP_GFX:
 561                         type = AMD_IP_BLOCK_TYPE_GFX;
 562                         break;
 563                 case AMDGPU_HW_IP_COMPUTE:
 564                         type = AMD_IP_BLOCK_TYPE_GFX;
 565                         break;
 566                 case AMDGPU_HW_IP_DMA:
 567                         type = AMD_IP_BLOCK_TYPE_SDMA;
 568                         break;
 569                 case AMDGPU_HW_IP_UVD:
 570                         type = AMD_IP_BLOCK_TYPE_UVD;
 571                         break;
 572                 case AMDGPU_HW_IP_VCE:
 573                         type = AMD_IP_BLOCK_TYPE_VCE;
 574                         break;
 575                 case AMDGPU_HW_IP_UVD_ENC:
 576                         type = AMD_IP_BLOCK_TYPE_UVD;
 577                         break;
 578                 case AMDGPU_HW_IP_VCN_DEC:
 579                 case AMDGPU_HW_IP_VCN_ENC:
 580                         type = AMD_IP_BLOCK_TYPE_VCN;
 581                         break;
 582                 case AMDGPU_HW_IP_VCN_JPEG:
 583                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 584                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 585                         break;
 586                 default:
 587                         return -EINVAL;
 588                 }
 589
 590                 for (i = 0; i < adev->num_ip_blocks; i++)
 591                         if (adev->ip_blocks[i].version->type == type &&
 592                             adev->ip_blocks[i].status.valid &&
 593                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 594                                 count++;
 595
 596                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 597         }
 598         case AMDGPU_INFO_TIMESTAMP:
 599                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 600                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 601         case AMDGPU_INFO_FW_VERSION: {
 602                 struct drm_amdgpu_info_firmware fw_info;
 603                 int ret;
 604
 605                 /* We only support one instance of each IP block right now. */
 606                 if (info->query_fw.ip_instance != 0)
 607                         return -EINVAL;
 608
 609                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 610                 if (ret)
 611                         return ret;
 612
 613                 return copy_to_user(out, &fw_info,
 614                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 615         }
 616         case AMDGPU_INFO_NUM_BYTES_MOVED:
 617                 ui64 = atomic64_read(&adev->num_bytes_moved);
 618                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 619         case AMDGPU_INFO_NUM_EVICTIONS:
 620                 ui64 = atomic64_read(&adev->num_evictions);
 621                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 622         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 623                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 624                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 625         case AMDGPU_INFO_VRAM_USAGE:
 626                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 627                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 628         case AMDGPU_INFO_VIS_VRAM_USAGE:
 629                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 630                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 631         case AMDGPU_INFO_GTT_USAGE:
 632                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 633                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 634         case AMDGPU_INFO_GDS_CONFIG: {
 635                 struct drm_amdgpu_info_gds gds_info;
 636
 637                 memset(&gds_info, 0, sizeof(gds_info));
 638                 gds_info.compute_partition_size = adev->gds.gds_size;
 639                 gds_info.gds_total_size = adev->gds.gds_size;
 640                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 641                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 642                 return copy_to_user(out, &gds_info,
 643                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 644         }
 645         case AMDGPU_INFO_VRAM_GTT: {
 646                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 647
 648                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 649                         atomic64_read(&adev->vram_pin_size) -
 650                         AMDGPU_VM_RESERVED_VRAM;
 651                 vram_gtt.vram_cpu_accessible_size =
 652                         min(adev->gmc.visible_vram_size -
 653                             atomic64_read(&adev->visible_pin_size),
 654                             vram_gtt.vram_size);
 655                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 656                 vram_gtt.gtt_size *= PAGE_SIZE;
 657                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 658                 return copy_to_user(out, &vram_gtt,
 659                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 660         }
 661         case AMDGPU_INFO_MEMORY: {
 662                 struct drm_amdgpu_memory_info mem;
 663                 struct ttm_resource_manager *vram_man =
 664                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 665                 struct ttm_resource_manager *gtt_man =
 666                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 667                 memset(&mem, 0, sizeof(mem));
 668                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 669                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 670                         atomic64_read(&adev->vram_pin_size) -
 671                         AMDGPU_VM_RESERVED_VRAM;
 672                 mem.vram.heap_usage =
 673                         amdgpu_vram_mgr_usage(vram_man);
 674                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 675
 676                 mem.cpu_accessible_vram.total_heap_size =
 677                         adev->gmc.visible_vram_size;
 678                 mem.cpu_accessible_vram.usable_heap_size =
 679                         min(adev->gmc.visible_vram_size -
 680                             atomic64_read(&adev->visible_pin_size),
 681                             mem.vram.usable_heap_size);
 682                 mem.cpu_accessible_vram.heap_usage =
 683                         amdgpu_vram_mgr_vis_usage(vram_man);
 684                 mem.cpu_accessible_vram.max_allocation =
 685                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 686
 687                 mem.gtt.total_heap_size = gtt_man->size;
 688                 mem.gtt.total_heap_size *= PAGE_SIZE;
 689                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 690                         atomic64_read(&adev->gart_pin_size);
 691                 mem.gtt.heap_usage =
 692                         amdgpu_gtt_mgr_usage(gtt_man);
 693                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 694
 695                 return copy_to_user(out, &mem,
 696                                     min((size_t)size, sizeof(mem)))
 697                                     ? -EFAULT : 0;
 698         }
 699         case AMDGPU_INFO_READ_MMR_REG: {
 700                 unsigned n, alloc_size;
 701                 uint32_t *regs;
 702                 unsigned se_num = (info->read_mmr_reg.instance >>
 703                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 704                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 705                 unsigned sh_num = (info->read_mmr_reg.instance >>
 706                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 707                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 708
 709                 /* set full masks if the userspace set all bits
 710                  * in the bitfields */
 711                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 712                         se_num = 0xffffffff;
 713                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 714                         return -EINVAL;
 715                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 716                         sh_num = 0xffffffff;
 717                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 718                         return -EINVAL;
 719
 720                 if (info->read_mmr_reg.count > 128)
 721                         return -EINVAL;
 722
 723                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 724                 if (!regs)
 725                         return -ENOMEM;
 726                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 727
 728                 amdgpu_gfx_off_ctrl(adev, false);
 729                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 730                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 731                                                       info->read_mmr_reg.dword_offset + i,
 732                                                       &regs[i])) {
 733                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 734                                               info->read_mmr_reg.dword_offset + i);
 735                                 kfree(regs);
 736                                 amdgpu_gfx_off_ctrl(adev, true);
 737                                 return -EFAULT;
 738                         }
 739                 }
 740                 amdgpu_gfx_off_ctrl(adev, true);
 741                 n = copy_to_user(out, regs, min(size, alloc_size));
 742                 kfree(regs);
 743                 return n ? -EFAULT : 0;
 744         }
 745         case AMDGPU_INFO_DEV_INFO: {
 746                 struct drm_amdgpu_info_device *dev_info;
 747                 uint64_t vm_size;
 748                 int ret;
 749
 750                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 751                 if (!dev_info)
 752                         return -ENOMEM;
 753
 754                 dev_info->device_id = adev->pdev->device;
 755                 dev_info->chip_rev = adev->rev_id;
 756                 dev_info->external_rev = adev->external_rev_id;
 757                 dev_info->pci_rev = adev->pdev->revision;
 758                 dev_info->family = adev->family;
 759                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 760                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 761                 /* return all clocks in KHz */
 762                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 763                 if (adev->pm.dpm_enabled) {
 764                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 765                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 766                 } else {
 767                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 768                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 769                 }
 770                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 771                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 772                         adev->gfx.config.max_shader_engines;
 773                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 774                 dev_info->_pad = 0;
 775                 dev_info->ids_flags = 0;
 776                 if (adev->flags & AMD_IS_APU)
 777                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 778                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 779                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 780                 if (amdgpu_is_tmz(adev))
 781                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 782
 783                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 784                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 785
 786                 /* Older VCE FW versions are buggy and can handle only 40bits */
 787                 if (adev->vce.fw_version &&
 788                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 789                         vm_size = min(vm_size, 1ULL << 40);
 790
 791                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 792                 dev_info->virtual_address_max =
 793                         min(vm_size, AMDGPU_GMC_HOLE_START);
 794
 795                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 796                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 797                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 798                 }
 799                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 800                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 801                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 802                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 803                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 804                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 805                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 806                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 807                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 808                        sizeof(adev->gfx.cu_info.bitmap));
 809                 dev_info->vram_type = adev->gmc.vram_type;
 810                 dev_info->vram_bit_width = adev->gmc.vram_width;
 811                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 812                 dev_info->gc_double_offchip_lds_buf =
 813                         adev->gfx.config.double_offchip_lds_buf;
 814                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 815                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 816                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 817                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 818                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 819                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 820                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 821
 822                 if (adev->family >= AMDGPU_FAMILY_NV)
 823                         dev_info->pa_sc_tile_steering_override =
 824                                 adev->gfx.config.pa_sc_tile_steering_override;
 825
 826                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 827
 828                 ret = copy_to_user(out, dev_info,
 829                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 830                 kfree(dev_info);
 831                 return ret;
 832         }
 833         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 834                 unsigned i;
 835                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 836                 struct amd_vce_state *vce_state;
 837
 838                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 839                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 840                         if (vce_state) {
 841                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 842                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 843                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 844                                 vce_clk_table.num_valid_entries++;
 845                         }
 846                 }
 847
 848                 return copy_to_user(out, &vce_clk_table,
 849                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 850         }
 851         case AMDGPU_INFO_VBIOS: {
 852                 uint32_t bios_size = adev->bios_size;
 853
 854                 switch (info->vbios_info.type) {
 855                 case AMDGPU_INFO_VBIOS_SIZE:
 856                         return copy_to_user(out, &bios_size,
 857                                         min((size_t)size, sizeof(bios_size)))
 858                                         ? -EFAULT : 0;
 859                 case AMDGPU_INFO_VBIOS_IMAGE: {
 860                         uint8_t *bios;
 861                         uint32_t bios_offset = info->vbios_info.offset;
 862
 863                         if (bios_offset >= bios_size)
 864                                 return -EINVAL;
 865
 866                         bios = adev->bios + bios_offset;
 867                         return copy_to_user(out, bios,
 868                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 869                                         ? -EFAULT : 0;
 870                 }
 871                 case AMDGPU_INFO_VBIOS_INFO: {
 872                         struct drm_amdgpu_info_vbios vbios_info = {};
 873                         struct atom_context *atom_context;
 874
 875                         atom_context = adev->mode_info.atom_context;
 876                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 877                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 878                         vbios_info.version = atom_context->version;
 879                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 880                                                 sizeof(atom_context->vbios_ver_str));
 881                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 882
 883                         return copy_to_user(out, &vbios_info,
 884                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 885                 }
 886                 default:
 887                         DRM_DEBUG_KMS("Invalid request %d\n",
 888                                         info->vbios_info.type);
 889                         return -EINVAL;
 890                 }
 891         }
 892         case AMDGPU_INFO_NUM_HANDLES: {
 893                 struct drm_amdgpu_info_num_handles handle;
 894
 895                 switch (info->query_hw_ip.type) {
 896                 case AMDGPU_HW_IP_UVD:
 897                         /* Starting Polaris, we support unlimited UVD handles */
 898                         if (adev->asic_type < CHIP_POLARIS10) {
 899                                 handle.uvd_max_handles = adev->uvd.max_handles;
 900                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 901
 902                                 return copy_to_user(out, &handle,
 903                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 904                         } else {
 905                                 return -ENODATA;
 906                         }
 907
 908                         break;
 909                 default:
 910                         return -EINVAL;
 911                 }
 912         }
 913         case AMDGPU_INFO_SENSOR: {
 914                 if (!adev->pm.dpm_enabled)
 915                         return -ENOENT;
 916
 917                 switch (info->sensor_info.type) {
 918                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 919                         /* get sclk in Mhz */
 920                         if (amdgpu_dpm_read_sensor(adev,
 921                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 922                                                    (void *)&ui32, &ui32_size)) {
 923                                 return -EINVAL;
 924                         }
 925                         ui32 /= 100;
 926                         break;
 927                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 928                         /* get mclk in Mhz */
 929                         if (amdgpu_dpm_read_sensor(adev,
 930                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 931                                                    (void *)&ui32, &ui32_size)) {
 932                                 return -EINVAL;
 933                         }
 934                         ui32 /= 100;
 935                         break;
 936                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 937                         /* get temperature in millidegrees C */
 938                         if (amdgpu_dpm_read_sensor(adev,
 939                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 940                                                    (void *)&ui32, &ui32_size)) {
 941                                 return -EINVAL;
 942                         }
 943                         break;
 944                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 945                         /* get GPU load */
 946                         if (amdgpu_dpm_read_sensor(adev,
 947                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 948                                                    (void *)&ui32, &ui32_size)) {
 949                                 return -EINVAL;
 950                         }
 951                         break;
 952                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 953                         /* get average GPU power */
 954                         if (amdgpu_dpm_read_sensor(adev,
 955                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 956                                                    (void *)&ui32, &ui32_size)) {
 957                                 return -EINVAL;
 958                         }
 959                         ui32 >>= 8;
 960                         break;
 961                 case AMDGPU_INFO_SENSOR_VDDNB:
 962                         /* get VDDNB in millivolts */
 963                         if (amdgpu_dpm_read_sensor(adev,
 964                                                    AMDGPU_PP_SENSOR_VDDNB,
 965                                                    (void *)&ui32, &ui32_size)) {
 966                                 return -EINVAL;
 967                         }
 968                         break;
 969                 case AMDGPU_INFO_SENSOR_VDDGFX:
 970                         /* get VDDGFX in millivolts */
 971                         if (amdgpu_dpm_read_sensor(adev,
 972                                                    AMDGPU_PP_SENSOR_VDDGFX,
 973                                                    (void *)&ui32, &ui32_size)) {
 974                                 return -EINVAL;
 975                         }
 976                         break;
 977                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 978                         /* get stable pstate sclk in Mhz */
 979                         if (amdgpu_dpm_read_sensor(adev,
 980                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 981                                                    (void *)&ui32, &ui32_size)) {
 982                                 return -EINVAL;
 983                         }
 984                         ui32 /= 100;
 985                         break;
 986                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 987                         /* get stable pstate mclk in Mhz */
 988                         if (amdgpu_dpm_read_sensor(adev,
 989                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 990                                                    (void *)&ui32, &ui32_size)) {
 991                                 return -EINVAL;
 992                         }
 993                         ui32 /= 100;
 994                         break;
 995                 default:
 996                         DRM_DEBUG_KMS("Invalid request %d\n",
 997                                       info->sensor_info.type);
 998                         return -EINVAL;
 999                 }
1000                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1001         }
1002         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1003                 ui32 = atomic_read(&adev->vram_lost_counter);
1004                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1005         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1006                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1007                 uint64_t ras_mask;
1008
1009                 if (!ras)
1010                         return -EINVAL;
1011                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1012
1013                 return copy_to_user(out, &ras_mask,
1014                                 min_t(u64, size, sizeof(ras_mask))) ?
1015                         -EFAULT : 0;
1016         }
1017         case AMDGPU_INFO_VIDEO_CAPS: {
1018                 const struct amdgpu_video_codecs *codecs;
1019                 struct drm_amdgpu_info_video_caps *caps;
1020                 int r;
1021
1022                 switch (info->video_cap.type) {
1023                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1024                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1025                         if (r)
1026                                 return -EINVAL;
1027                         break;
1028                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1029                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1030                         if (r)
1031                                 return -EINVAL;
1032                         break;
1033                 default:
1034                         DRM_DEBUG_KMS("Invalid request %d\n",
1035                                       info->video_cap.type);
1036                         return -EINVAL;
1037                 }
1038
1039                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1040                 if (!caps)
1041                         return -ENOMEM;
1042
1043                 for (i = 0; i < codecs->codec_count; i++) {
1044                         int idx = codecs->codec_array[i].codec_type;
1045
1046                         switch (idx) {
1047                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1048                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1049                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1050                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1051                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1052                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1053                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1054                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1055                                 caps->codec_info[idx].valid = 1;
1056                                 caps->codec_info[idx].max_width =
1057                                         codecs->codec_array[i].max_width;
1058                                 caps->codec_info[idx].max_height =
1059                                         codecs->codec_array[i].max_height;
1060                                 caps->codec_info[idx].max_pixels_per_frame =
1061                                         codecs->codec_array[i].max_pixels_per_frame;
1062                                 caps->codec_info[idx].max_level =
1063                                         codecs->codec_array[i].max_level;
1064                                 break;
1065                         default:
1066                                 break;
1067                         }
1068                 }
1069                 r = copy_to_user(out, caps,
1070                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1071                 kfree(caps);
1072                 return r;
1073         }
1074         default:
1075                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1076                 return -EINVAL;
1077         }
1078         return 0;
1079 }
1080
1081
1082 /*
1083  * Outdated mess for old drm with Xorg being in charge (void function now).
1084  */
1085 /**
1086  * amdgpu_driver_lastclose_kms - drm callback for last close
1087  *
1088  * @dev: drm dev pointer
1089  *
1090  * Switch vga_switcheroo state after last close (all asics).
1091  */
1092 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1093 {
1094         drm_fb_helper_lastclose(dev);
1095         vga_switcheroo_process_delayed_switch();
1096 }
1097
1098 /**
1099  * amdgpu_driver_open_kms - drm callback for open
1100  *
1101  * @dev: drm dev pointer
1102  * @file_priv: drm file
1103  *
1104  * On device open, init vm on cayman+ (all asics).
1105  * Returns 0 on success, error on failure.
1106  */
1107 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1108 {
1109         struct amdgpu_device *adev = drm_to_adev(dev);
1110         struct amdgpu_fpriv *fpriv;
1111         int r, pasid;
1112
1113         /* Ensure IB tests are run on ring */
1114         flush_delayed_work(&adev->delayed_init_work);
1115
1116
1117         if (amdgpu_ras_intr_triggered()) {
1118                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1119                 return -EHWPOISON;
1120         }
1121
1122         file_priv->driver_priv = NULL;
1123
1124         r = pm_runtime_get_sync(dev->dev);
1125         if (r < 0)
1126                 goto pm_put;
1127
1128         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1129         if (unlikely(!fpriv)) {
1130                 r = -ENOMEM;
1131                 goto out_suspend;
1132         }
1133
1134         pasid = amdgpu_pasid_alloc(16);
1135         if (pasid < 0) {
1136                 dev_warn(adev->dev, "No more PASIDs available!");
1137                 pasid = 0;
1138         }
1139
1140         r = amdgpu_vm_init(adev, &fpriv->vm, pasid);
1141         if (r)
1142                 goto error_pasid;
1143
1144         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1145         if (!fpriv->prt_va) {
1146                 r = -ENOMEM;
1147                 goto error_vm;
1148         }
1149
1150         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1151                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1152
1153                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1154                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1155                 if (r)
1156                         goto error_vm;
1157         }
1158
1159         mutex_init(&fpriv->bo_list_lock);
1160         idr_init(&fpriv->bo_list_handles);
1161
1162         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1163
1164         file_priv->driver_priv = fpriv;
1165         goto out_suspend;
1166
1167 error_vm:
1168         amdgpu_vm_fini(adev, &fpriv->vm);
1169
1170 error_pasid:
1171         if (pasid)
1172                 amdgpu_pasid_free(pasid);
1173
1174         kfree(fpriv);
1175
1176 out_suspend:
1177         pm_runtime_mark_last_busy(dev->dev);
1178 pm_put:
1179         pm_runtime_put_autosuspend(dev->dev);
1180
1181         return r;
1182 }
1183
1184 /**
1185  * amdgpu_driver_postclose_kms - drm callback for post close
1186  *
1187  * @dev: drm dev pointer
1188  * @file_priv: drm file
1189  *
1190  * On device post close, tear down vm on cayman+ (all asics).
1191  */
1192 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1193                                  struct drm_file *file_priv)
1194 {
1195         struct amdgpu_device *adev = drm_to_adev(dev);
1196         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1197         struct amdgpu_bo_list *list;
1198         struct amdgpu_bo *pd;
1199         u32 pasid;
1200         int handle;
1201
1202         if (!fpriv)
1203                 return;
1204
1205         pm_runtime_get_sync(dev->dev);
1206
1207         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1208                 amdgpu_uvd_free_handles(adev, file_priv);
1209         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1210                 amdgpu_vce_free_handles(adev, file_priv);
1211
1212         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1213
1214         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1215                 /* TODO: how to handle reserve failure */
1216                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1217                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1218                 fpriv->csa_va = NULL;
1219                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1220         }
1221
1222         pasid = fpriv->vm.pasid;
1223         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1224
1225         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1226         amdgpu_vm_fini(adev, &fpriv->vm);
1227
1228         if (pasid)
1229                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1230         amdgpu_bo_unref(&pd);
1231
1232         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1233                 amdgpu_bo_list_put(list);
1234
1235         idr_destroy(&fpriv->bo_list_handles);
1236         mutex_destroy(&fpriv->bo_list_lock);
1237
1238         kfree(fpriv);
1239         file_priv->driver_priv = NULL;
1240
1241         pm_runtime_mark_last_busy(dev->dev);
1242         pm_runtime_put_autosuspend(dev->dev);
1243 }
1244
1245
1246 void amdgpu_driver_release_kms(struct drm_device *dev)
1247 {
1248         struct amdgpu_device *adev = drm_to_adev(dev);
1249
1250         amdgpu_device_fini_sw(adev);
1251         pci_set_drvdata(adev->pdev, NULL);
1252 }
1253
1254 /*
1255  * VBlank related functions.
1256  */
1257 /**
1258  * amdgpu_get_vblank_counter_kms - get frame count
1259  *
1260  * @crtc: crtc to get the frame count from
1261  *
1262  * Gets the frame count on the requested crtc (all asics).
1263  * Returns frame count on success, -EINVAL on failure.
1264  */
1265 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1266 {
1267         struct drm_device *dev = crtc->dev;
1268         unsigned int pipe = crtc->index;
1269         struct amdgpu_device *adev = drm_to_adev(dev);
1270         int vpos, hpos, stat;
1271         u32 count;
1272
1273         if (pipe >= adev->mode_info.num_crtc) {
1274                 DRM_ERROR("Invalid crtc %u\n", pipe);
1275                 return -EINVAL;
1276         }
1277
1278         /* The hw increments its frame counter at start of vsync, not at start
1279          * of vblank, as is required by DRM core vblank counter handling.
1280          * Cook the hw count here to make it appear to the caller as if it
1281          * incremented at start of vblank. We measure distance to start of
1282          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1283          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1284          * result by 1 to give the proper appearance to caller.
1285          */
1286         if (adev->mode_info.crtcs[pipe]) {
1287                 /* Repeat readout if needed to provide stable result if
1288                  * we cross start of vsync during the queries.
1289                  */
1290                 do {
1291                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1292                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1293                          * vpos as distance to start of vblank, instead of
1294                          * regular vertical scanout pos.
1295                          */
1296                         stat = amdgpu_display_get_crtc_scanoutpos(
1297                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1298                                 &vpos, &hpos, NULL, NULL,
1299                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1300                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1301
1302                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1303                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1304                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1305                 } else {
1306                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1307                                       pipe, vpos);
1308
1309                         /* Bump counter if we are at >= leading edge of vblank,
1310                          * but before vsync where vpos would turn negative and
1311                          * the hw counter really increments.
1312                          */
1313                         if (vpos >= 0)
1314                                 count++;
1315                 }
1316         } else {
1317                 /* Fallback to use value as is. */
1318                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1319                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1320         }
1321
1322         return count;
1323 }
1324
1325 /**
1326  * amdgpu_enable_vblank_kms - enable vblank interrupt
1327  *
1328  * @crtc: crtc to enable vblank interrupt for
1329  *
1330  * Enable the interrupt on the requested crtc (all asics).
1331  * Returns 0 on success, -EINVAL on failure.
1332  */
1333 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1334 {
1335         struct drm_device *dev = crtc->dev;
1336         unsigned int pipe = crtc->index;
1337         struct amdgpu_device *adev = drm_to_adev(dev);
1338         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1339
1340         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1341 }
1342
1343 /**
1344  * amdgpu_disable_vblank_kms - disable vblank interrupt
1345  *
1346  * @crtc: crtc to disable vblank interrupt for
1347  *
1348  * Disable the interrupt on the requested crtc (all asics).
1349  */
1350 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1351 {
1352         struct drm_device *dev = crtc->dev;
1353         unsigned int pipe = crtc->index;
1354         struct amdgpu_device *adev = drm_to_adev(dev);
1355         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1356
1357         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1358 }
1359
1360 /*
1361  * Debugfs info
1362  */
1363 #if defined(CONFIG_DEBUG_FS)
1364
1365 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1366 {
1367         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1368         struct drm_amdgpu_info_firmware fw_info;
1369         struct drm_amdgpu_query_fw query_fw;
1370         struct atom_context *ctx = adev->mode_info.atom_context;
1371         int ret, i;
1372
1373         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1374 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1375                 TA_FW_NAME(XGMI),
1376                 TA_FW_NAME(RAS),
1377                 TA_FW_NAME(HDCP),
1378                 TA_FW_NAME(DTM),
1379                 TA_FW_NAME(RAP),
1380                 TA_FW_NAME(SECUREDISPLAY),
1381 #undef TA_FW_NAME
1382         };
1383
1384         /* VCE */
1385         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1386         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1387         if (ret)
1388                 return ret;
1389         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1390                    fw_info.feature, fw_info.ver);
1391
1392         /* UVD */
1393         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1394         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1395         if (ret)
1396                 return ret;
1397         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1398                    fw_info.feature, fw_info.ver);
1399
1400         /* GMC */
1401         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1402         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1403         if (ret)
1404                 return ret;
1405         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1406                    fw_info.feature, fw_info.ver);
1407
1408         /* ME */
1409         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1410         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1411         if (ret)
1412                 return ret;
1413         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1414                    fw_info.feature, fw_info.ver);
1415
1416         /* PFP */
1417         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1418         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1419         if (ret)
1420                 return ret;
1421         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1422                    fw_info.feature, fw_info.ver);
1423
1424         /* CE */
1425         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1426         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1427         if (ret)
1428                 return ret;
1429         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1430                    fw_info.feature, fw_info.ver);
1431
1432         /* RLC */
1433         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1434         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1435         if (ret)
1436                 return ret;
1437         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1438                    fw_info.feature, fw_info.ver);
1439
1440         /* RLC SAVE RESTORE LIST CNTL */
1441         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1442         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1443         if (ret)
1444                 return ret;
1445         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1446                    fw_info.feature, fw_info.ver);
1447
1448         /* RLC SAVE RESTORE LIST GPM MEM */
1449         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1450         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1451         if (ret)
1452                 return ret;
1453         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1454                    fw_info.feature, fw_info.ver);
1455
1456         /* RLC SAVE RESTORE LIST SRM MEM */
1457         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1458         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1459         if (ret)
1460                 return ret;
1461         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1462                    fw_info.feature, fw_info.ver);
1463
1464         /* MEC */
1465         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1466         query_fw.index = 0;
1467         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1468         if (ret)
1469                 return ret;
1470         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1471                    fw_info.feature, fw_info.ver);
1472
1473         /* MEC2 */
1474         if (adev->gfx.mec2_fw) {
1475                 query_fw.index = 1;
1476                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1477                 if (ret)
1478                         return ret;
1479                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1480                            fw_info.feature, fw_info.ver);
1481         }
1482
1483         /* PSP SOS */
1484         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1485         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1486         if (ret)
1487                 return ret;
1488         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1489                    fw_info.feature, fw_info.ver);
1490
1491
1492         /* PSP ASD */
1493         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1494         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1495         if (ret)
1496                 return ret;
1497         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1498                    fw_info.feature, fw_info.ver);
1499
1500         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1501         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1502                 query_fw.index = i;
1503                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1504                 if (ret)
1505                         continue;
1506
1507                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1508                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1509         }
1510
1511         /* SMC */
1512         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1513         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1514         if (ret)
1515                 return ret;
1516         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1517                    fw_info.feature, fw_info.ver);
1518
1519         /* SDMA */
1520         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1521         for (i = 0; i < adev->sdma.num_instances; i++) {
1522                 query_fw.index = i;
1523                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1524                 if (ret)
1525                         return ret;
1526                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1527                            i, fw_info.feature, fw_info.ver);
1528         }
1529
1530         /* VCN */
1531         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1532         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1533         if (ret)
1534                 return ret;
1535         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1536                    fw_info.feature, fw_info.ver);
1537
1538         /* DMCU */
1539         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1540         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1541         if (ret)
1542                 return ret;
1543         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1544                    fw_info.feature, fw_info.ver);
1545
1546         /* DMCUB */
1547         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1548         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1549         if (ret)
1550                 return ret;
1551         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1552                    fw_info.feature, fw_info.ver);
1553
1554         /* TOC */
1555         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1556         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1557         if (ret)
1558                 return ret;
1559         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1560                    fw_info.feature, fw_info.ver);
1561
1562         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1563
1564         return 0;
1565 }
1566
1567 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1568
1569 #endif
1570
1571 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1572 {
1573 #if defined(CONFIG_DEBUG_FS)
1574         struct drm_minor *minor = adev_to_drm(adev)->primary;
1575         struct dentry *root = minor->debugfs_root;
1576
1577         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1578                             adev, &amdgpu_debugfs_firmware_info_fops);
1579
1580 #endif
1581 }