drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38 #include <linux/pci.h>
  39 #include <linux/pm_runtime.h>
  40 #include "amdgpu_amdkfd.h"
  41 #include "amdgpu_gem.h"
  42 #include "amdgpu_display.h"
  43 #include "amdgpu_ras.h"
  44
  45 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  46 {
  47         struct amdgpu_gpu_instance *gpu_instance;
  48         int i;
  49
  50         mutex_lock(&mgpu_info.mutex);
  51
  52         for (i = 0; i < mgpu_info.num_gpu; i++) {
  53                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  54                 if (gpu_instance->adev == adev) {
  55                         mgpu_info.gpu_ins[i] =
  56                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  57                         mgpu_info.num_gpu--;
  58                         if (adev->flags & AMD_IS_APU)
  59                                 mgpu_info.num_apu--;
  60                         else
  61                                 mgpu_info.num_dgpu--;
  62                         break;
  63                 }
  64         }
  65
  66         mutex_unlock(&mgpu_info.mutex);
  67 }
  68
  69 /**
  70  * amdgpu_driver_unload_kms - Main unload function for KMS.
  71  *
  72  * @dev: drm dev pointer
  73  *
  74  * This is the main unload function for KMS (all asics).
  75  * Returns 0 on success.
  76  */
  77 void amdgpu_driver_unload_kms(struct drm_device *dev)
  78 {
  79         struct amdgpu_device *adev = drm_to_adev(dev);
  80
  81         if (adev == NULL)
  82                 return;
  83
  84         amdgpu_unregister_gpu_instance(adev);
  85
  86         if (adev->rmmio == NULL)
  87                 return;
  88
  89         if (adev->runpm) {
  90                 pm_runtime_get_sync(dev->dev);
  91                 pm_runtime_forbid(dev->dev);
  92         }
  93
  94         amdgpu_acpi_fini(adev);
  95         amdgpu_device_fini(adev);
  96 }
  97
  98 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
  99 {
 100         struct amdgpu_gpu_instance *gpu_instance;
 101
 102         mutex_lock(&mgpu_info.mutex);
 103
 104         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 105                 DRM_ERROR("Cannot register more gpu instance\n");
 106                 mutex_unlock(&mgpu_info.mutex);
 107                 return;
 108         }
 109
 110         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 111         gpu_instance->adev = adev;
 112         gpu_instance->mgpu_fan_enabled = 0;
 113
 114         mgpu_info.num_gpu++;
 115         if (adev->flags & AMD_IS_APU)
 116                 mgpu_info.num_apu++;
 117         else
 118                 mgpu_info.num_dgpu++;
 119
 120         mutex_unlock(&mgpu_info.mutex);
 121 }
 122
 123 /**
 124  * amdgpu_driver_load_kms - Main load function for KMS.
 125  *
 126  * @adev: pointer to struct amdgpu_device
 127  * @flags: device flags
 128  *
 129  * This is the main load function for KMS (all asics).
 130  * Returns 0 on success, error on failure.
 131  */
 132 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 133 {
 134         struct drm_device *dev;
 135         struct pci_dev *parent;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         if (amdgpu_has_atpx() &&
 141             (amdgpu_is_atpx_hybrid() ||
 142              amdgpu_has_atpx_dgpu_power_cntl()) &&
 143             ((flags & AMD_IS_APU) == 0) &&
 144             !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
 145                 flags |= AMD_IS_PX;
 146
 147         parent = pci_upstream_bridge(adev->pdev);
 148         adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
 149
 150         /* amdgpu_device_init should report only fatal error
 151          * like memory allocation failure or iomapping failure,
 152          * or memory manager initialization failure, it must
 153          * properly initialize the GPU MC controller and permit
 154          * VRAM allocation
 155          */
 156         r = amdgpu_device_init(adev, flags);
 157         if (r) {
 158                 dev_err(dev->dev, "Fatal error during GPU init\n");
 159                 goto out;
 160         }
 161
 162         if (amdgpu_device_supports_atpx(dev) &&
 163             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 164                 adev->runpm = true;
 165                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 166         } else if (amdgpu_device_supports_boco(dev) &&
 167                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 168                 adev->runpm = true;
 169                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 170         } else if (amdgpu_device_supports_baco(dev) &&
 171                    (amdgpu_runtime_pm != 0)) {
 172                 switch (adev->asic_type) {
 173                 case CHIP_VEGA20:
 174                 case CHIP_ARCTURUS:
 175                 case CHIP_SIENNA_CICHLID:
 176                 case CHIP_NAVY_FLOUNDER:
 177                         /* enable runpm if runpm=1 */
 178                         if (amdgpu_runtime_pm > 0)
 179                                 adev->runpm = true;
 180                         break;
 181                 case CHIP_VEGA10:
 182                         /* turn runpm on if noretry=0 */
 183                         if (!adev->gmc.noretry)
 184                                 adev->runpm = true;
 185                         break;
 186                 default:
 187                         /* enable runpm on CI+ */
 188                         adev->runpm = true;
 189                         break;
 190                 }
 191                 if (adev->runpm)
 192                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 193         }
 194
 195         /* Call ACPI methods: require modeset init
 196          * but failure is not fatal
 197          */
 198
 199         acpi_status = amdgpu_acpi_init(adev);
 200         if (acpi_status)
 201                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 202
 203         if (adev->runpm) {
 204                 /* only need to skip on ATPX */
 205                 if (amdgpu_device_supports_atpx(dev) &&
 206                     !amdgpu_is_atpx_hybrid())
 207                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 208                 pm_runtime_use_autosuspend(dev->dev);
 209                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 210                 pm_runtime_allow(dev->dev);
 211                 pm_runtime_mark_last_busy(dev->dev);
 212                 pm_runtime_put_autosuspend(dev->dev);
 213         }
 214
 215 out:
 216         if (r) {
 217                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 218                 if (adev->rmmio && adev->runpm)
 219                         pm_runtime_put_noidle(dev->dev);
 220                 amdgpu_driver_unload_kms(dev);
 221         }
 222
 223         return r;
 224 }
 225
 226 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 227                                 struct drm_amdgpu_query_fw *query_fw,
 228                                 struct amdgpu_device *adev)
 229 {
 230         switch (query_fw->fw_type) {
 231         case AMDGPU_INFO_FW_VCE:
 232                 fw_info->ver = adev->vce.fw_version;
 233                 fw_info->feature = adev->vce.fb_version;
 234                 break;
 235         case AMDGPU_INFO_FW_UVD:
 236                 fw_info->ver = adev->uvd.fw_version;
 237                 fw_info->feature = 0;
 238                 break;
 239         case AMDGPU_INFO_FW_VCN:
 240                 fw_info->ver = adev->vcn.fw_version;
 241                 fw_info->feature = 0;
 242                 break;
 243         case AMDGPU_INFO_FW_GMC:
 244                 fw_info->ver = adev->gmc.fw_version;
 245                 fw_info->feature = 0;
 246                 break;
 247         case AMDGPU_INFO_FW_GFX_ME:
 248                 fw_info->ver = adev->gfx.me_fw_version;
 249                 fw_info->feature = adev->gfx.me_feature_version;
 250                 break;
 251         case AMDGPU_INFO_FW_GFX_PFP:
 252                 fw_info->ver = adev->gfx.pfp_fw_version;
 253                 fw_info->feature = adev->gfx.pfp_feature_version;
 254                 break;
 255         case AMDGPU_INFO_FW_GFX_CE:
 256                 fw_info->ver = adev->gfx.ce_fw_version;
 257                 fw_info->feature = adev->gfx.ce_feature_version;
 258                 break;
 259         case AMDGPU_INFO_FW_GFX_RLC:
 260                 fw_info->ver = adev->gfx.rlc_fw_version;
 261                 fw_info->feature = adev->gfx.rlc_feature_version;
 262                 break;
 263         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 264                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 265                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 266                 break;
 267         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 268                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 269                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 270                 break;
 271         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 272                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 273                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 274                 break;
 275         case AMDGPU_INFO_FW_GFX_MEC:
 276                 if (query_fw->index == 0) {
 277                         fw_info->ver = adev->gfx.mec_fw_version;
 278                         fw_info->feature = adev->gfx.mec_feature_version;
 279                 } else if (query_fw->index == 1) {
 280                         fw_info->ver = adev->gfx.mec2_fw_version;
 281                         fw_info->feature = adev->gfx.mec2_feature_version;
 282                 } else
 283                         return -EINVAL;
 284                 break;
 285         case AMDGPU_INFO_FW_SMC:
 286                 fw_info->ver = adev->pm.fw_version;
 287                 fw_info->feature = 0;
 288                 break;
 289         case AMDGPU_INFO_FW_TA:
 290                 switch (query_fw->index) {
 291                 case 0:
 292                         fw_info->ver = adev->psp.ta_fw_version;
 293                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 294                         break;
 295                 case 1:
 296                         fw_info->ver = adev->psp.ta_fw_version;
 297                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 298                         break;
 299                 case 2:
 300                         fw_info->ver = adev->psp.ta_fw_version;
 301                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 302                         break;
 303                 case 3:
 304                         fw_info->ver = adev->psp.ta_fw_version;
 305                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 306                         break;
 307                 default:
 308                         return -EINVAL;
 309                 }
 310                 break;
 311         case AMDGPU_INFO_FW_SDMA:
 312                 if (query_fw->index >= adev->sdma.num_instances)
 313                         return -EINVAL;
 314                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 315                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 316                 break;
 317         case AMDGPU_INFO_FW_SOS:
 318                 fw_info->ver = adev->psp.sos_fw_version;
 319                 fw_info->feature = adev->psp.sos_feature_version;
 320                 break;
 321         case AMDGPU_INFO_FW_ASD:
 322                 fw_info->ver = adev->psp.asd_fw_version;
 323                 fw_info->feature = adev->psp.asd_feature_version;
 324                 break;
 325         case AMDGPU_INFO_FW_DMCU:
 326                 fw_info->ver = adev->dm.dmcu_fw_version;
 327                 fw_info->feature = 0;
 328                 break;
 329         case AMDGPU_INFO_FW_DMCUB:
 330                 fw_info->ver = adev->dm.dmcub_fw_version;
 331                 fw_info->feature = 0;
 332                 break;
 333         case AMDGPU_INFO_FW_TOC:
 334                 fw_info->ver = adev->psp.toc_fw_version;
 335                 fw_info->feature = adev->psp.toc_feature_version;
 336                 break;
 337         default:
 338                 return -EINVAL;
 339         }
 340         return 0;
 341 }
 342
 343 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 344                              struct drm_amdgpu_info *info,
 345                              struct drm_amdgpu_info_hw_ip *result)
 346 {
 347         uint32_t ib_start_alignment = 0;
 348         uint32_t ib_size_alignment = 0;
 349         enum amd_ip_block_type type;
 350         unsigned int num_rings = 0;
 351         unsigned int i, j;
 352
 353         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 354                 return -EINVAL;
 355
 356         switch (info->query_hw_ip.type) {
 357         case AMDGPU_HW_IP_GFX:
 358                 type = AMD_IP_BLOCK_TYPE_GFX;
 359                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 360                         if (adev->gfx.gfx_ring[i].sched.ready)
 361                                 ++num_rings;
 362                 ib_start_alignment = 32;
 363                 ib_size_alignment = 32;
 364                 break;
 365         case AMDGPU_HW_IP_COMPUTE:
 366                 type = AMD_IP_BLOCK_TYPE_GFX;
 367                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 368                         if (adev->gfx.compute_ring[i].sched.ready)
 369                                 ++num_rings;
 370                 ib_start_alignment = 32;
 371                 ib_size_alignment = 32;
 372                 break;
 373         case AMDGPU_HW_IP_DMA:
 374                 type = AMD_IP_BLOCK_TYPE_SDMA;
 375                 for (i = 0; i < adev->sdma.num_instances; i++)
 376                         if (adev->sdma.instance[i].ring.sched.ready)
 377                                 ++num_rings;
 378                 ib_start_alignment = 256;
 379                 ib_size_alignment = 4;
 380                 break;
 381         case AMDGPU_HW_IP_UVD:
 382                 type = AMD_IP_BLOCK_TYPE_UVD;
 383                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 384                         if (adev->uvd.harvest_config & (1 << i))
 385                                 continue;
 386
 387                         if (adev->uvd.inst[i].ring.sched.ready)
 388                                 ++num_rings;
 389                 }
 390                 ib_start_alignment = 64;
 391                 ib_size_alignment = 64;
 392                 break;
 393         case AMDGPU_HW_IP_VCE:
 394                 type = AMD_IP_BLOCK_TYPE_VCE;
 395                 for (i = 0; i < adev->vce.num_rings; i++)
 396                         if (adev->vce.ring[i].sched.ready)
 397                                 ++num_rings;
 398                 ib_start_alignment = 4;
 399                 ib_size_alignment = 1;
 400                 break;
 401         case AMDGPU_HW_IP_UVD_ENC:
 402                 type = AMD_IP_BLOCK_TYPE_UVD;
 403                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 404                         if (adev->uvd.harvest_config & (1 << i))
 405                                 continue;
 406
 407                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 408                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 409                                         ++num_rings;
 410                 }
 411                 ib_start_alignment = 64;
 412                 ib_size_alignment = 64;
 413                 break;
 414         case AMDGPU_HW_IP_VCN_DEC:
 415                 type = AMD_IP_BLOCK_TYPE_VCN;
 416                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 417                         if (adev->uvd.harvest_config & (1 << i))
 418                                 continue;
 419
 420                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 421                                 ++num_rings;
 422                 }
 423                 ib_start_alignment = 16;
 424                 ib_size_alignment = 16;
 425                 break;
 426         case AMDGPU_HW_IP_VCN_ENC:
 427                 type = AMD_IP_BLOCK_TYPE_VCN;
 428                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 429                         if (adev->uvd.harvest_config & (1 << i))
 430                                 continue;
 431
 432                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 433                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 434                                         ++num_rings;
 435                 }
 436                 ib_start_alignment = 64;
 437                 ib_size_alignment = 1;
 438                 break;
 439         case AMDGPU_HW_IP_VCN_JPEG:
 440                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 441                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 442
 443                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 444                         if (adev->jpeg.harvest_config & (1 << i))
 445                                 continue;
 446
 447                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 448                                 ++num_rings;
 449                 }
 450                 ib_start_alignment = 16;
 451                 ib_size_alignment = 16;
 452                 break;
 453         default:
 454                 return -EINVAL;
 455         }
 456
 457         for (i = 0; i < adev->num_ip_blocks; i++)
 458                 if (adev->ip_blocks[i].version->type == type &&
 459                     adev->ip_blocks[i].status.valid)
 460                         break;
 461
 462         if (i == adev->num_ip_blocks)
 463                 return 0;
 464
 465         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 466                         num_rings);
 467
 468         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 469         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 470         result->capabilities_flags = 0;
 471         result->available_rings = (1 << num_rings) - 1;
 472         result->ib_start_alignment = ib_start_alignment;
 473         result->ib_size_alignment = ib_size_alignment;
 474         return 0;
 475 }
 476
 477 /*
 478  * Userspace get information ioctl
 479  */
 480 /**
 481  * amdgpu_info_ioctl - answer a device specific request.
 482  *
 483  * @dev: drm device pointer
 484  * @data: request object
 485  * @filp: drm filp
 486  *
 487  * This function is used to pass device specific parameters to the userspace
 488  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 489  * etc. (all asics).
 490  * Returns 0 on success, -EINVAL on failure.
 491  */
 492 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 493 {
 494         struct amdgpu_device *adev = drm_to_adev(dev);
 495         struct drm_amdgpu_info *info = data;
 496         struct amdgpu_mode_info *minfo = &adev->mode_info;
 497         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 498         uint32_t size = info->return_size;
 499         struct drm_crtc *crtc;
 500         uint32_t ui32 = 0;
 501         uint64_t ui64 = 0;
 502         int i, found;
 503         int ui32_size = sizeof(ui32);
 504
 505         if (!info->return_size || !info->return_pointer)
 506                 return -EINVAL;
 507
 508         switch (info->query) {
 509         case AMDGPU_INFO_ACCEL_WORKING:
 510                 ui32 = adev->accel_working;
 511                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 512         case AMDGPU_INFO_CRTC_FROM_ID:
 513                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 514                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 515                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 516                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 517                                 ui32 = amdgpu_crtc->crtc_id;
 518                                 found = 1;
 519                                 break;
 520                         }
 521                 }
 522                 if (!found) {
 523                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 524                         return -EINVAL;
 525                 }
 526                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 527         case AMDGPU_INFO_HW_IP_INFO: {
 528                 struct drm_amdgpu_info_hw_ip ip = {};
 529                 int ret;
 530
 531                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 532                 if (ret)
 533                         return ret;
 534
 535                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 536                 return ret ? -EFAULT : 0;
 537         }
 538         case AMDGPU_INFO_HW_IP_COUNT: {
 539                 enum amd_ip_block_type type;
 540                 uint32_t count = 0;
 541
 542                 switch (info->query_hw_ip.type) {
 543                 case AMDGPU_HW_IP_GFX:
 544                         type = AMD_IP_BLOCK_TYPE_GFX;
 545                         break;
 546                 case AMDGPU_HW_IP_COMPUTE:
 547                         type = AMD_IP_BLOCK_TYPE_GFX;
 548                         break;
 549                 case AMDGPU_HW_IP_DMA:
 550                         type = AMD_IP_BLOCK_TYPE_SDMA;
 551                         break;
 552                 case AMDGPU_HW_IP_UVD:
 553                         type = AMD_IP_BLOCK_TYPE_UVD;
 554                         break;
 555                 case AMDGPU_HW_IP_VCE:
 556                         type = AMD_IP_BLOCK_TYPE_VCE;
 557                         break;
 558                 case AMDGPU_HW_IP_UVD_ENC:
 559                         type = AMD_IP_BLOCK_TYPE_UVD;
 560                         break;
 561                 case AMDGPU_HW_IP_VCN_DEC:
 562                 case AMDGPU_HW_IP_VCN_ENC:
 563                         type = AMD_IP_BLOCK_TYPE_VCN;
 564                         break;
 565                 case AMDGPU_HW_IP_VCN_JPEG:
 566                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 567                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 568                         break;
 569                 default:
 570                         return -EINVAL;
 571                 }
 572
 573                 for (i = 0; i < adev->num_ip_blocks; i++)
 574                         if (adev->ip_blocks[i].version->type == type &&
 575                             adev->ip_blocks[i].status.valid &&
 576                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 577                                 count++;
 578
 579                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 580         }
 581         case AMDGPU_INFO_TIMESTAMP:
 582                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 583                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 584         case AMDGPU_INFO_FW_VERSION: {
 585                 struct drm_amdgpu_info_firmware fw_info;
 586                 int ret;
 587
 588                 /* We only support one instance of each IP block right now. */
 589                 if (info->query_fw.ip_instance != 0)
 590                         return -EINVAL;
 591
 592                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 593                 if (ret)
 594                         return ret;
 595
 596                 return copy_to_user(out, &fw_info,
 597                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 598         }
 599         case AMDGPU_INFO_NUM_BYTES_MOVED:
 600                 ui64 = atomic64_read(&adev->num_bytes_moved);
 601                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 602         case AMDGPU_INFO_NUM_EVICTIONS:
 603                 ui64 = atomic64_read(&adev->num_evictions);
 604                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 605         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 606                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 607                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 608         case AMDGPU_INFO_VRAM_USAGE:
 609                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 610                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 611         case AMDGPU_INFO_VIS_VRAM_USAGE:
 612                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 613                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 614         case AMDGPU_INFO_GTT_USAGE:
 615                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 616                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 617         case AMDGPU_INFO_GDS_CONFIG: {
 618                 struct drm_amdgpu_info_gds gds_info;
 619
 620                 memset(&gds_info, 0, sizeof(gds_info));
 621                 gds_info.compute_partition_size = adev->gds.gds_size;
 622                 gds_info.gds_total_size = adev->gds.gds_size;
 623                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 624                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 625                 return copy_to_user(out, &gds_info,
 626                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 627         }
 628         case AMDGPU_INFO_VRAM_GTT: {
 629                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 630
 631                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 632                         atomic64_read(&adev->vram_pin_size) -
 633                         AMDGPU_VM_RESERVED_VRAM;
 634                 vram_gtt.vram_cpu_accessible_size =
 635                         min(adev->gmc.visible_vram_size -
 636                             atomic64_read(&adev->visible_pin_size),
 637                             vram_gtt.vram_size);
 638                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 639                 vram_gtt.gtt_size *= PAGE_SIZE;
 640                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 641                 return copy_to_user(out, &vram_gtt,
 642                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 643         }
 644         case AMDGPU_INFO_MEMORY: {
 645                 struct drm_amdgpu_memory_info mem;
 646                 struct ttm_resource_manager *vram_man =
 647                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 648                 struct ttm_resource_manager *gtt_man =
 649                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 650                 memset(&mem, 0, sizeof(mem));
 651                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 652                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 653                         atomic64_read(&adev->vram_pin_size) -
 654                         AMDGPU_VM_RESERVED_VRAM;
 655                 mem.vram.heap_usage =
 656                         amdgpu_vram_mgr_usage(vram_man);
 657                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 658
 659                 mem.cpu_accessible_vram.total_heap_size =
 660                         adev->gmc.visible_vram_size;
 661                 mem.cpu_accessible_vram.usable_heap_size =
 662                         min(adev->gmc.visible_vram_size -
 663                             atomic64_read(&adev->visible_pin_size),
 664                             mem.vram.usable_heap_size);
 665                 mem.cpu_accessible_vram.heap_usage =
 666                         amdgpu_vram_mgr_vis_usage(vram_man);
 667                 mem.cpu_accessible_vram.max_allocation =
 668                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 669
 670                 mem.gtt.total_heap_size = gtt_man->size;
 671                 mem.gtt.total_heap_size *= PAGE_SIZE;
 672                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 673                         atomic64_read(&adev->gart_pin_size);
 674                 mem.gtt.heap_usage =
 675                         amdgpu_gtt_mgr_usage(gtt_man);
 676                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 677
 678                 return copy_to_user(out, &mem,
 679                                     min((size_t)size, sizeof(mem)))
 680                                     ? -EFAULT : 0;
 681         }
 682         case AMDGPU_INFO_READ_MMR_REG: {
 683                 unsigned n, alloc_size;
 684                 uint32_t *regs;
 685                 unsigned se_num = (info->read_mmr_reg.instance >>
 686                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 687                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 688                 unsigned sh_num = (info->read_mmr_reg.instance >>
 689                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 690                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 691
 692                 /* set full masks if the userspace set all bits
 693                  * in the bitfields */
 694                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 695                         se_num = 0xffffffff;
 696                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 697                         return -EINVAL;
 698                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 699                         sh_num = 0xffffffff;
 700                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 701                         return -EINVAL;
 702
 703                 if (info->read_mmr_reg.count > 128)
 704                         return -EINVAL;
 705
 706                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 707                 if (!regs)
 708                         return -ENOMEM;
 709                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 710
 711                 amdgpu_gfx_off_ctrl(adev, false);
 712                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 713                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 714                                                       info->read_mmr_reg.dword_offset + i,
 715                                                       &regs[i])) {
 716                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 717                                               info->read_mmr_reg.dword_offset + i);
 718                                 kfree(regs);
 719                                 amdgpu_gfx_off_ctrl(adev, true);
 720                                 return -EFAULT;
 721                         }
 722                 }
 723                 amdgpu_gfx_off_ctrl(adev, true);
 724                 n = copy_to_user(out, regs, min(size, alloc_size));
 725                 kfree(regs);
 726                 return n ? -EFAULT : 0;
 727         }
 728         case AMDGPU_INFO_DEV_INFO: {
 729                 struct drm_amdgpu_info_device *dev_info;
 730                 uint64_t vm_size;
 731                 int ret;
 732
 733                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 734                 if (!dev_info)
 735                         return -ENOMEM;
 736
 737                 dev_info->device_id = adev->pdev->device;
 738                 dev_info->chip_rev = adev->rev_id;
 739                 dev_info->external_rev = adev->external_rev_id;
 740                 dev_info->pci_rev = adev->pdev->revision;
 741                 dev_info->family = adev->family;
 742                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 743                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 744                 /* return all clocks in KHz */
 745                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 746                 if (adev->pm.dpm_enabled) {
 747                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 748                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 749                 } else {
 750                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 751                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 752                 }
 753                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 754                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 755                         adev->gfx.config.max_shader_engines;
 756                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 757                 dev_info->_pad = 0;
 758                 dev_info->ids_flags = 0;
 759                 if (adev->flags & AMD_IS_APU)
 760                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 761                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 762                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 763                 if (amdgpu_is_tmz(adev))
 764                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 765
 766                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 767                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 768
 769                 /* Older VCE FW versions are buggy and can handle only 40bits */
 770                 if (adev->vce.fw_version &&
 771                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 772                         vm_size = min(vm_size, 1ULL << 40);
 773
 774                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 775                 dev_info->virtual_address_max =
 776                         min(vm_size, AMDGPU_GMC_HOLE_START);
 777
 778                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 779                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 780                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 781                 }
 782                 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 783                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 784                 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 785                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 786                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 787                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 788                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 789                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 790                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 791                        sizeof(adev->gfx.cu_info.bitmap));
 792                 dev_info->vram_type = adev->gmc.vram_type;
 793                 dev_info->vram_bit_width = adev->gmc.vram_width;
 794                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 795                 dev_info->gc_double_offchip_lds_buf =
 796                         adev->gfx.config.double_offchip_lds_buf;
 797                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 798                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 799                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 800                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 801                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 802                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 803                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 804
 805                 if (adev->family >= AMDGPU_FAMILY_NV)
 806                         dev_info->pa_sc_tile_steering_override =
 807                                 adev->gfx.config.pa_sc_tile_steering_override;
 808
 809                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 810
 811                 ret = copy_to_user(out, dev_info,
 812                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 813                 kfree(dev_info);
 814                 return ret;
 815         }
 816         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 817                 unsigned i;
 818                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 819                 struct amd_vce_state *vce_state;
 820
 821                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 822                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 823                         if (vce_state) {
 824                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 825                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 826                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 827                                 vce_clk_table.num_valid_entries++;
 828                         }
 829                 }
 830
 831                 return copy_to_user(out, &vce_clk_table,
 832                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 833         }
 834         case AMDGPU_INFO_VBIOS: {
 835                 uint32_t bios_size = adev->bios_size;
 836
 837                 switch (info->vbios_info.type) {
 838                 case AMDGPU_INFO_VBIOS_SIZE:
 839                         return copy_to_user(out, &bios_size,
 840                                         min((size_t)size, sizeof(bios_size)))
 841                                         ? -EFAULT : 0;
 842                 case AMDGPU_INFO_VBIOS_IMAGE: {
 843                         uint8_t *bios;
 844                         uint32_t bios_offset = info->vbios_info.offset;
 845
 846                         if (bios_offset >= bios_size)
 847                                 return -EINVAL;
 848
 849                         bios = adev->bios + bios_offset;
 850                         return copy_to_user(out, bios,
 851                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 852                                         ? -EFAULT : 0;
 853                 }
 854                 default:
 855                         DRM_DEBUG_KMS("Invalid request %d\n",
 856                                         info->vbios_info.type);
 857                         return -EINVAL;
 858                 }
 859         }
 860         case AMDGPU_INFO_NUM_HANDLES: {
 861                 struct drm_amdgpu_info_num_handles handle;
 862
 863                 switch (info->query_hw_ip.type) {
 864                 case AMDGPU_HW_IP_UVD:
 865                         /* Starting Polaris, we support unlimited UVD handles */
 866                         if (adev->asic_type < CHIP_POLARIS10) {
 867                                 handle.uvd_max_handles = adev->uvd.max_handles;
 868                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 869
 870                                 return copy_to_user(out, &handle,
 871                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 872                         } else {
 873                                 return -ENODATA;
 874                         }
 875
 876                         break;
 877                 default:
 878                         return -EINVAL;
 879                 }
 880         }
 881         case AMDGPU_INFO_SENSOR: {
 882                 if (!adev->pm.dpm_enabled)
 883                         return -ENOENT;
 884
 885                 switch (info->sensor_info.type) {
 886                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 887                         /* get sclk in Mhz */
 888                         if (amdgpu_dpm_read_sensor(adev,
 889                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 890                                                    (void *)&ui32, &ui32_size)) {
 891                                 return -EINVAL;
 892                         }
 893                         ui32 /= 100;
 894                         break;
 895                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 896                         /* get mclk in Mhz */
 897                         if (amdgpu_dpm_read_sensor(adev,
 898                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 899                                                    (void *)&ui32, &ui32_size)) {
 900                                 return -EINVAL;
 901                         }
 902                         ui32 /= 100;
 903                         break;
 904                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 905                         /* get temperature in millidegrees C */
 906                         if (amdgpu_dpm_read_sensor(adev,
 907                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 908                                                    (void *)&ui32, &ui32_size)) {
 909                                 return -EINVAL;
 910                         }
 911                         break;
 912                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 913                         /* get GPU load */
 914                         if (amdgpu_dpm_read_sensor(adev,
 915                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 916                                                    (void *)&ui32, &ui32_size)) {
 917                                 return -EINVAL;
 918                         }
 919                         break;
 920                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 921                         /* get average GPU power */
 922                         if (amdgpu_dpm_read_sensor(adev,
 923                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 924                                                    (void *)&ui32, &ui32_size)) {
 925                                 return -EINVAL;
 926                         }
 927                         ui32 >>= 8;
 928                         break;
 929                 case AMDGPU_INFO_SENSOR_VDDNB:
 930                         /* get VDDNB in millivolts */
 931                         if (amdgpu_dpm_read_sensor(adev,
 932                                                    AMDGPU_PP_SENSOR_VDDNB,
 933                                                    (void *)&ui32, &ui32_size)) {
 934                                 return -EINVAL;
 935                         }
 936                         break;
 937                 case AMDGPU_INFO_SENSOR_VDDGFX:
 938                         /* get VDDGFX in millivolts */
 939                         if (amdgpu_dpm_read_sensor(adev,
 940                                                    AMDGPU_PP_SENSOR_VDDGFX,
 941                                                    (void *)&ui32, &ui32_size)) {
 942                                 return -EINVAL;
 943                         }
 944                         break;
 945                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 946                         /* get stable pstate sclk in Mhz */
 947                         if (amdgpu_dpm_read_sensor(adev,
 948                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 949                                                    (void *)&ui32, &ui32_size)) {
 950                                 return -EINVAL;
 951                         }
 952                         ui32 /= 100;
 953                         break;
 954                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 955                         /* get stable pstate mclk in Mhz */
 956                         if (amdgpu_dpm_read_sensor(adev,
 957                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 958                                                    (void *)&ui32, &ui32_size)) {
 959                                 return -EINVAL;
 960                         }
 961                         ui32 /= 100;
 962                         break;
 963                 default:
 964                         DRM_DEBUG_KMS("Invalid request %d\n",
 965                                       info->sensor_info.type);
 966                         return -EINVAL;
 967                 }
 968                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 969         }
 970         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 971                 ui32 = atomic_read(&adev->vram_lost_counter);
 972                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 973         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 974                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 975                 uint64_t ras_mask;
 976
 977                 if (!ras)
 978                         return -EINVAL;
 979                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 980
 981                 return copy_to_user(out, &ras_mask,
 982                                 min_t(u64, size, sizeof(ras_mask))) ?
 983                         -EFAULT : 0;
 984         }
 985         default:
 986                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 987                 return -EINVAL;
 988         }
 989         return 0;
 990 }
 991
 992
 993 /*
 994  * Outdated mess for old drm with Xorg being in charge (void function now).
 995  */
 996 /**
 997  * amdgpu_driver_lastclose_kms - drm callback for last close
 998  *
 999  * @dev: drm dev pointer
1000  *
1001  * Switch vga_switcheroo state after last close (all asics).
1002  */
1003 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1004 {
1005         drm_fb_helper_lastclose(dev);
1006         vga_switcheroo_process_delayed_switch();
1007 }
1008
1009 /**
1010  * amdgpu_driver_open_kms - drm callback for open
1011  *
1012  * @dev: drm dev pointer
1013  * @file_priv: drm file
1014  *
1015  * On device open, init vm on cayman+ (all asics).
1016  * Returns 0 on success, error on failure.
1017  */
1018 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1019 {
1020         struct amdgpu_device *adev = drm_to_adev(dev);
1021         struct amdgpu_fpriv *fpriv;
1022         int r, pasid;
1023
1024         /* Ensure IB tests are run on ring */
1025         flush_delayed_work(&adev->delayed_init_work);
1026
1027
1028         if (amdgpu_ras_intr_triggered()) {
1029                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1030                 return -EHWPOISON;
1031         }
1032
1033         file_priv->driver_priv = NULL;
1034
1035         r = pm_runtime_get_sync(dev->dev);
1036         if (r < 0)
1037                 goto pm_put;
1038
1039         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1040         if (unlikely(!fpriv)) {
1041                 r = -ENOMEM;
1042                 goto out_suspend;
1043         }
1044
1045         pasid = amdgpu_pasid_alloc(16);
1046         if (pasid < 0) {
1047                 dev_warn(adev->dev, "No more PASIDs available!");
1048                 pasid = 0;
1049         }
1050         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1051         if (r)
1052                 goto error_pasid;
1053
1054         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1055         if (!fpriv->prt_va) {
1056                 r = -ENOMEM;
1057                 goto error_vm;
1058         }
1059
1060         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1061                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1062
1063                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1064                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1065                 if (r)
1066                         goto error_vm;
1067         }
1068
1069         mutex_init(&fpriv->bo_list_lock);
1070         idr_init(&fpriv->bo_list_handles);
1071
1072         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1073
1074         file_priv->driver_priv = fpriv;
1075         goto out_suspend;
1076
1077 error_vm:
1078         amdgpu_vm_fini(adev, &fpriv->vm);
1079
1080 error_pasid:
1081         if (pasid)
1082                 amdgpu_pasid_free(pasid);
1083
1084         kfree(fpriv);
1085
1086 out_suspend:
1087         pm_runtime_mark_last_busy(dev->dev);
1088 pm_put:
1089         pm_runtime_put_autosuspend(dev->dev);
1090
1091         return r;
1092 }
1093
1094 /**
1095  * amdgpu_driver_postclose_kms - drm callback for post close
1096  *
1097  * @dev: drm dev pointer
1098  * @file_priv: drm file
1099  *
1100  * On device post close, tear down vm on cayman+ (all asics).
1101  */
1102 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1103                                  struct drm_file *file_priv)
1104 {
1105         struct amdgpu_device *adev = drm_to_adev(dev);
1106         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1107         struct amdgpu_bo_list *list;
1108         struct amdgpu_bo *pd;
1109         u32 pasid;
1110         int handle;
1111
1112         if (!fpriv)
1113                 return;
1114
1115         pm_runtime_get_sync(dev->dev);
1116
1117         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1118                 amdgpu_uvd_free_handles(adev, file_priv);
1119         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1120                 amdgpu_vce_free_handles(adev, file_priv);
1121
1122         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1123
1124         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1125                 /* TODO: how to handle reserve failure */
1126                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1127                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1128                 fpriv->csa_va = NULL;
1129                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1130         }
1131
1132         pasid = fpriv->vm.pasid;
1133         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1134
1135         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1136         amdgpu_vm_fini(adev, &fpriv->vm);
1137
1138         if (pasid)
1139                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1140         amdgpu_bo_unref(&pd);
1141
1142         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1143                 amdgpu_bo_list_put(list);
1144
1145         idr_destroy(&fpriv->bo_list_handles);
1146         mutex_destroy(&fpriv->bo_list_lock);
1147
1148         kfree(fpriv);
1149         file_priv->driver_priv = NULL;
1150
1151         pm_runtime_mark_last_busy(dev->dev);
1152         pm_runtime_put_autosuspend(dev->dev);
1153 }
1154
1155 /*
1156  * VBlank related functions.
1157  */
1158 /**
1159  * amdgpu_get_vblank_counter_kms - get frame count
1160  *
1161  * @crtc: crtc to get the frame count from
1162  *
1163  * Gets the frame count on the requested crtc (all asics).
1164  * Returns frame count on success, -EINVAL on failure.
1165  */
1166 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1167 {
1168         struct drm_device *dev = crtc->dev;
1169         unsigned int pipe = crtc->index;
1170         struct amdgpu_device *adev = drm_to_adev(dev);
1171         int vpos, hpos, stat;
1172         u32 count;
1173
1174         if (pipe >= adev->mode_info.num_crtc) {
1175                 DRM_ERROR("Invalid crtc %u\n", pipe);
1176                 return -EINVAL;
1177         }
1178
1179         /* The hw increments its frame counter at start of vsync, not at start
1180          * of vblank, as is required by DRM core vblank counter handling.
1181          * Cook the hw count here to make it appear to the caller as if it
1182          * incremented at start of vblank. We measure distance to start of
1183          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1184          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1185          * result by 1 to give the proper appearance to caller.
1186          */
1187         if (adev->mode_info.crtcs[pipe]) {
1188                 /* Repeat readout if needed to provide stable result if
1189                  * we cross start of vsync during the queries.
1190                  */
1191                 do {
1192                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1193                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1194                          * vpos as distance to start of vblank, instead of
1195                          * regular vertical scanout pos.
1196                          */
1197                         stat = amdgpu_display_get_crtc_scanoutpos(
1198                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1199                                 &vpos, &hpos, NULL, NULL,
1200                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1201                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1202
1203                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1204                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1205                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1206                 } else {
1207                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1208                                       pipe, vpos);
1209
1210                         /* Bump counter if we are at >= leading edge of vblank,
1211                          * but before vsync where vpos would turn negative and
1212                          * the hw counter really increments.
1213                          */
1214                         if (vpos >= 0)
1215                                 count++;
1216                 }
1217         } else {
1218                 /* Fallback to use value as is. */
1219                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1220                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1221         }
1222
1223         return count;
1224 }
1225
1226 /**
1227  * amdgpu_enable_vblank_kms - enable vblank interrupt
1228  *
1229  * @crtc: crtc to enable vblank interrupt for
1230  *
1231  * Enable the interrupt on the requested crtc (all asics).
1232  * Returns 0 on success, -EINVAL on failure.
1233  */
1234 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1235 {
1236         struct drm_device *dev = crtc->dev;
1237         unsigned int pipe = crtc->index;
1238         struct amdgpu_device *adev = drm_to_adev(dev);
1239         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1240
1241         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1242 }
1243
1244 /**
1245  * amdgpu_disable_vblank_kms - disable vblank interrupt
1246  *
1247  * @crtc: crtc to disable vblank interrupt for
1248  *
1249  * Disable the interrupt on the requested crtc (all asics).
1250  */
1251 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1252 {
1253         struct drm_device *dev = crtc->dev;
1254         unsigned int pipe = crtc->index;
1255         struct amdgpu_device *adev = drm_to_adev(dev);
1256         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1257
1258         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1259 }
1260
1261 /*
1262  * Debugfs info
1263  */
1264 #if defined(CONFIG_DEBUG_FS)
1265
1266 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1267 {
1268         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1269         struct drm_amdgpu_info_firmware fw_info;
1270         struct drm_amdgpu_query_fw query_fw;
1271         struct atom_context *ctx = adev->mode_info.atom_context;
1272         int ret, i;
1273
1274         /* VCE */
1275         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1276         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1277         if (ret)
1278                 return ret;
1279         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1280                    fw_info.feature, fw_info.ver);
1281
1282         /* UVD */
1283         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1284         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1285         if (ret)
1286                 return ret;
1287         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1288                    fw_info.feature, fw_info.ver);
1289
1290         /* GMC */
1291         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1292         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1293         if (ret)
1294                 return ret;
1295         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1296                    fw_info.feature, fw_info.ver);
1297
1298         /* ME */
1299         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1300         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1301         if (ret)
1302                 return ret;
1303         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1304                    fw_info.feature, fw_info.ver);
1305
1306         /* PFP */
1307         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1308         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1309         if (ret)
1310                 return ret;
1311         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1312                    fw_info.feature, fw_info.ver);
1313
1314         /* CE */
1315         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1316         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1317         if (ret)
1318                 return ret;
1319         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1320                    fw_info.feature, fw_info.ver);
1321
1322         /* RLC */
1323         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1324         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1325         if (ret)
1326                 return ret;
1327         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1328                    fw_info.feature, fw_info.ver);
1329
1330         /* RLC SAVE RESTORE LIST CNTL */
1331         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1332         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1333         if (ret)
1334                 return ret;
1335         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1336                    fw_info.feature, fw_info.ver);
1337
1338         /* RLC SAVE RESTORE LIST GPM MEM */
1339         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1340         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1341         if (ret)
1342                 return ret;
1343         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1344                    fw_info.feature, fw_info.ver);
1345
1346         /* RLC SAVE RESTORE LIST SRM MEM */
1347         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1348         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1349         if (ret)
1350                 return ret;
1351         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1352                    fw_info.feature, fw_info.ver);
1353
1354         /* MEC */
1355         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1356         query_fw.index = 0;
1357         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1358         if (ret)
1359                 return ret;
1360         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1361                    fw_info.feature, fw_info.ver);
1362
1363         /* MEC2 */
1364         if (adev->gfx.mec2_fw) {
1365                 query_fw.index = 1;
1366                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1367                 if (ret)
1368                         return ret;
1369                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1370                            fw_info.feature, fw_info.ver);
1371         }
1372
1373         /* PSP SOS */
1374         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1375         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1376         if (ret)
1377                 return ret;
1378         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1379                    fw_info.feature, fw_info.ver);
1380
1381
1382         /* PSP ASD */
1383         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1384         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1385         if (ret)
1386                 return ret;
1387         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1388                    fw_info.feature, fw_info.ver);
1389
1390         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1391         for (i = 0; i < 4; i++) {
1392                 query_fw.index = i;
1393                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1394                 if (ret)
1395                         continue;
1396                 switch (query_fw.index) {
1397                 case 0:
1398                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1399                                         "RAS", fw_info.feature, fw_info.ver);
1400                         break;
1401                 case 1:
1402                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1403                                         "XGMI", fw_info.feature, fw_info.ver);
1404                         break;
1405                 case 2:
1406                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1407                                         "HDCP", fw_info.feature, fw_info.ver);
1408                         break;
1409                 case 3:
1410                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1411                                         "DTM", fw_info.feature, fw_info.ver);
1412                         break;
1413                 default:
1414                         return -EINVAL;
1415                 }
1416         }
1417
1418         /* SMC */
1419         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1420         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1421         if (ret)
1422                 return ret;
1423         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1424                    fw_info.feature, fw_info.ver);
1425
1426         /* SDMA */
1427         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1428         for (i = 0; i < adev->sdma.num_instances; i++) {
1429                 query_fw.index = i;
1430                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1431                 if (ret)
1432                         return ret;
1433                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1434                            i, fw_info.feature, fw_info.ver);
1435         }
1436
1437         /* VCN */
1438         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1439         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1440         if (ret)
1441                 return ret;
1442         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1443                    fw_info.feature, fw_info.ver);
1444
1445         /* DMCU */
1446         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1447         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1448         if (ret)
1449                 return ret;
1450         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1451                    fw_info.feature, fw_info.ver);
1452
1453         /* DMCUB */
1454         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1455         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1456         if (ret)
1457                 return ret;
1458         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1459                    fw_info.feature, fw_info.ver);
1460
1461         /* TOC */
1462         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1463         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1464         if (ret)
1465                 return ret;
1466         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1467                    fw_info.feature, fw_info.ver);
1468
1469         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1470
1471         return 0;
1472 }
1473
1474 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1475
1476 #endif
1477
1478 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1479 {
1480 #if defined(CONFIG_DEBUG_FS)
1481         struct drm_minor *minor = adev_to_drm(adev)->primary;
1482         struct dentry *root = minor->debugfs_root;
1483
1484         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1485                             adev, &amdgpu_debugfs_firmware_info_fops);
1486
1487 #endif
1488 }