drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38 #include <linux/pci.h>
  39 #include <linux/pm_runtime.h>
  40 #include "amdgpu_amdkfd.h"
  41 #include "amdgpu_gem.h"
  42 #include "amdgpu_display.h"
  43 #include "amdgpu_ras.h"
  44
  45 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  46 {
  47         struct amdgpu_gpu_instance *gpu_instance;
  48         int i;
  49
  50         mutex_lock(&mgpu_info.mutex);
  51
  52         for (i = 0; i < mgpu_info.num_gpu; i++) {
  53                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  54                 if (gpu_instance->adev == adev) {
  55                         mgpu_info.gpu_ins[i] =
  56                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  57                         mgpu_info.num_gpu--;
  58                         if (adev->flags & AMD_IS_APU)
  59                                 mgpu_info.num_apu--;
  60                         else
  61                                 mgpu_info.num_dgpu--;
  62                         break;
  63                 }
  64         }
  65
  66         mutex_unlock(&mgpu_info.mutex);
  67 }
  68
  69 /**
  70  * amdgpu_driver_unload_kms - Main unload function for KMS.
  71  *
  72  * @dev: drm dev pointer
  73  *
  74  * This is the main unload function for KMS (all asics).
  75  * Returns 0 on success.
  76  */
  77 void amdgpu_driver_unload_kms(struct drm_device *dev)
  78 {
  79         struct amdgpu_device *adev = drm_to_adev(dev);
  80
  81         if (adev == NULL)
  82                 return;
  83
  84         amdgpu_unregister_gpu_instance(adev);
  85
  86         if (adev->rmmio == NULL)
  87                 return;
  88
  89         if (adev->runpm) {
  90                 pm_runtime_get_sync(dev->dev);
  91                 pm_runtime_forbid(dev->dev);
  92         }
  93
  94         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  95                 DRM_WARN("smart shift update failed\n");
  96
  97         amdgpu_acpi_fini(adev);
  98         amdgpu_device_fini(adev);
  99 }
 100
 101 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 102 {
 103         struct amdgpu_gpu_instance *gpu_instance;
 104
 105         mutex_lock(&mgpu_info.mutex);
 106
 107         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 108                 DRM_ERROR("Cannot register more gpu instance\n");
 109                 mutex_unlock(&mgpu_info.mutex);
 110                 return;
 111         }
 112
 113         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 114         gpu_instance->adev = adev;
 115         gpu_instance->mgpu_fan_enabled = 0;
 116
 117         mgpu_info.num_gpu++;
 118         if (adev->flags & AMD_IS_APU)
 119                 mgpu_info.num_apu++;
 120         else
 121                 mgpu_info.num_dgpu++;
 122
 123         mutex_unlock(&mgpu_info.mutex);
 124 }
 125
 126 /**
 127  * amdgpu_driver_load_kms - Main load function for KMS.
 128  *
 129  * @adev: pointer to struct amdgpu_device
 130  * @flags: device flags
 131  *
 132  * This is the main load function for KMS (all asics).
 133  * Returns 0 on success, error on failure.
 134  */
 135 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 136 {
 137         struct drm_device *dev;
 138         struct pci_dev *parent;
 139         int r, acpi_status;
 140
 141         dev = adev_to_drm(adev);
 142
 143         if (amdgpu_has_atpx() &&
 144             (amdgpu_is_atpx_hybrid() ||
 145              amdgpu_has_atpx_dgpu_power_cntl()) &&
 146             ((flags & AMD_IS_APU) == 0) &&
 147             !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
 148                 flags |= AMD_IS_PX;
 149
 150         parent = pci_upstream_bridge(adev->pdev);
 151         adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
 152
 153         /* amdgpu_device_init should report only fatal error
 154          * like memory allocation failure or iomapping failure,
 155          * or memory manager initialization failure, it must
 156          * properly initialize the GPU MC controller and permit
 157          * VRAM allocation
 158          */
 159         r = amdgpu_device_init(adev, flags);
 160         if (r) {
 161                 dev_err(dev->dev, "Fatal error during GPU init\n");
 162                 goto out;
 163         }
 164
 165         if (amdgpu_device_supports_px(dev) &&
 166             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 167                 adev->runpm = true;
 168                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 169         } else if (amdgpu_device_supports_boco(dev) &&
 170                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 171                 adev->runpm = true;
 172                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 173         } else if (amdgpu_device_supports_baco(dev) &&
 174                    (amdgpu_runtime_pm != 0)) {
 175                 switch (adev->asic_type) {
 176                 case CHIP_VEGA20:
 177                 case CHIP_ARCTURUS:
 178                         /* enable runpm if runpm=1 */
 179                         if (amdgpu_runtime_pm > 0)
 180                                 adev->runpm = true;
 181                         break;
 182                 case CHIP_VEGA10:
 183                         /* turn runpm on if noretry=0 */
 184                         if (!adev->gmc.noretry)
 185                                 adev->runpm = true;
 186                         break;
 187                 default:
 188                         /* enable runpm on CI+ */
 189                         adev->runpm = true;
 190                         break;
 191                 }
 192                 if (adev->runpm)
 193                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 194         }
 195
 196         /* Call ACPI methods: require modeset init
 197          * but failure is not fatal
 198          */
 199
 200         acpi_status = amdgpu_acpi_init(adev);
 201         if (acpi_status)
 202                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 203
 204         if (adev->runpm) {
 205                 /* only need to skip on ATPX */
 206                 if (amdgpu_device_supports_px(dev))
 207                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 208                 /* we want direct complete for BOCO */
 209                 if (amdgpu_device_supports_boco(dev))
 210                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
 211                                                 DPM_FLAG_SMART_SUSPEND |
 212                                                 DPM_FLAG_MAY_SKIP_RESUME);
 213                 pm_runtime_use_autosuspend(dev->dev);
 214                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 215                 pm_runtime_allow(dev->dev);
 216                 pm_runtime_mark_last_busy(dev->dev);
 217                 pm_runtime_put_autosuspend(dev->dev);
 218         }
 219
 220         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 221                 DRM_WARN("smart shift update failed\n");
 222
 223 out:
 224         if (r) {
 225                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 226                 if (adev->rmmio && adev->runpm)
 227                         pm_runtime_put_noidle(dev->dev);
 228                 amdgpu_driver_unload_kms(dev);
 229         }
 230
 231         return r;
 232 }
 233
 234 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 235                                 struct drm_amdgpu_query_fw *query_fw,
 236                                 struct amdgpu_device *adev)
 237 {
 238         switch (query_fw->fw_type) {
 239         case AMDGPU_INFO_FW_VCE:
 240                 fw_info->ver = adev->vce.fw_version;
 241                 fw_info->feature = adev->vce.fb_version;
 242                 break;
 243         case AMDGPU_INFO_FW_UVD:
 244                 fw_info->ver = adev->uvd.fw_version;
 245                 fw_info->feature = 0;
 246                 break;
 247         case AMDGPU_INFO_FW_VCN:
 248                 fw_info->ver = adev->vcn.fw_version;
 249                 fw_info->feature = 0;
 250                 break;
 251         case AMDGPU_INFO_FW_GMC:
 252                 fw_info->ver = adev->gmc.fw_version;
 253                 fw_info->feature = 0;
 254                 break;
 255         case AMDGPU_INFO_FW_GFX_ME:
 256                 fw_info->ver = adev->gfx.me_fw_version;
 257                 fw_info->feature = adev->gfx.me_feature_version;
 258                 break;
 259         case AMDGPU_INFO_FW_GFX_PFP:
 260                 fw_info->ver = adev->gfx.pfp_fw_version;
 261                 fw_info->feature = adev->gfx.pfp_feature_version;
 262                 break;
 263         case AMDGPU_INFO_FW_GFX_CE:
 264                 fw_info->ver = adev->gfx.ce_fw_version;
 265                 fw_info->feature = adev->gfx.ce_feature_version;
 266                 break;
 267         case AMDGPU_INFO_FW_GFX_RLC:
 268                 fw_info->ver = adev->gfx.rlc_fw_version;
 269                 fw_info->feature = adev->gfx.rlc_feature_version;
 270                 break;
 271         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 272                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 273                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 274                 break;
 275         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 276                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 277                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 278                 break;
 279         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 280                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 281                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 282                 break;
 283         case AMDGPU_INFO_FW_GFX_MEC:
 284                 if (query_fw->index == 0) {
 285                         fw_info->ver = adev->gfx.mec_fw_version;
 286                         fw_info->feature = adev->gfx.mec_feature_version;
 287                 } else if (query_fw->index == 1) {
 288                         fw_info->ver = adev->gfx.mec2_fw_version;
 289                         fw_info->feature = adev->gfx.mec2_feature_version;
 290                 } else
 291                         return -EINVAL;
 292                 break;
 293         case AMDGPU_INFO_FW_SMC:
 294                 fw_info->ver = adev->pm.fw_version;
 295                 fw_info->feature = 0;
 296                 break;
 297         case AMDGPU_INFO_FW_TA:
 298                 switch (query_fw->index) {
 299                 case TA_FW_TYPE_PSP_XGMI:
 300                         fw_info->ver = adev->psp.ta_fw_version;
 301                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 302                         break;
 303                 case TA_FW_TYPE_PSP_RAS:
 304                         fw_info->ver = adev->psp.ta_fw_version;
 305                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 306                         break;
 307                 case TA_FW_TYPE_PSP_HDCP:
 308                         fw_info->ver = adev->psp.ta_fw_version;
 309                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 310                         break;
 311                 case TA_FW_TYPE_PSP_DTM:
 312                         fw_info->ver = adev->psp.ta_fw_version;
 313                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 314                         break;
 315                 case TA_FW_TYPE_PSP_RAP:
 316                         fw_info->ver = adev->psp.ta_fw_version;
 317                         fw_info->feature = adev->psp.ta_rap_ucode_version;
 318                         break;
 319                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 320                         fw_info->ver = adev->psp.ta_fw_version;
 321                         fw_info->feature = adev->psp.ta_securedisplay_ucode_version;
 322                         break;
 323                 default:
 324                         return -EINVAL;
 325                 }
 326                 break;
 327         case AMDGPU_INFO_FW_SDMA:
 328                 if (query_fw->index >= adev->sdma.num_instances)
 329                         return -EINVAL;
 330                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 331                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 332                 break;
 333         case AMDGPU_INFO_FW_SOS:
 334                 fw_info->ver = adev->psp.sos_fw_version;
 335                 fw_info->feature = adev->psp.sos_feature_version;
 336                 break;
 337         case AMDGPU_INFO_FW_ASD:
 338                 fw_info->ver = adev->psp.asd_fw_version;
 339                 fw_info->feature = adev->psp.asd_feature_version;
 340                 break;
 341         case AMDGPU_INFO_FW_DMCU:
 342                 fw_info->ver = adev->dm.dmcu_fw_version;
 343                 fw_info->feature = 0;
 344                 break;
 345         case AMDGPU_INFO_FW_DMCUB:
 346                 fw_info->ver = adev->dm.dmcub_fw_version;
 347                 fw_info->feature = 0;
 348                 break;
 349         case AMDGPU_INFO_FW_TOC:
 350                 fw_info->ver = adev->psp.toc_fw_version;
 351                 fw_info->feature = adev->psp.toc_feature_version;
 352                 break;
 353         default:
 354                 return -EINVAL;
 355         }
 356         return 0;
 357 }
 358
 359 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 360                              struct drm_amdgpu_info *info,
 361                              struct drm_amdgpu_info_hw_ip *result)
 362 {
 363         uint32_t ib_start_alignment = 0;
 364         uint32_t ib_size_alignment = 0;
 365         enum amd_ip_block_type type;
 366         unsigned int num_rings = 0;
 367         unsigned int i, j;
 368
 369         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 370                 return -EINVAL;
 371
 372         switch (info->query_hw_ip.type) {
 373         case AMDGPU_HW_IP_GFX:
 374                 type = AMD_IP_BLOCK_TYPE_GFX;
 375                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 376                         if (adev->gfx.gfx_ring[i].sched.ready)
 377                                 ++num_rings;
 378                 ib_start_alignment = 32;
 379                 ib_size_alignment = 32;
 380                 break;
 381         case AMDGPU_HW_IP_COMPUTE:
 382                 type = AMD_IP_BLOCK_TYPE_GFX;
 383                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 384                         if (adev->gfx.compute_ring[i].sched.ready)
 385                                 ++num_rings;
 386                 ib_start_alignment = 32;
 387                 ib_size_alignment = 32;
 388                 break;
 389         case AMDGPU_HW_IP_DMA:
 390                 type = AMD_IP_BLOCK_TYPE_SDMA;
 391                 for (i = 0; i < adev->sdma.num_instances; i++)
 392                         if (adev->sdma.instance[i].ring.sched.ready)
 393                                 ++num_rings;
 394                 ib_start_alignment = 256;
 395                 ib_size_alignment = 4;
 396                 break;
 397         case AMDGPU_HW_IP_UVD:
 398                 type = AMD_IP_BLOCK_TYPE_UVD;
 399                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 400                         if (adev->uvd.harvest_config & (1 << i))
 401                                 continue;
 402
 403                         if (adev->uvd.inst[i].ring.sched.ready)
 404                                 ++num_rings;
 405                 }
 406                 ib_start_alignment = 64;
 407                 ib_size_alignment = 64;
 408                 break;
 409         case AMDGPU_HW_IP_VCE:
 410                 type = AMD_IP_BLOCK_TYPE_VCE;
 411                 for (i = 0; i < adev->vce.num_rings; i++)
 412                         if (adev->vce.ring[i].sched.ready)
 413                                 ++num_rings;
 414                 ib_start_alignment = 4;
 415                 ib_size_alignment = 1;
 416                 break;
 417         case AMDGPU_HW_IP_UVD_ENC:
 418                 type = AMD_IP_BLOCK_TYPE_UVD;
 419                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 420                         if (adev->uvd.harvest_config & (1 << i))
 421                                 continue;
 422
 423                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 424                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 425                                         ++num_rings;
 426                 }
 427                 ib_start_alignment = 64;
 428                 ib_size_alignment = 64;
 429                 break;
 430         case AMDGPU_HW_IP_VCN_DEC:
 431                 type = AMD_IP_BLOCK_TYPE_VCN;
 432                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 433                         if (adev->uvd.harvest_config & (1 << i))
 434                                 continue;
 435
 436                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 437                                 ++num_rings;
 438                 }
 439                 ib_start_alignment = 16;
 440                 ib_size_alignment = 16;
 441                 break;
 442         case AMDGPU_HW_IP_VCN_ENC:
 443                 type = AMD_IP_BLOCK_TYPE_VCN;
 444                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 445                         if (adev->uvd.harvest_config & (1 << i))
 446                                 continue;
 447
 448                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 449                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 450                                         ++num_rings;
 451                 }
 452                 ib_start_alignment = 64;
 453                 ib_size_alignment = 1;
 454                 break;
 455         case AMDGPU_HW_IP_VCN_JPEG:
 456                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 457                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 458
 459                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 460                         if (adev->jpeg.harvest_config & (1 << i))
 461                                 continue;
 462
 463                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 464                                 ++num_rings;
 465                 }
 466                 ib_start_alignment = 16;
 467                 ib_size_alignment = 16;
 468                 break;
 469         default:
 470                 return -EINVAL;
 471         }
 472
 473         for (i = 0; i < adev->num_ip_blocks; i++)
 474                 if (adev->ip_blocks[i].version->type == type &&
 475                     adev->ip_blocks[i].status.valid)
 476                         break;
 477
 478         if (i == adev->num_ip_blocks)
 479                 return 0;
 480
 481         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 482                         num_rings);
 483
 484         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 485         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 486         result->capabilities_flags = 0;
 487         result->available_rings = (1 << num_rings) - 1;
 488         result->ib_start_alignment = ib_start_alignment;
 489         result->ib_size_alignment = ib_size_alignment;
 490         return 0;
 491 }
 492
 493 /*
 494  * Userspace get information ioctl
 495  */
 496 /**
 497  * amdgpu_info_ioctl - answer a device specific request.
 498  *
 499  * @dev: drm device pointer
 500  * @data: request object
 501  * @filp: drm filp
 502  *
 503  * This function is used to pass device specific parameters to the userspace
 504  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 505  * etc. (all asics).
 506  * Returns 0 on success, -EINVAL on failure.
 507  */
 508 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 509 {
 510         struct amdgpu_device *adev = drm_to_adev(dev);
 511         struct drm_amdgpu_info *info = data;
 512         struct amdgpu_mode_info *minfo = &adev->mode_info;
 513         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 514         uint32_t size = info->return_size;
 515         struct drm_crtc *crtc;
 516         uint32_t ui32 = 0;
 517         uint64_t ui64 = 0;
 518         int i, found;
 519         int ui32_size = sizeof(ui32);
 520
 521         if (!info->return_size || !info->return_pointer)
 522                 return -EINVAL;
 523
 524         switch (info->query) {
 525         case AMDGPU_INFO_ACCEL_WORKING:
 526                 ui32 = adev->accel_working;
 527                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 528         case AMDGPU_INFO_CRTC_FROM_ID:
 529                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 530                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 531                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 532                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 533                                 ui32 = amdgpu_crtc->crtc_id;
 534                                 found = 1;
 535                                 break;
 536                         }
 537                 }
 538                 if (!found) {
 539                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 540                         return -EINVAL;
 541                 }
 542                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 543         case AMDGPU_INFO_HW_IP_INFO: {
 544                 struct drm_amdgpu_info_hw_ip ip = {};
 545                 int ret;
 546
 547                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 548                 if (ret)
 549                         return ret;
 550
 551                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 552                 return ret ? -EFAULT : 0;
 553         }
 554         case AMDGPU_INFO_HW_IP_COUNT: {
 555                 enum amd_ip_block_type type;
 556                 uint32_t count = 0;
 557
 558                 switch (info->query_hw_ip.type) {
 559                 case AMDGPU_HW_IP_GFX:
 560                         type = AMD_IP_BLOCK_TYPE_GFX;
 561                         break;
 562                 case AMDGPU_HW_IP_COMPUTE:
 563                         type = AMD_IP_BLOCK_TYPE_GFX;
 564                         break;
 565                 case AMDGPU_HW_IP_DMA:
 566                         type = AMD_IP_BLOCK_TYPE_SDMA;
 567                         break;
 568                 case AMDGPU_HW_IP_UVD:
 569                         type = AMD_IP_BLOCK_TYPE_UVD;
 570                         break;
 571                 case AMDGPU_HW_IP_VCE:
 572                         type = AMD_IP_BLOCK_TYPE_VCE;
 573                         break;
 574                 case AMDGPU_HW_IP_UVD_ENC:
 575                         type = AMD_IP_BLOCK_TYPE_UVD;
 576                         break;
 577                 case AMDGPU_HW_IP_VCN_DEC:
 578                 case AMDGPU_HW_IP_VCN_ENC:
 579                         type = AMD_IP_BLOCK_TYPE_VCN;
 580                         break;
 581                 case AMDGPU_HW_IP_VCN_JPEG:
 582                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 583                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 584                         break;
 585                 default:
 586                         return -EINVAL;
 587                 }
 588
 589                 for (i = 0; i < adev->num_ip_blocks; i++)
 590                         if (adev->ip_blocks[i].version->type == type &&
 591                             adev->ip_blocks[i].status.valid &&
 592                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 593                                 count++;
 594
 595                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 596         }
 597         case AMDGPU_INFO_TIMESTAMP:
 598                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 599                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 600         case AMDGPU_INFO_FW_VERSION: {
 601                 struct drm_amdgpu_info_firmware fw_info;
 602                 int ret;
 603
 604                 /* We only support one instance of each IP block right now. */
 605                 if (info->query_fw.ip_instance != 0)
 606                         return -EINVAL;
 607
 608                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 609                 if (ret)
 610                         return ret;
 611
 612                 return copy_to_user(out, &fw_info,
 613                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 614         }
 615         case AMDGPU_INFO_NUM_BYTES_MOVED:
 616                 ui64 = atomic64_read(&adev->num_bytes_moved);
 617                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 618         case AMDGPU_INFO_NUM_EVICTIONS:
 619                 ui64 = atomic64_read(&adev->num_evictions);
 620                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 621         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 622                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 623                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 624         case AMDGPU_INFO_VRAM_USAGE:
 625                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 626                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 627         case AMDGPU_INFO_VIS_VRAM_USAGE:
 628                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 629                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 630         case AMDGPU_INFO_GTT_USAGE:
 631                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 632                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 633         case AMDGPU_INFO_GDS_CONFIG: {
 634                 struct drm_amdgpu_info_gds gds_info;
 635
 636                 memset(&gds_info, 0, sizeof(gds_info));
 637                 gds_info.compute_partition_size = adev->gds.gds_size;
 638                 gds_info.gds_total_size = adev->gds.gds_size;
 639                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 640                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 641                 return copy_to_user(out, &gds_info,
 642                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 643         }
 644         case AMDGPU_INFO_VRAM_GTT: {
 645                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 646
 647                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 648                         atomic64_read(&adev->vram_pin_size) -
 649                         AMDGPU_VM_RESERVED_VRAM;
 650                 vram_gtt.vram_cpu_accessible_size =
 651                         min(adev->gmc.visible_vram_size -
 652                             atomic64_read(&adev->visible_pin_size),
 653                             vram_gtt.vram_size);
 654                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 655                 vram_gtt.gtt_size *= PAGE_SIZE;
 656                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 657                 return copy_to_user(out, &vram_gtt,
 658                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 659         }
 660         case AMDGPU_INFO_MEMORY: {
 661                 struct drm_amdgpu_memory_info mem;
 662                 struct ttm_resource_manager *vram_man =
 663                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 664                 struct ttm_resource_manager *gtt_man =
 665                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 666                 memset(&mem, 0, sizeof(mem));
 667                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 668                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 669                         atomic64_read(&adev->vram_pin_size) -
 670                         AMDGPU_VM_RESERVED_VRAM;
 671                 mem.vram.heap_usage =
 672                         amdgpu_vram_mgr_usage(vram_man);
 673                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 674
 675                 mem.cpu_accessible_vram.total_heap_size =
 676                         adev->gmc.visible_vram_size;
 677                 mem.cpu_accessible_vram.usable_heap_size =
 678                         min(adev->gmc.visible_vram_size -
 679                             atomic64_read(&adev->visible_pin_size),
 680                             mem.vram.usable_heap_size);
 681                 mem.cpu_accessible_vram.heap_usage =
 682                         amdgpu_vram_mgr_vis_usage(vram_man);
 683                 mem.cpu_accessible_vram.max_allocation =
 684                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 685
 686                 mem.gtt.total_heap_size = gtt_man->size;
 687                 mem.gtt.total_heap_size *= PAGE_SIZE;
 688                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 689                         atomic64_read(&adev->gart_pin_size);
 690                 mem.gtt.heap_usage =
 691                         amdgpu_gtt_mgr_usage(gtt_man);
 692                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 693
 694                 return copy_to_user(out, &mem,
 695                                     min((size_t)size, sizeof(mem)))
 696                                     ? -EFAULT : 0;
 697         }
 698         case AMDGPU_INFO_READ_MMR_REG: {
 699                 unsigned n, alloc_size;
 700                 uint32_t *regs;
 701                 unsigned se_num = (info->read_mmr_reg.instance >>
 702                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 703                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 704                 unsigned sh_num = (info->read_mmr_reg.instance >>
 705                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 706                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 707
 708                 /* set full masks if the userspace set all bits
 709                  * in the bitfields */
 710                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 711                         se_num = 0xffffffff;
 712                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 713                         return -EINVAL;
 714                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 715                         sh_num = 0xffffffff;
 716                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 717                         return -EINVAL;
 718
 719                 if (info->read_mmr_reg.count > 128)
 720                         return -EINVAL;
 721
 722                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 723                 if (!regs)
 724                         return -ENOMEM;
 725                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 726
 727                 amdgpu_gfx_off_ctrl(adev, false);
 728                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 729                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 730                                                       info->read_mmr_reg.dword_offset + i,
 731                                                       &regs[i])) {
 732                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 733                                               info->read_mmr_reg.dword_offset + i);
 734                                 kfree(regs);
 735                                 amdgpu_gfx_off_ctrl(adev, true);
 736                                 return -EFAULT;
 737                         }
 738                 }
 739                 amdgpu_gfx_off_ctrl(adev, true);
 740                 n = copy_to_user(out, regs, min(size, alloc_size));
 741                 kfree(regs);
 742                 return n ? -EFAULT : 0;
 743         }
 744         case AMDGPU_INFO_DEV_INFO: {
 745                 struct drm_amdgpu_info_device *dev_info;
 746                 uint64_t vm_size;
 747                 int ret;
 748
 749                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 750                 if (!dev_info)
 751                         return -ENOMEM;
 752
 753                 dev_info->device_id = adev->pdev->device;
 754                 dev_info->chip_rev = adev->rev_id;
 755                 dev_info->external_rev = adev->external_rev_id;
 756                 dev_info->pci_rev = adev->pdev->revision;
 757                 dev_info->family = adev->family;
 758                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 759                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 760                 /* return all clocks in KHz */
 761                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 762                 if (adev->pm.dpm_enabled) {
 763                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 764                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 765                 } else {
 766                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 767                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 768                 }
 769                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 770                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 771                         adev->gfx.config.max_shader_engines;
 772                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 773                 dev_info->_pad = 0;
 774                 dev_info->ids_flags = 0;
 775                 if (adev->flags & AMD_IS_APU)
 776                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 777                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 778                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 779                 if (amdgpu_is_tmz(adev))
 780                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 781
 782                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 783                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 784
 785                 /* Older VCE FW versions are buggy and can handle only 40bits */
 786                 if (adev->vce.fw_version &&
 787                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 788                         vm_size = min(vm_size, 1ULL << 40);
 789
 790                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 791                 dev_info->virtual_address_max =
 792                         min(vm_size, AMDGPU_GMC_HOLE_START);
 793
 794                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 795                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 796                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 797                 }
 798                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 799                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 800                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 801                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 802                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 803                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 804                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 805                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 806                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 807                        sizeof(adev->gfx.cu_info.bitmap));
 808                 dev_info->vram_type = adev->gmc.vram_type;
 809                 dev_info->vram_bit_width = adev->gmc.vram_width;
 810                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 811                 dev_info->gc_double_offchip_lds_buf =
 812                         adev->gfx.config.double_offchip_lds_buf;
 813                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 814                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 815                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 816                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 817                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 818                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 819                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 820
 821                 if (adev->family >= AMDGPU_FAMILY_NV)
 822                         dev_info->pa_sc_tile_steering_override =
 823                                 adev->gfx.config.pa_sc_tile_steering_override;
 824
 825                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 826
 827                 ret = copy_to_user(out, dev_info,
 828                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 829                 kfree(dev_info);
 830                 return ret;
 831         }
 832         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 833                 unsigned i;
 834                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 835                 struct amd_vce_state *vce_state;
 836
 837                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 838                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 839                         if (vce_state) {
 840                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 841                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 842                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 843                                 vce_clk_table.num_valid_entries++;
 844                         }
 845                 }
 846
 847                 return copy_to_user(out, &vce_clk_table,
 848                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 849         }
 850         case AMDGPU_INFO_VBIOS: {
 851                 uint32_t bios_size = adev->bios_size;
 852
 853                 switch (info->vbios_info.type) {
 854                 case AMDGPU_INFO_VBIOS_SIZE:
 855                         return copy_to_user(out, &bios_size,
 856                                         min((size_t)size, sizeof(bios_size)))
 857                                         ? -EFAULT : 0;
 858                 case AMDGPU_INFO_VBIOS_IMAGE: {
 859                         uint8_t *bios;
 860                         uint32_t bios_offset = info->vbios_info.offset;
 861
 862                         if (bios_offset >= bios_size)
 863                                 return -EINVAL;
 864
 865                         bios = adev->bios + bios_offset;
 866                         return copy_to_user(out, bios,
 867                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 868                                         ? -EFAULT : 0;
 869                 }
 870                 case AMDGPU_INFO_VBIOS_INFO: {
 871                         struct drm_amdgpu_info_vbios vbios_info = {};
 872                         struct atom_context *atom_context;
 873
 874                         atom_context = adev->mode_info.atom_context;
 875                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 876                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 877                         vbios_info.version = atom_context->version;
 878                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 879                                                 sizeof(atom_context->vbios_ver_str));
 880                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 881
 882                         return copy_to_user(out, &vbios_info,
 883                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 884                 }
 885                 default:
 886                         DRM_DEBUG_KMS("Invalid request %d\n",
 887                                         info->vbios_info.type);
 888                         return -EINVAL;
 889                 }
 890         }
 891         case AMDGPU_INFO_NUM_HANDLES: {
 892                 struct drm_amdgpu_info_num_handles handle;
 893
 894                 switch (info->query_hw_ip.type) {
 895                 case AMDGPU_HW_IP_UVD:
 896                         /* Starting Polaris, we support unlimited UVD handles */
 897                         if (adev->asic_type < CHIP_POLARIS10) {
 898                                 handle.uvd_max_handles = adev->uvd.max_handles;
 899                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 900
 901                                 return copy_to_user(out, &handle,
 902                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 903                         } else {
 904                                 return -ENODATA;
 905                         }
 906
 907                         break;
 908                 default:
 909                         return -EINVAL;
 910                 }
 911         }
 912         case AMDGPU_INFO_SENSOR: {
 913                 if (!adev->pm.dpm_enabled)
 914                         return -ENOENT;
 915
 916                 switch (info->sensor_info.type) {
 917                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 918                         /* get sclk in Mhz */
 919                         if (amdgpu_dpm_read_sensor(adev,
 920                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 921                                                    (void *)&ui32, &ui32_size)) {
 922                                 return -EINVAL;
 923                         }
 924                         ui32 /= 100;
 925                         break;
 926                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 927                         /* get mclk in Mhz */
 928                         if (amdgpu_dpm_read_sensor(adev,
 929                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 930                                                    (void *)&ui32, &ui32_size)) {
 931                                 return -EINVAL;
 932                         }
 933                         ui32 /= 100;
 934                         break;
 935                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 936                         /* get temperature in millidegrees C */
 937                         if (amdgpu_dpm_read_sensor(adev,
 938                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 939                                                    (void *)&ui32, &ui32_size)) {
 940                                 return -EINVAL;
 941                         }
 942                         break;
 943                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 944                         /* get GPU load */
 945                         if (amdgpu_dpm_read_sensor(adev,
 946                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 947                                                    (void *)&ui32, &ui32_size)) {
 948                                 return -EINVAL;
 949                         }
 950                         break;
 951                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 952                         /* get average GPU power */
 953                         if (amdgpu_dpm_read_sensor(adev,
 954                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 955                                                    (void *)&ui32, &ui32_size)) {
 956                                 return -EINVAL;
 957                         }
 958                         ui32 >>= 8;
 959                         break;
 960                 case AMDGPU_INFO_SENSOR_VDDNB:
 961                         /* get VDDNB in millivolts */
 962                         if (amdgpu_dpm_read_sensor(adev,
 963                                                    AMDGPU_PP_SENSOR_VDDNB,
 964                                                    (void *)&ui32, &ui32_size)) {
 965                                 return -EINVAL;
 966                         }
 967                         break;
 968                 case AMDGPU_INFO_SENSOR_VDDGFX:
 969                         /* get VDDGFX in millivolts */
 970                         if (amdgpu_dpm_read_sensor(adev,
 971                                                    AMDGPU_PP_SENSOR_VDDGFX,
 972                                                    (void *)&ui32, &ui32_size)) {
 973                                 return -EINVAL;
 974                         }
 975                         break;
 976                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 977                         /* get stable pstate sclk in Mhz */
 978                         if (amdgpu_dpm_read_sensor(adev,
 979                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 980                                                    (void *)&ui32, &ui32_size)) {
 981                                 return -EINVAL;
 982                         }
 983                         ui32 /= 100;
 984                         break;
 985                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 986                         /* get stable pstate mclk in Mhz */
 987                         if (amdgpu_dpm_read_sensor(adev,
 988                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 989                                                    (void *)&ui32, &ui32_size)) {
 990                                 return -EINVAL;
 991                         }
 992                         ui32 /= 100;
 993                         break;
 994                 default:
 995                         DRM_DEBUG_KMS("Invalid request %d\n",
 996                                       info->sensor_info.type);
 997                         return -EINVAL;
 998                 }
 999                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1000         }
1001         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1002                 ui32 = atomic_read(&adev->vram_lost_counter);
1003                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1004         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1005                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1006                 uint64_t ras_mask;
1007
1008                 if (!ras)
1009                         return -EINVAL;
1010                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1011
1012                 return copy_to_user(out, &ras_mask,
1013                                 min_t(u64, size, sizeof(ras_mask))) ?
1014                         -EFAULT : 0;
1015         }
1016         case AMDGPU_INFO_VIDEO_CAPS: {
1017                 const struct amdgpu_video_codecs *codecs;
1018                 struct drm_amdgpu_info_video_caps *caps;
1019                 int r;
1020
1021                 switch (info->video_cap.type) {
1022                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1023                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1024                         if (r)
1025                                 return -EINVAL;
1026                         break;
1027                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1028                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1029                         if (r)
1030                                 return -EINVAL;
1031                         break;
1032                 default:
1033                         DRM_DEBUG_KMS("Invalid request %d\n",
1034                                       info->video_cap.type);
1035                         return -EINVAL;
1036                 }
1037
1038                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1039                 if (!caps)
1040                         return -ENOMEM;
1041
1042                 for (i = 0; i < codecs->codec_count; i++) {
1043                         int idx = codecs->codec_array[i].codec_type;
1044
1045                         switch (idx) {
1046                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1047                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1048                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1049                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1050                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1051                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1052                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1053                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1054                                 caps->codec_info[idx].valid = 1;
1055                                 caps->codec_info[idx].max_width =
1056                                         codecs->codec_array[i].max_width;
1057                                 caps->codec_info[idx].max_height =
1058                                         codecs->codec_array[i].max_height;
1059                                 caps->codec_info[idx].max_pixels_per_frame =
1060                                         codecs->codec_array[i].max_pixels_per_frame;
1061                                 caps->codec_info[idx].max_level =
1062                                         codecs->codec_array[i].max_level;
1063                                 break;
1064                         default:
1065                                 break;
1066                         }
1067                 }
1068                 r = copy_to_user(out, caps,
1069                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1070                 kfree(caps);
1071                 return r;
1072         }
1073         default:
1074                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1075                 return -EINVAL;
1076         }
1077         return 0;
1078 }
1079
1080
1081 /*
1082  * Outdated mess for old drm with Xorg being in charge (void function now).
1083  */
1084 /**
1085  * amdgpu_driver_lastclose_kms - drm callback for last close
1086  *
1087  * @dev: drm dev pointer
1088  *
1089  * Switch vga_switcheroo state after last close (all asics).
1090  */
1091 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1092 {
1093         drm_fb_helper_lastclose(dev);
1094         vga_switcheroo_process_delayed_switch();
1095 }
1096
1097 /**
1098  * amdgpu_driver_open_kms - drm callback for open
1099  *
1100  * @dev: drm dev pointer
1101  * @file_priv: drm file
1102  *
1103  * On device open, init vm on cayman+ (all asics).
1104  * Returns 0 on success, error on failure.
1105  */
1106 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1107 {
1108         struct amdgpu_device *adev = drm_to_adev(dev);
1109         struct amdgpu_fpriv *fpriv;
1110         int r, pasid;
1111
1112         /* Ensure IB tests are run on ring */
1113         flush_delayed_work(&adev->delayed_init_work);
1114
1115
1116         if (amdgpu_ras_intr_triggered()) {
1117                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1118                 return -EHWPOISON;
1119         }
1120
1121         file_priv->driver_priv = NULL;
1122
1123         r = pm_runtime_get_sync(dev->dev);
1124         if (r < 0)
1125                 goto pm_put;
1126
1127         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1128         if (unlikely(!fpriv)) {
1129                 r = -ENOMEM;
1130                 goto out_suspend;
1131         }
1132
1133         pasid = amdgpu_pasid_alloc(16);
1134         if (pasid < 0) {
1135                 dev_warn(adev->dev, "No more PASIDs available!");
1136                 pasid = 0;
1137         }
1138
1139         r = amdgpu_vm_init(adev, &fpriv->vm, pasid);
1140         if (r)
1141                 goto error_pasid;
1142
1143         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1144         if (!fpriv->prt_va) {
1145                 r = -ENOMEM;
1146                 goto error_vm;
1147         }
1148
1149         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1150                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1151
1152                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1153                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1154                 if (r)
1155                         goto error_vm;
1156         }
1157
1158         mutex_init(&fpriv->bo_list_lock);
1159         idr_init(&fpriv->bo_list_handles);
1160
1161         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1162
1163         file_priv->driver_priv = fpriv;
1164         goto out_suspend;
1165
1166 error_vm:
1167         amdgpu_vm_fini(adev, &fpriv->vm);
1168
1169 error_pasid:
1170         if (pasid)
1171                 amdgpu_pasid_free(pasid);
1172
1173         kfree(fpriv);
1174
1175 out_suspend:
1176         pm_runtime_mark_last_busy(dev->dev);
1177 pm_put:
1178         pm_runtime_put_autosuspend(dev->dev);
1179
1180         return r;
1181 }
1182
1183 /**
1184  * amdgpu_driver_postclose_kms - drm callback for post close
1185  *
1186  * @dev: drm dev pointer
1187  * @file_priv: drm file
1188  *
1189  * On device post close, tear down vm on cayman+ (all asics).
1190  */
1191 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1192                                  struct drm_file *file_priv)
1193 {
1194         struct amdgpu_device *adev = drm_to_adev(dev);
1195         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1196         struct amdgpu_bo_list *list;
1197         struct amdgpu_bo *pd;
1198         u32 pasid;
1199         int handle;
1200
1201         if (!fpriv)
1202                 return;
1203
1204         pm_runtime_get_sync(dev->dev);
1205
1206         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1207                 amdgpu_uvd_free_handles(adev, file_priv);
1208         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1209                 amdgpu_vce_free_handles(adev, file_priv);
1210
1211         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1212
1213         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1214                 /* TODO: how to handle reserve failure */
1215                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1216                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1217                 fpriv->csa_va = NULL;
1218                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1219         }
1220
1221         pasid = fpriv->vm.pasid;
1222         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1223
1224         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1225         amdgpu_vm_fini(adev, &fpriv->vm);
1226
1227         if (pasid)
1228                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1229         amdgpu_bo_unref(&pd);
1230
1231         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1232                 amdgpu_bo_list_put(list);
1233
1234         idr_destroy(&fpriv->bo_list_handles);
1235         mutex_destroy(&fpriv->bo_list_lock);
1236
1237         kfree(fpriv);
1238         file_priv->driver_priv = NULL;
1239
1240         pm_runtime_mark_last_busy(dev->dev);
1241         pm_runtime_put_autosuspend(dev->dev);
1242 }
1243
1244 /*
1245  * VBlank related functions.
1246  */
1247 /**
1248  * amdgpu_get_vblank_counter_kms - get frame count
1249  *
1250  * @crtc: crtc to get the frame count from
1251  *
1252  * Gets the frame count on the requested crtc (all asics).
1253  * Returns frame count on success, -EINVAL on failure.
1254  */
1255 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1256 {
1257         struct drm_device *dev = crtc->dev;
1258         unsigned int pipe = crtc->index;
1259         struct amdgpu_device *adev = drm_to_adev(dev);
1260         int vpos, hpos, stat;
1261         u32 count;
1262
1263         if (pipe >= adev->mode_info.num_crtc) {
1264                 DRM_ERROR("Invalid crtc %u\n", pipe);
1265                 return -EINVAL;
1266         }
1267
1268         /* The hw increments its frame counter at start of vsync, not at start
1269          * of vblank, as is required by DRM core vblank counter handling.
1270          * Cook the hw count here to make it appear to the caller as if it
1271          * incremented at start of vblank. We measure distance to start of
1272          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1273          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1274          * result by 1 to give the proper appearance to caller.
1275          */
1276         if (adev->mode_info.crtcs[pipe]) {
1277                 /* Repeat readout if needed to provide stable result if
1278                  * we cross start of vsync during the queries.
1279                  */
1280                 do {
1281                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1282                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1283                          * vpos as distance to start of vblank, instead of
1284                          * regular vertical scanout pos.
1285                          */
1286                         stat = amdgpu_display_get_crtc_scanoutpos(
1287                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1288                                 &vpos, &hpos, NULL, NULL,
1289                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1290                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1291
1292                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1293                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1294                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1295                 } else {
1296                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1297                                       pipe, vpos);
1298
1299                         /* Bump counter if we are at >= leading edge of vblank,
1300                          * but before vsync where vpos would turn negative and
1301                          * the hw counter really increments.
1302                          */
1303                         if (vpos >= 0)
1304                                 count++;
1305                 }
1306         } else {
1307                 /* Fallback to use value as is. */
1308                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1309                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1310         }
1311
1312         return count;
1313 }
1314
1315 /**
1316  * amdgpu_enable_vblank_kms - enable vblank interrupt
1317  *
1318  * @crtc: crtc to enable vblank interrupt for
1319  *
1320  * Enable the interrupt on the requested crtc (all asics).
1321  * Returns 0 on success, -EINVAL on failure.
1322  */
1323 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1324 {
1325         struct drm_device *dev = crtc->dev;
1326         unsigned int pipe = crtc->index;
1327         struct amdgpu_device *adev = drm_to_adev(dev);
1328         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1329
1330         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1331 }
1332
1333 /**
1334  * amdgpu_disable_vblank_kms - disable vblank interrupt
1335  *
1336  * @crtc: crtc to disable vblank interrupt for
1337  *
1338  * Disable the interrupt on the requested crtc (all asics).
1339  */
1340 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1341 {
1342         struct drm_device *dev = crtc->dev;
1343         unsigned int pipe = crtc->index;
1344         struct amdgpu_device *adev = drm_to_adev(dev);
1345         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1346
1347         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1348 }
1349
1350 /*
1351  * Debugfs info
1352  */
1353 #if defined(CONFIG_DEBUG_FS)
1354
1355 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1356 {
1357         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1358         struct drm_amdgpu_info_firmware fw_info;
1359         struct drm_amdgpu_query_fw query_fw;
1360         struct atom_context *ctx = adev->mode_info.atom_context;
1361         int ret, i;
1362
1363         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1364 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1365                 TA_FW_NAME(XGMI),
1366                 TA_FW_NAME(RAS),
1367                 TA_FW_NAME(HDCP),
1368                 TA_FW_NAME(DTM),
1369                 TA_FW_NAME(RAP),
1370                 TA_FW_NAME(SECUREDISPLAY),
1371 #undef TA_FW_NAME
1372         };
1373
1374         /* VCE */
1375         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1376         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1377         if (ret)
1378                 return ret;
1379         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1380                    fw_info.feature, fw_info.ver);
1381
1382         /* UVD */
1383         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1384         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1385         if (ret)
1386                 return ret;
1387         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1388                    fw_info.feature, fw_info.ver);
1389
1390         /* GMC */
1391         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1392         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1393         if (ret)
1394                 return ret;
1395         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1396                    fw_info.feature, fw_info.ver);
1397
1398         /* ME */
1399         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1400         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1401         if (ret)
1402                 return ret;
1403         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1404                    fw_info.feature, fw_info.ver);
1405
1406         /* PFP */
1407         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1408         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1409         if (ret)
1410                 return ret;
1411         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1412                    fw_info.feature, fw_info.ver);
1413
1414         /* CE */
1415         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1416         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1417         if (ret)
1418                 return ret;
1419         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1420                    fw_info.feature, fw_info.ver);
1421
1422         /* RLC */
1423         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1424         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1425         if (ret)
1426                 return ret;
1427         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1428                    fw_info.feature, fw_info.ver);
1429
1430         /* RLC SAVE RESTORE LIST CNTL */
1431         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1432         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1433         if (ret)
1434                 return ret;
1435         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1436                    fw_info.feature, fw_info.ver);
1437
1438         /* RLC SAVE RESTORE LIST GPM MEM */
1439         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1440         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1441         if (ret)
1442                 return ret;
1443         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1444                    fw_info.feature, fw_info.ver);
1445
1446         /* RLC SAVE RESTORE LIST SRM MEM */
1447         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1448         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1449         if (ret)
1450                 return ret;
1451         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1452                    fw_info.feature, fw_info.ver);
1453
1454         /* MEC */
1455         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1456         query_fw.index = 0;
1457         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1458         if (ret)
1459                 return ret;
1460         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1461                    fw_info.feature, fw_info.ver);
1462
1463         /* MEC2 */
1464         if (adev->gfx.mec2_fw) {
1465                 query_fw.index = 1;
1466                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467                 if (ret)
1468                         return ret;
1469                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1470                            fw_info.feature, fw_info.ver);
1471         }
1472
1473         /* PSP SOS */
1474         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1475         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1476         if (ret)
1477                 return ret;
1478         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1479                    fw_info.feature, fw_info.ver);
1480
1481
1482         /* PSP ASD */
1483         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1484         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1485         if (ret)
1486                 return ret;
1487         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1488                    fw_info.feature, fw_info.ver);
1489
1490         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1491         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1492                 query_fw.index = i;
1493                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1494                 if (ret)
1495                         continue;
1496
1497                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1498                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1499         }
1500
1501         /* SMC */
1502         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1503         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1504         if (ret)
1505                 return ret;
1506         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1507                    fw_info.feature, fw_info.ver);
1508
1509         /* SDMA */
1510         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1511         for (i = 0; i < adev->sdma.num_instances; i++) {
1512                 query_fw.index = i;
1513                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1514                 if (ret)
1515                         return ret;
1516                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1517                            i, fw_info.feature, fw_info.ver);
1518         }
1519
1520         /* VCN */
1521         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1522         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1523         if (ret)
1524                 return ret;
1525         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1526                    fw_info.feature, fw_info.ver);
1527
1528         /* DMCU */
1529         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1530         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1531         if (ret)
1532                 return ret;
1533         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1534                    fw_info.feature, fw_info.ver);
1535
1536         /* DMCUB */
1537         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1538         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1539         if (ret)
1540                 return ret;
1541         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1542                    fw_info.feature, fw_info.ver);
1543
1544         /* TOC */
1545         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1546         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1547         if (ret)
1548                 return ret;
1549         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1550                    fw_info.feature, fw_info.ver);
1551
1552         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1553
1554         return 0;
1555 }
1556
1557 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1558
1559 #endif
1560
1561 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1562 {
1563 #if defined(CONFIG_DEBUG_FS)
1564         struct drm_minor *minor = adev_to_drm(adev)->primary;
1565         struct dentry *root = minor->debugfs_root;
1566
1567         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1568                             adev, &amdgpu_debugfs_firmware_info_fops);
1569
1570 #endif
1571 }