drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (adev->runpm) {
  91                 pm_runtime_get_sync(dev->dev);
  92                 pm_runtime_forbid(dev->dev);
  93         }
  94
  95         amdgpu_acpi_fini(adev);
  96         amdgpu_device_fini(adev);
  97 }
  98
  99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 100 {
 101         struct amdgpu_gpu_instance *gpu_instance;
 102
 103         mutex_lock(&mgpu_info.mutex);
 104
 105         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 106                 DRM_ERROR("Cannot register more gpu instance\n");
 107                 mutex_unlock(&mgpu_info.mutex);
 108                 return;
 109         }
 110
 111         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 112         gpu_instance->adev = adev;
 113         gpu_instance->mgpu_fan_enabled = 0;
 114
 115         mgpu_info.num_gpu++;
 116         if (adev->flags & AMD_IS_APU)
 117                 mgpu_info.num_apu++;
 118         else
 119                 mgpu_info.num_dgpu++;
 120
 121         mutex_unlock(&mgpu_info.mutex);
 122 }
 123
 124 /**
 125  * amdgpu_driver_load_kms - Main load function for KMS.
 126  *
 127  * @adev: pointer to struct amdgpu_device
 128  * @flags: device flags
 129  *
 130  * This is the main load function for KMS (all asics).
 131  * Returns 0 on success, error on failure.
 132  */
 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 134 {
 135         struct drm_device *dev;
 136         struct pci_dev *parent;
 137         int r, acpi_status;
 138
 139         dev = adev_to_drm(adev);
 140
 141         if (amdgpu_has_atpx() &&
 142             (amdgpu_is_atpx_hybrid() ||
 143              amdgpu_has_atpx_dgpu_power_cntl()) &&
 144             ((flags & AMD_IS_APU) == 0) &&
 145             !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
 146                 flags |= AMD_IS_PX;
 147
 148         parent = pci_upstream_bridge(adev->pdev);
 149         adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
 150
 151         /* amdgpu_device_init should report only fatal error
 152          * like memory allocation failure or iomapping failure,
 153          * or memory manager initialization failure, it must
 154          * properly initialize the GPU MC controller and permit
 155          * VRAM allocation
 156          */
 157         r = amdgpu_device_init(adev, flags);
 158         if (r) {
 159                 dev_err(dev->dev, "Fatal error during GPU init\n");
 160                 goto out;
 161         }
 162
 163         if (amdgpu_device_supports_atpx(dev) &&
 164             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 165                 adev->runpm = true;
 166                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 167         } else if (amdgpu_device_supports_boco(dev) &&
 168                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 169                 adev->runpm = true;
 170                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 171         } else if (amdgpu_device_supports_baco(dev) &&
 172                    (amdgpu_runtime_pm != 0)) {
 173                 switch (adev->asic_type) {
 174                 case CHIP_VEGA20:
 175                 case CHIP_ARCTURUS:
 176                         /* enable runpm if runpm=1 */
 177                         if (amdgpu_runtime_pm > 0)
 178                                 adev->runpm = true;
 179                         break;
 180                 case CHIP_VEGA10:
 181                         /* turn runpm on if noretry=0 */
 182                         if (!adev->gmc.noretry)
 183                                 adev->runpm = true;
 184                         break;
 185                 default:
 186                         /* enable runpm on CI+ */
 187                         adev->runpm = true;
 188                         break;
 189                 }
 190                 if (adev->runpm)
 191                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 192         }
 193
 194         /* Call ACPI methods: require modeset init
 195          * but failure is not fatal
 196          */
 197
 198         acpi_status = amdgpu_acpi_init(adev);
 199         if (acpi_status)
 200                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 201
 202         if (adev->runpm) {
 203                 /* only need to skip on ATPX */
 204                 if (amdgpu_device_supports_atpx(dev) &&
 205                     !amdgpu_is_atpx_hybrid())
 206                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 207                 pm_runtime_use_autosuspend(dev->dev);
 208                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 209                 pm_runtime_allow(dev->dev);
 210                 pm_runtime_mark_last_busy(dev->dev);
 211                 pm_runtime_put_autosuspend(dev->dev);
 212         }
 213
 214 out:
 215         if (r) {
 216                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 217                 if (adev->rmmio && adev->runpm)
 218                         pm_runtime_put_noidle(dev->dev);
 219                 amdgpu_driver_unload_kms(dev);
 220         }
 221
 222         return r;
 223 }
 224
 225 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 226                                 struct drm_amdgpu_query_fw *query_fw,
 227                                 struct amdgpu_device *adev)
 228 {
 229         switch (query_fw->fw_type) {
 230         case AMDGPU_INFO_FW_VCE:
 231                 fw_info->ver = adev->vce.fw_version;
 232                 fw_info->feature = adev->vce.fb_version;
 233                 break;
 234         case AMDGPU_INFO_FW_UVD:
 235                 fw_info->ver = adev->uvd.fw_version;
 236                 fw_info->feature = 0;
 237                 break;
 238         case AMDGPU_INFO_FW_VCN:
 239                 fw_info->ver = adev->vcn.fw_version;
 240                 fw_info->feature = 0;
 241                 break;
 242         case AMDGPU_INFO_FW_GMC:
 243                 fw_info->ver = adev->gmc.fw_version;
 244                 fw_info->feature = 0;
 245                 break;
 246         case AMDGPU_INFO_FW_GFX_ME:
 247                 fw_info->ver = adev->gfx.me_fw_version;
 248                 fw_info->feature = adev->gfx.me_feature_version;
 249                 break;
 250         case AMDGPU_INFO_FW_GFX_PFP:
 251                 fw_info->ver = adev->gfx.pfp_fw_version;
 252                 fw_info->feature = adev->gfx.pfp_feature_version;
 253                 break;
 254         case AMDGPU_INFO_FW_GFX_CE:
 255                 fw_info->ver = adev->gfx.ce_fw_version;
 256                 fw_info->feature = adev->gfx.ce_feature_version;
 257                 break;
 258         case AMDGPU_INFO_FW_GFX_RLC:
 259                 fw_info->ver = adev->gfx.rlc_fw_version;
 260                 fw_info->feature = adev->gfx.rlc_feature_version;
 261                 break;
 262         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 263                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 264                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 265                 break;
 266         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 267                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 268                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 269                 break;
 270         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 271                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 272                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 273                 break;
 274         case AMDGPU_INFO_FW_GFX_MEC:
 275                 if (query_fw->index == 0) {
 276                         fw_info->ver = adev->gfx.mec_fw_version;
 277                         fw_info->feature = adev->gfx.mec_feature_version;
 278                 } else if (query_fw->index == 1) {
 279                         fw_info->ver = adev->gfx.mec2_fw_version;
 280                         fw_info->feature = adev->gfx.mec2_feature_version;
 281                 } else
 282                         return -EINVAL;
 283                 break;
 284         case AMDGPU_INFO_FW_SMC:
 285                 fw_info->ver = adev->pm.fw_version;
 286                 fw_info->feature = 0;
 287                 break;
 288         case AMDGPU_INFO_FW_TA:
 289                 switch (query_fw->index) {
 290                 case 0:
 291                         fw_info->ver = adev->psp.ta_fw_version;
 292                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 293                         break;
 294                 case 1:
 295                         fw_info->ver = adev->psp.ta_fw_version;
 296                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 297                         break;
 298                 case 2:
 299                         fw_info->ver = adev->psp.ta_fw_version;
 300                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 301                         break;
 302                 case 3:
 303                         fw_info->ver = adev->psp.ta_fw_version;
 304                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 305                         break;
 306                 default:
 307                         return -EINVAL;
 308                 }
 309                 break;
 310         case AMDGPU_INFO_FW_SDMA:
 311                 if (query_fw->index >= adev->sdma.num_instances)
 312                         return -EINVAL;
 313                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 314                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 315                 break;
 316         case AMDGPU_INFO_FW_SOS:
 317                 fw_info->ver = adev->psp.sos_fw_version;
 318                 fw_info->feature = adev->psp.sos_feature_version;
 319                 break;
 320         case AMDGPU_INFO_FW_ASD:
 321                 fw_info->ver = adev->psp.asd_fw_version;
 322                 fw_info->feature = adev->psp.asd_feature_version;
 323                 break;
 324         case AMDGPU_INFO_FW_DMCU:
 325                 fw_info->ver = adev->dm.dmcu_fw_version;
 326                 fw_info->feature = 0;
 327                 break;
 328         case AMDGPU_INFO_FW_DMCUB:
 329                 fw_info->ver = adev->dm.dmcub_fw_version;
 330                 fw_info->feature = 0;
 331                 break;
 332         case AMDGPU_INFO_FW_TOC:
 333                 fw_info->ver = adev->psp.toc_fw_version;
 334                 fw_info->feature = adev->psp.toc_feature_version;
 335                 break;
 336         default:
 337                 return -EINVAL;
 338         }
 339         return 0;
 340 }
 341
 342 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 343                              struct drm_amdgpu_info *info,
 344                              struct drm_amdgpu_info_hw_ip *result)
 345 {
 346         uint32_t ib_start_alignment = 0;
 347         uint32_t ib_size_alignment = 0;
 348         enum amd_ip_block_type type;
 349         unsigned int num_rings = 0;
 350         unsigned int i, j;
 351
 352         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 353                 return -EINVAL;
 354
 355         switch (info->query_hw_ip.type) {
 356         case AMDGPU_HW_IP_GFX:
 357                 type = AMD_IP_BLOCK_TYPE_GFX;
 358                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 359                         if (adev->gfx.gfx_ring[i].sched.ready)
 360                                 ++num_rings;
 361                 ib_start_alignment = 32;
 362                 ib_size_alignment = 32;
 363                 break;
 364         case AMDGPU_HW_IP_COMPUTE:
 365                 type = AMD_IP_BLOCK_TYPE_GFX;
 366                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 367                         if (adev->gfx.compute_ring[i].sched.ready)
 368                                 ++num_rings;
 369                 ib_start_alignment = 32;
 370                 ib_size_alignment = 32;
 371                 break;
 372         case AMDGPU_HW_IP_DMA:
 373                 type = AMD_IP_BLOCK_TYPE_SDMA;
 374                 for (i = 0; i < adev->sdma.num_instances; i++)
 375                         if (adev->sdma.instance[i].ring.sched.ready)
 376                                 ++num_rings;
 377                 ib_start_alignment = 256;
 378                 ib_size_alignment = 4;
 379                 break;
 380         case AMDGPU_HW_IP_UVD:
 381                 type = AMD_IP_BLOCK_TYPE_UVD;
 382                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 383                         if (adev->uvd.harvest_config & (1 << i))
 384                                 continue;
 385
 386                         if (adev->uvd.inst[i].ring.sched.ready)
 387                                 ++num_rings;
 388                 }
 389                 ib_start_alignment = 64;
 390                 ib_size_alignment = 64;
 391                 break;
 392         case AMDGPU_HW_IP_VCE:
 393                 type = AMD_IP_BLOCK_TYPE_VCE;
 394                 for (i = 0; i < adev->vce.num_rings; i++)
 395                         if (adev->vce.ring[i].sched.ready)
 396                                 ++num_rings;
 397                 ib_start_alignment = 4;
 398                 ib_size_alignment = 1;
 399                 break;
 400         case AMDGPU_HW_IP_UVD_ENC:
 401                 type = AMD_IP_BLOCK_TYPE_UVD;
 402                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 403                         if (adev->uvd.harvest_config & (1 << i))
 404                                 continue;
 405
 406                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 407                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 408                                         ++num_rings;
 409                 }
 410                 ib_start_alignment = 64;
 411                 ib_size_alignment = 64;
 412                 break;
 413         case AMDGPU_HW_IP_VCN_DEC:
 414                 type = AMD_IP_BLOCK_TYPE_VCN;
 415                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 416                         if (adev->uvd.harvest_config & (1 << i))
 417                                 continue;
 418
 419                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 420                                 ++num_rings;
 421                 }
 422                 ib_start_alignment = 16;
 423                 ib_size_alignment = 16;
 424                 break;
 425         case AMDGPU_HW_IP_VCN_ENC:
 426                 type = AMD_IP_BLOCK_TYPE_VCN;
 427                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 428                         if (adev->uvd.harvest_config & (1 << i))
 429                                 continue;
 430
 431                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 432                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 433                                         ++num_rings;
 434                 }
 435                 ib_start_alignment = 64;
 436                 ib_size_alignment = 1;
 437                 break;
 438         case AMDGPU_HW_IP_VCN_JPEG:
 439                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 440                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 441
 442                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 443                         if (adev->jpeg.harvest_config & (1 << i))
 444                                 continue;
 445
 446                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 447                                 ++num_rings;
 448                 }
 449                 ib_start_alignment = 16;
 450                 ib_size_alignment = 16;
 451                 break;
 452         default:
 453                 return -EINVAL;
 454         }
 455
 456         for (i = 0; i < adev->num_ip_blocks; i++)
 457                 if (adev->ip_blocks[i].version->type == type &&
 458                     adev->ip_blocks[i].status.valid)
 459                         break;
 460
 461         if (i == adev->num_ip_blocks)
 462                 return 0;
 463
 464         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 465                         num_rings);
 466
 467         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 468         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 469         result->capabilities_flags = 0;
 470         result->available_rings = (1 << num_rings) - 1;
 471         result->ib_start_alignment = ib_start_alignment;
 472         result->ib_size_alignment = ib_size_alignment;
 473         return 0;
 474 }
 475
 476 /*
 477  * Userspace get information ioctl
 478  */
 479 /**
 480  * amdgpu_info_ioctl - answer a device specific request.
 481  *
 482  * @dev: drm device pointer
 483  * @data: request object
 484  * @filp: drm filp
 485  *
 486  * This function is used to pass device specific parameters to the userspace
 487  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 488  * etc. (all asics).
 489  * Returns 0 on success, -EINVAL on failure.
 490  */
 491 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 492 {
 493         struct amdgpu_device *adev = drm_to_adev(dev);
 494         struct drm_amdgpu_info *info = data;
 495         struct amdgpu_mode_info *minfo = &adev->mode_info;
 496         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 497         uint32_t size = info->return_size;
 498         struct drm_crtc *crtc;
 499         uint32_t ui32 = 0;
 500         uint64_t ui64 = 0;
 501         int i, found;
 502         int ui32_size = sizeof(ui32);
 503
 504         if (!info->return_size || !info->return_pointer)
 505                 return -EINVAL;
 506
 507         switch (info->query) {
 508         case AMDGPU_INFO_ACCEL_WORKING:
 509                 ui32 = adev->accel_working;
 510                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 511         case AMDGPU_INFO_CRTC_FROM_ID:
 512                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 513                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 514                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 515                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 516                                 ui32 = amdgpu_crtc->crtc_id;
 517                                 found = 1;
 518                                 break;
 519                         }
 520                 }
 521                 if (!found) {
 522                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 523                         return -EINVAL;
 524                 }
 525                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 526         case AMDGPU_INFO_HW_IP_INFO: {
 527                 struct drm_amdgpu_info_hw_ip ip = {};
 528                 int ret;
 529
 530                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 531                 if (ret)
 532                         return ret;
 533
 534                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 535                 return ret ? -EFAULT : 0;
 536         }
 537         case AMDGPU_INFO_HW_IP_COUNT: {
 538                 enum amd_ip_block_type type;
 539                 uint32_t count = 0;
 540
 541                 switch (info->query_hw_ip.type) {
 542                 case AMDGPU_HW_IP_GFX:
 543                         type = AMD_IP_BLOCK_TYPE_GFX;
 544                         break;
 545                 case AMDGPU_HW_IP_COMPUTE:
 546                         type = AMD_IP_BLOCK_TYPE_GFX;
 547                         break;
 548                 case AMDGPU_HW_IP_DMA:
 549                         type = AMD_IP_BLOCK_TYPE_SDMA;
 550                         break;
 551                 case AMDGPU_HW_IP_UVD:
 552                         type = AMD_IP_BLOCK_TYPE_UVD;
 553                         break;
 554                 case AMDGPU_HW_IP_VCE:
 555                         type = AMD_IP_BLOCK_TYPE_VCE;
 556                         break;
 557                 case AMDGPU_HW_IP_UVD_ENC:
 558                         type = AMD_IP_BLOCK_TYPE_UVD;
 559                         break;
 560                 case AMDGPU_HW_IP_VCN_DEC:
 561                 case AMDGPU_HW_IP_VCN_ENC:
 562                         type = AMD_IP_BLOCK_TYPE_VCN;
 563                         break;
 564                 case AMDGPU_HW_IP_VCN_JPEG:
 565                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 566                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 567                         break;
 568                 default:
 569                         return -EINVAL;
 570                 }
 571
 572                 for (i = 0; i < adev->num_ip_blocks; i++)
 573                         if (adev->ip_blocks[i].version->type == type &&
 574                             adev->ip_blocks[i].status.valid &&
 575                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 576                                 count++;
 577
 578                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 579         }
 580         case AMDGPU_INFO_TIMESTAMP:
 581                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 582                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 583         case AMDGPU_INFO_FW_VERSION: {
 584                 struct drm_amdgpu_info_firmware fw_info;
 585                 int ret;
 586
 587                 /* We only support one instance of each IP block right now. */
 588                 if (info->query_fw.ip_instance != 0)
 589                         return -EINVAL;
 590
 591                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 592                 if (ret)
 593                         return ret;
 594
 595                 return copy_to_user(out, &fw_info,
 596                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 597         }
 598         case AMDGPU_INFO_NUM_BYTES_MOVED:
 599                 ui64 = atomic64_read(&adev->num_bytes_moved);
 600                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 601         case AMDGPU_INFO_NUM_EVICTIONS:
 602                 ui64 = atomic64_read(&adev->num_evictions);
 603                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 604         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 605                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 606                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 607         case AMDGPU_INFO_VRAM_USAGE:
 608                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 609                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 610         case AMDGPU_INFO_VIS_VRAM_USAGE:
 611                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 612                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 613         case AMDGPU_INFO_GTT_USAGE:
 614                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 615                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 616         case AMDGPU_INFO_GDS_CONFIG: {
 617                 struct drm_amdgpu_info_gds gds_info;
 618
 619                 memset(&gds_info, 0, sizeof(gds_info));
 620                 gds_info.compute_partition_size = adev->gds.gds_size;
 621                 gds_info.gds_total_size = adev->gds.gds_size;
 622                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 623                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 624                 return copy_to_user(out, &gds_info,
 625                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 626         }
 627         case AMDGPU_INFO_VRAM_GTT: {
 628                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 629
 630                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 631                         atomic64_read(&adev->vram_pin_size) -
 632                         AMDGPU_VM_RESERVED_VRAM;
 633                 vram_gtt.vram_cpu_accessible_size =
 634                         min(adev->gmc.visible_vram_size -
 635                             atomic64_read(&adev->visible_pin_size),
 636                             vram_gtt.vram_size);
 637                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 638                 vram_gtt.gtt_size *= PAGE_SIZE;
 639                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 640                 return copy_to_user(out, &vram_gtt,
 641                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 642         }
 643         case AMDGPU_INFO_MEMORY: {
 644                 struct drm_amdgpu_memory_info mem;
 645                 struct ttm_resource_manager *vram_man =
 646                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 647                 struct ttm_resource_manager *gtt_man =
 648                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 649                 memset(&mem, 0, sizeof(mem));
 650                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 651                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 652                         atomic64_read(&adev->vram_pin_size) -
 653                         AMDGPU_VM_RESERVED_VRAM;
 654                 mem.vram.heap_usage =
 655                         amdgpu_vram_mgr_usage(vram_man);
 656                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 657
 658                 mem.cpu_accessible_vram.total_heap_size =
 659                         adev->gmc.visible_vram_size;
 660                 mem.cpu_accessible_vram.usable_heap_size =
 661                         min(adev->gmc.visible_vram_size -
 662                             atomic64_read(&adev->visible_pin_size),
 663                             mem.vram.usable_heap_size);
 664                 mem.cpu_accessible_vram.heap_usage =
 665                         amdgpu_vram_mgr_vis_usage(vram_man);
 666                 mem.cpu_accessible_vram.max_allocation =
 667                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 668
 669                 mem.gtt.total_heap_size = gtt_man->size;
 670                 mem.gtt.total_heap_size *= PAGE_SIZE;
 671                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 672                         atomic64_read(&adev->gart_pin_size);
 673                 mem.gtt.heap_usage =
 674                         amdgpu_gtt_mgr_usage(gtt_man);
 675                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 676
 677                 return copy_to_user(out, &mem,
 678                                     min((size_t)size, sizeof(mem)))
 679                                     ? -EFAULT : 0;
 680         }
 681         case AMDGPU_INFO_READ_MMR_REG: {
 682                 unsigned n, alloc_size;
 683                 uint32_t *regs;
 684                 unsigned se_num = (info->read_mmr_reg.instance >>
 685                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 686                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 687                 unsigned sh_num = (info->read_mmr_reg.instance >>
 688                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 689                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 690
 691                 /* set full masks if the userspace set all bits
 692                  * in the bitfields */
 693                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 694                         se_num = 0xffffffff;
 695                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 696                         return -EINVAL;
 697                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 698                         sh_num = 0xffffffff;
 699                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 700                         return -EINVAL;
 701
 702                 if (info->read_mmr_reg.count > 128)
 703                         return -EINVAL;
 704
 705                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 706                 if (!regs)
 707                         return -ENOMEM;
 708                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 709
 710                 amdgpu_gfx_off_ctrl(adev, false);
 711                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 712                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 713                                                       info->read_mmr_reg.dword_offset + i,
 714                                                       &regs[i])) {
 715                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 716                                               info->read_mmr_reg.dword_offset + i);
 717                                 kfree(regs);
 718                                 amdgpu_gfx_off_ctrl(adev, true);
 719                                 return -EFAULT;
 720                         }
 721                 }
 722                 amdgpu_gfx_off_ctrl(adev, true);
 723                 n = copy_to_user(out, regs, min(size, alloc_size));
 724                 kfree(regs);
 725                 return n ? -EFAULT : 0;
 726         }
 727         case AMDGPU_INFO_DEV_INFO: {
 728                 struct drm_amdgpu_info_device *dev_info;
 729                 uint64_t vm_size;
 730                 int ret;
 731
 732                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 733                 if (!dev_info)
 734                         return -ENOMEM;
 735
 736                 dev_info->device_id = adev->pdev->device;
 737                 dev_info->chip_rev = adev->rev_id;
 738                 dev_info->external_rev = adev->external_rev_id;
 739                 dev_info->pci_rev = adev->pdev->revision;
 740                 dev_info->family = adev->family;
 741                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 742                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 743                 /* return all clocks in KHz */
 744                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 745                 if (adev->pm.dpm_enabled) {
 746                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 747                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 748                 } else {
 749                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 750                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 751                 }
 752                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 753                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 754                         adev->gfx.config.max_shader_engines;
 755                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 756                 dev_info->_pad = 0;
 757                 dev_info->ids_flags = 0;
 758                 if (adev->flags & AMD_IS_APU)
 759                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 760                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 761                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 762                 if (amdgpu_is_tmz(adev))
 763                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 764
 765                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 766                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 767
 768                 /* Older VCE FW versions are buggy and can handle only 40bits */
 769                 if (adev->vce.fw_version &&
 770                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 771                         vm_size = min(vm_size, 1ULL << 40);
 772
 773                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 774                 dev_info->virtual_address_max =
 775                         min(vm_size, AMDGPU_GMC_HOLE_START);
 776
 777                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 778                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 779                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 780                 }
 781                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 782                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 783                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 784                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 785                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 786                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 787                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 788                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 789                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 790                        sizeof(adev->gfx.cu_info.bitmap));
 791                 dev_info->vram_type = adev->gmc.vram_type;
 792                 dev_info->vram_bit_width = adev->gmc.vram_width;
 793                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 794                 dev_info->gc_double_offchip_lds_buf =
 795                         adev->gfx.config.double_offchip_lds_buf;
 796                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 797                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 798                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 799                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 800                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 801                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 802                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 803
 804                 if (adev->family >= AMDGPU_FAMILY_NV)
 805                         dev_info->pa_sc_tile_steering_override =
 806                                 adev->gfx.config.pa_sc_tile_steering_override;
 807
 808                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 809
 810                 ret = copy_to_user(out, dev_info,
 811                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 812                 kfree(dev_info);
 813                 return ret;
 814         }
 815         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 816                 unsigned i;
 817                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 818                 struct amd_vce_state *vce_state;
 819
 820                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 821                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 822                         if (vce_state) {
 823                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 824                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 825                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 826                                 vce_clk_table.num_valid_entries++;
 827                         }
 828                 }
 829
 830                 return copy_to_user(out, &vce_clk_table,
 831                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 832         }
 833         case AMDGPU_INFO_VBIOS: {
 834                 uint32_t bios_size = adev->bios_size;
 835
 836                 switch (info->vbios_info.type) {
 837                 case AMDGPU_INFO_VBIOS_SIZE:
 838                         return copy_to_user(out, &bios_size,
 839                                         min((size_t)size, sizeof(bios_size)))
 840                                         ? -EFAULT : 0;
 841                 case AMDGPU_INFO_VBIOS_IMAGE: {
 842                         uint8_t *bios;
 843                         uint32_t bios_offset = info->vbios_info.offset;
 844
 845                         if (bios_offset >= bios_size)
 846                                 return -EINVAL;
 847
 848                         bios = adev->bios + bios_offset;
 849                         return copy_to_user(out, bios,
 850                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 851                                         ? -EFAULT : 0;
 852                 }
 853                 default:
 854                         DRM_DEBUG_KMS("Invalid request %d\n",
 855                                         info->vbios_info.type);
 856                         return -EINVAL;
 857                 }
 858         }
 859         case AMDGPU_INFO_NUM_HANDLES: {
 860                 struct drm_amdgpu_info_num_handles handle;
 861
 862                 switch (info->query_hw_ip.type) {
 863                 case AMDGPU_HW_IP_UVD:
 864                         /* Starting Polaris, we support unlimited UVD handles */
 865                         if (adev->asic_type < CHIP_POLARIS10) {
 866                                 handle.uvd_max_handles = adev->uvd.max_handles;
 867                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 868
 869                                 return copy_to_user(out, &handle,
 870                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 871                         } else {
 872                                 return -ENODATA;
 873                         }
 874
 875                         break;
 876                 default:
 877                         return -EINVAL;
 878                 }
 879         }
 880         case AMDGPU_INFO_SENSOR: {
 881                 if (!adev->pm.dpm_enabled)
 882                         return -ENOENT;
 883
 884                 switch (info->sensor_info.type) {
 885                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 886                         /* get sclk in Mhz */
 887                         if (amdgpu_dpm_read_sensor(adev,
 888                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 889                                                    (void *)&ui32, &ui32_size)) {
 890                                 return -EINVAL;
 891                         }
 892                         ui32 /= 100;
 893                         break;
 894                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 895                         /* get mclk in Mhz */
 896                         if (amdgpu_dpm_read_sensor(adev,
 897                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 898                                                    (void *)&ui32, &ui32_size)) {
 899                                 return -EINVAL;
 900                         }
 901                         ui32 /= 100;
 902                         break;
 903                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 904                         /* get temperature in millidegrees C */
 905                         if (amdgpu_dpm_read_sensor(adev,
 906                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 907                                                    (void *)&ui32, &ui32_size)) {
 908                                 return -EINVAL;
 909                         }
 910                         break;
 911                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 912                         /* get GPU load */
 913                         if (amdgpu_dpm_read_sensor(adev,
 914                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 915                                                    (void *)&ui32, &ui32_size)) {
 916                                 return -EINVAL;
 917                         }
 918                         break;
 919                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 920                         /* get average GPU power */
 921                         if (amdgpu_dpm_read_sensor(adev,
 922                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 923                                                    (void *)&ui32, &ui32_size)) {
 924                                 return -EINVAL;
 925                         }
 926                         ui32 >>= 8;
 927                         break;
 928                 case AMDGPU_INFO_SENSOR_VDDNB:
 929                         /* get VDDNB in millivolts */
 930                         if (amdgpu_dpm_read_sensor(adev,
 931                                                    AMDGPU_PP_SENSOR_VDDNB,
 932                                                    (void *)&ui32, &ui32_size)) {
 933                                 return -EINVAL;
 934                         }
 935                         break;
 936                 case AMDGPU_INFO_SENSOR_VDDGFX:
 937                         /* get VDDGFX in millivolts */
 938                         if (amdgpu_dpm_read_sensor(adev,
 939                                                    AMDGPU_PP_SENSOR_VDDGFX,
 940                                                    (void *)&ui32, &ui32_size)) {
 941                                 return -EINVAL;
 942                         }
 943                         break;
 944                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 945                         /* get stable pstate sclk in Mhz */
 946                         if (amdgpu_dpm_read_sensor(adev,
 947                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 948                                                    (void *)&ui32, &ui32_size)) {
 949                                 return -EINVAL;
 950                         }
 951                         ui32 /= 100;
 952                         break;
 953                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 954                         /* get stable pstate mclk in Mhz */
 955                         if (amdgpu_dpm_read_sensor(adev,
 956                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 957                                                    (void *)&ui32, &ui32_size)) {
 958                                 return -EINVAL;
 959                         }
 960                         ui32 /= 100;
 961                         break;
 962                 default:
 963                         DRM_DEBUG_KMS("Invalid request %d\n",
 964                                       info->sensor_info.type);
 965                         return -EINVAL;
 966                 }
 967                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 968         }
 969         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 970                 ui32 = atomic_read(&adev->vram_lost_counter);
 971                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 972         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 973                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 974                 uint64_t ras_mask;
 975
 976                 if (!ras)
 977                         return -EINVAL;
 978                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 979
 980                 return copy_to_user(out, &ras_mask,
 981                                 min_t(u64, size, sizeof(ras_mask))) ?
 982                         -EFAULT : 0;
 983         }
 984         default:
 985                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 986                 return -EINVAL;
 987         }
 988         return 0;
 989 }
 990
 991
 992 /*
 993  * Outdated mess for old drm with Xorg being in charge (void function now).
 994  */
 995 /**
 996  * amdgpu_driver_lastclose_kms - drm callback for last close
 997  *
 998  * @dev: drm dev pointer
 999  *
1000  * Switch vga_switcheroo state after last close (all asics).
1001  */
1002 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1003 {
1004         drm_fb_helper_lastclose(dev);
1005         vga_switcheroo_process_delayed_switch();
1006 }
1007
1008 /**
1009  * amdgpu_driver_open_kms - drm callback for open
1010  *
1011  * @dev: drm dev pointer
1012  * @file_priv: drm file
1013  *
1014  * On device open, init vm on cayman+ (all asics).
1015  * Returns 0 on success, error on failure.
1016  */
1017 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1018 {
1019         struct amdgpu_device *adev = drm_to_adev(dev);
1020         struct amdgpu_fpriv *fpriv;
1021         int r, pasid;
1022
1023         /* Ensure IB tests are run on ring */
1024         flush_delayed_work(&adev->delayed_init_work);
1025
1026
1027         if (amdgpu_ras_intr_triggered()) {
1028                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1029                 return -EHWPOISON;
1030         }
1031
1032         file_priv->driver_priv = NULL;
1033
1034         r = pm_runtime_get_sync(dev->dev);
1035         if (r < 0)
1036                 goto pm_put;
1037
1038         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1039         if (unlikely(!fpriv)) {
1040                 r = -ENOMEM;
1041                 goto out_suspend;
1042         }
1043
1044         pasid = amdgpu_pasid_alloc(16);
1045         if (pasid < 0) {
1046                 dev_warn(adev->dev, "No more PASIDs available!");
1047                 pasid = 0;
1048         }
1049         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1050         if (r)
1051                 goto error_pasid;
1052
1053         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1054         if (!fpriv->prt_va) {
1055                 r = -ENOMEM;
1056                 goto error_vm;
1057         }
1058
1059         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1060                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1061
1062                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1063                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1064                 if (r)
1065                         goto error_vm;
1066         }
1067
1068         mutex_init(&fpriv->bo_list_lock);
1069         idr_init(&fpriv->bo_list_handles);
1070
1071         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1072
1073         file_priv->driver_priv = fpriv;
1074         goto out_suspend;
1075
1076 error_vm:
1077         amdgpu_vm_fini(adev, &fpriv->vm);
1078
1079 error_pasid:
1080         if (pasid)
1081                 amdgpu_pasid_free(pasid);
1082
1083         kfree(fpriv);
1084
1085 out_suspend:
1086         pm_runtime_mark_last_busy(dev->dev);
1087 pm_put:
1088         pm_runtime_put_autosuspend(dev->dev);
1089
1090         return r;
1091 }
1092
1093 /**
1094  * amdgpu_driver_postclose_kms - drm callback for post close
1095  *
1096  * @dev: drm dev pointer
1097  * @file_priv: drm file
1098  *
1099  * On device post close, tear down vm on cayman+ (all asics).
1100  */
1101 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1102                                  struct drm_file *file_priv)
1103 {
1104         struct amdgpu_device *adev = drm_to_adev(dev);
1105         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1106         struct amdgpu_bo_list *list;
1107         struct amdgpu_bo *pd;
1108         u32 pasid;
1109         int handle;
1110
1111         if (!fpriv)
1112                 return;
1113
1114         pm_runtime_get_sync(dev->dev);
1115
1116         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1117                 amdgpu_uvd_free_handles(adev, file_priv);
1118         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1119                 amdgpu_vce_free_handles(adev, file_priv);
1120
1121         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1122
1123         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1124                 /* TODO: how to handle reserve failure */
1125                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1126                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1127                 fpriv->csa_va = NULL;
1128                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1129         }
1130
1131         pasid = fpriv->vm.pasid;
1132         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1133
1134         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1135         amdgpu_vm_fini(adev, &fpriv->vm);
1136
1137         if (pasid)
1138                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1139         amdgpu_bo_unref(&pd);
1140
1141         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1142                 amdgpu_bo_list_put(list);
1143
1144         idr_destroy(&fpriv->bo_list_handles);
1145         mutex_destroy(&fpriv->bo_list_lock);
1146
1147         kfree(fpriv);
1148         file_priv->driver_priv = NULL;
1149
1150         pm_runtime_mark_last_busy(dev->dev);
1151         pm_runtime_put_autosuspend(dev->dev);
1152 }
1153
1154 /*
1155  * VBlank related functions.
1156  */
1157 /**
1158  * amdgpu_get_vblank_counter_kms - get frame count
1159  *
1160  * @crtc: crtc to get the frame count from
1161  *
1162  * Gets the frame count on the requested crtc (all asics).
1163  * Returns frame count on success, -EINVAL on failure.
1164  */
1165 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1166 {
1167         struct drm_device *dev = crtc->dev;
1168         unsigned int pipe = crtc->index;
1169         struct amdgpu_device *adev = drm_to_adev(dev);
1170         int vpos, hpos, stat;
1171         u32 count;
1172
1173         if (pipe >= adev->mode_info.num_crtc) {
1174                 DRM_ERROR("Invalid crtc %u\n", pipe);
1175                 return -EINVAL;
1176         }
1177
1178         /* The hw increments its frame counter at start of vsync, not at start
1179          * of vblank, as is required by DRM core vblank counter handling.
1180          * Cook the hw count here to make it appear to the caller as if it
1181          * incremented at start of vblank. We measure distance to start of
1182          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1183          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1184          * result by 1 to give the proper appearance to caller.
1185          */
1186         if (adev->mode_info.crtcs[pipe]) {
1187                 /* Repeat readout if needed to provide stable result if
1188                  * we cross start of vsync during the queries.
1189                  */
1190                 do {
1191                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1192                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1193                          * vpos as distance to start of vblank, instead of
1194                          * regular vertical scanout pos.
1195                          */
1196                         stat = amdgpu_display_get_crtc_scanoutpos(
1197                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1198                                 &vpos, &hpos, NULL, NULL,
1199                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1200                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1201
1202                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1203                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1204                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1205                 } else {
1206                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1207                                       pipe, vpos);
1208
1209                         /* Bump counter if we are at >= leading edge of vblank,
1210                          * but before vsync where vpos would turn negative and
1211                          * the hw counter really increments.
1212                          */
1213                         if (vpos >= 0)
1214                                 count++;
1215                 }
1216         } else {
1217                 /* Fallback to use value as is. */
1218                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1219                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1220         }
1221
1222         return count;
1223 }
1224
1225 /**
1226  * amdgpu_enable_vblank_kms - enable vblank interrupt
1227  *
1228  * @crtc: crtc to enable vblank interrupt for
1229  *
1230  * Enable the interrupt on the requested crtc (all asics).
1231  * Returns 0 on success, -EINVAL on failure.
1232  */
1233 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1234 {
1235         struct drm_device *dev = crtc->dev;
1236         unsigned int pipe = crtc->index;
1237         struct amdgpu_device *adev = drm_to_adev(dev);
1238         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1239
1240         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1241 }
1242
1243 /**
1244  * amdgpu_disable_vblank_kms - disable vblank interrupt
1245  *
1246  * @crtc: crtc to disable vblank interrupt for
1247  *
1248  * Disable the interrupt on the requested crtc (all asics).
1249  */
1250 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1251 {
1252         struct drm_device *dev = crtc->dev;
1253         unsigned int pipe = crtc->index;
1254         struct amdgpu_device *adev = drm_to_adev(dev);
1255         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1256
1257         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1258 }
1259
1260 /*
1261  * Debugfs info
1262  */
1263 #if defined(CONFIG_DEBUG_FS)
1264
1265 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1266 {
1267         struct drm_info_node *node = (struct drm_info_node *) m->private;
1268         struct drm_device *dev = node->minor->dev;
1269         struct amdgpu_device *adev = drm_to_adev(dev);
1270         struct drm_amdgpu_info_firmware fw_info;
1271         struct drm_amdgpu_query_fw query_fw;
1272         struct atom_context *ctx = adev->mode_info.atom_context;
1273         int ret, i;
1274
1275         /* VCE */
1276         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1277         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1278         if (ret)
1279                 return ret;
1280         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1281                    fw_info.feature, fw_info.ver);
1282
1283         /* UVD */
1284         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1285         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1286         if (ret)
1287                 return ret;
1288         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1289                    fw_info.feature, fw_info.ver);
1290
1291         /* GMC */
1292         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1293         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1294         if (ret)
1295                 return ret;
1296         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1297                    fw_info.feature, fw_info.ver);
1298
1299         /* ME */
1300         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1301         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1302         if (ret)
1303                 return ret;
1304         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1305                    fw_info.feature, fw_info.ver);
1306
1307         /* PFP */
1308         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1309         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1310         if (ret)
1311                 return ret;
1312         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1313                    fw_info.feature, fw_info.ver);
1314
1315         /* CE */
1316         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1317         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1318         if (ret)
1319                 return ret;
1320         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1321                    fw_info.feature, fw_info.ver);
1322
1323         /* RLC */
1324         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1325         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1326         if (ret)
1327                 return ret;
1328         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1329                    fw_info.feature, fw_info.ver);
1330
1331         /* RLC SAVE RESTORE LIST CNTL */
1332         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1333         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1334         if (ret)
1335                 return ret;
1336         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1337                    fw_info.feature, fw_info.ver);
1338
1339         /* RLC SAVE RESTORE LIST GPM MEM */
1340         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1341         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1342         if (ret)
1343                 return ret;
1344         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1345                    fw_info.feature, fw_info.ver);
1346
1347         /* RLC SAVE RESTORE LIST SRM MEM */
1348         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1349         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1350         if (ret)
1351                 return ret;
1352         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1353                    fw_info.feature, fw_info.ver);
1354
1355         /* MEC */
1356         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1357         query_fw.index = 0;
1358         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1359         if (ret)
1360                 return ret;
1361         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1362                    fw_info.feature, fw_info.ver);
1363
1364         /* MEC2 */
1365         if (adev->gfx.mec2_fw) {
1366                 query_fw.index = 1;
1367                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1368                 if (ret)
1369                         return ret;
1370                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1371                            fw_info.feature, fw_info.ver);
1372         }
1373
1374         /* PSP SOS */
1375         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1376         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1377         if (ret)
1378                 return ret;
1379         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1380                    fw_info.feature, fw_info.ver);
1381
1382
1383         /* PSP ASD */
1384         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1385         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1386         if (ret)
1387                 return ret;
1388         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1389                    fw_info.feature, fw_info.ver);
1390
1391         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1392         for (i = 0; i < 4; i++) {
1393                 query_fw.index = i;
1394                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1395                 if (ret)
1396                         continue;
1397                 switch (query_fw.index) {
1398                 case 0:
1399                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1400                                         "RAS", fw_info.feature, fw_info.ver);
1401                         break;
1402                 case 1:
1403                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1404                                         "XGMI", fw_info.feature, fw_info.ver);
1405                         break;
1406                 case 2:
1407                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1408                                         "HDCP", fw_info.feature, fw_info.ver);
1409                         break;
1410                 case 3:
1411                         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1412                                         "DTM", fw_info.feature, fw_info.ver);
1413                         break;
1414                 default:
1415                         return -EINVAL;
1416                 }
1417         }
1418
1419         /* SMC */
1420         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1421         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1422         if (ret)
1423                 return ret;
1424         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1425                    fw_info.feature, fw_info.ver);
1426
1427         /* SDMA */
1428         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1429         for (i = 0; i < adev->sdma.num_instances; i++) {
1430                 query_fw.index = i;
1431                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1432                 if (ret)
1433                         return ret;
1434                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1435                            i, fw_info.feature, fw_info.ver);
1436         }
1437
1438         /* VCN */
1439         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1440         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1441         if (ret)
1442                 return ret;
1443         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1444                    fw_info.feature, fw_info.ver);
1445
1446         /* DMCU */
1447         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1448         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1449         if (ret)
1450                 return ret;
1451         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1452                    fw_info.feature, fw_info.ver);
1453
1454         /* DMCUB */
1455         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1456         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1457         if (ret)
1458                 return ret;
1459         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1460                    fw_info.feature, fw_info.ver);
1461
1462         /* TOC */
1463         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1464         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1465         if (ret)
1466                 return ret;
1467         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1468                    fw_info.feature, fw_info.ver);
1469
1470         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1471
1472         return 0;
1473 }
1474
1475 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1476         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1477 };
1478 #endif
1479
1480 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1481 {
1482 #if defined(CONFIG_DEBUG_FS)
1483         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1484                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1485 #else
1486         return 0;
1487 #endif
1488 }