drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_sched.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include "amdgpu_amdkfd.h"
  40 #include "amdgpu_gem.h"
  41 #include "amdgpu_display.h"
  42
  43 static void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  44 {
  45         struct amdgpu_gpu_instance *gpu_instance;
  46         int i;
  47
  48         mutex_lock(&mgpu_info.mutex);
  49
  50         for (i = 0; i < mgpu_info.num_gpu; i++) {
  51                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  52                 if (gpu_instance->adev == adev) {
  53                         mgpu_info.gpu_ins[i] =
  54                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  55                         mgpu_info.num_gpu--;
  56                         if (adev->flags & AMD_IS_APU)
  57                                 mgpu_info.num_apu--;
  58                         else
  59                                 mgpu_info.num_dgpu--;
  60                         break;
  61                 }
  62         }
  63
  64         mutex_unlock(&mgpu_info.mutex);
  65 }
  66
  67 /**
  68  * amdgpu_driver_unload_kms - Main unload function for KMS.
  69  *
  70  * @dev: drm dev pointer
  71  *
  72  * This is the main unload function for KMS (all asics).
  73  * Returns 0 on success.
  74  */
  75 void amdgpu_driver_unload_kms(struct drm_device *dev)
  76 {
  77         struct amdgpu_device *adev = dev->dev_private;
  78
  79         if (adev == NULL)
  80                 return;
  81
  82         amdgpu_unregister_gpu_instance(adev);
  83
  84         if (adev->rmmio == NULL)
  85                 goto done_free;
  86
  87         if (amdgpu_sriov_vf(adev))
  88                 amdgpu_virt_request_full_gpu(adev, false);
  89
  90         if (amdgpu_device_is_px(dev)) {
  91                 pm_runtime_get_sync(dev->dev);
  92                 pm_runtime_forbid(dev->dev);
  93         }
  94
  95         amdgpu_acpi_fini(adev);
  96
  97         amdgpu_device_fini(adev);
  98
  99 done_free:
 100         kfree(adev);
 101         dev->dev_private = NULL;
 102 }
 103
 104 static void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 105 {
 106         struct amdgpu_gpu_instance *gpu_instance;
 107
 108         mutex_lock(&mgpu_info.mutex);
 109
 110         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 111                 DRM_ERROR("Cannot register more gpu instance\n");
 112                 mutex_unlock(&mgpu_info.mutex);
 113                 return;
 114         }
 115
 116         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 117         gpu_instance->adev = adev;
 118         gpu_instance->mgpu_fan_enabled = 0;
 119
 120         mgpu_info.num_gpu++;
 121         if (adev->flags & AMD_IS_APU)
 122                 mgpu_info.num_apu++;
 123         else
 124                 mgpu_info.num_dgpu++;
 125
 126         mutex_unlock(&mgpu_info.mutex);
 127 }
 128
 129 /**
 130  * amdgpu_driver_load_kms - Main load function for KMS.
 131  *
 132  * @dev: drm dev pointer
 133  * @flags: device flags
 134  *
 135  * This is the main load function for KMS (all asics).
 136  * Returns 0 on success, error on failure.
 137  */
 138 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 139 {
 140         struct amdgpu_device *adev;
 141         int r, acpi_status;
 142
 143 #ifdef CONFIG_DRM_AMDGPU_SI
 144         if (!amdgpu_si_support) {
 145                 switch (flags & AMD_ASIC_MASK) {
 146                 case CHIP_TAHITI:
 147                 case CHIP_PITCAIRN:
 148                 case CHIP_VERDE:
 149                 case CHIP_OLAND:
 150                 case CHIP_HAINAN:
 151                         dev_info(dev->dev,
 152                                  "SI support provided by radeon.\n");
 153                         dev_info(dev->dev,
 154                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 155                                 );
 156                         return -ENODEV;
 157                 }
 158         }
 159 #endif
 160 #ifdef CONFIG_DRM_AMDGPU_CIK
 161         if (!amdgpu_cik_support) {
 162                 switch (flags & AMD_ASIC_MASK) {
 163                 case CHIP_KAVERI:
 164                 case CHIP_BONAIRE:
 165                 case CHIP_HAWAII:
 166                 case CHIP_KABINI:
 167                 case CHIP_MULLINS:
 168                         dev_info(dev->dev,
 169                                  "CIK support provided by radeon.\n");
 170                         dev_info(dev->dev,
 171                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 172                                 );
 173                         return -ENODEV;
 174                 }
 175         }
 176 #endif
 177
 178         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 179         if (adev == NULL) {
 180                 return -ENOMEM;
 181         }
 182         dev->dev_private = (void *)adev;
 183
 184         if ((amdgpu_runtime_pm != 0) &&
 185             amdgpu_has_atpx() &&
 186             (amdgpu_is_atpx_hybrid() ||
 187              amdgpu_has_atpx_dgpu_power_cntl()) &&
 188             ((flags & AMD_IS_APU) == 0) &&
 189             !pci_is_thunderbolt_attached(dev->pdev))
 190                 flags |= AMD_IS_PX;
 191
 192         /* amdgpu_device_init should report only fatal error
 193          * like memory allocation failure or iomapping failure,
 194          * or memory manager initialization failure, it must
 195          * properly initialize the GPU MC controller and permit
 196          * VRAM allocation
 197          */
 198         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 199         if (r) {
 200                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 201                 goto out;
 202         }
 203
 204         /* Call ACPI methods: require modeset init
 205          * but failure is not fatal
 206          */
 207         if (!r) {
 208                 acpi_status = amdgpu_acpi_init(adev);
 209                 if (acpi_status)
 210                 dev_dbg(&dev->pdev->dev,
 211                                 "Error during ACPI methods call\n");
 212         }
 213
 214         if (amdgpu_device_is_px(dev)) {
 215                 pm_runtime_use_autosuspend(dev->dev);
 216                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 217                 pm_runtime_set_active(dev->dev);
 218                 pm_runtime_allow(dev->dev);
 219                 pm_runtime_mark_last_busy(dev->dev);
 220                 pm_runtime_put_autosuspend(dev->dev);
 221         }
 222
 223         amdgpu_register_gpu_instance(adev);
 224 out:
 225         if (r) {
 226                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 227                 if (adev->rmmio && amdgpu_device_is_px(dev))
 228                         pm_runtime_put_noidle(dev->dev);
 229                 amdgpu_driver_unload_kms(dev);
 230         }
 231
 232         return r;
 233 }
 234
 235 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 236                                 struct drm_amdgpu_query_fw *query_fw,
 237                                 struct amdgpu_device *adev)
 238 {
 239         switch (query_fw->fw_type) {
 240         case AMDGPU_INFO_FW_VCE:
 241                 fw_info->ver = adev->vce.fw_version;
 242                 fw_info->feature = adev->vce.fb_version;
 243                 break;
 244         case AMDGPU_INFO_FW_UVD:
 245                 fw_info->ver = adev->uvd.fw_version;
 246                 fw_info->feature = 0;
 247                 break;
 248         case AMDGPU_INFO_FW_VCN:
 249                 fw_info->ver = adev->vcn.fw_version;
 250                 fw_info->feature = 0;
 251                 break;
 252         case AMDGPU_INFO_FW_GMC:
 253                 fw_info->ver = adev->gmc.fw_version;
 254                 fw_info->feature = 0;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_ME:
 257                 fw_info->ver = adev->gfx.me_fw_version;
 258                 fw_info->feature = adev->gfx.me_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_PFP:
 261                 fw_info->ver = adev->gfx.pfp_fw_version;
 262                 fw_info->feature = adev->gfx.pfp_feature_version;
 263                 break;
 264         case AMDGPU_INFO_FW_GFX_CE:
 265                 fw_info->ver = adev->gfx.ce_fw_version;
 266                 fw_info->feature = adev->gfx.ce_feature_version;
 267                 break;
 268         case AMDGPU_INFO_FW_GFX_RLC:
 269                 fw_info->ver = adev->gfx.rlc_fw_version;
 270                 fw_info->feature = adev->gfx.rlc_feature_version;
 271                 break;
 272         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 273                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 274                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 275                 break;
 276         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 277                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 278                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 279                 break;
 280         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 281                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 282                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 283                 break;
 284         case AMDGPU_INFO_FW_GFX_MEC:
 285                 if (query_fw->index == 0) {
 286                         fw_info->ver = adev->gfx.mec_fw_version;
 287                         fw_info->feature = adev->gfx.mec_feature_version;
 288                 } else if (query_fw->index == 1) {
 289                         fw_info->ver = adev->gfx.mec2_fw_version;
 290                         fw_info->feature = adev->gfx.mec2_feature_version;
 291                 } else
 292                         return -EINVAL;
 293                 break;
 294         case AMDGPU_INFO_FW_SMC:
 295                 fw_info->ver = adev->pm.fw_version;
 296                 fw_info->feature = 0;
 297                 break;
 298         case AMDGPU_INFO_FW_SDMA:
 299                 if (query_fw->index >= adev->sdma.num_instances)
 300                         return -EINVAL;
 301                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 302                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 303                 break;
 304         case AMDGPU_INFO_FW_SOS:
 305                 fw_info->ver = adev->psp.sos_fw_version;
 306                 fw_info->feature = adev->psp.sos_feature_version;
 307                 break;
 308         case AMDGPU_INFO_FW_ASD:
 309                 fw_info->ver = adev->psp.asd_fw_version;
 310                 fw_info->feature = adev->psp.asd_feature_version;
 311                 break;
 312         case AMDGPU_INFO_FW_DMCU:
 313                 fw_info->ver = adev->dm.dmcu_fw_version;
 314                 fw_info->feature = 0;
 315                 break;
 316         default:
 317                 return -EINVAL;
 318         }
 319         return 0;
 320 }
 321
 322 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 323                              struct drm_amdgpu_info *info,
 324                              struct drm_amdgpu_info_hw_ip *result)
 325 {
 326         uint32_t ib_start_alignment = 0;
 327         uint32_t ib_size_alignment = 0;
 328         enum amd_ip_block_type type;
 329         unsigned int num_rings = 0;
 330         unsigned int i, j;
 331
 332         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 333                 return -EINVAL;
 334
 335         switch (info->query_hw_ip.type) {
 336         case AMDGPU_HW_IP_GFX:
 337                 type = AMD_IP_BLOCK_TYPE_GFX;
 338                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 339                         if (adev->gfx.gfx_ring[i].ready)
 340                                 ++num_rings;
 341                 ib_start_alignment = 32;
 342                 ib_size_alignment = 32;
 343                 break;
 344         case AMDGPU_HW_IP_COMPUTE:
 345                 type = AMD_IP_BLOCK_TYPE_GFX;
 346                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 347                         if (adev->gfx.compute_ring[i].ready)
 348                                 ++num_rings;
 349                 ib_start_alignment = 32;
 350                 ib_size_alignment = 32;
 351                 break;
 352         case AMDGPU_HW_IP_DMA:
 353                 type = AMD_IP_BLOCK_TYPE_SDMA;
 354                 for (i = 0; i < adev->sdma.num_instances; i++)
 355                         if (adev->sdma.instance[i].ring.ready)
 356                                 ++num_rings;
 357                 ib_start_alignment = 256;
 358                 ib_size_alignment = 4;
 359                 break;
 360         case AMDGPU_HW_IP_UVD:
 361                 type = AMD_IP_BLOCK_TYPE_UVD;
 362                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 363                         if (adev->uvd.harvest_config & (1 << i))
 364                                 continue;
 365
 366                         if (adev->uvd.inst[i].ring.ready)
 367                                 ++num_rings;
 368                 }
 369                 ib_start_alignment = 64;
 370                 ib_size_alignment = 64;
 371                 break;
 372         case AMDGPU_HW_IP_VCE:
 373                 type = AMD_IP_BLOCK_TYPE_VCE;
 374                 for (i = 0; i < adev->vce.num_rings; i++)
 375                         if (adev->vce.ring[i].ready)
 376                                 ++num_rings;
 377                 ib_start_alignment = 4;
 378                 ib_size_alignment = 1;
 379                 break;
 380         case AMDGPU_HW_IP_UVD_ENC:
 381                 type = AMD_IP_BLOCK_TYPE_UVD;
 382                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 383                         if (adev->uvd.harvest_config & (1 << i))
 384                                 continue;
 385
 386                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 387                                 if (adev->uvd.inst[i].ring_enc[j].ready)
 388                                         ++num_rings;
 389                 }
 390                 ib_start_alignment = 64;
 391                 ib_size_alignment = 64;
 392                 break;
 393         case AMDGPU_HW_IP_VCN_DEC:
 394                 type = AMD_IP_BLOCK_TYPE_VCN;
 395                 if (adev->vcn.ring_dec.ready)
 396                         ++num_rings;
 397                 ib_start_alignment = 16;
 398                 ib_size_alignment = 16;
 399                 break;
 400         case AMDGPU_HW_IP_VCN_ENC:
 401                 type = AMD_IP_BLOCK_TYPE_VCN;
 402                 for (i = 0; i < adev->vcn.num_enc_rings; i++)
 403                         if (adev->vcn.ring_enc[i].ready)
 404                                 ++num_rings;
 405                 ib_start_alignment = 64;
 406                 ib_size_alignment = 1;
 407                 break;
 408         case AMDGPU_HW_IP_VCN_JPEG:
 409                 type = AMD_IP_BLOCK_TYPE_VCN;
 410                 if (adev->vcn.ring_jpeg.ready)
 411                         ++num_rings;
 412                 ib_start_alignment = 16;
 413                 ib_size_alignment = 16;
 414                 break;
 415         default:
 416                 return -EINVAL;
 417         }
 418
 419         for (i = 0; i < adev->num_ip_blocks; i++)
 420                 if (adev->ip_blocks[i].version->type == type &&
 421                     adev->ip_blocks[i].status.valid)
 422                         break;
 423
 424         if (i == adev->num_ip_blocks)
 425                 return 0;
 426
 427         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 428                         num_rings);
 429
 430         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 431         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 432         result->capabilities_flags = 0;
 433         result->available_rings = (1 << num_rings) - 1;
 434         result->ib_start_alignment = ib_start_alignment;
 435         result->ib_size_alignment = ib_size_alignment;
 436         return 0;
 437 }
 438
 439 /*
 440  * Userspace get information ioctl
 441  */
 442 /**
 443  * amdgpu_info_ioctl - answer a device specific request.
 444  *
 445  * @adev: amdgpu device pointer
 446  * @data: request object
 447  * @filp: drm filp
 448  *
 449  * This function is used to pass device specific parameters to the userspace
 450  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 451  * etc. (all asics).
 452  * Returns 0 on success, -EINVAL on failure.
 453  */
 454 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 455 {
 456         struct amdgpu_device *adev = dev->dev_private;
 457         struct drm_amdgpu_info *info = data;
 458         struct amdgpu_mode_info *minfo = &adev->mode_info;
 459         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 460         uint32_t size = info->return_size;
 461         struct drm_crtc *crtc;
 462         uint32_t ui32 = 0;
 463         uint64_t ui64 = 0;
 464         int i, found;
 465         int ui32_size = sizeof(ui32);
 466
 467         if (!info->return_size || !info->return_pointer)
 468                 return -EINVAL;
 469
 470         /* Ensure IB tests are run on ring */
 471         flush_delayed_work(&adev->late_init_work);
 472
 473         switch (info->query) {
 474         case AMDGPU_INFO_ACCEL_WORKING:
 475                 ui32 = adev->accel_working;
 476                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 477         case AMDGPU_INFO_CRTC_FROM_ID:
 478                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 479                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 480                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 481                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 482                                 ui32 = amdgpu_crtc->crtc_id;
 483                                 found = 1;
 484                                 break;
 485                         }
 486                 }
 487                 if (!found) {
 488                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 489                         return -EINVAL;
 490                 }
 491                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 492         case AMDGPU_INFO_HW_IP_INFO: {
 493                 struct drm_amdgpu_info_hw_ip ip = {};
 494                 int ret;
 495
 496                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 497                 if (ret)
 498                         return ret;
 499
 500                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 501                 return ret ? -EFAULT : 0;
 502         }
 503         case AMDGPU_INFO_HW_IP_COUNT: {
 504                 enum amd_ip_block_type type;
 505                 uint32_t count = 0;
 506
 507                 switch (info->query_hw_ip.type) {
 508                 case AMDGPU_HW_IP_GFX:
 509                         type = AMD_IP_BLOCK_TYPE_GFX;
 510                         break;
 511                 case AMDGPU_HW_IP_COMPUTE:
 512                         type = AMD_IP_BLOCK_TYPE_GFX;
 513                         break;
 514                 case AMDGPU_HW_IP_DMA:
 515                         type = AMD_IP_BLOCK_TYPE_SDMA;
 516                         break;
 517                 case AMDGPU_HW_IP_UVD:
 518                         type = AMD_IP_BLOCK_TYPE_UVD;
 519                         break;
 520                 case AMDGPU_HW_IP_VCE:
 521                         type = AMD_IP_BLOCK_TYPE_VCE;
 522                         break;
 523                 case AMDGPU_HW_IP_UVD_ENC:
 524                         type = AMD_IP_BLOCK_TYPE_UVD;
 525                         break;
 526                 case AMDGPU_HW_IP_VCN_DEC:
 527                 case AMDGPU_HW_IP_VCN_ENC:
 528                 case AMDGPU_HW_IP_VCN_JPEG:
 529                         type = AMD_IP_BLOCK_TYPE_VCN;
 530                         break;
 531                 default:
 532                         return -EINVAL;
 533                 }
 534
 535                 for (i = 0; i < adev->num_ip_blocks; i++)
 536                         if (adev->ip_blocks[i].version->type == type &&
 537                             adev->ip_blocks[i].status.valid &&
 538                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 539                                 count++;
 540
 541                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 542         }
 543         case AMDGPU_INFO_TIMESTAMP:
 544                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 545                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 546         case AMDGPU_INFO_FW_VERSION: {
 547                 struct drm_amdgpu_info_firmware fw_info;
 548                 int ret;
 549
 550                 /* We only support one instance of each IP block right now. */
 551                 if (info->query_fw.ip_instance != 0)
 552                         return -EINVAL;
 553
 554                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 555                 if (ret)
 556                         return ret;
 557
 558                 return copy_to_user(out, &fw_info,
 559                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 560         }
 561         case AMDGPU_INFO_NUM_BYTES_MOVED:
 562                 ui64 = atomic64_read(&adev->num_bytes_moved);
 563                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 564         case AMDGPU_INFO_NUM_EVICTIONS:
 565                 ui64 = atomic64_read(&adev->num_evictions);
 566                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 567         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 568                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 569                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 570         case AMDGPU_INFO_VRAM_USAGE:
 571                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 572                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 573         case AMDGPU_INFO_VIS_VRAM_USAGE:
 574                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 575                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 576         case AMDGPU_INFO_GTT_USAGE:
 577                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 578                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 579         case AMDGPU_INFO_GDS_CONFIG: {
 580                 struct drm_amdgpu_info_gds gds_info;
 581
 582                 memset(&gds_info, 0, sizeof(gds_info));
 583                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size;
 584                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size;
 585                 gds_info.gds_total_size = adev->gds.mem.total_size;
 586                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size;
 587                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size;
 588                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size;
 589                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size;
 590                 return copy_to_user(out, &gds_info,
 591                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 592         }
 593         case AMDGPU_INFO_VRAM_GTT: {
 594                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 595
 596                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 597                         atomic64_read(&adev->vram_pin_size);
 598                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 599                         atomic64_read(&adev->visible_pin_size);
 600                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 601                 vram_gtt.gtt_size *= PAGE_SIZE;
 602                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 603                 return copy_to_user(out, &vram_gtt,
 604                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 605         }
 606         case AMDGPU_INFO_MEMORY: {
 607                 struct drm_amdgpu_memory_info mem;
 608
 609                 memset(&mem, 0, sizeof(mem));
 610                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 611                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 612                         atomic64_read(&adev->vram_pin_size);
 613                 mem.vram.heap_usage =
 614                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 615                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 616
 617                 mem.cpu_accessible_vram.total_heap_size =
 618                         adev->gmc.visible_vram_size;
 619                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 620                         atomic64_read(&adev->visible_pin_size);
 621                 mem.cpu_accessible_vram.heap_usage =
 622                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 623                 mem.cpu_accessible_vram.max_allocation =
 624                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 625
 626                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 627                 mem.gtt.total_heap_size *= PAGE_SIZE;
 628                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 629                         atomic64_read(&adev->gart_pin_size);
 630                 mem.gtt.heap_usage =
 631                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 632                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 633
 634                 return copy_to_user(out, &mem,
 635                                     min((size_t)size, sizeof(mem)))
 636                                     ? -EFAULT : 0;
 637         }
 638         case AMDGPU_INFO_READ_MMR_REG: {
 639                 unsigned n, alloc_size;
 640                 uint32_t *regs;
 641                 unsigned se_num = (info->read_mmr_reg.instance >>
 642                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 643                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 644                 unsigned sh_num = (info->read_mmr_reg.instance >>
 645                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 646                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 647
 648                 /* set full masks if the userspace set all bits
 649                  * in the bitfields */
 650                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 651                         se_num = 0xffffffff;
 652                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 653                         sh_num = 0xffffffff;
 654
 655                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 656                 if (!regs)
 657                         return -ENOMEM;
 658                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 659
 660                 for (i = 0; i < info->read_mmr_reg.count; i++)
 661                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 662                                                       info->read_mmr_reg.dword_offset + i,
 663                                                       &regs[i])) {
 664                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 665                                               info->read_mmr_reg.dword_offset + i);
 666                                 kfree(regs);
 667                                 return -EFAULT;
 668                         }
 669                 n = copy_to_user(out, regs, min(size, alloc_size));
 670                 kfree(regs);
 671                 return n ? -EFAULT : 0;
 672         }
 673         case AMDGPU_INFO_DEV_INFO: {
 674                 struct drm_amdgpu_info_device dev_info = {};
 675                 uint64_t vm_size;
 676
 677                 dev_info.device_id = dev->pdev->device;
 678                 dev_info.chip_rev = adev->rev_id;
 679                 dev_info.external_rev = adev->external_rev_id;
 680                 dev_info.pci_rev = dev->pdev->revision;
 681                 dev_info.family = adev->family;
 682                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 683                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 684                 /* return all clocks in KHz */
 685                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 686                 if (adev->pm.dpm_enabled) {
 687                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 688                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 689                 } else {
 690                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 691                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 692                 }
 693                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 694                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 695                         adev->gfx.config.max_shader_engines;
 696                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 697                 dev_info._pad = 0;
 698                 dev_info.ids_flags = 0;
 699                 if (adev->flags & AMD_IS_APU)
 700                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 701                 if (amdgpu_sriov_vf(adev))
 702                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 703
 704                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 705                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 706
 707                 /* Older VCE FW versions are buggy and can handle only 40bits */
 708                 if (adev->vce.fw_version &&
 709                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 710                         vm_size = min(vm_size, 1ULL << 40);
 711
 712                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 713                 dev_info.virtual_address_max =
 714                         min(vm_size, AMDGPU_GMC_HOLE_START);
 715
 716                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 717                         dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
 718                         dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 719                 }
 720                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 721                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 722                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 723                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 724                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 725                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 726                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 727                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 728                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 729                        sizeof(adev->gfx.cu_info.bitmap));
 730                 dev_info.vram_type = adev->gmc.vram_type;
 731                 dev_info.vram_bit_width = adev->gmc.vram_width;
 732                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 733                 dev_info.gc_double_offchip_lds_buf =
 734                         adev->gfx.config.double_offchip_lds_buf;
 735
 736                 if (amdgpu_ngg) {
 737                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 738                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 739                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 740                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 741                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 742                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 743                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 744                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 745                 }
 746                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 747                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 748                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 749                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 750                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 751                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 752                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 753
 754                 return copy_to_user(out, &dev_info,
 755                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 756         }
 757         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 758                 unsigned i;
 759                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 760                 struct amd_vce_state *vce_state;
 761
 762                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 763                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 764                         if (vce_state) {
 765                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 766                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 767                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 768                                 vce_clk_table.num_valid_entries++;
 769                         }
 770                 }
 771
 772                 return copy_to_user(out, &vce_clk_table,
 773                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 774         }
 775         case AMDGPU_INFO_VBIOS: {
 776                 uint32_t bios_size = adev->bios_size;
 777
 778                 switch (info->vbios_info.type) {
 779                 case AMDGPU_INFO_VBIOS_SIZE:
 780                         return copy_to_user(out, &bios_size,
 781                                         min((size_t)size, sizeof(bios_size)))
 782                                         ? -EFAULT : 0;
 783                 case AMDGPU_INFO_VBIOS_IMAGE: {
 784                         uint8_t *bios;
 785                         uint32_t bios_offset = info->vbios_info.offset;
 786
 787                         if (bios_offset >= bios_size)
 788                                 return -EINVAL;
 789
 790                         bios = adev->bios + bios_offset;
 791                         return copy_to_user(out, bios,
 792                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 793                                         ? -EFAULT : 0;
 794                 }
 795                 default:
 796                         DRM_DEBUG_KMS("Invalid request %d\n",
 797                                         info->vbios_info.type);
 798                         return -EINVAL;
 799                 }
 800         }
 801         case AMDGPU_INFO_NUM_HANDLES: {
 802                 struct drm_amdgpu_info_num_handles handle;
 803
 804                 switch (info->query_hw_ip.type) {
 805                 case AMDGPU_HW_IP_UVD:
 806                         /* Starting Polaris, we support unlimited UVD handles */
 807                         if (adev->asic_type < CHIP_POLARIS10) {
 808                                 handle.uvd_max_handles = adev->uvd.max_handles;
 809                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 810
 811                                 return copy_to_user(out, &handle,
 812                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 813                         } else {
 814                                 return -ENODATA;
 815                         }
 816
 817                         break;
 818                 default:
 819                         return -EINVAL;
 820                 }
 821         }
 822         case AMDGPU_INFO_SENSOR: {
 823                 if (!adev->pm.dpm_enabled)
 824                         return -ENOENT;
 825
 826                 switch (info->sensor_info.type) {
 827                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 828                         /* get sclk in Mhz */
 829                         if (amdgpu_dpm_read_sensor(adev,
 830                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 831                                                    (void *)&ui32, &ui32_size)) {
 832                                 return -EINVAL;
 833                         }
 834                         ui32 /= 100;
 835                         break;
 836                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 837                         /* get mclk in Mhz */
 838                         if (amdgpu_dpm_read_sensor(adev,
 839                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 840                                                    (void *)&ui32, &ui32_size)) {
 841                                 return -EINVAL;
 842                         }
 843                         ui32 /= 100;
 844                         break;
 845                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 846                         /* get temperature in millidegrees C */
 847                         if (amdgpu_dpm_read_sensor(adev,
 848                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 849                                                    (void *)&ui32, &ui32_size)) {
 850                                 return -EINVAL;
 851                         }
 852                         break;
 853                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 854                         /* get GPU load */
 855                         if (amdgpu_dpm_read_sensor(adev,
 856                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 857                                                    (void *)&ui32, &ui32_size)) {
 858                                 return -EINVAL;
 859                         }
 860                         break;
 861                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 862                         /* get average GPU power */
 863                         if (amdgpu_dpm_read_sensor(adev,
 864                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 865                                                    (void *)&ui32, &ui32_size)) {
 866                                 return -EINVAL;
 867                         }
 868                         ui32 >>= 8;
 869                         break;
 870                 case AMDGPU_INFO_SENSOR_VDDNB:
 871                         /* get VDDNB in millivolts */
 872                         if (amdgpu_dpm_read_sensor(adev,
 873                                                    AMDGPU_PP_SENSOR_VDDNB,
 874                                                    (void *)&ui32, &ui32_size)) {
 875                                 return -EINVAL;
 876                         }
 877                         break;
 878                 case AMDGPU_INFO_SENSOR_VDDGFX:
 879                         /* get VDDGFX in millivolts */
 880                         if (amdgpu_dpm_read_sensor(adev,
 881                                                    AMDGPU_PP_SENSOR_VDDGFX,
 882                                                    (void *)&ui32, &ui32_size)) {
 883                                 return -EINVAL;
 884                         }
 885                         break;
 886                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 887                         /* get stable pstate sclk in Mhz */
 888                         if (amdgpu_dpm_read_sensor(adev,
 889                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 890                                                    (void *)&ui32, &ui32_size)) {
 891                                 return -EINVAL;
 892                         }
 893                         ui32 /= 100;
 894                         break;
 895                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 896                         /* get stable pstate mclk in Mhz */
 897                         if (amdgpu_dpm_read_sensor(adev,
 898                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 899                                                    (void *)&ui32, &ui32_size)) {
 900                                 return -EINVAL;
 901                         }
 902                         ui32 /= 100;
 903                         break;
 904                 default:
 905                         DRM_DEBUG_KMS("Invalid request %d\n",
 906                                       info->sensor_info.type);
 907                         return -EINVAL;
 908                 }
 909                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 910         }
 911         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 912                 ui32 = atomic_read(&adev->vram_lost_counter);
 913                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 914         default:
 915                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 916                 return -EINVAL;
 917         }
 918         return 0;
 919 }
 920
 921
 922 /*
 923  * Outdated mess for old drm with Xorg being in charge (void function now).
 924  */
 925 /**
 926  * amdgpu_driver_lastclose_kms - drm callback for last close
 927  *
 928  * @dev: drm dev pointer
 929  *
 930  * Switch vga_switcheroo state after last close (all asics).
 931  */
 932 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 933 {
 934         drm_fb_helper_lastclose(dev);
 935         vga_switcheroo_process_delayed_switch();
 936 }
 937
 938 /**
 939  * amdgpu_driver_open_kms - drm callback for open
 940  *
 941  * @dev: drm dev pointer
 942  * @file_priv: drm file
 943  *
 944  * On device open, init vm on cayman+ (all asics).
 945  * Returns 0 on success, error on failure.
 946  */
 947 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 948 {
 949         struct amdgpu_device *adev = dev->dev_private;
 950         struct amdgpu_fpriv *fpriv;
 951         int r, pasid;
 952
 953         file_priv->driver_priv = NULL;
 954
 955         r = pm_runtime_get_sync(dev->dev);
 956         if (r < 0)
 957                 return r;
 958
 959         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 960         if (unlikely(!fpriv)) {
 961                 r = -ENOMEM;
 962                 goto out_suspend;
 963         }
 964
 965         pasid = amdgpu_pasid_alloc(16);
 966         if (pasid < 0) {
 967                 dev_warn(adev->dev, "No more PASIDs available!");
 968                 pasid = 0;
 969         }
 970         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 971         if (r)
 972                 goto error_pasid;
 973
 974         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 975         if (!fpriv->prt_va) {
 976                 r = -ENOMEM;
 977                 goto error_vm;
 978         }
 979
 980         if (amdgpu_sriov_vf(adev)) {
 981                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
 982                 if (r)
 983                         goto error_vm;
 984         }
 985
 986         mutex_init(&fpriv->bo_list_lock);
 987         idr_init(&fpriv->bo_list_handles);
 988
 989         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 990
 991         file_priv->driver_priv = fpriv;
 992         goto out_suspend;
 993
 994 error_vm:
 995         amdgpu_vm_fini(adev, &fpriv->vm);
 996
 997 error_pasid:
 998         if (pasid)
 999                 amdgpu_pasid_free(pasid);
1000
1001         kfree(fpriv);
1002
1003 out_suspend:
1004         pm_runtime_mark_last_busy(dev->dev);
1005         pm_runtime_put_autosuspend(dev->dev);
1006
1007         return r;
1008 }
1009
1010 /**
1011  * amdgpu_driver_postclose_kms - drm callback for post close
1012  *
1013  * @dev: drm dev pointer
1014  * @file_priv: drm file
1015  *
1016  * On device post close, tear down vm on cayman+ (all asics).
1017  */
1018 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1019                                  struct drm_file *file_priv)
1020 {
1021         struct amdgpu_device *adev = dev->dev_private;
1022         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1023         struct amdgpu_bo_list *list;
1024         struct amdgpu_bo *pd;
1025         unsigned int pasid;
1026         int handle;
1027
1028         if (!fpriv)
1029                 return;
1030
1031         pm_runtime_get_sync(dev->dev);
1032
1033         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1034                 amdgpu_uvd_free_handles(adev, file_priv);
1035         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1036                 amdgpu_vce_free_handles(adev, file_priv);
1037
1038         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1039
1040         if (amdgpu_sriov_vf(adev)) {
1041                 /* TODO: how to handle reserve failure */
1042                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1043                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1044                 fpriv->csa_va = NULL;
1045                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1046         }
1047
1048         pasid = fpriv->vm.pasid;
1049         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1050
1051         amdgpu_vm_fini(adev, &fpriv->vm);
1052         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1053
1054         if (pasid)
1055                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
1056         amdgpu_bo_unref(&pd);
1057
1058         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1059                 amdgpu_bo_list_put(list);
1060
1061         idr_destroy(&fpriv->bo_list_handles);
1062         mutex_destroy(&fpriv->bo_list_lock);
1063
1064         kfree(fpriv);
1065         file_priv->driver_priv = NULL;
1066
1067         pm_runtime_mark_last_busy(dev->dev);
1068         pm_runtime_put_autosuspend(dev->dev);
1069 }
1070
1071 /*
1072  * VBlank related functions.
1073  */
1074 /**
1075  * amdgpu_get_vblank_counter_kms - get frame count
1076  *
1077  * @dev: drm dev pointer
1078  * @pipe: crtc to get the frame count from
1079  *
1080  * Gets the frame count on the requested crtc (all asics).
1081  * Returns frame count on success, -EINVAL on failure.
1082  */
1083 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1084 {
1085         struct amdgpu_device *adev = dev->dev_private;
1086         int vpos, hpos, stat;
1087         u32 count;
1088
1089         if (pipe >= adev->mode_info.num_crtc) {
1090                 DRM_ERROR("Invalid crtc %u\n", pipe);
1091                 return -EINVAL;
1092         }
1093
1094         /* The hw increments its frame counter at start of vsync, not at start
1095          * of vblank, as is required by DRM core vblank counter handling.
1096          * Cook the hw count here to make it appear to the caller as if it
1097          * incremented at start of vblank. We measure distance to start of
1098          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1099          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1100          * result by 1 to give the proper appearance to caller.
1101          */
1102         if (adev->mode_info.crtcs[pipe]) {
1103                 /* Repeat readout if needed to provide stable result if
1104                  * we cross start of vsync during the queries.
1105                  */
1106                 do {
1107                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1108                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1109                          * vpos as distance to start of vblank, instead of
1110                          * regular vertical scanout pos.
1111                          */
1112                         stat = amdgpu_display_get_crtc_scanoutpos(
1113                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1114                                 &vpos, &hpos, NULL, NULL,
1115                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1116                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1117
1118                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1119                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1120                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1121                 } else {
1122                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1123                                       pipe, vpos);
1124
1125                         /* Bump counter if we are at >= leading edge of vblank,
1126                          * but before vsync where vpos would turn negative and
1127                          * the hw counter really increments.
1128                          */
1129                         if (vpos >= 0)
1130                                 count++;
1131                 }
1132         } else {
1133                 /* Fallback to use value as is. */
1134                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1135                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1136         }
1137
1138         return count;
1139 }
1140
1141 /**
1142  * amdgpu_enable_vblank_kms - enable vblank interrupt
1143  *
1144  * @dev: drm dev pointer
1145  * @pipe: crtc to enable vblank interrupt for
1146  *
1147  * Enable the interrupt on the requested crtc (all asics).
1148  * Returns 0 on success, -EINVAL on failure.
1149  */
1150 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1151 {
1152         struct amdgpu_device *adev = dev->dev_private;
1153         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1154
1155         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1156 }
1157
1158 /**
1159  * amdgpu_disable_vblank_kms - disable vblank interrupt
1160  *
1161  * @dev: drm dev pointer
1162  * @pipe: crtc to disable vblank interrupt for
1163  *
1164  * Disable the interrupt on the requested crtc (all asics).
1165  */
1166 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1167 {
1168         struct amdgpu_device *adev = dev->dev_private;
1169         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1170
1171         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1172 }
1173
1174 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1175         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1176         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1177         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1178         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1179         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1180         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1181         /* KMS */
1182         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1183         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1184         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1185         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1186         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1187         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1188         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1189         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1190         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1191         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1192 };
1193 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1194
1195 /*
1196  * Debugfs info
1197  */
1198 #if defined(CONFIG_DEBUG_FS)
1199
1200 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1201 {
1202         struct drm_info_node *node = (struct drm_info_node *) m->private;
1203         struct drm_device *dev = node->minor->dev;
1204         struct amdgpu_device *adev = dev->dev_private;
1205         struct drm_amdgpu_info_firmware fw_info;
1206         struct drm_amdgpu_query_fw query_fw;
1207         struct atom_context *ctx = adev->mode_info.atom_context;
1208         int ret, i;
1209
1210         /* VCE */
1211         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1212         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1213         if (ret)
1214                 return ret;
1215         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1216                    fw_info.feature, fw_info.ver);
1217
1218         /* UVD */
1219         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1220         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1221         if (ret)
1222                 return ret;
1223         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1224                    fw_info.feature, fw_info.ver);
1225
1226         /* GMC */
1227         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1228         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1229         if (ret)
1230                 return ret;
1231         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1232                    fw_info.feature, fw_info.ver);
1233
1234         /* ME */
1235         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1236         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1237         if (ret)
1238                 return ret;
1239         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1240                    fw_info.feature, fw_info.ver);
1241
1242         /* PFP */
1243         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1244         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1245         if (ret)
1246                 return ret;
1247         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1248                    fw_info.feature, fw_info.ver);
1249
1250         /* CE */
1251         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1252         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1253         if (ret)
1254                 return ret;
1255         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1256                    fw_info.feature, fw_info.ver);
1257
1258         /* RLC */
1259         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1260         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1261         if (ret)
1262                 return ret;
1263         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1264                    fw_info.feature, fw_info.ver);
1265
1266         /* RLC SAVE RESTORE LIST CNTL */
1267         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1268         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1269         if (ret)
1270                 return ret;
1271         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1272                    fw_info.feature, fw_info.ver);
1273
1274         /* RLC SAVE RESTORE LIST GPM MEM */
1275         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1276         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1277         if (ret)
1278                 return ret;
1279         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1280                    fw_info.feature, fw_info.ver);
1281
1282         /* RLC SAVE RESTORE LIST SRM MEM */
1283         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1284         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1285         if (ret)
1286                 return ret;
1287         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1288                    fw_info.feature, fw_info.ver);
1289
1290         /* MEC */
1291         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1292         query_fw.index = 0;
1293         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1294         if (ret)
1295                 return ret;
1296         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1297                    fw_info.feature, fw_info.ver);
1298
1299         /* MEC2 */
1300         if (adev->asic_type == CHIP_KAVERI ||
1301             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1302                 query_fw.index = 1;
1303                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1304                 if (ret)
1305                         return ret;
1306                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1307                            fw_info.feature, fw_info.ver);
1308         }
1309
1310         /* PSP SOS */
1311         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1312         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1313         if (ret)
1314                 return ret;
1315         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1316                    fw_info.feature, fw_info.ver);
1317
1318
1319         /* PSP ASD */
1320         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1321         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1322         if (ret)
1323                 return ret;
1324         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1325                    fw_info.feature, fw_info.ver);
1326
1327         /* SMC */
1328         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1329         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1330         if (ret)
1331                 return ret;
1332         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1333                    fw_info.feature, fw_info.ver);
1334
1335         /* SDMA */
1336         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1337         for (i = 0; i < adev->sdma.num_instances; i++) {
1338                 query_fw.index = i;
1339                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1340                 if (ret)
1341                         return ret;
1342                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1343                            i, fw_info.feature, fw_info.ver);
1344         }
1345
1346         /* VCN */
1347         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1348         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1349         if (ret)
1350                 return ret;
1351         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1352                    fw_info.feature, fw_info.ver);
1353
1354         /* DMCU */
1355         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1356         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1357         if (ret)
1358                 return ret;
1359         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1360                    fw_info.feature, fw_info.ver);
1361
1362
1363         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1364
1365         return 0;
1366 }
1367
1368 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1369         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1370 };
1371 #endif
1372
1373 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1374 {
1375 #if defined(CONFIG_DEBUG_FS)
1376         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1377                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1378 #else
1379         return 0;
1380 #endif
1381 }