drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_sched.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46
  47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  48 {
  49         struct amdgpu_gpu_instance *gpu_instance;
  50         int i;
  51
  52         mutex_lock(&mgpu_info.mutex);
  53
  54         for (i = 0; i < mgpu_info.num_gpu; i++) {
  55                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  56                 if (gpu_instance->adev == adev) {
  57                         mgpu_info.gpu_ins[i] =
  58                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  59                         mgpu_info.num_gpu--;
  60                         if (adev->flags & AMD_IS_APU)
  61                                 mgpu_info.num_apu--;
  62                         else
  63                                 mgpu_info.num_dgpu--;
  64                         break;
  65                 }
  66         }
  67
  68         mutex_unlock(&mgpu_info.mutex);
  69 }
  70
  71 /**
  72  * amdgpu_driver_unload_kms - Main unload function for KMS.
  73  *
  74  * @dev: drm dev pointer
  75  *
  76  * This is the main unload function for KMS (all asics).
  77  * Returns 0 on success.
  78  */
  79 void amdgpu_driver_unload_kms(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev == NULL)
  84                 return;
  85
  86         amdgpu_unregister_gpu_instance(adev);
  87
  88         if (adev->rmmio == NULL)
  89                 goto done_free;
  90
  91         if (adev->runpm) {
  92                 pm_runtime_get_sync(dev->dev);
  93                 pm_runtime_forbid(dev->dev);
  94         }
  95
  96         amdgpu_acpi_fini(adev);
  97
  98         amdgpu_device_fini(adev);
  99
 100 done_free:
 101         kfree(adev);
 102         dev->dev_private = NULL;
 103 }
 104
 105 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 106 {
 107         struct amdgpu_gpu_instance *gpu_instance;
 108
 109         mutex_lock(&mgpu_info.mutex);
 110
 111         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 112                 DRM_ERROR("Cannot register more gpu instance\n");
 113                 mutex_unlock(&mgpu_info.mutex);
 114                 return;
 115         }
 116
 117         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 118         gpu_instance->adev = adev;
 119         gpu_instance->mgpu_fan_enabled = 0;
 120
 121         mgpu_info.num_gpu++;
 122         if (adev->flags & AMD_IS_APU)
 123                 mgpu_info.num_apu++;
 124         else
 125                 mgpu_info.num_dgpu++;
 126
 127         mutex_unlock(&mgpu_info.mutex);
 128 }
 129
 130 /**
 131  * amdgpu_driver_load_kms - Main load function for KMS.
 132  *
 133  * @dev: drm dev pointer
 134  * @flags: device flags
 135  *
 136  * This is the main load function for KMS (all asics).
 137  * Returns 0 on success, error on failure.
 138  */
 139 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 140 {
 141         struct amdgpu_device *adev;
 142         int r, acpi_status;
 143
 144         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 145         if (adev == NULL) {
 146                 return -ENOMEM;
 147         }
 148         dev->dev_private = (void *)adev;
 149
 150         if (amdgpu_has_atpx() &&
 151             (amdgpu_is_atpx_hybrid() ||
 152              amdgpu_has_atpx_dgpu_power_cntl()) &&
 153             ((flags & AMD_IS_APU) == 0) &&
 154             !pci_is_thunderbolt_attached(dev->pdev))
 155                 flags |= AMD_IS_PX;
 156
 157         /* amdgpu_device_init should report only fatal error
 158          * like memory allocation failure or iomapping failure,
 159          * or memory manager initialization failure, it must
 160          * properly initialize the GPU MC controller and permit
 161          * VRAM allocation
 162          */
 163         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 164         if (r) {
 165                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 166                 goto out;
 167         }
 168
 169         if (amdgpu_device_supports_boco(dev) &&
 170             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 171                 adev->runpm = true;
 172         } else if (amdgpu_device_supports_baco(dev) &&
 173                    (amdgpu_runtime_pm != 0)) {
 174                 switch (adev->asic_type) {
 175 #ifdef CONFIG_DRM_AMDGPU_CIK
 176                 case CHIP_BONAIRE:
 177                 case CHIP_HAWAII:
 178 #endif
 179                 case CHIP_VEGA10:
 180                 case CHIP_VEGA20:
 181                 case CHIP_ARCTURUS:
 182                 case CHIP_SIENNA_CICHLID:
 183                         /* enable runpm if runpm=1 */
 184                         if (amdgpu_runtime_pm > 0)
 185                                 adev->runpm = true;
 186                         break;
 187                 default:
 188                         /* enable runpm on VI+ */
 189                         adev->runpm = true;
 190                         break;
 191                 }
 192         }
 193
 194         /* Call ACPI methods: require modeset init
 195          * but failure is not fatal
 196          */
 197
 198         acpi_status = amdgpu_acpi_init(adev);
 199         if (acpi_status)
 200                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
 201
 202         if (adev->runpm) {
 203                 /* only need to skip on ATPX */
 204                 if (amdgpu_device_supports_boco(dev) &&
 205                     !amdgpu_is_atpx_hybrid())
 206                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
 207                 pm_runtime_use_autosuspend(dev->dev);
 208                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 209                 pm_runtime_allow(dev->dev);
 210                 pm_runtime_mark_last_busy(dev->dev);
 211                 pm_runtime_put_autosuspend(dev->dev);
 212         }
 213
 214 out:
 215         if (r) {
 216                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 217                 if (adev->rmmio && adev->runpm)
 218                         pm_runtime_put_noidle(dev->dev);
 219                 amdgpu_driver_unload_kms(dev);
 220         }
 221
 222         return r;
 223 }
 224
 225 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 226                                 struct drm_amdgpu_query_fw *query_fw,
 227                                 struct amdgpu_device *adev)
 228 {
 229         switch (query_fw->fw_type) {
 230         case AMDGPU_INFO_FW_VCE:
 231                 fw_info->ver = adev->vce.fw_version;
 232                 fw_info->feature = adev->vce.fb_version;
 233                 break;
 234         case AMDGPU_INFO_FW_UVD:
 235                 fw_info->ver = adev->uvd.fw_version;
 236                 fw_info->feature = 0;
 237                 break;
 238         case AMDGPU_INFO_FW_VCN:
 239                 fw_info->ver = adev->vcn.fw_version;
 240                 fw_info->feature = 0;
 241                 break;
 242         case AMDGPU_INFO_FW_GMC:
 243                 fw_info->ver = adev->gmc.fw_version;
 244                 fw_info->feature = 0;
 245                 break;
 246         case AMDGPU_INFO_FW_GFX_ME:
 247                 fw_info->ver = adev->gfx.me_fw_version;
 248                 fw_info->feature = adev->gfx.me_feature_version;
 249                 break;
 250         case AMDGPU_INFO_FW_GFX_PFP:
 251                 fw_info->ver = adev->gfx.pfp_fw_version;
 252                 fw_info->feature = adev->gfx.pfp_feature_version;
 253                 break;
 254         case AMDGPU_INFO_FW_GFX_CE:
 255                 fw_info->ver = adev->gfx.ce_fw_version;
 256                 fw_info->feature = adev->gfx.ce_feature_version;
 257                 break;
 258         case AMDGPU_INFO_FW_GFX_RLC:
 259                 fw_info->ver = adev->gfx.rlc_fw_version;
 260                 fw_info->feature = adev->gfx.rlc_feature_version;
 261                 break;
 262         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 263                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 264                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 265                 break;
 266         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 267                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 268                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 269                 break;
 270         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 271                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 272                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 273                 break;
 274         case AMDGPU_INFO_FW_GFX_MEC:
 275                 if (query_fw->index == 0) {
 276                         fw_info->ver = adev->gfx.mec_fw_version;
 277                         fw_info->feature = adev->gfx.mec_feature_version;
 278                 } else if (query_fw->index == 1) {
 279                         fw_info->ver = adev->gfx.mec2_fw_version;
 280                         fw_info->feature = adev->gfx.mec2_feature_version;
 281                 } else
 282                         return -EINVAL;
 283                 break;
 284         case AMDGPU_INFO_FW_SMC:
 285                 fw_info->ver = adev->pm.fw_version;
 286                 fw_info->feature = 0;
 287                 break;
 288         case AMDGPU_INFO_FW_TA:
 289                 if (query_fw->index > 1)
 290                         return -EINVAL;
 291                 if (query_fw->index == 0) {
 292                         fw_info->ver = adev->psp.ta_fw_version;
 293                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 294                 } else {
 295                         fw_info->ver = adev->psp.ta_fw_version;
 296                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 297                 }
 298                 break;
 299         case AMDGPU_INFO_FW_SDMA:
 300                 if (query_fw->index >= adev->sdma.num_instances)
 301                         return -EINVAL;
 302                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 303                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 304                 break;
 305         case AMDGPU_INFO_FW_SOS:
 306                 fw_info->ver = adev->psp.sos_fw_version;
 307                 fw_info->feature = adev->psp.sos_feature_version;
 308                 break;
 309         case AMDGPU_INFO_FW_ASD:
 310                 fw_info->ver = adev->psp.asd_fw_version;
 311                 fw_info->feature = adev->psp.asd_feature_version;
 312                 break;
 313         case AMDGPU_INFO_FW_DMCU:
 314                 fw_info->ver = adev->dm.dmcu_fw_version;
 315                 fw_info->feature = 0;
 316                 break;
 317         case AMDGPU_INFO_FW_DMCUB:
 318                 fw_info->ver = adev->dm.dmcub_fw_version;
 319                 fw_info->feature = 0;
 320                 break;
 321         default:
 322                 return -EINVAL;
 323         }
 324         return 0;
 325 }
 326
 327 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 328                              struct drm_amdgpu_info *info,
 329                              struct drm_amdgpu_info_hw_ip *result)
 330 {
 331         uint32_t ib_start_alignment = 0;
 332         uint32_t ib_size_alignment = 0;
 333         enum amd_ip_block_type type;
 334         unsigned int num_rings = 0;
 335         unsigned int i, j;
 336
 337         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 338                 return -EINVAL;
 339
 340         switch (info->query_hw_ip.type) {
 341         case AMDGPU_HW_IP_GFX:
 342                 type = AMD_IP_BLOCK_TYPE_GFX;
 343                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 344                         if (adev->gfx.gfx_ring[i].sched.ready)
 345                                 ++num_rings;
 346                 ib_start_alignment = 32;
 347                 ib_size_alignment = 32;
 348                 break;
 349         case AMDGPU_HW_IP_COMPUTE:
 350                 type = AMD_IP_BLOCK_TYPE_GFX;
 351                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 352                         if (adev->gfx.compute_ring[i].sched.ready)
 353                                 ++num_rings;
 354                 ib_start_alignment = 32;
 355                 ib_size_alignment = 32;
 356                 break;
 357         case AMDGPU_HW_IP_DMA:
 358                 type = AMD_IP_BLOCK_TYPE_SDMA;
 359                 for (i = 0; i < adev->sdma.num_instances; i++)
 360                         if (adev->sdma.instance[i].ring.sched.ready)
 361                                 ++num_rings;
 362                 ib_start_alignment = 256;
 363                 ib_size_alignment = 4;
 364                 break;
 365         case AMDGPU_HW_IP_UVD:
 366                 type = AMD_IP_BLOCK_TYPE_UVD;
 367                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 368                         if (adev->uvd.harvest_config & (1 << i))
 369                                 continue;
 370
 371                         if (adev->uvd.inst[i].ring.sched.ready)
 372                                 ++num_rings;
 373                 }
 374                 ib_start_alignment = 64;
 375                 ib_size_alignment = 64;
 376                 break;
 377         case AMDGPU_HW_IP_VCE:
 378                 type = AMD_IP_BLOCK_TYPE_VCE;
 379                 for (i = 0; i < adev->vce.num_rings; i++)
 380                         if (adev->vce.ring[i].sched.ready)
 381                                 ++num_rings;
 382                 ib_start_alignment = 4;
 383                 ib_size_alignment = 1;
 384                 break;
 385         case AMDGPU_HW_IP_UVD_ENC:
 386                 type = AMD_IP_BLOCK_TYPE_UVD;
 387                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 388                         if (adev->uvd.harvest_config & (1 << i))
 389                                 continue;
 390
 391                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 392                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 393                                         ++num_rings;
 394                 }
 395                 ib_start_alignment = 64;
 396                 ib_size_alignment = 64;
 397                 break;
 398         case AMDGPU_HW_IP_VCN_DEC:
 399                 type = AMD_IP_BLOCK_TYPE_VCN;
 400                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 401                         if (adev->uvd.harvest_config & (1 << i))
 402                                 continue;
 403
 404                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 405                                 ++num_rings;
 406                 }
 407                 ib_start_alignment = 16;
 408                 ib_size_alignment = 16;
 409                 break;
 410         case AMDGPU_HW_IP_VCN_ENC:
 411                 type = AMD_IP_BLOCK_TYPE_VCN;
 412                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 413                         if (adev->uvd.harvest_config & (1 << i))
 414                                 continue;
 415
 416                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 417                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 418                                         ++num_rings;
 419                 }
 420                 ib_start_alignment = 64;
 421                 ib_size_alignment = 1;
 422                 break;
 423         case AMDGPU_HW_IP_VCN_JPEG:
 424                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 425                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 426
 427                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 428                         if (adev->jpeg.harvest_config & (1 << i))
 429                                 continue;
 430
 431                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 432                                 ++num_rings;
 433                 }
 434                 ib_start_alignment = 16;
 435                 ib_size_alignment = 16;
 436                 break;
 437         default:
 438                 return -EINVAL;
 439         }
 440
 441         for (i = 0; i < adev->num_ip_blocks; i++)
 442                 if (adev->ip_blocks[i].version->type == type &&
 443                     adev->ip_blocks[i].status.valid)
 444                         break;
 445
 446         if (i == adev->num_ip_blocks)
 447                 return 0;
 448
 449         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 450                         num_rings);
 451
 452         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 453         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 454         result->capabilities_flags = 0;
 455         result->available_rings = (1 << num_rings) - 1;
 456         result->ib_start_alignment = ib_start_alignment;
 457         result->ib_size_alignment = ib_size_alignment;
 458         return 0;
 459 }
 460
 461 /*
 462  * Userspace get information ioctl
 463  */
 464 /**
 465  * amdgpu_info_ioctl - answer a device specific request.
 466  *
 467  * @adev: amdgpu device pointer
 468  * @data: request object
 469  * @filp: drm filp
 470  *
 471  * This function is used to pass device specific parameters to the userspace
 472  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 473  * etc. (all asics).
 474  * Returns 0 on success, -EINVAL on failure.
 475  */
 476 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 477 {
 478         struct amdgpu_device *adev = dev->dev_private;
 479         struct drm_amdgpu_info *info = data;
 480         struct amdgpu_mode_info *minfo = &adev->mode_info;
 481         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 482         uint32_t size = info->return_size;
 483         struct drm_crtc *crtc;
 484         uint32_t ui32 = 0;
 485         uint64_t ui64 = 0;
 486         int i, found;
 487         int ui32_size = sizeof(ui32);
 488
 489         if (!info->return_size || !info->return_pointer)
 490                 return -EINVAL;
 491
 492         switch (info->query) {
 493         case AMDGPU_INFO_ACCEL_WORKING:
 494                 ui32 = adev->accel_working;
 495                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 496         case AMDGPU_INFO_CRTC_FROM_ID:
 497                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 498                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 499                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 500                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 501                                 ui32 = amdgpu_crtc->crtc_id;
 502                                 found = 1;
 503                                 break;
 504                         }
 505                 }
 506                 if (!found) {
 507                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 508                         return -EINVAL;
 509                 }
 510                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 511         case AMDGPU_INFO_HW_IP_INFO: {
 512                 struct drm_amdgpu_info_hw_ip ip = {};
 513                 int ret;
 514
 515                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 516                 if (ret)
 517                         return ret;
 518
 519                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 520                 return ret ? -EFAULT : 0;
 521         }
 522         case AMDGPU_INFO_HW_IP_COUNT: {
 523                 enum amd_ip_block_type type;
 524                 uint32_t count = 0;
 525
 526                 switch (info->query_hw_ip.type) {
 527                 case AMDGPU_HW_IP_GFX:
 528                         type = AMD_IP_BLOCK_TYPE_GFX;
 529                         break;
 530                 case AMDGPU_HW_IP_COMPUTE:
 531                         type = AMD_IP_BLOCK_TYPE_GFX;
 532                         break;
 533                 case AMDGPU_HW_IP_DMA:
 534                         type = AMD_IP_BLOCK_TYPE_SDMA;
 535                         break;
 536                 case AMDGPU_HW_IP_UVD:
 537                         type = AMD_IP_BLOCK_TYPE_UVD;
 538                         break;
 539                 case AMDGPU_HW_IP_VCE:
 540                         type = AMD_IP_BLOCK_TYPE_VCE;
 541                         break;
 542                 case AMDGPU_HW_IP_UVD_ENC:
 543                         type = AMD_IP_BLOCK_TYPE_UVD;
 544                         break;
 545                 case AMDGPU_HW_IP_VCN_DEC:
 546                 case AMDGPU_HW_IP_VCN_ENC:
 547                         type = AMD_IP_BLOCK_TYPE_VCN;
 548                         break;
 549                 case AMDGPU_HW_IP_VCN_JPEG:
 550                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 551                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 552                         break;
 553                 default:
 554                         return -EINVAL;
 555                 }
 556
 557                 for (i = 0; i < adev->num_ip_blocks; i++)
 558                         if (adev->ip_blocks[i].version->type == type &&
 559                             adev->ip_blocks[i].status.valid &&
 560                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 561                                 count++;
 562
 563                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 564         }
 565         case AMDGPU_INFO_TIMESTAMP:
 566                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 567                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 568         case AMDGPU_INFO_FW_VERSION: {
 569                 struct drm_amdgpu_info_firmware fw_info;
 570                 int ret;
 571
 572                 /* We only support one instance of each IP block right now. */
 573                 if (info->query_fw.ip_instance != 0)
 574                         return -EINVAL;
 575
 576                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 577                 if (ret)
 578                         return ret;
 579
 580                 return copy_to_user(out, &fw_info,
 581                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 582         }
 583         case AMDGPU_INFO_NUM_BYTES_MOVED:
 584                 ui64 = atomic64_read(&adev->num_bytes_moved);
 585                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 586         case AMDGPU_INFO_NUM_EVICTIONS:
 587                 ui64 = atomic64_read(&adev->num_evictions);
 588                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 589         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 590                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 591                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 592         case AMDGPU_INFO_VRAM_USAGE:
 593                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 594                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 595         case AMDGPU_INFO_VIS_VRAM_USAGE:
 596                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 597                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 598         case AMDGPU_INFO_GTT_USAGE:
 599                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 600                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 601         case AMDGPU_INFO_GDS_CONFIG: {
 602                 struct drm_amdgpu_info_gds gds_info;
 603
 604                 memset(&gds_info, 0, sizeof(gds_info));
 605                 gds_info.compute_partition_size = adev->gds.gds_size;
 606                 gds_info.gds_total_size = adev->gds.gds_size;
 607                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 608                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 609                 return copy_to_user(out, &gds_info,
 610                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 611         }
 612         case AMDGPU_INFO_VRAM_GTT: {
 613                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 614
 615                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 616                         atomic64_read(&adev->vram_pin_size) -
 617                         AMDGPU_VM_RESERVED_VRAM;
 618                 vram_gtt.vram_cpu_accessible_size =
 619                         min(adev->gmc.visible_vram_size -
 620                             atomic64_read(&adev->visible_pin_size),
 621                             vram_gtt.vram_size);
 622                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 623                 vram_gtt.gtt_size *= PAGE_SIZE;
 624                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 625                 return copy_to_user(out, &vram_gtt,
 626                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 627         }
 628         case AMDGPU_INFO_MEMORY: {
 629                 struct drm_amdgpu_memory_info mem;
 630
 631                 memset(&mem, 0, sizeof(mem));
 632                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 633                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 634                         atomic64_read(&adev->vram_pin_size) -
 635                         AMDGPU_VM_RESERVED_VRAM;
 636                 mem.vram.heap_usage =
 637                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 638                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 639
 640                 mem.cpu_accessible_vram.total_heap_size =
 641                         adev->gmc.visible_vram_size;
 642                 mem.cpu_accessible_vram.usable_heap_size =
 643                         min(adev->gmc.visible_vram_size -
 644                             atomic64_read(&adev->visible_pin_size),
 645                             mem.vram.usable_heap_size);
 646                 mem.cpu_accessible_vram.heap_usage =
 647                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 648                 mem.cpu_accessible_vram.max_allocation =
 649                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 650
 651                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 652                 mem.gtt.total_heap_size *= PAGE_SIZE;
 653                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 654                         atomic64_read(&adev->gart_pin_size);
 655                 mem.gtt.heap_usage =
 656                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 657                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 658
 659                 return copy_to_user(out, &mem,
 660                                     min((size_t)size, sizeof(mem)))
 661                                     ? -EFAULT : 0;
 662         }
 663         case AMDGPU_INFO_READ_MMR_REG: {
 664                 unsigned n, alloc_size;
 665                 uint32_t *regs;
 666                 unsigned se_num = (info->read_mmr_reg.instance >>
 667                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 668                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 669                 unsigned sh_num = (info->read_mmr_reg.instance >>
 670                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 671                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 672
 673                 /* set full masks if the userspace set all bits
 674                  * in the bitfields */
 675                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 676                         se_num = 0xffffffff;
 677                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 678                         sh_num = 0xffffffff;
 679
 680                 if (info->read_mmr_reg.count > 128)
 681                         return -EINVAL;
 682
 683                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 684                 if (!regs)
 685                         return -ENOMEM;
 686                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 687
 688                 amdgpu_gfx_off_ctrl(adev, false);
 689                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 690                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 691                                                       info->read_mmr_reg.dword_offset + i,
 692                                                       &regs[i])) {
 693                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 694                                               info->read_mmr_reg.dword_offset + i);
 695                                 kfree(regs);
 696                                 amdgpu_gfx_off_ctrl(adev, true);
 697                                 return -EFAULT;
 698                         }
 699                 }
 700                 amdgpu_gfx_off_ctrl(adev, true);
 701                 n = copy_to_user(out, regs, min(size, alloc_size));
 702                 kfree(regs);
 703                 return n ? -EFAULT : 0;
 704         }
 705         case AMDGPU_INFO_DEV_INFO: {
 706                 struct drm_amdgpu_info_device dev_info = {};
 707                 uint64_t vm_size;
 708
 709                 dev_info.device_id = dev->pdev->device;
 710                 dev_info.chip_rev = adev->rev_id;
 711                 dev_info.external_rev = adev->external_rev_id;
 712                 dev_info.pci_rev = dev->pdev->revision;
 713                 dev_info.family = adev->family;
 714                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 715                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 716                 /* return all clocks in KHz */
 717                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 718                 if (adev->pm.dpm_enabled) {
 719                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 720                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 721                 } else {
 722                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 723                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 724                 }
 725                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 726                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 727                         adev->gfx.config.max_shader_engines;
 728                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 729                 dev_info._pad = 0;
 730                 dev_info.ids_flags = 0;
 731                 if (adev->flags & AMD_IS_APU)
 732                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 733                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 734                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 735
 736                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 737                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 738
 739                 /* Older VCE FW versions are buggy and can handle only 40bits */
 740                 if (adev->vce.fw_version &&
 741                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 742                         vm_size = min(vm_size, 1ULL << 40);
 743
 744                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 745                 dev_info.virtual_address_max =
 746                         min(vm_size, AMDGPU_GMC_HOLE_START);
 747
 748                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 749                         dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
 750                         dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 751                 }
 752                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 753                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 754                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 755                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 756                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 757                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 758                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 759                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 760                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 761                        sizeof(adev->gfx.cu_info.bitmap));
 762                 dev_info.vram_type = adev->gmc.vram_type;
 763                 dev_info.vram_bit_width = adev->gmc.vram_width;
 764                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 765                 dev_info.gc_double_offchip_lds_buf =
 766                         adev->gfx.config.double_offchip_lds_buf;
 767                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 768                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 769                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 770                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 771                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 772                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 773                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 774
 775                 if (adev->family >= AMDGPU_FAMILY_NV)
 776                         dev_info.pa_sc_tile_steering_override =
 777                                 adev->gfx.config.pa_sc_tile_steering_override;
 778
 779                 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 780
 781                 return copy_to_user(out, &dev_info,
 782                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 783         }
 784         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 785                 unsigned i;
 786                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 787                 struct amd_vce_state *vce_state;
 788
 789                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 790                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 791                         if (vce_state) {
 792                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 793                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 794                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 795                                 vce_clk_table.num_valid_entries++;
 796                         }
 797                 }
 798
 799                 return copy_to_user(out, &vce_clk_table,
 800                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 801         }
 802         case AMDGPU_INFO_VBIOS: {
 803                 uint32_t bios_size = adev->bios_size;
 804
 805                 switch (info->vbios_info.type) {
 806                 case AMDGPU_INFO_VBIOS_SIZE:
 807                         return copy_to_user(out, &bios_size,
 808                                         min((size_t)size, sizeof(bios_size)))
 809                                         ? -EFAULT : 0;
 810                 case AMDGPU_INFO_VBIOS_IMAGE: {
 811                         uint8_t *bios;
 812                         uint32_t bios_offset = info->vbios_info.offset;
 813
 814                         if (bios_offset >= bios_size)
 815                                 return -EINVAL;
 816
 817                         bios = adev->bios + bios_offset;
 818                         return copy_to_user(out, bios,
 819                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 820                                         ? -EFAULT : 0;
 821                 }
 822                 default:
 823                         DRM_DEBUG_KMS("Invalid request %d\n",
 824                                         info->vbios_info.type);
 825                         return -EINVAL;
 826                 }
 827         }
 828         case AMDGPU_INFO_NUM_HANDLES: {
 829                 struct drm_amdgpu_info_num_handles handle;
 830
 831                 switch (info->query_hw_ip.type) {
 832                 case AMDGPU_HW_IP_UVD:
 833                         /* Starting Polaris, we support unlimited UVD handles */
 834                         if (adev->asic_type < CHIP_POLARIS10) {
 835                                 handle.uvd_max_handles = adev->uvd.max_handles;
 836                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 837
 838                                 return copy_to_user(out, &handle,
 839                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 840                         } else {
 841                                 return -ENODATA;
 842                         }
 843
 844                         break;
 845                 default:
 846                         return -EINVAL;
 847                 }
 848         }
 849         case AMDGPU_INFO_SENSOR: {
 850                 if (!adev->pm.dpm_enabled)
 851                         return -ENOENT;
 852
 853                 switch (info->sensor_info.type) {
 854                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 855                         /* get sclk in Mhz */
 856                         if (amdgpu_dpm_read_sensor(adev,
 857                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 858                                                    (void *)&ui32, &ui32_size)) {
 859                                 return -EINVAL;
 860                         }
 861                         ui32 /= 100;
 862                         break;
 863                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 864                         /* get mclk in Mhz */
 865                         if (amdgpu_dpm_read_sensor(adev,
 866                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 867                                                    (void *)&ui32, &ui32_size)) {
 868                                 return -EINVAL;
 869                         }
 870                         ui32 /= 100;
 871                         break;
 872                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 873                         /* get temperature in millidegrees C */
 874                         if (amdgpu_dpm_read_sensor(adev,
 875                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 876                                                    (void *)&ui32, &ui32_size)) {
 877                                 return -EINVAL;
 878                         }
 879                         break;
 880                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 881                         /* get GPU load */
 882                         if (amdgpu_dpm_read_sensor(adev,
 883                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 884                                                    (void *)&ui32, &ui32_size)) {
 885                                 return -EINVAL;
 886                         }
 887                         break;
 888                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 889                         /* get average GPU power */
 890                         if (amdgpu_dpm_read_sensor(adev,
 891                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 892                                                    (void *)&ui32, &ui32_size)) {
 893                                 return -EINVAL;
 894                         }
 895                         ui32 >>= 8;
 896                         break;
 897                 case AMDGPU_INFO_SENSOR_VDDNB:
 898                         /* get VDDNB in millivolts */
 899                         if (amdgpu_dpm_read_sensor(adev,
 900                                                    AMDGPU_PP_SENSOR_VDDNB,
 901                                                    (void *)&ui32, &ui32_size)) {
 902                                 return -EINVAL;
 903                         }
 904                         break;
 905                 case AMDGPU_INFO_SENSOR_VDDGFX:
 906                         /* get VDDGFX in millivolts */
 907                         if (amdgpu_dpm_read_sensor(adev,
 908                                                    AMDGPU_PP_SENSOR_VDDGFX,
 909                                                    (void *)&ui32, &ui32_size)) {
 910                                 return -EINVAL;
 911                         }
 912                         break;
 913                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 914                         /* get stable pstate sclk in Mhz */
 915                         if (amdgpu_dpm_read_sensor(adev,
 916                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 917                                                    (void *)&ui32, &ui32_size)) {
 918                                 return -EINVAL;
 919                         }
 920                         ui32 /= 100;
 921                         break;
 922                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 923                         /* get stable pstate mclk in Mhz */
 924                         if (amdgpu_dpm_read_sensor(adev,
 925                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 926                                                    (void *)&ui32, &ui32_size)) {
 927                                 return -EINVAL;
 928                         }
 929                         ui32 /= 100;
 930                         break;
 931                 default:
 932                         DRM_DEBUG_KMS("Invalid request %d\n",
 933                                       info->sensor_info.type);
 934                         return -EINVAL;
 935                 }
 936                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 937         }
 938         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 939                 ui32 = atomic_read(&adev->vram_lost_counter);
 940                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 941         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 942                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 943                 uint64_t ras_mask;
 944
 945                 if (!ras)
 946                         return -EINVAL;
 947                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 948
 949                 return copy_to_user(out, &ras_mask,
 950                                 min_t(u64, size, sizeof(ras_mask))) ?
 951                         -EFAULT : 0;
 952         }
 953         default:
 954                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 955                 return -EINVAL;
 956         }
 957         return 0;
 958 }
 959
 960
 961 /*
 962  * Outdated mess for old drm with Xorg being in charge (void function now).
 963  */
 964 /**
 965  * amdgpu_driver_lastclose_kms - drm callback for last close
 966  *
 967  * @dev: drm dev pointer
 968  *
 969  * Switch vga_switcheroo state after last close (all asics).
 970  */
 971 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 972 {
 973         drm_fb_helper_lastclose(dev);
 974         vga_switcheroo_process_delayed_switch();
 975 }
 976
 977 /**
 978  * amdgpu_driver_open_kms - drm callback for open
 979  *
 980  * @dev: drm dev pointer
 981  * @file_priv: drm file
 982  *
 983  * On device open, init vm on cayman+ (all asics).
 984  * Returns 0 on success, error on failure.
 985  */
 986 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 987 {
 988         struct amdgpu_device *adev = dev->dev_private;
 989         struct amdgpu_fpriv *fpriv;
 990         int r, pasid;
 991
 992         /* Ensure IB tests are run on ring */
 993         flush_delayed_work(&adev->delayed_init_work);
 994
 995
 996         if (amdgpu_ras_intr_triggered()) {
 997                 DRM_ERROR("RAS Intr triggered, device disabled!!");
 998                 return -EHWPOISON;
 999         }
1000
1001         file_priv->driver_priv = NULL;
1002
1003         r = pm_runtime_get_sync(dev->dev);
1004         if (r < 0)
1005                 goto pm_put;
1006
1007         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1008         if (unlikely(!fpriv)) {
1009                 r = -ENOMEM;
1010                 goto out_suspend;
1011         }
1012
1013         pasid = amdgpu_pasid_alloc(16);
1014         if (pasid < 0) {
1015                 dev_warn(adev->dev, "No more PASIDs available!");
1016                 pasid = 0;
1017         }
1018         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1019         if (r)
1020                 goto error_pasid;
1021
1022         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1023         if (!fpriv->prt_va) {
1024                 r = -ENOMEM;
1025                 goto error_vm;
1026         }
1027
1028         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1029                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1030
1031                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1032                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1033                 if (r)
1034                         goto error_vm;
1035         }
1036
1037         mutex_init(&fpriv->bo_list_lock);
1038         idr_init(&fpriv->bo_list_handles);
1039
1040         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1041
1042         file_priv->driver_priv = fpriv;
1043         goto out_suspend;
1044
1045 error_vm:
1046         amdgpu_vm_fini(adev, &fpriv->vm);
1047
1048 error_pasid:
1049         if (pasid)
1050                 amdgpu_pasid_free(pasid);
1051
1052         kfree(fpriv);
1053
1054 out_suspend:
1055         pm_runtime_mark_last_busy(dev->dev);
1056 pm_put:
1057         pm_runtime_put_autosuspend(dev->dev);
1058
1059         return r;
1060 }
1061
1062 /**
1063  * amdgpu_driver_postclose_kms - drm callback for post close
1064  *
1065  * @dev: drm dev pointer
1066  * @file_priv: drm file
1067  *
1068  * On device post close, tear down vm on cayman+ (all asics).
1069  */
1070 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1071                                  struct drm_file *file_priv)
1072 {
1073         struct amdgpu_device *adev = dev->dev_private;
1074         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1075         struct amdgpu_bo_list *list;
1076         struct amdgpu_bo *pd;
1077         unsigned int pasid;
1078         int handle;
1079
1080         if (!fpriv)
1081                 return;
1082
1083         pm_runtime_get_sync(dev->dev);
1084
1085         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1086                 amdgpu_uvd_free_handles(adev, file_priv);
1087         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1088                 amdgpu_vce_free_handles(adev, file_priv);
1089
1090         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1091
1092         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1093                 /* TODO: how to handle reserve failure */
1094                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1095                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1096                 fpriv->csa_va = NULL;
1097                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1098         }
1099
1100         pasid = fpriv->vm.pasid;
1101         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1102
1103         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1104         amdgpu_vm_fini(adev, &fpriv->vm);
1105
1106         if (pasid)
1107                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1108         amdgpu_bo_unref(&pd);
1109
1110         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1111                 amdgpu_bo_list_put(list);
1112
1113         idr_destroy(&fpriv->bo_list_handles);
1114         mutex_destroy(&fpriv->bo_list_lock);
1115
1116         kfree(fpriv);
1117         file_priv->driver_priv = NULL;
1118
1119         pm_runtime_mark_last_busy(dev->dev);
1120         pm_runtime_put_autosuspend(dev->dev);
1121 }
1122
1123 /*
1124  * VBlank related functions.
1125  */
1126 /**
1127  * amdgpu_get_vblank_counter_kms - get frame count
1128  *
1129  * @crtc: crtc to get the frame count from
1130  *
1131  * Gets the frame count on the requested crtc (all asics).
1132  * Returns frame count on success, -EINVAL on failure.
1133  */
1134 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1135 {
1136         struct drm_device *dev = crtc->dev;
1137         unsigned int pipe = crtc->index;
1138         struct amdgpu_device *adev = dev->dev_private;
1139         int vpos, hpos, stat;
1140         u32 count;
1141
1142         if (pipe >= adev->mode_info.num_crtc) {
1143                 DRM_ERROR("Invalid crtc %u\n", pipe);
1144                 return -EINVAL;
1145         }
1146
1147         /* The hw increments its frame counter at start of vsync, not at start
1148          * of vblank, as is required by DRM core vblank counter handling.
1149          * Cook the hw count here to make it appear to the caller as if it
1150          * incremented at start of vblank. We measure distance to start of
1151          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1152          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1153          * result by 1 to give the proper appearance to caller.
1154          */
1155         if (adev->mode_info.crtcs[pipe]) {
1156                 /* Repeat readout if needed to provide stable result if
1157                  * we cross start of vsync during the queries.
1158                  */
1159                 do {
1160                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1161                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1162                          * vpos as distance to start of vblank, instead of
1163                          * regular vertical scanout pos.
1164                          */
1165                         stat = amdgpu_display_get_crtc_scanoutpos(
1166                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1167                                 &vpos, &hpos, NULL, NULL,
1168                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1169                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1170
1171                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1172                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1173                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1174                 } else {
1175                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1176                                       pipe, vpos);
1177
1178                         /* Bump counter if we are at >= leading edge of vblank,
1179                          * but before vsync where vpos would turn negative and
1180                          * the hw counter really increments.
1181                          */
1182                         if (vpos >= 0)
1183                                 count++;
1184                 }
1185         } else {
1186                 /* Fallback to use value as is. */
1187                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1188                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1189         }
1190
1191         return count;
1192 }
1193
1194 /**
1195  * amdgpu_enable_vblank_kms - enable vblank interrupt
1196  *
1197  * @crtc: crtc to enable vblank interrupt for
1198  *
1199  * Enable the interrupt on the requested crtc (all asics).
1200  * Returns 0 on success, -EINVAL on failure.
1201  */
1202 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1203 {
1204         struct drm_device *dev = crtc->dev;
1205         unsigned int pipe = crtc->index;
1206         struct amdgpu_device *adev = dev->dev_private;
1207         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1208
1209         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1210 }
1211
1212 /**
1213  * amdgpu_disable_vblank_kms - disable vblank interrupt
1214  *
1215  * @crtc: crtc to disable vblank interrupt for
1216  *
1217  * Disable the interrupt on the requested crtc (all asics).
1218  */
1219 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1220 {
1221         struct drm_device *dev = crtc->dev;
1222         unsigned int pipe = crtc->index;
1223         struct amdgpu_device *adev = dev->dev_private;
1224         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1225
1226         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1227 }
1228
1229 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1230         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1231         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1232         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1233         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1234         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1235         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1236         /* KMS */
1237         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1238         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1239         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1240         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1241         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1242         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1243         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1244         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1245         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1246         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1247 };
1248 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1249
1250 /*
1251  * Debugfs info
1252  */
1253 #if defined(CONFIG_DEBUG_FS)
1254
1255 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1256 {
1257         struct drm_info_node *node = (struct drm_info_node *) m->private;
1258         struct drm_device *dev = node->minor->dev;
1259         struct amdgpu_device *adev = dev->dev_private;
1260         struct drm_amdgpu_info_firmware fw_info;
1261         struct drm_amdgpu_query_fw query_fw;
1262         struct atom_context *ctx = adev->mode_info.atom_context;
1263         int ret, i;
1264
1265         /* VCE */
1266         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1267         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1268         if (ret)
1269                 return ret;
1270         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1271                    fw_info.feature, fw_info.ver);
1272
1273         /* UVD */
1274         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1275         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1276         if (ret)
1277                 return ret;
1278         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1279                    fw_info.feature, fw_info.ver);
1280
1281         /* GMC */
1282         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1283         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1284         if (ret)
1285                 return ret;
1286         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1287                    fw_info.feature, fw_info.ver);
1288
1289         /* ME */
1290         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1291         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1292         if (ret)
1293                 return ret;
1294         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1295                    fw_info.feature, fw_info.ver);
1296
1297         /* PFP */
1298         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1299         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1300         if (ret)
1301                 return ret;
1302         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1303                    fw_info.feature, fw_info.ver);
1304
1305         /* CE */
1306         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1307         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1308         if (ret)
1309                 return ret;
1310         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1311                    fw_info.feature, fw_info.ver);
1312
1313         /* RLC */
1314         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1315         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1316         if (ret)
1317                 return ret;
1318         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1319                    fw_info.feature, fw_info.ver);
1320
1321         /* RLC SAVE RESTORE LIST CNTL */
1322         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1323         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1324         if (ret)
1325                 return ret;
1326         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1327                    fw_info.feature, fw_info.ver);
1328
1329         /* RLC SAVE RESTORE LIST GPM MEM */
1330         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1331         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1332         if (ret)
1333                 return ret;
1334         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1335                    fw_info.feature, fw_info.ver);
1336
1337         /* RLC SAVE RESTORE LIST SRM MEM */
1338         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1339         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1340         if (ret)
1341                 return ret;
1342         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1343                    fw_info.feature, fw_info.ver);
1344
1345         /* MEC */
1346         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1347         query_fw.index = 0;
1348         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1349         if (ret)
1350                 return ret;
1351         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1352                    fw_info.feature, fw_info.ver);
1353
1354         /* MEC2 */
1355         if (adev->gfx.mec2_fw) {
1356                 query_fw.index = 1;
1357                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1358                 if (ret)
1359                         return ret;
1360                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1361                            fw_info.feature, fw_info.ver);
1362         }
1363
1364         /* PSP SOS */
1365         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1366         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1367         if (ret)
1368                 return ret;
1369         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1370                    fw_info.feature, fw_info.ver);
1371
1372
1373         /* PSP ASD */
1374         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1375         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1376         if (ret)
1377                 return ret;
1378         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1379                    fw_info.feature, fw_info.ver);
1380
1381         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1382         for (i = 0; i < 2; i++) {
1383                 query_fw.index = i;
1384                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1385                 if (ret)
1386                         continue;
1387                 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n",
1388                                 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver);
1389         }
1390
1391         /* SMC */
1392         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1393         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1394         if (ret)
1395                 return ret;
1396         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1397                    fw_info.feature, fw_info.ver);
1398
1399         /* SDMA */
1400         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1401         for (i = 0; i < adev->sdma.num_instances; i++) {
1402                 query_fw.index = i;
1403                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1404                 if (ret)
1405                         return ret;
1406                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1407                            i, fw_info.feature, fw_info.ver);
1408         }
1409
1410         /* VCN */
1411         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1412         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1413         if (ret)
1414                 return ret;
1415         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1416                    fw_info.feature, fw_info.ver);
1417
1418         /* DMCU */
1419         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1420         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1421         if (ret)
1422                 return ret;
1423         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1424                    fw_info.feature, fw_info.ver);
1425
1426         /* DMCUB */
1427         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1428         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1429         if (ret)
1430                 return ret;
1431         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1432                    fw_info.feature, fw_info.ver);
1433
1434
1435         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1436
1437         return 0;
1438 }
1439
1440 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1441         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1442 };
1443 #endif
1444
1445 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1446 {
1447 #if defined(CONFIG_DEBUG_FS)
1448         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1449                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1450 #else
1451         return 0;
1452 #endif
1453 }