drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_sched.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46
  47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  48 {
  49         struct amdgpu_gpu_instance *gpu_instance;
  50         int i;
  51
  52         mutex_lock(&mgpu_info.mutex);
  53
  54         for (i = 0; i < mgpu_info.num_gpu; i++) {
  55                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  56                 if (gpu_instance->adev == adev) {
  57                         mgpu_info.gpu_ins[i] =
  58                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  59                         mgpu_info.num_gpu--;
  60                         if (adev->flags & AMD_IS_APU)
  61                                 mgpu_info.num_apu--;
  62                         else
  63                                 mgpu_info.num_dgpu--;
  64                         break;
  65                 }
  66         }
  67
  68         mutex_unlock(&mgpu_info.mutex);
  69 }
  70
  71 /**
  72  * amdgpu_driver_unload_kms - Main unload function for KMS.
  73  *
  74  * @dev: drm dev pointer
  75  *
  76  * This is the main unload function for KMS (all asics).
  77  * Returns 0 on success.
  78  */
  79 void amdgpu_driver_unload_kms(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev == NULL)
  84                 return;
  85
  86         amdgpu_unregister_gpu_instance(adev);
  87
  88         if (adev->rmmio == NULL)
  89                 goto done_free;
  90
  91         if (amdgpu_sriov_vf(adev))
  92                 amdgpu_virt_request_full_gpu(adev, false);
  93
  94         if (amdgpu_device_is_px(dev)) {
  95                 pm_runtime_get_sync(dev->dev);
  96                 pm_runtime_forbid(dev->dev);
  97         }
  98
  99         amdgpu_acpi_fini(adev);
 100
 101         amdgpu_device_fini(adev);
 102
 103 done_free:
 104         kfree(adev);
 105         dev->dev_private = NULL;
 106 }
 107
 108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 109 {
 110         struct amdgpu_gpu_instance *gpu_instance;
 111
 112         mutex_lock(&mgpu_info.mutex);
 113
 114         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 115                 DRM_ERROR("Cannot register more gpu instance\n");
 116                 mutex_unlock(&mgpu_info.mutex);
 117                 return;
 118         }
 119
 120         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 121         gpu_instance->adev = adev;
 122         gpu_instance->mgpu_fan_enabled = 0;
 123
 124         mgpu_info.num_gpu++;
 125         if (adev->flags & AMD_IS_APU)
 126                 mgpu_info.num_apu++;
 127         else
 128                 mgpu_info.num_dgpu++;
 129
 130         mutex_unlock(&mgpu_info.mutex);
 131 }
 132
 133 /**
 134  * amdgpu_driver_load_kms - Main load function for KMS.
 135  *
 136  * @dev: drm dev pointer
 137  * @flags: device flags
 138  *
 139  * This is the main load function for KMS (all asics).
 140  * Returns 0 on success, error on failure.
 141  */
 142 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 143 {
 144         struct amdgpu_device *adev;
 145         int r, acpi_status;
 146
 147 #ifdef CONFIG_DRM_AMDGPU_SI
 148         if (!amdgpu_si_support) {
 149                 switch (flags & AMD_ASIC_MASK) {
 150                 case CHIP_TAHITI:
 151                 case CHIP_PITCAIRN:
 152                 case CHIP_VERDE:
 153                 case CHIP_OLAND:
 154                 case CHIP_HAINAN:
 155                         dev_info(dev->dev,
 156                                  "SI support provided by radeon.\n");
 157                         dev_info(dev->dev,
 158                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 159                                 );
 160                         return -ENODEV;
 161                 }
 162         }
 163 #endif
 164 #ifdef CONFIG_DRM_AMDGPU_CIK
 165         if (!amdgpu_cik_support) {
 166                 switch (flags & AMD_ASIC_MASK) {
 167                 case CHIP_KAVERI:
 168                 case CHIP_BONAIRE:
 169                 case CHIP_HAWAII:
 170                 case CHIP_KABINI:
 171                 case CHIP_MULLINS:
 172                         dev_info(dev->dev,
 173                                  "CIK support provided by radeon.\n");
 174                         dev_info(dev->dev,
 175                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 176                                 );
 177                         return -ENODEV;
 178                 }
 179         }
 180 #endif
 181
 182         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 183         if (adev == NULL) {
 184                 return -ENOMEM;
 185         }
 186         dev->dev_private = (void *)adev;
 187
 188         if ((amdgpu_runtime_pm != 0) &&
 189             amdgpu_has_atpx() &&
 190             (amdgpu_is_atpx_hybrid() ||
 191              amdgpu_has_atpx_dgpu_power_cntl()) &&
 192             ((flags & AMD_IS_APU) == 0) &&
 193             !pci_is_thunderbolt_attached(dev->pdev))
 194                 flags |= AMD_IS_PX;
 195
 196         /* amdgpu_device_init should report only fatal error
 197          * like memory allocation failure or iomapping failure,
 198          * or memory manager initialization failure, it must
 199          * properly initialize the GPU MC controller and permit
 200          * VRAM allocation
 201          */
 202         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 203         if (r) {
 204                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 205                 goto out;
 206         }
 207
 208         /* Call ACPI methods: require modeset init
 209          * but failure is not fatal
 210          */
 211         if (!r) {
 212                 acpi_status = amdgpu_acpi_init(adev);
 213                 if (acpi_status)
 214                         dev_dbg(&dev->pdev->dev,
 215                                 "Error during ACPI methods call\n");
 216         }
 217
 218         if (amdgpu_device_is_px(dev)) {
 219                 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
 220                 pm_runtime_use_autosuspend(dev->dev);
 221                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 222                 pm_runtime_set_active(dev->dev);
 223                 pm_runtime_allow(dev->dev);
 224                 pm_runtime_mark_last_busy(dev->dev);
 225                 pm_runtime_put_autosuspend(dev->dev);
 226         }
 227
 228         amdgpu_register_gpu_instance(adev);
 229 out:
 230         if (r) {
 231                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 232                 if (adev->rmmio && amdgpu_device_is_px(dev))
 233                         pm_runtime_put_noidle(dev->dev);
 234                 amdgpu_driver_unload_kms(dev);
 235         }
 236
 237         return r;
 238 }
 239
 240 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 241                                 struct drm_amdgpu_query_fw *query_fw,
 242                                 struct amdgpu_device *adev)
 243 {
 244         switch (query_fw->fw_type) {
 245         case AMDGPU_INFO_FW_VCE:
 246                 fw_info->ver = adev->vce.fw_version;
 247                 fw_info->feature = adev->vce.fb_version;
 248                 break;
 249         case AMDGPU_INFO_FW_UVD:
 250                 fw_info->ver = adev->uvd.fw_version;
 251                 fw_info->feature = 0;
 252                 break;
 253         case AMDGPU_INFO_FW_VCN:
 254                 fw_info->ver = adev->vcn.fw_version;
 255                 fw_info->feature = 0;
 256                 break;
 257         case AMDGPU_INFO_FW_GMC:
 258                 fw_info->ver = adev->gmc.fw_version;
 259                 fw_info->feature = 0;
 260                 break;
 261         case AMDGPU_INFO_FW_GFX_ME:
 262                 fw_info->ver = adev->gfx.me_fw_version;
 263                 fw_info->feature = adev->gfx.me_feature_version;
 264                 break;
 265         case AMDGPU_INFO_FW_GFX_PFP:
 266                 fw_info->ver = adev->gfx.pfp_fw_version;
 267                 fw_info->feature = adev->gfx.pfp_feature_version;
 268                 break;
 269         case AMDGPU_INFO_FW_GFX_CE:
 270                 fw_info->ver = adev->gfx.ce_fw_version;
 271                 fw_info->feature = adev->gfx.ce_feature_version;
 272                 break;
 273         case AMDGPU_INFO_FW_GFX_RLC:
 274                 fw_info->ver = adev->gfx.rlc_fw_version;
 275                 fw_info->feature = adev->gfx.rlc_feature_version;
 276                 break;
 277         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 278                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 279                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 280                 break;
 281         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 282                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 283                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 284                 break;
 285         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 286                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 287                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 288                 break;
 289         case AMDGPU_INFO_FW_GFX_MEC:
 290                 if (query_fw->index == 0) {
 291                         fw_info->ver = adev->gfx.mec_fw_version;
 292                         fw_info->feature = adev->gfx.mec_feature_version;
 293                 } else if (query_fw->index == 1) {
 294                         fw_info->ver = adev->gfx.mec2_fw_version;
 295                         fw_info->feature = adev->gfx.mec2_feature_version;
 296                 } else
 297                         return -EINVAL;
 298                 break;
 299         case AMDGPU_INFO_FW_SMC:
 300                 fw_info->ver = adev->pm.fw_version;
 301                 fw_info->feature = 0;
 302                 break;
 303         case AMDGPU_INFO_FW_TA:
 304                 if (query_fw->index > 1)
 305                         return -EINVAL;
 306                 if (query_fw->index == 0) {
 307                         fw_info->ver = adev->psp.ta_fw_version;
 308                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 309                 } else {
 310                         fw_info->ver = adev->psp.ta_fw_version;
 311                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 312                 }
 313                 break;
 314         case AMDGPU_INFO_FW_SDMA:
 315                 if (query_fw->index >= adev->sdma.num_instances)
 316                         return -EINVAL;
 317                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 318                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 319                 break;
 320         case AMDGPU_INFO_FW_SOS:
 321                 fw_info->ver = adev->psp.sos_fw_version;
 322                 fw_info->feature = adev->psp.sos_feature_version;
 323                 break;
 324         case AMDGPU_INFO_FW_ASD:
 325                 fw_info->ver = adev->psp.asd_fw_version;
 326                 fw_info->feature = adev->psp.asd_feature_version;
 327                 break;
 328         case AMDGPU_INFO_FW_DMCU:
 329                 fw_info->ver = adev->dm.dmcu_fw_version;
 330                 fw_info->feature = 0;
 331                 break;
 332         default:
 333                 return -EINVAL;
 334         }
 335         return 0;
 336 }
 337
 338 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 339                              struct drm_amdgpu_info *info,
 340                              struct drm_amdgpu_info_hw_ip *result)
 341 {
 342         uint32_t ib_start_alignment = 0;
 343         uint32_t ib_size_alignment = 0;
 344         enum amd_ip_block_type type;
 345         unsigned int num_rings = 0;
 346         unsigned int i, j;
 347
 348         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 349                 return -EINVAL;
 350
 351         switch (info->query_hw_ip.type) {
 352         case AMDGPU_HW_IP_GFX:
 353                 type = AMD_IP_BLOCK_TYPE_GFX;
 354                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 355                         if (adev->gfx.gfx_ring[i].sched.ready)
 356                                 ++num_rings;
 357                 ib_start_alignment = 32;
 358                 ib_size_alignment = 32;
 359                 break;
 360         case AMDGPU_HW_IP_COMPUTE:
 361                 type = AMD_IP_BLOCK_TYPE_GFX;
 362                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 363                         if (adev->gfx.compute_ring[i].sched.ready)
 364                                 ++num_rings;
 365                 ib_start_alignment = 32;
 366                 ib_size_alignment = 32;
 367                 break;
 368         case AMDGPU_HW_IP_DMA:
 369                 type = AMD_IP_BLOCK_TYPE_SDMA;
 370                 for (i = 0; i < adev->sdma.num_instances; i++)
 371                         if (adev->sdma.instance[i].ring.sched.ready)
 372                                 ++num_rings;
 373                 ib_start_alignment = 256;
 374                 ib_size_alignment = 4;
 375                 break;
 376         case AMDGPU_HW_IP_UVD:
 377                 type = AMD_IP_BLOCK_TYPE_UVD;
 378                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 379                         if (adev->uvd.harvest_config & (1 << i))
 380                                 continue;
 381
 382                         if (adev->uvd.inst[i].ring.sched.ready)
 383                                 ++num_rings;
 384                 }
 385                 ib_start_alignment = 64;
 386                 ib_size_alignment = 64;
 387                 break;
 388         case AMDGPU_HW_IP_VCE:
 389                 type = AMD_IP_BLOCK_TYPE_VCE;
 390                 for (i = 0; i < adev->vce.num_rings; i++)
 391                         if (adev->vce.ring[i].sched.ready)
 392                                 ++num_rings;
 393                 ib_start_alignment = 4;
 394                 ib_size_alignment = 1;
 395                 break;
 396         case AMDGPU_HW_IP_UVD_ENC:
 397                 type = AMD_IP_BLOCK_TYPE_UVD;
 398                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 399                         if (adev->uvd.harvest_config & (1 << i))
 400                                 continue;
 401
 402                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 403                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 404                                         ++num_rings;
 405                 }
 406                 ib_start_alignment = 64;
 407                 ib_size_alignment = 64;
 408                 break;
 409         case AMDGPU_HW_IP_VCN_DEC:
 410                 type = AMD_IP_BLOCK_TYPE_VCN;
 411                 if (adev->vcn.ring_dec.sched.ready)
 412                         ++num_rings;
 413                 ib_start_alignment = 16;
 414                 ib_size_alignment = 16;
 415                 break;
 416         case AMDGPU_HW_IP_VCN_ENC:
 417                 type = AMD_IP_BLOCK_TYPE_VCN;
 418                 for (i = 0; i < adev->vcn.num_enc_rings; i++)
 419                         if (adev->vcn.ring_enc[i].sched.ready)
 420                                 ++num_rings;
 421                 ib_start_alignment = 64;
 422                 ib_size_alignment = 1;
 423                 break;
 424         case AMDGPU_HW_IP_VCN_JPEG:
 425                 type = AMD_IP_BLOCK_TYPE_VCN;
 426                 if (adev->vcn.ring_jpeg.sched.ready)
 427                         ++num_rings;
 428                 ib_start_alignment = 16;
 429                 ib_size_alignment = 16;
 430                 break;
 431         default:
 432                 return -EINVAL;
 433         }
 434
 435         for (i = 0; i < adev->num_ip_blocks; i++)
 436                 if (adev->ip_blocks[i].version->type == type &&
 437                     adev->ip_blocks[i].status.valid)
 438                         break;
 439
 440         if (i == adev->num_ip_blocks)
 441                 return 0;
 442
 443         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 444                         num_rings);
 445
 446         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 447         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 448         result->capabilities_flags = 0;
 449         result->available_rings = (1 << num_rings) - 1;
 450         result->ib_start_alignment = ib_start_alignment;
 451         result->ib_size_alignment = ib_size_alignment;
 452         return 0;
 453 }
 454
 455 /*
 456  * Userspace get information ioctl
 457  */
 458 /**
 459  * amdgpu_info_ioctl - answer a device specific request.
 460  *
 461  * @adev: amdgpu device pointer
 462  * @data: request object
 463  * @filp: drm filp
 464  *
 465  * This function is used to pass device specific parameters to the userspace
 466  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 467  * etc. (all asics).
 468  * Returns 0 on success, -EINVAL on failure.
 469  */
 470 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 471 {
 472         struct amdgpu_device *adev = dev->dev_private;
 473         struct drm_amdgpu_info *info = data;
 474         struct amdgpu_mode_info *minfo = &adev->mode_info;
 475         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 476         uint32_t size = info->return_size;
 477         struct drm_crtc *crtc;
 478         uint32_t ui32 = 0;
 479         uint64_t ui64 = 0;
 480         int i, found;
 481         int ui32_size = sizeof(ui32);
 482
 483         if (!info->return_size || !info->return_pointer)
 484                 return -EINVAL;
 485
 486         switch (info->query) {
 487         case AMDGPU_INFO_ACCEL_WORKING:
 488                 ui32 = adev->accel_working;
 489                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 490         case AMDGPU_INFO_CRTC_FROM_ID:
 491                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 492                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 493                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 494                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 495                                 ui32 = amdgpu_crtc->crtc_id;
 496                                 found = 1;
 497                                 break;
 498                         }
 499                 }
 500                 if (!found) {
 501                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 502                         return -EINVAL;
 503                 }
 504                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 505         case AMDGPU_INFO_HW_IP_INFO: {
 506                 struct drm_amdgpu_info_hw_ip ip = {};
 507                 int ret;
 508
 509                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 510                 if (ret)
 511                         return ret;
 512
 513                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 514                 return ret ? -EFAULT : 0;
 515         }
 516         case AMDGPU_INFO_HW_IP_COUNT: {
 517                 enum amd_ip_block_type type;
 518                 uint32_t count = 0;
 519
 520                 switch (info->query_hw_ip.type) {
 521                 case AMDGPU_HW_IP_GFX:
 522                         type = AMD_IP_BLOCK_TYPE_GFX;
 523                         break;
 524                 case AMDGPU_HW_IP_COMPUTE:
 525                         type = AMD_IP_BLOCK_TYPE_GFX;
 526                         break;
 527                 case AMDGPU_HW_IP_DMA:
 528                         type = AMD_IP_BLOCK_TYPE_SDMA;
 529                         break;
 530                 case AMDGPU_HW_IP_UVD:
 531                         type = AMD_IP_BLOCK_TYPE_UVD;
 532                         break;
 533                 case AMDGPU_HW_IP_VCE:
 534                         type = AMD_IP_BLOCK_TYPE_VCE;
 535                         break;
 536                 case AMDGPU_HW_IP_UVD_ENC:
 537                         type = AMD_IP_BLOCK_TYPE_UVD;
 538                         break;
 539                 case AMDGPU_HW_IP_VCN_DEC:
 540                 case AMDGPU_HW_IP_VCN_ENC:
 541                 case AMDGPU_HW_IP_VCN_JPEG:
 542                         type = AMD_IP_BLOCK_TYPE_VCN;
 543                         break;
 544                 default:
 545                         return -EINVAL;
 546                 }
 547
 548                 for (i = 0; i < adev->num_ip_blocks; i++)
 549                         if (adev->ip_blocks[i].version->type == type &&
 550                             adev->ip_blocks[i].status.valid &&
 551                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 552                                 count++;
 553
 554                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 555         }
 556         case AMDGPU_INFO_TIMESTAMP:
 557                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 558                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 559         case AMDGPU_INFO_FW_VERSION: {
 560                 struct drm_amdgpu_info_firmware fw_info;
 561                 int ret;
 562
 563                 /* We only support one instance of each IP block right now. */
 564                 if (info->query_fw.ip_instance != 0)
 565                         return -EINVAL;
 566
 567                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 568                 if (ret)
 569                         return ret;
 570
 571                 return copy_to_user(out, &fw_info,
 572                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 573         }
 574         case AMDGPU_INFO_NUM_BYTES_MOVED:
 575                 ui64 = atomic64_read(&adev->num_bytes_moved);
 576                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 577         case AMDGPU_INFO_NUM_EVICTIONS:
 578                 ui64 = atomic64_read(&adev->num_evictions);
 579                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 580         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 581                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 582                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 583         case AMDGPU_INFO_VRAM_USAGE:
 584                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 585                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 586         case AMDGPU_INFO_VIS_VRAM_USAGE:
 587                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 588                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 589         case AMDGPU_INFO_GTT_USAGE:
 590                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 591                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 592         case AMDGPU_INFO_GDS_CONFIG: {
 593                 struct drm_amdgpu_info_gds gds_info;
 594
 595                 memset(&gds_info, 0, sizeof(gds_info));
 596                 gds_info.compute_partition_size = adev->gds.gds_size;
 597                 gds_info.gds_total_size = adev->gds.gds_size;
 598                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 599                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 600                 return copy_to_user(out, &gds_info,
 601                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 602         }
 603         case AMDGPU_INFO_VRAM_GTT: {
 604                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 605
 606                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 607                         atomic64_read(&adev->vram_pin_size);
 608                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 609                         atomic64_read(&adev->visible_pin_size);
 610                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 611                 vram_gtt.gtt_size *= PAGE_SIZE;
 612                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 613                 return copy_to_user(out, &vram_gtt,
 614                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 615         }
 616         case AMDGPU_INFO_MEMORY: {
 617                 struct drm_amdgpu_memory_info mem;
 618
 619                 memset(&mem, 0, sizeof(mem));
 620                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 621                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 622                         atomic64_read(&adev->vram_pin_size);
 623                 mem.vram.heap_usage =
 624                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 625                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 626
 627                 mem.cpu_accessible_vram.total_heap_size =
 628                         adev->gmc.visible_vram_size;
 629                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 630                         atomic64_read(&adev->visible_pin_size);
 631                 mem.cpu_accessible_vram.heap_usage =
 632                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 633                 mem.cpu_accessible_vram.max_allocation =
 634                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 635
 636                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 637                 mem.gtt.total_heap_size *= PAGE_SIZE;
 638                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 639                         atomic64_read(&adev->gart_pin_size);
 640                 mem.gtt.heap_usage =
 641                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 642                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 643
 644                 return copy_to_user(out, &mem,
 645                                     min((size_t)size, sizeof(mem)))
 646                                     ? -EFAULT : 0;
 647         }
 648         case AMDGPU_INFO_READ_MMR_REG: {
 649                 unsigned n, alloc_size;
 650                 uint32_t *regs;
 651                 unsigned se_num = (info->read_mmr_reg.instance >>
 652                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 653                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 654                 unsigned sh_num = (info->read_mmr_reg.instance >>
 655                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 656                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 657
 658                 /* set full masks if the userspace set all bits
 659                  * in the bitfields */
 660                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 661                         se_num = 0xffffffff;
 662                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 663                         sh_num = 0xffffffff;
 664
 665                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 666                 if (!regs)
 667                         return -ENOMEM;
 668                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 669
 670                 for (i = 0; i < info->read_mmr_reg.count; i++)
 671                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 672                                                       info->read_mmr_reg.dword_offset + i,
 673                                                       &regs[i])) {
 674                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 675                                               info->read_mmr_reg.dword_offset + i);
 676                                 kfree(regs);
 677                                 return -EFAULT;
 678                         }
 679                 n = copy_to_user(out, regs, min(size, alloc_size));
 680                 kfree(regs);
 681                 return n ? -EFAULT : 0;
 682         }
 683         case AMDGPU_INFO_DEV_INFO: {
 684                 struct drm_amdgpu_info_device dev_info = {};
 685                 uint64_t vm_size;
 686
 687                 dev_info.device_id = dev->pdev->device;
 688                 dev_info.chip_rev = adev->rev_id;
 689                 dev_info.external_rev = adev->external_rev_id;
 690                 dev_info.pci_rev = dev->pdev->revision;
 691                 dev_info.family = adev->family;
 692                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 693                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 694                 /* return all clocks in KHz */
 695                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 696                 if (adev->pm.dpm_enabled) {
 697                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 698                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 699                 } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 700                            adev->virt.ops->get_pp_clk) {
 701                         dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev, false) * 10;
 702                         dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev, false) * 10;
 703                 } else {
 704                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 705                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 706                 }
 707                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 708                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 709                         adev->gfx.config.max_shader_engines;
 710                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 711                 dev_info._pad = 0;
 712                 dev_info.ids_flags = 0;
 713                 if (adev->flags & AMD_IS_APU)
 714                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 715                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 716                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 717
 718                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 719                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 720
 721                 /* Older VCE FW versions are buggy and can handle only 40bits */
 722                 if (adev->vce.fw_version &&
 723                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 724                         vm_size = min(vm_size, 1ULL << 40);
 725
 726                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 727                 dev_info.virtual_address_max =
 728                         min(vm_size, AMDGPU_GMC_HOLE_START);
 729
 730                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 731                         dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
 732                         dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 733                 }
 734                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 735                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 736                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 737                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 738                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 739                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 740                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 741                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 742                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 743                        sizeof(adev->gfx.cu_info.bitmap));
 744                 dev_info.vram_type = adev->gmc.vram_type;
 745                 dev_info.vram_bit_width = adev->gmc.vram_width;
 746                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 747                 dev_info.gc_double_offchip_lds_buf =
 748                         adev->gfx.config.double_offchip_lds_buf;
 749
 750                 if (amdgpu_ngg) {
 751                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 752                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 753                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 754                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 755                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 756                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 757                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 758                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 759                 }
 760                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 761                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 762                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 763                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 764                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 765                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 766                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 767
 768                 if (adev->family >= AMDGPU_FAMILY_NV)
 769                         dev_info.pa_sc_tile_steering_override =
 770                                 adev->gfx.config.pa_sc_tile_steering_override;
 771
 772                 return copy_to_user(out, &dev_info,
 773                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 774         }
 775         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 776                 unsigned i;
 777                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 778                 struct amd_vce_state *vce_state;
 779
 780                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 781                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 782                         if (vce_state) {
 783                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 784                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 785                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 786                                 vce_clk_table.num_valid_entries++;
 787                         }
 788                 }
 789
 790                 return copy_to_user(out, &vce_clk_table,
 791                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 792         }
 793         case AMDGPU_INFO_VBIOS: {
 794                 uint32_t bios_size = adev->bios_size;
 795
 796                 switch (info->vbios_info.type) {
 797                 case AMDGPU_INFO_VBIOS_SIZE:
 798                         return copy_to_user(out, &bios_size,
 799                                         min((size_t)size, sizeof(bios_size)))
 800                                         ? -EFAULT : 0;
 801                 case AMDGPU_INFO_VBIOS_IMAGE: {
 802                         uint8_t *bios;
 803                         uint32_t bios_offset = info->vbios_info.offset;
 804
 805                         if (bios_offset >= bios_size)
 806                                 return -EINVAL;
 807
 808                         bios = adev->bios + bios_offset;
 809                         return copy_to_user(out, bios,
 810                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 811                                         ? -EFAULT : 0;
 812                 }
 813                 default:
 814                         DRM_DEBUG_KMS("Invalid request %d\n",
 815                                         info->vbios_info.type);
 816                         return -EINVAL;
 817                 }
 818         }
 819         case AMDGPU_INFO_NUM_HANDLES: {
 820                 struct drm_amdgpu_info_num_handles handle;
 821
 822                 switch (info->query_hw_ip.type) {
 823                 case AMDGPU_HW_IP_UVD:
 824                         /* Starting Polaris, we support unlimited UVD handles */
 825                         if (adev->asic_type < CHIP_POLARIS10) {
 826                                 handle.uvd_max_handles = adev->uvd.max_handles;
 827                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 828
 829                                 return copy_to_user(out, &handle,
 830                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 831                         } else {
 832                                 return -ENODATA;
 833                         }
 834
 835                         break;
 836                 default:
 837                         return -EINVAL;
 838                 }
 839         }
 840         case AMDGPU_INFO_SENSOR: {
 841                 if (!adev->pm.dpm_enabled)
 842                         return -ENOENT;
 843
 844                 switch (info->sensor_info.type) {
 845                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 846                         /* get sclk in Mhz */
 847                         if (amdgpu_dpm_read_sensor(adev,
 848                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 849                                                    (void *)&ui32, &ui32_size)) {
 850                                 return -EINVAL;
 851                         }
 852                         ui32 /= 100;
 853                         break;
 854                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 855                         /* get mclk in Mhz */
 856                         if (amdgpu_dpm_read_sensor(adev,
 857                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 858                                                    (void *)&ui32, &ui32_size)) {
 859                                 return -EINVAL;
 860                         }
 861                         ui32 /= 100;
 862                         break;
 863                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 864                         /* get temperature in millidegrees C */
 865                         if (amdgpu_dpm_read_sensor(adev,
 866                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 867                                                    (void *)&ui32, &ui32_size)) {
 868                                 return -EINVAL;
 869                         }
 870                         break;
 871                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 872                         /* get GPU load */
 873                         if (amdgpu_dpm_read_sensor(adev,
 874                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 875                                                    (void *)&ui32, &ui32_size)) {
 876                                 return -EINVAL;
 877                         }
 878                         break;
 879                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 880                         /* get average GPU power */
 881                         if (amdgpu_dpm_read_sensor(adev,
 882                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 883                                                    (void *)&ui32, &ui32_size)) {
 884                                 return -EINVAL;
 885                         }
 886                         ui32 >>= 8;
 887                         break;
 888                 case AMDGPU_INFO_SENSOR_VDDNB:
 889                         /* get VDDNB in millivolts */
 890                         if (amdgpu_dpm_read_sensor(adev,
 891                                                    AMDGPU_PP_SENSOR_VDDNB,
 892                                                    (void *)&ui32, &ui32_size)) {
 893                                 return -EINVAL;
 894                         }
 895                         break;
 896                 case AMDGPU_INFO_SENSOR_VDDGFX:
 897                         /* get VDDGFX in millivolts */
 898                         if (amdgpu_dpm_read_sensor(adev,
 899                                                    AMDGPU_PP_SENSOR_VDDGFX,
 900                                                    (void *)&ui32, &ui32_size)) {
 901                                 return -EINVAL;
 902                         }
 903                         break;
 904                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 905                         /* get stable pstate sclk in Mhz */
 906                         if (amdgpu_dpm_read_sensor(adev,
 907                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 908                                                    (void *)&ui32, &ui32_size)) {
 909                                 return -EINVAL;
 910                         }
 911                         ui32 /= 100;
 912                         break;
 913                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 914                         /* get stable pstate mclk in Mhz */
 915                         if (amdgpu_dpm_read_sensor(adev,
 916                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 917                                                    (void *)&ui32, &ui32_size)) {
 918                                 return -EINVAL;
 919                         }
 920                         ui32 /= 100;
 921                         break;
 922                 default:
 923                         DRM_DEBUG_KMS("Invalid request %d\n",
 924                                       info->sensor_info.type);
 925                         return -EINVAL;
 926                 }
 927                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 928         }
 929         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 930                 ui32 = atomic_read(&adev->vram_lost_counter);
 931                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 932         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 933                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 934                 uint64_t ras_mask;
 935
 936                 if (!ras)
 937                         return -EINVAL;
 938                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 939
 940                 return copy_to_user(out, &ras_mask,
 941                                 min_t(u64, size, sizeof(ras_mask))) ?
 942                         -EFAULT : 0;
 943         }
 944         default:
 945                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 946                 return -EINVAL;
 947         }
 948         return 0;
 949 }
 950
 951
 952 /*
 953  * Outdated mess for old drm with Xorg being in charge (void function now).
 954  */
 955 /**
 956  * amdgpu_driver_lastclose_kms - drm callback for last close
 957  *
 958  * @dev: drm dev pointer
 959  *
 960  * Switch vga_switcheroo state after last close (all asics).
 961  */
 962 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 963 {
 964         drm_fb_helper_lastclose(dev);
 965         vga_switcheroo_process_delayed_switch();
 966 }
 967
 968 /**
 969  * amdgpu_driver_open_kms - drm callback for open
 970  *
 971  * @dev: drm dev pointer
 972  * @file_priv: drm file
 973  *
 974  * On device open, init vm on cayman+ (all asics).
 975  * Returns 0 on success, error on failure.
 976  */
 977 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 978 {
 979         struct amdgpu_device *adev = dev->dev_private;
 980         struct amdgpu_fpriv *fpriv;
 981         int r, pasid;
 982
 983         /* Ensure IB tests are run on ring */
 984         flush_delayed_work(&adev->delayed_init_work);
 985
 986         file_priv->driver_priv = NULL;
 987
 988         r = pm_runtime_get_sync(dev->dev);
 989         if (r < 0)
 990                 return r;
 991
 992         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 993         if (unlikely(!fpriv)) {
 994                 r = -ENOMEM;
 995                 goto out_suspend;
 996         }
 997
 998         pasid = amdgpu_pasid_alloc(16);
 999         if (pasid < 0) {
1000                 dev_warn(adev->dev, "No more PASIDs available!");
1001                 pasid = 0;
1002         }
1003         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1004         if (r)
1005                 goto error_pasid;
1006
1007         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1008         if (!fpriv->prt_va) {
1009                 r = -ENOMEM;
1010                 goto error_vm;
1011         }
1012
1013         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1014                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1015
1016                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1017                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1018                 if (r)
1019                         goto error_vm;
1020         }
1021
1022         mutex_init(&fpriv->bo_list_lock);
1023         idr_init(&fpriv->bo_list_handles);
1024
1025         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1026
1027         file_priv->driver_priv = fpriv;
1028         goto out_suspend;
1029
1030 error_vm:
1031         amdgpu_vm_fini(adev, &fpriv->vm);
1032
1033 error_pasid:
1034         if (pasid)
1035                 amdgpu_pasid_free(pasid);
1036
1037         kfree(fpriv);
1038
1039 out_suspend:
1040         pm_runtime_mark_last_busy(dev->dev);
1041         pm_runtime_put_autosuspend(dev->dev);
1042
1043         return r;
1044 }
1045
1046 /**
1047  * amdgpu_driver_postclose_kms - drm callback for post close
1048  *
1049  * @dev: drm dev pointer
1050  * @file_priv: drm file
1051  *
1052  * On device post close, tear down vm on cayman+ (all asics).
1053  */
1054 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1055                                  struct drm_file *file_priv)
1056 {
1057         struct amdgpu_device *adev = dev->dev_private;
1058         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1059         struct amdgpu_bo_list *list;
1060         struct amdgpu_bo *pd;
1061         unsigned int pasid;
1062         int handle;
1063
1064         if (!fpriv)
1065                 return;
1066
1067         pm_runtime_get_sync(dev->dev);
1068
1069         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1070                 amdgpu_uvd_free_handles(adev, file_priv);
1071         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1072                 amdgpu_vce_free_handles(adev, file_priv);
1073
1074         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1075
1076         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1077                 /* TODO: how to handle reserve failure */
1078                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1079                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1080                 fpriv->csa_va = NULL;
1081                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1082         }
1083
1084         pasid = fpriv->vm.pasid;
1085         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1086
1087         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1088         amdgpu_vm_fini(adev, &fpriv->vm);
1089
1090         if (pasid)
1091                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
1092         amdgpu_bo_unref(&pd);
1093
1094         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1095                 amdgpu_bo_list_put(list);
1096
1097         idr_destroy(&fpriv->bo_list_handles);
1098         mutex_destroy(&fpriv->bo_list_lock);
1099
1100         kfree(fpriv);
1101         file_priv->driver_priv = NULL;
1102
1103         pm_runtime_mark_last_busy(dev->dev);
1104         pm_runtime_put_autosuspend(dev->dev);
1105 }
1106
1107 /*
1108  * VBlank related functions.
1109  */
1110 /**
1111  * amdgpu_get_vblank_counter_kms - get frame count
1112  *
1113  * @dev: drm dev pointer
1114  * @pipe: crtc to get the frame count from
1115  *
1116  * Gets the frame count on the requested crtc (all asics).
1117  * Returns frame count on success, -EINVAL on failure.
1118  */
1119 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1120 {
1121         struct amdgpu_device *adev = dev->dev_private;
1122         int vpos, hpos, stat;
1123         u32 count;
1124
1125         if (pipe >= adev->mode_info.num_crtc) {
1126                 DRM_ERROR("Invalid crtc %u\n", pipe);
1127                 return -EINVAL;
1128         }
1129
1130         /* The hw increments its frame counter at start of vsync, not at start
1131          * of vblank, as is required by DRM core vblank counter handling.
1132          * Cook the hw count here to make it appear to the caller as if it
1133          * incremented at start of vblank. We measure distance to start of
1134          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1135          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1136          * result by 1 to give the proper appearance to caller.
1137          */
1138         if (adev->mode_info.crtcs[pipe]) {
1139                 /* Repeat readout if needed to provide stable result if
1140                  * we cross start of vsync during the queries.
1141                  */
1142                 do {
1143                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1144                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1145                          * vpos as distance to start of vblank, instead of
1146                          * regular vertical scanout pos.
1147                          */
1148                         stat = amdgpu_display_get_crtc_scanoutpos(
1149                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1150                                 &vpos, &hpos, NULL, NULL,
1151                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1152                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1153
1154                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1155                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1156                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1157                 } else {
1158                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1159                                       pipe, vpos);
1160
1161                         /* Bump counter if we are at >= leading edge of vblank,
1162                          * but before vsync where vpos would turn negative and
1163                          * the hw counter really increments.
1164                          */
1165                         if (vpos >= 0)
1166                                 count++;
1167                 }
1168         } else {
1169                 /* Fallback to use value as is. */
1170                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1171                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1172         }
1173
1174         return count;
1175 }
1176
1177 /**
1178  * amdgpu_enable_vblank_kms - enable vblank interrupt
1179  *
1180  * @dev: drm dev pointer
1181  * @pipe: crtc to enable vblank interrupt for
1182  *
1183  * Enable the interrupt on the requested crtc (all asics).
1184  * Returns 0 on success, -EINVAL on failure.
1185  */
1186 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1187 {
1188         struct amdgpu_device *adev = dev->dev_private;
1189         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1190
1191         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1192 }
1193
1194 /**
1195  * amdgpu_disable_vblank_kms - disable vblank interrupt
1196  *
1197  * @dev: drm dev pointer
1198  * @pipe: crtc to disable vblank interrupt for
1199  *
1200  * Disable the interrupt on the requested crtc (all asics).
1201  */
1202 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1203 {
1204         struct amdgpu_device *adev = dev->dev_private;
1205         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1206
1207         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1208 }
1209
1210 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1211         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1212         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1213         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1214         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1215         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1216         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1217         /* KMS */
1218         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1219         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1220         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1221         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1222         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1223         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1224         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1225         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1226         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1227         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1228 };
1229 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1230
1231 /*
1232  * Debugfs info
1233  */
1234 #if defined(CONFIG_DEBUG_FS)
1235
1236 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1237 {
1238         struct drm_info_node *node = (struct drm_info_node *) m->private;
1239         struct drm_device *dev = node->minor->dev;
1240         struct amdgpu_device *adev = dev->dev_private;
1241         struct drm_amdgpu_info_firmware fw_info;
1242         struct drm_amdgpu_query_fw query_fw;
1243         struct atom_context *ctx = adev->mode_info.atom_context;
1244         int ret, i;
1245
1246         /* VCE */
1247         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1248         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1249         if (ret)
1250                 return ret;
1251         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1252                    fw_info.feature, fw_info.ver);
1253
1254         /* UVD */
1255         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1256         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1257         if (ret)
1258                 return ret;
1259         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1260                    fw_info.feature, fw_info.ver);
1261
1262         /* GMC */
1263         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1264         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1265         if (ret)
1266                 return ret;
1267         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1268                    fw_info.feature, fw_info.ver);
1269
1270         /* ME */
1271         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1272         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1273         if (ret)
1274                 return ret;
1275         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1276                    fw_info.feature, fw_info.ver);
1277
1278         /* PFP */
1279         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1280         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1281         if (ret)
1282                 return ret;
1283         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1284                    fw_info.feature, fw_info.ver);
1285
1286         /* CE */
1287         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1288         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1289         if (ret)
1290                 return ret;
1291         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1292                    fw_info.feature, fw_info.ver);
1293
1294         /* RLC */
1295         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1296         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1297         if (ret)
1298                 return ret;
1299         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1300                    fw_info.feature, fw_info.ver);
1301
1302         /* RLC SAVE RESTORE LIST CNTL */
1303         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1304         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1305         if (ret)
1306                 return ret;
1307         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1308                    fw_info.feature, fw_info.ver);
1309
1310         /* RLC SAVE RESTORE LIST GPM MEM */
1311         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1312         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1313         if (ret)
1314                 return ret;
1315         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1316                    fw_info.feature, fw_info.ver);
1317
1318         /* RLC SAVE RESTORE LIST SRM MEM */
1319         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1320         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1321         if (ret)
1322                 return ret;
1323         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1324                    fw_info.feature, fw_info.ver);
1325
1326         /* MEC */
1327         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1328         query_fw.index = 0;
1329         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1330         if (ret)
1331                 return ret;
1332         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1333                    fw_info.feature, fw_info.ver);
1334
1335         /* MEC2 */
1336         if (adev->asic_type == CHIP_KAVERI ||
1337             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1338                 query_fw.index = 1;
1339                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1340                 if (ret)
1341                         return ret;
1342                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1343                            fw_info.feature, fw_info.ver);
1344         }
1345
1346         /* PSP SOS */
1347         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1348         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1349         if (ret)
1350                 return ret;
1351         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1352                    fw_info.feature, fw_info.ver);
1353
1354
1355         /* PSP ASD */
1356         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1357         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1358         if (ret)
1359                 return ret;
1360         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1361                    fw_info.feature, fw_info.ver);
1362
1363         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1364         for (i = 0; i < 2; i++) {
1365                 query_fw.index = i;
1366                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1367                 if (ret)
1368                         continue;
1369                 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n",
1370                                 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver);
1371         }
1372
1373         /* SMC */
1374         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1375         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1376         if (ret)
1377                 return ret;
1378         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1379                    fw_info.feature, fw_info.ver);
1380
1381         /* SDMA */
1382         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1383         for (i = 0; i < adev->sdma.num_instances; i++) {
1384                 query_fw.index = i;
1385                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1386                 if (ret)
1387                         return ret;
1388                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1389                            i, fw_info.feature, fw_info.ver);
1390         }
1391
1392         /* VCN */
1393         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1394         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1395         if (ret)
1396                 return ret;
1397         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1398                    fw_info.feature, fw_info.ver);
1399
1400         /* DMCU */
1401         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1402         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1403         if (ret)
1404                 return ret;
1405         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1406                    fw_info.feature, fw_info.ver);
1407
1408
1409         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1410
1411         return 0;
1412 }
1413
1414 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1415         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1416 };
1417 #endif
1418
1419 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1420 {
1421 #if defined(CONFIG_DEBUG_FS)
1422         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1423                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1424 #else
1425         return 0;
1426 #endif
1427 }