2 * Copyright 2019 Advanced Micro Devices, Inc.
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28 #include "amdgpu_jpeg.h"
29 #include "amdgpu_pm.h"
31 #include "soc15_common.h"
33 #define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
35 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
37 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
39 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
40 mutex_init(&adev->jpeg.jpeg_pg_lock);
41 atomic_set(&adev->jpeg.total_submission_cnt, 0);
46 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
50 cancel_delayed_work_sync(&adev->jpeg.idle_work);
52 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
53 if (adev->jpeg.harvest_config & (1 << i))
56 amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec);
59 mutex_destroy(&adev->jpeg.jpeg_pg_lock);
64 int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
66 cancel_delayed_work_sync(&adev->jpeg.idle_work);
71 int amdgpu_jpeg_resume(struct amdgpu_device *adev)
76 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
78 struct amdgpu_device *adev =
79 container_of(work, struct amdgpu_device, jpeg.idle_work.work);
80 unsigned int fences = 0;
83 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
84 if (adev->jpeg.harvest_config & (1 << i))
87 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec);
90 if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
91 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
94 schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
97 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
99 struct amdgpu_device *adev = ring->adev;
101 atomic_inc(&adev->jpeg.total_submission_cnt);
102 cancel_delayed_work_sync(&adev->jpeg.idle_work);
104 mutex_lock(&adev->jpeg.jpeg_pg_lock);
105 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
106 AMD_PG_STATE_UNGATE);
107 mutex_unlock(&adev->jpeg.jpeg_pg_lock);
110 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
112 atomic_dec(&ring->adev->jpeg.total_submission_cnt);
113 schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
116 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
118 struct amdgpu_device *adev = ring->adev;
123 WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
124 r = amdgpu_ring_alloc(ring, 3);
128 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
129 amdgpu_ring_write(ring, 0xDEADBEEF);
130 amdgpu_ring_commit(ring);
132 for (i = 0; i < adev->usec_timeout; i++) {
133 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
134 if (tmp == 0xDEADBEEF)
139 if (i >= adev->usec_timeout)
145 static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
146 struct dma_fence **fence)
148 struct amdgpu_device *adev = ring->adev;
149 struct amdgpu_job *job;
150 struct amdgpu_ib *ib;
151 struct dma_fence *f = NULL;
152 const unsigned ib_size_dw = 16;
155 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
156 AMDGPU_IB_POOL_DIRECT, &job);
162 ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
163 ib->ptr[1] = 0xDEADBEEF;
164 for (i = 2; i < 16; i += 2) {
165 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
170 r = amdgpu_job_submit_direct(job, ring, &f);
175 *fence = dma_fence_get(f);
181 amdgpu_job_free(job);
185 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
187 struct amdgpu_device *adev = ring->adev;
190 struct dma_fence *fence = NULL;
193 r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
197 r = dma_fence_wait_timeout(fence, false, timeout);
207 for (i = 0; i < adev->usec_timeout; i++) {
208 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
209 if (tmp == 0xDEADBEEF)
214 if (i >= adev->usec_timeout)
217 dma_fence_put(fence);