drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/kthread.h>
  25 #include <linux/wait.h>
  26 #include <linux/sched.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_trace.h"
  30
  31 static void amdgpu_job_timedout(struct drm_sched_job *s_job)
  32 {
  33         struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
  34         struct amdgpu_job *job = to_amdgpu_job(s_job);
  35         struct amdgpu_task_info ti;
  36
  37         memset(&ti, 0, sizeof(struct amdgpu_task_info));
  38
  39         if (amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
  40                 DRM_ERROR("ring %s timeout, but soft recovered\n",
  41                           s_job->sched->name);
  42                 return;
  43         }
  44
  45         amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
  46         DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
  47                   job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
  48                   ring->fence_drv.sync_seq);
  49         DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
  50                   ti.process_name, ti.tgid, ti.task_name, ti.pid);
  51
  52         if (amdgpu_device_should_recover_gpu(ring->adev))
  53                 amdgpu_device_gpu_recover(ring->adev, job);
  54         else
  55                 drm_sched_suspend_timeout(&ring->sched);
  56 }
  57
  58 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
  59                      struct amdgpu_job **job, struct amdgpu_vm *vm)
  60 {
  61         size_t size = sizeof(struct amdgpu_job);
  62
  63         if (num_ibs == 0)
  64                 return -EINVAL;
  65
  66         size += sizeof(struct amdgpu_ib) * num_ibs;
  67
  68         *job = kzalloc(size, GFP_KERNEL);
  69         if (!*job)
  70                 return -ENOMEM;
  71
  72         /*
  73          * Initialize the scheduler to at least some ring so that we always
  74          * have a pointer to adev.
  75          */
  76         (*job)->base.sched = &adev->rings[0]->sched;
  77         (*job)->vm = vm;
  78         (*job)->ibs = (void *)&(*job)[1];
  79         (*job)->num_ibs = num_ibs;
  80
  81         amdgpu_sync_create(&(*job)->sync);
  82         amdgpu_sync_create(&(*job)->sched_sync);
  83         (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
  84         (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
  85
  86         return 0;
  87 }
  88
  89 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
  90                 enum amdgpu_ib_pool_type pool_type,
  91                 struct amdgpu_job **job)
  92 {
  93         int r;
  94
  95         r = amdgpu_job_alloc(adev, 1, job, NULL);
  96         if (r)
  97                 return r;
  98
  99         r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
 100         if (r)
 101                 kfree(*job);
 102
 103         return r;
 104 }
 105
 106 void amdgpu_job_free_resources(struct amdgpu_job *job)
 107 {
 108         struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
 109         struct dma_fence *f;
 110         unsigned i;
 111
 112         /* use sched fence if available */
 113         f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
 114
 115         for (i = 0; i < job->num_ibs; ++i)
 116                 amdgpu_ib_free(ring->adev, &job->ibs[i], f);
 117 }
 118
 119 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
 120 {
 121         struct amdgpu_job *job = to_amdgpu_job(s_job);
 122
 123         drm_sched_job_cleanup(s_job);
 124
 125         dma_fence_put(job->fence);
 126         amdgpu_sync_free(&job->sync);
 127         amdgpu_sync_free(&job->sched_sync);
 128         kfree(job);
 129 }
 130
 131 void amdgpu_job_free(struct amdgpu_job *job)
 132 {
 133         amdgpu_job_free_resources(job);
 134
 135         dma_fence_put(job->fence);
 136         amdgpu_sync_free(&job->sync);
 137         amdgpu_sync_free(&job->sched_sync);
 138         kfree(job);
 139 }
 140
 141 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
 142                       void *owner, struct dma_fence **f)
 143 {
 144         enum drm_sched_priority priority;
 145         int r;
 146
 147         if (!f)
 148                 return -EINVAL;
 149
 150         r = drm_sched_job_init(&job->base, entity, owner);
 151         if (r)
 152                 return r;
 153
 154         *f = dma_fence_get(&job->base.s_fence->finished);
 155         amdgpu_job_free_resources(job);
 156         priority = job->base.s_priority;
 157         drm_sched_entity_push_job(&job->base, entity);
 158
 159         return 0;
 160 }
 161
 162 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
 163                              struct dma_fence **fence)
 164 {
 165         int r;
 166
 167         job->base.sched = &ring->sched;
 168         r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence);
 169         job->fence = dma_fence_get(*fence);
 170         if (r)
 171                 return r;
 172
 173         amdgpu_job_free(job);
 174         return 0;
 175 }
 176
 177 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
 178                                                struct drm_sched_entity *s_entity)
 179 {
 180         struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
 181         struct amdgpu_job *job = to_amdgpu_job(sched_job);
 182         struct amdgpu_vm *vm = job->vm;
 183         struct dma_fence *fence;
 184         bool explicit = false;
 185         int r;
 186
 187         fence = amdgpu_sync_get_fence(&job->sync, &explicit);
 188         if (fence && explicit) {
 189                 if (drm_sched_dependency_optimized(fence, s_entity)) {
 190                         r = amdgpu_sync_fence(&job->sched_sync, fence, false);
 191                         if (r)
 192                                 DRM_ERROR("Error adding fence (%d)\n", r);
 193                 }
 194         }
 195
 196         while (fence == NULL && vm && !job->vmid) {
 197                 r = amdgpu_vmid_grab(vm, ring, &job->sync,
 198                                      &job->base.s_fence->finished,
 199                                      job);
 200                 if (r)
 201                         DRM_ERROR("Error getting VM ID (%d)\n", r);
 202
 203                 fence = amdgpu_sync_get_fence(&job->sync, NULL);
 204         }
 205
 206         return fence;
 207 }
 208
 209 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
 210 {
 211         struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
 212         struct dma_fence *fence = NULL, *finished;
 213         struct amdgpu_job *job;
 214         int r = 0;
 215
 216         job = to_amdgpu_job(sched_job);
 217         finished = &job->base.s_fence->finished;
 218
 219         BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
 220
 221         trace_amdgpu_sched_run_job(job);
 222
 223         if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter))
 224                 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
 225
 226         if (finished->error < 0) {
 227                 DRM_INFO("Skip scheduling IBs!\n");
 228         } else {
 229                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
 230                                        &fence);
 231                 if (r)
 232                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
 233         }
 234         /* if gpu reset, hw fence will be replaced here */
 235         dma_fence_put(job->fence);
 236         job->fence = dma_fence_get(fence);
 237
 238         amdgpu_job_free_resources(job);
 239
 240         fence = r ? ERR_PTR(r) : fence;
 241         return fence;
 242 }
 243
 244 #define to_drm_sched_job(sched_job)             \
 245                 container_of((sched_job), struct drm_sched_job, queue_node)
 246
 247 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
 248 {
 249         struct drm_sched_job *s_job;
 250         struct drm_sched_entity *s_entity = NULL;
 251         int i;
 252
 253         /* Signal all jobs not yet scheduled */
 254         for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
 255                 struct drm_sched_rq *rq = &sched->sched_rq[i];
 256
 257                 if (!rq)
 258                         continue;
 259
 260                 spin_lock(&rq->lock);
 261                 list_for_each_entry(s_entity, &rq->entities, list) {
 262                         while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
 263                                 struct drm_sched_fence *s_fence = s_job->s_fence;
 264
 265                                 dma_fence_signal(&s_fence->scheduled);
 266                                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 267                                 dma_fence_signal(&s_fence->finished);
 268                         }
 269                 }
 270                 spin_unlock(&rq->lock);
 271         }
 272
 273         /* Signal all jobs already scheduled to HW */
 274         list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
 275                 struct drm_sched_fence *s_fence = s_job->s_fence;
 276
 277                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 278                 dma_fence_signal(&s_fence->finished);
 279         }
 280 }
 281
 282 const struct drm_sched_backend_ops amdgpu_sched_ops = {
 283         .dependency = amdgpu_job_dependency,
 284         .run_job = amdgpu_job_run,
 285         .timedout_job = amdgpu_job_timedout,
 286         .free_job = amdgpu_job_free_cb
 287 };