2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 * DOC: Interrupt Handling
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
45 #include <linux/irq.h>
46 #include <linux/pci.h>
48 #include <drm/drm_crtc_helper.h>
49 #include <drm/drm_irq.h>
50 #include <drm/drm_vblank.h>
51 #include <drm/amdgpu_drm.h>
52 #include <drm/drm_drv.h>
54 #include "amdgpu_ih.h"
56 #include "amdgpu_connectors.h"
57 #include "amdgpu_trace.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_ras.h"
61 #include <linux/pm_runtime.h>
63 #ifdef CONFIG_DRM_AMD_DC
64 #include "amdgpu_dm_irq.h"
67 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
69 const char *soc15_ih_clientid_name[] = {
105 * amdgpu_hotplug_work_func - work handler for display hotplug event
107 * @work: work struct pointer
109 * This is the hotplug event work handler (all ASICs).
110 * The work gets scheduled from the IRQ handler if there
111 * was a hotplug interrupt. It walks through the connector table
112 * and calls hotplug handler for each connector. After this, it sends
113 * a DRM hotplug event to alert userspace.
115 * This design approach is required in order to defer hotplug event handling
116 * from the IRQ handler to a work handler because hotplug handler has to use
117 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
120 static void amdgpu_hotplug_work_func(struct work_struct *work)
122 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
124 struct drm_device *dev = adev_to_drm(adev);
125 struct drm_mode_config *mode_config = &dev->mode_config;
126 struct drm_connector *connector;
127 struct drm_connector_list_iter iter;
129 mutex_lock(&mode_config->mutex);
130 drm_connector_list_iter_begin(dev, &iter);
131 drm_for_each_connector_iter(connector, &iter)
132 amdgpu_connector_hotplug(connector);
133 drm_connector_list_iter_end(&iter);
134 mutex_unlock(&mode_config->mutex);
135 /* Just fire off a uevent and let userspace tell us what to do */
136 drm_helper_hpd_irq_event(dev);
140 * amdgpu_irq_disable_all - disable *all* interrupts
142 * @adev: amdgpu device pointer
144 * Disable all types of interrupts from all sources.
146 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
148 unsigned long irqflags;
152 spin_lock_irqsave(&adev->irq.lock, irqflags);
153 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
154 if (!adev->irq.client[i].sources)
157 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
158 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
160 if (!src || !src->funcs->set || !src->num_types)
163 for (k = 0; k < src->num_types; ++k) {
164 atomic_set(&src->enabled_types[k], 0);
165 r = src->funcs->set(adev, src, k,
166 AMDGPU_IRQ_STATE_DISABLE);
168 DRM_ERROR("error disabling interrupt (%d)\n",
173 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
177 * amdgpu_irq_handler - IRQ handler
179 * @irq: IRQ number (unused)
180 * @arg: pointer to DRM device
182 * IRQ handler for amdgpu driver (all ASICs).
185 * result of handling the IRQ, as defined by &irqreturn_t
187 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
189 struct drm_device *dev = (struct drm_device *) arg;
190 struct amdgpu_device *adev = drm_to_adev(dev);
193 ret = amdgpu_ih_process(adev, &adev->irq.ih);
194 if (ret == IRQ_HANDLED)
195 pm_runtime_mark_last_busy(dev->dev);
197 /* For the hardware that cannot enable bif ring for both ras_controller_irq
198 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
199 * register to check whether the interrupt is triggered or not, and properly
200 * ack the interrupt if it is there
202 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
203 if (adev->nbio.ras_funcs &&
204 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring)
205 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring(adev);
207 if (adev->nbio.ras_funcs &&
208 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring)
209 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
216 * amdgpu_irq_handle_ih1 - kick of processing for IH1
218 * @work: work structure in struct amdgpu_irq
220 * Kick of processing IH ring 1.
222 static void amdgpu_irq_handle_ih1(struct work_struct *work)
224 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
227 amdgpu_ih_process(adev, &adev->irq.ih1);
231 * amdgpu_irq_handle_ih2 - kick of processing for IH2
233 * @work: work structure in struct amdgpu_irq
235 * Kick of processing IH ring 2.
237 static void amdgpu_irq_handle_ih2(struct work_struct *work)
239 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
242 amdgpu_ih_process(adev, &adev->irq.ih2);
246 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft
248 * @work: work structure in struct amdgpu_irq
250 * Kick of processing IH soft ring.
252 static void amdgpu_irq_handle_ih_soft(struct work_struct *work)
254 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
257 amdgpu_ih_process(adev, &adev->irq.ih_soft);
261 * amdgpu_msi_ok - check whether MSI functionality is enabled
263 * @adev: amdgpu device pointer (unused)
265 * Checks whether MSI functionality has been disabled via module parameter
269 * *true* if MSIs are allowed to be enabled or *false* otherwise
271 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
275 else if (amdgpu_msi == 0)
282 * amdgpu_irq_init - initialize interrupt handling
284 * @adev: amdgpu device pointer
286 * Sets up work functions for hotplug and reset interrupts, enables MSI
287 * functionality, initializes vblank, hotplug and reset interrupt handling.
290 * 0 on success or error code on failure
292 int amdgpu_irq_init(struct amdgpu_device *adev)
296 spin_lock_init(&adev->irq.lock);
298 /* Enable MSI if not disabled by module parameter */
299 adev->irq.msi_enabled = false;
301 if (amdgpu_msi_ok(adev)) {
302 int nvec = pci_msix_vec_count(adev->pdev);
308 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
310 /* we only need one vector */
311 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
313 adev->irq.msi_enabled = true;
314 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
318 if (!amdgpu_device_has_dc_support(adev)) {
319 if (!adev->enable_virtual_display)
320 /* Disable vblank IRQs aggressively for power-saving */
321 /* XXX: can this be enabled for DC? */
322 adev_to_drm(adev)->vblank_disable_immediate = true;
324 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
329 INIT_WORK(&adev->hotplug_work,
330 amdgpu_hotplug_work_func);
333 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
334 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
335 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
337 adev->irq.installed = true;
338 /* Use vector 0 for MSI-X */
339 r = drm_irq_install(adev_to_drm(adev), pci_irq_vector(adev->pdev, 0));
341 adev->irq.installed = false;
342 if (!amdgpu_device_has_dc_support(adev))
343 flush_work(&adev->hotplug_work);
346 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
348 DRM_DEBUG("amdgpu: irq initialized.\n");
353 void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
355 if (adev->irq.installed) {
356 drm_irq_uninstall(&adev->ddev);
357 adev->irq.installed = false;
358 if (adev->irq.msi_enabled)
359 pci_free_irq_vectors(adev->pdev);
361 if (!amdgpu_device_has_dc_support(adev))
362 flush_work(&adev->hotplug_work);
365 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
366 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
367 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
368 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
372 * amdgpu_irq_fini - shut down interrupt handling
374 * @adev: amdgpu device pointer
376 * Tears down work functions for hotplug and reset interrupts, disables MSI
377 * functionality, shuts down vblank, hotplug and reset interrupt handling,
378 * turns off interrupts from all sources (all ASICs).
380 void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
384 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
385 if (!adev->irq.client[i].sources)
388 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
389 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
394 kfree(src->enabled_types);
395 src->enabled_types = NULL;
397 kfree(adev->irq.client[i].sources);
398 adev->irq.client[i].sources = NULL;
403 * amdgpu_irq_add_id - register IRQ source
405 * @adev: amdgpu device pointer
406 * @client_id: client id
408 * @source: IRQ source pointer
410 * Registers IRQ source on a client.
413 * 0 on success or error code otherwise
415 int amdgpu_irq_add_id(struct amdgpu_device *adev,
416 unsigned client_id, unsigned src_id,
417 struct amdgpu_irq_src *source)
419 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
422 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
428 if (!adev->irq.client[client_id].sources) {
429 adev->irq.client[client_id].sources =
430 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
431 sizeof(struct amdgpu_irq_src *),
433 if (!adev->irq.client[client_id].sources)
437 if (adev->irq.client[client_id].sources[src_id] != NULL)
440 if (source->num_types && !source->enabled_types) {
443 types = kcalloc(source->num_types, sizeof(atomic_t),
448 source->enabled_types = types;
451 adev->irq.client[client_id].sources[src_id] = source;
456 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
458 * @adev: amdgpu device pointer
459 * @ih: interrupt ring instance
461 * Dispatches IRQ to IP blocks.
463 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
464 struct amdgpu_ih_ring *ih)
466 u32 ring_index = ih->rptr >> 2;
467 struct amdgpu_iv_entry entry;
468 unsigned client_id, src_id;
469 struct amdgpu_irq_src *src;
470 bool handled = false;
474 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
475 amdgpu_ih_decode_iv(adev, &entry);
477 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
479 client_id = entry.client_id;
480 src_id = entry.src_id;
482 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
483 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
485 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
486 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
488 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
489 adev->irq.virq[src_id]) {
490 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
492 } else if (!adev->irq.client[client_id].sources) {
493 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
496 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
497 r = src->funcs->process(adev, src, &entry);
499 DRM_ERROR("error processing interrupt (%d)\n", r);
504 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
507 /* Send it to amdkfd as well if it isn't already handled */
509 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
513 * amdgpu_irq_delegate - delegate IV to soft IH ring
515 * @adev: amdgpu device pointer
517 * @num_dw: size of IV
519 * Delegate the IV to the soft IH ring and schedule processing of it. Used
520 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.
522 void amdgpu_irq_delegate(struct amdgpu_device *adev,
523 struct amdgpu_iv_entry *entry,
526 amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw);
527 schedule_work(&adev->irq.ih_soft_work);
531 * amdgpu_irq_update - update hardware interrupt state
533 * @adev: amdgpu device pointer
534 * @src: interrupt source pointer
535 * @type: type of interrupt
537 * Updates interrupt state for the specific source (all ASICs).
539 int amdgpu_irq_update(struct amdgpu_device *adev,
540 struct amdgpu_irq_src *src, unsigned type)
542 unsigned long irqflags;
543 enum amdgpu_interrupt_state state;
546 spin_lock_irqsave(&adev->irq.lock, irqflags);
548 /* We need to determine after taking the lock, otherwise
549 we might disable just enabled interrupts again */
550 if (amdgpu_irq_enabled(adev, src, type))
551 state = AMDGPU_IRQ_STATE_ENABLE;
553 state = AMDGPU_IRQ_STATE_DISABLE;
555 r = src->funcs->set(adev, src, type, state);
556 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
561 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
563 * @adev: amdgpu device pointer
565 * Updates state of all types of interrupts on all sources on resume after
568 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
572 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
573 if (!adev->irq.client[i].sources)
576 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
577 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
579 if (!src || !src->funcs || !src->funcs->set)
581 for (k = 0; k < src->num_types; k++)
582 amdgpu_irq_update(adev, src, k);
588 * amdgpu_irq_get - enable interrupt
590 * @adev: amdgpu device pointer
591 * @src: interrupt source pointer
592 * @type: type of interrupt
594 * Enables specified type of interrupt on the specified source (all ASICs).
597 * 0 on success or error code otherwise
599 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
602 if (!adev_to_drm(adev)->irq_enabled)
605 if (type >= src->num_types)
608 if (!src->enabled_types || !src->funcs->set)
611 if (atomic_inc_return(&src->enabled_types[type]) == 1)
612 return amdgpu_irq_update(adev, src, type);
618 * amdgpu_irq_put - disable interrupt
620 * @adev: amdgpu device pointer
621 * @src: interrupt source pointer
622 * @type: type of interrupt
624 * Enables specified type of interrupt on the specified source (all ASICs).
627 * 0 on success or error code otherwise
629 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
632 if (!adev_to_drm(adev)->irq_enabled)
635 if (type >= src->num_types)
638 if (!src->enabled_types || !src->funcs->set)
641 if (atomic_dec_and_test(&src->enabled_types[type]))
642 return amdgpu_irq_update(adev, src, type);
648 * amdgpu_irq_enabled - check whether interrupt is enabled or not
650 * @adev: amdgpu device pointer
651 * @src: interrupt source pointer
652 * @type: type of interrupt
654 * Checks whether the given type of interrupt is enabled on the given source.
657 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
660 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
663 if (!adev_to_drm(adev)->irq_enabled)
666 if (type >= src->num_types)
669 if (!src->enabled_types || !src->funcs->set)
672 return !!atomic_read(&src->enabled_types[type]);
675 /* XXX: Generic IRQ handling */
676 static void amdgpu_irq_mask(struct irq_data *irqd)
681 static void amdgpu_irq_unmask(struct irq_data *irqd)
686 /* amdgpu hardware interrupt chip descriptor */
687 static struct irq_chip amdgpu_irq_chip = {
689 .irq_mask = amdgpu_irq_mask,
690 .irq_unmask = amdgpu_irq_unmask,
694 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
696 * @d: amdgpu IRQ domain pointer (unused)
697 * @irq: virtual IRQ number
698 * @hwirq: hardware irq number
700 * Current implementation assigns simple interrupt handler to the given virtual
704 * 0 on success or error code otherwise
706 static int amdgpu_irqdomain_map(struct irq_domain *d,
707 unsigned int irq, irq_hw_number_t hwirq)
709 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
712 irq_set_chip_and_handler(irq,
713 &amdgpu_irq_chip, handle_simple_irq);
717 /* Implementation of methods for amdgpu IRQ domain */
718 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
719 .map = amdgpu_irqdomain_map,
723 * amdgpu_irq_add_domain - create a linear IRQ domain
725 * @adev: amdgpu device pointer
727 * Creates an IRQ domain for GPU interrupt sources
728 * that may be driven by another driver (e.g., ACP).
731 * 0 on success or error code otherwise
733 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
735 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
736 &amdgpu_hw_irqdomain_ops, adev);
737 if (!adev->irq.domain) {
738 DRM_ERROR("GPU irq add domain failed\n");
746 * amdgpu_irq_remove_domain - remove the IRQ domain
748 * @adev: amdgpu device pointer
750 * Removes the IRQ domain for GPU interrupt sources
751 * that may be driven by another driver (e.g., ACP).
753 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
755 if (adev->irq.domain) {
756 irq_domain_remove(adev->irq.domain);
757 adev->irq.domain = NULL;
762 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
764 * @adev: amdgpu device pointer
765 * @src_id: IH source id
767 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
768 * Use this for components that generate a GPU interrupt, but are driven
769 * by a different driver (e.g., ACP).
774 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
776 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
778 return adev->irq.virq[src_id];