2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 * DOC: Interrupt Handling
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
45 #include <linux/irq.h>
46 #include <linux/pci.h>
48 #include <drm/drm_crtc_helper.h>
49 #include <drm/drm_irq.h>
50 #include <drm/drm_vblank.h>
51 #include <drm/amdgpu_drm.h>
53 #include "amdgpu_ih.h"
55 #include "amdgpu_connectors.h"
56 #include "amdgpu_trace.h"
57 #include "amdgpu_amdkfd.h"
58 #include "amdgpu_ras.h"
60 #include <linux/pm_runtime.h>
62 #ifdef CONFIG_DRM_AMD_DC
63 #include "amdgpu_dm_irq.h"
66 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
68 const char *soc15_ih_clientid_name[] = {
104 * amdgpu_hotplug_work_func - work handler for display hotplug event
106 * @work: work struct pointer
108 * This is the hotplug event work handler (all ASICs).
109 * The work gets scheduled from the IRQ handler if there
110 * was a hotplug interrupt. It walks through the connector table
111 * and calls hotplug handler for each connector. After this, it sends
112 * a DRM hotplug event to alert userspace.
114 * This design approach is required in order to defer hotplug event handling
115 * from the IRQ handler to a work handler because hotplug handler has to use
116 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
119 static void amdgpu_hotplug_work_func(struct work_struct *work)
121 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
123 struct drm_device *dev = adev_to_drm(adev);
124 struct drm_mode_config *mode_config = &dev->mode_config;
125 struct drm_connector *connector;
126 struct drm_connector_list_iter iter;
128 mutex_lock(&mode_config->mutex);
129 drm_connector_list_iter_begin(dev, &iter);
130 drm_for_each_connector_iter(connector, &iter)
131 amdgpu_connector_hotplug(connector);
132 drm_connector_list_iter_end(&iter);
133 mutex_unlock(&mode_config->mutex);
134 /* Just fire off a uevent and let userspace tell us what to do */
135 drm_helper_hpd_irq_event(dev);
139 * amdgpu_irq_disable_all - disable *all* interrupts
141 * @adev: amdgpu device pointer
143 * Disable all types of interrupts from all sources.
145 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
147 unsigned long irqflags;
151 spin_lock_irqsave(&adev->irq.lock, irqflags);
152 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
153 if (!adev->irq.client[i].sources)
156 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
157 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
159 if (!src || !src->funcs->set || !src->num_types)
162 for (k = 0; k < src->num_types; ++k) {
163 atomic_set(&src->enabled_types[k], 0);
164 r = src->funcs->set(adev, src, k,
165 AMDGPU_IRQ_STATE_DISABLE);
167 DRM_ERROR("error disabling interrupt (%d)\n",
172 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
176 * amdgpu_irq_handler - IRQ handler
178 * @irq: IRQ number (unused)
179 * @arg: pointer to DRM device
181 * IRQ handler for amdgpu driver (all ASICs).
184 * result of handling the IRQ, as defined by &irqreturn_t
186 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
188 struct drm_device *dev = (struct drm_device *) arg;
189 struct amdgpu_device *adev = drm_to_adev(dev);
192 ret = amdgpu_ih_process(adev, &adev->irq.ih);
193 if (ret == IRQ_HANDLED)
194 pm_runtime_mark_last_busy(dev->dev);
196 /* For the hardware that cannot enable bif ring for both ras_controller_irq
197 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
198 * register to check whether the interrupt is triggered or not, and properly
199 * ack the interrupt if it is there
201 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
202 if (adev->nbio.ras_funcs &&
203 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring)
204 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring(adev);
206 if (adev->nbio.ras_funcs &&
207 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring)
208 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
215 * amdgpu_irq_handle_ih1 - kick of processing for IH1
217 * @work: work structure in struct amdgpu_irq
219 * Kick of processing IH ring 1.
221 static void amdgpu_irq_handle_ih1(struct work_struct *work)
223 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
226 amdgpu_ih_process(adev, &adev->irq.ih1);
230 * amdgpu_irq_handle_ih2 - kick of processing for IH2
232 * @work: work structure in struct amdgpu_irq
234 * Kick of processing IH ring 2.
236 static void amdgpu_irq_handle_ih2(struct work_struct *work)
238 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
241 amdgpu_ih_process(adev, &adev->irq.ih2);
245 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft
247 * @work: work structure in struct amdgpu_irq
249 * Kick of processing IH soft ring.
251 static void amdgpu_irq_handle_ih_soft(struct work_struct *work)
253 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
256 amdgpu_ih_process(adev, &adev->irq.ih_soft);
260 * amdgpu_msi_ok - check whether MSI functionality is enabled
262 * @adev: amdgpu device pointer (unused)
264 * Checks whether MSI functionality has been disabled via module parameter
268 * *true* if MSIs are allowed to be enabled or *false* otherwise
270 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
274 else if (amdgpu_msi == 0)
281 * amdgpu_irq_init - initialize interrupt handling
283 * @adev: amdgpu device pointer
285 * Sets up work functions for hotplug and reset interrupts, enables MSI
286 * functionality, initializes vblank, hotplug and reset interrupt handling.
289 * 0 on success or error code on failure
291 int amdgpu_irq_init(struct amdgpu_device *adev)
295 spin_lock_init(&adev->irq.lock);
297 /* Enable MSI if not disabled by module parameter */
298 adev->irq.msi_enabled = false;
300 if (amdgpu_msi_ok(adev)) {
301 int nvec = pci_msix_vec_count(adev->pdev);
307 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
309 /* we only need one vector */
310 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
312 adev->irq.msi_enabled = true;
313 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
317 if (!amdgpu_device_has_dc_support(adev)) {
318 if (!adev->enable_virtual_display)
319 /* Disable vblank IRQs aggressively for power-saving */
320 /* XXX: can this be enabled for DC? */
321 adev_to_drm(adev)->vblank_disable_immediate = true;
323 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
328 INIT_WORK(&adev->hotplug_work,
329 amdgpu_hotplug_work_func);
332 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
333 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
334 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
336 adev->irq.installed = true;
337 /* Use vector 0 for MSI-X */
338 r = drm_irq_install(adev_to_drm(adev), pci_irq_vector(adev->pdev, 0));
340 adev->irq.installed = false;
341 if (!amdgpu_device_has_dc_support(adev))
342 flush_work(&adev->hotplug_work);
345 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
347 DRM_DEBUG("amdgpu: irq initialized.\n");
352 * amdgpu_irq_fini - shut down interrupt handling
354 * @adev: amdgpu device pointer
356 * Tears down work functions for hotplug and reset interrupts, disables MSI
357 * functionality, shuts down vblank, hotplug and reset interrupt handling,
358 * turns off interrupts from all sources (all ASICs).
360 void amdgpu_irq_fini(struct amdgpu_device *adev)
364 if (adev->irq.installed) {
365 drm_irq_uninstall(adev_to_drm(adev));
366 adev->irq.installed = false;
367 if (adev->irq.msi_enabled)
368 pci_free_irq_vectors(adev->pdev);
369 if (!amdgpu_device_has_dc_support(adev))
370 flush_work(&adev->hotplug_work);
373 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
374 if (!adev->irq.client[i].sources)
377 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
378 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
383 kfree(src->enabled_types);
384 src->enabled_types = NULL;
386 kfree(adev->irq.client[i].sources);
387 adev->irq.client[i].sources = NULL;
392 * amdgpu_irq_add_id - register IRQ source
394 * @adev: amdgpu device pointer
395 * @client_id: client id
397 * @source: IRQ source pointer
399 * Registers IRQ source on a client.
402 * 0 on success or error code otherwise
404 int amdgpu_irq_add_id(struct amdgpu_device *adev,
405 unsigned client_id, unsigned src_id,
406 struct amdgpu_irq_src *source)
408 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
411 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
417 if (!adev->irq.client[client_id].sources) {
418 adev->irq.client[client_id].sources =
419 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
420 sizeof(struct amdgpu_irq_src *),
422 if (!adev->irq.client[client_id].sources)
426 if (adev->irq.client[client_id].sources[src_id] != NULL)
429 if (source->num_types && !source->enabled_types) {
432 types = kcalloc(source->num_types, sizeof(atomic_t),
437 source->enabled_types = types;
440 adev->irq.client[client_id].sources[src_id] = source;
445 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
447 * @adev: amdgpu device pointer
448 * @ih: interrupt ring instance
450 * Dispatches IRQ to IP blocks.
452 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
453 struct amdgpu_ih_ring *ih)
455 u32 ring_index = ih->rptr >> 2;
456 struct amdgpu_iv_entry entry;
457 unsigned client_id, src_id;
458 struct amdgpu_irq_src *src;
459 bool handled = false;
463 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
464 amdgpu_ih_decode_iv(adev, &entry);
466 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
468 client_id = entry.client_id;
469 src_id = entry.src_id;
471 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
472 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
474 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
475 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
477 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
478 adev->irq.virq[src_id]) {
479 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
481 } else if (!adev->irq.client[client_id].sources) {
482 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
485 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
486 r = src->funcs->process(adev, src, &entry);
488 DRM_ERROR("error processing interrupt (%d)\n", r);
493 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
496 /* Send it to amdkfd as well if it isn't already handled */
498 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
502 * amdgpu_irq_delegate - delegate IV to soft IH ring
504 * @adev: amdgpu device pointer
506 * @num_dw: size of IV
508 * Delegate the IV to the soft IH ring and schedule processing of it. Used
509 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.
511 void amdgpu_irq_delegate(struct amdgpu_device *adev,
512 struct amdgpu_iv_entry *entry,
515 amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw);
516 schedule_work(&adev->irq.ih_soft_work);
520 * amdgpu_irq_update - update hardware interrupt state
522 * @adev: amdgpu device pointer
523 * @src: interrupt source pointer
524 * @type: type of interrupt
526 * Updates interrupt state for the specific source (all ASICs).
528 int amdgpu_irq_update(struct amdgpu_device *adev,
529 struct amdgpu_irq_src *src, unsigned type)
531 unsigned long irqflags;
532 enum amdgpu_interrupt_state state;
535 spin_lock_irqsave(&adev->irq.lock, irqflags);
537 /* We need to determine after taking the lock, otherwise
538 we might disable just enabled interrupts again */
539 if (amdgpu_irq_enabled(adev, src, type))
540 state = AMDGPU_IRQ_STATE_ENABLE;
542 state = AMDGPU_IRQ_STATE_DISABLE;
544 r = src->funcs->set(adev, src, type, state);
545 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
550 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
552 * @adev: amdgpu device pointer
554 * Updates state of all types of interrupts on all sources on resume after
557 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
561 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
562 if (!adev->irq.client[i].sources)
565 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
566 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
568 if (!src || !src->funcs || !src->funcs->set)
570 for (k = 0; k < src->num_types; k++)
571 amdgpu_irq_update(adev, src, k);
577 * amdgpu_irq_get - enable interrupt
579 * @adev: amdgpu device pointer
580 * @src: interrupt source pointer
581 * @type: type of interrupt
583 * Enables specified type of interrupt on the specified source (all ASICs).
586 * 0 on success or error code otherwise
588 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
591 if (!adev_to_drm(adev)->irq_enabled)
594 if (type >= src->num_types)
597 if (!src->enabled_types || !src->funcs->set)
600 if (atomic_inc_return(&src->enabled_types[type]) == 1)
601 return amdgpu_irq_update(adev, src, type);
607 * amdgpu_irq_put - disable interrupt
609 * @adev: amdgpu device pointer
610 * @src: interrupt source pointer
611 * @type: type of interrupt
613 * Enables specified type of interrupt on the specified source (all ASICs).
616 * 0 on success or error code otherwise
618 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
621 if (!adev_to_drm(adev)->irq_enabled)
624 if (type >= src->num_types)
627 if (!src->enabled_types || !src->funcs->set)
630 if (atomic_dec_and_test(&src->enabled_types[type]))
631 return amdgpu_irq_update(adev, src, type);
637 * amdgpu_irq_enabled - check whether interrupt is enabled or not
639 * @adev: amdgpu device pointer
640 * @src: interrupt source pointer
641 * @type: type of interrupt
643 * Checks whether the given type of interrupt is enabled on the given source.
646 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
649 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
652 if (!adev_to_drm(adev)->irq_enabled)
655 if (type >= src->num_types)
658 if (!src->enabled_types || !src->funcs->set)
661 return !!atomic_read(&src->enabled_types[type]);
664 /* XXX: Generic IRQ handling */
665 static void amdgpu_irq_mask(struct irq_data *irqd)
670 static void amdgpu_irq_unmask(struct irq_data *irqd)
675 /* amdgpu hardware interrupt chip descriptor */
676 static struct irq_chip amdgpu_irq_chip = {
678 .irq_mask = amdgpu_irq_mask,
679 .irq_unmask = amdgpu_irq_unmask,
683 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
685 * @d: amdgpu IRQ domain pointer (unused)
686 * @irq: virtual IRQ number
687 * @hwirq: hardware irq number
689 * Current implementation assigns simple interrupt handler to the given virtual
693 * 0 on success or error code otherwise
695 static int amdgpu_irqdomain_map(struct irq_domain *d,
696 unsigned int irq, irq_hw_number_t hwirq)
698 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
701 irq_set_chip_and_handler(irq,
702 &amdgpu_irq_chip, handle_simple_irq);
706 /* Implementation of methods for amdgpu IRQ domain */
707 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
708 .map = amdgpu_irqdomain_map,
712 * amdgpu_irq_add_domain - create a linear IRQ domain
714 * @adev: amdgpu device pointer
716 * Creates an IRQ domain for GPU interrupt sources
717 * that may be driven by another driver (e.g., ACP).
720 * 0 on success or error code otherwise
722 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
724 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
725 &amdgpu_hw_irqdomain_ops, adev);
726 if (!adev->irq.domain) {
727 DRM_ERROR("GPU irq add domain failed\n");
735 * amdgpu_irq_remove_domain - remove the IRQ domain
737 * @adev: amdgpu device pointer
739 * Removes the IRQ domain for GPU interrupt sources
740 * that may be driven by another driver (e.g., ACP).
742 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
744 if (adev->irq.domain) {
745 irq_domain_remove(adev->irq.domain);
746 adev->irq.domain = NULL;
751 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
753 * @adev: amdgpu device pointer
754 * @src_id: IH source id
756 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
757 * Use this for components that generate a GPU interrupt, but are driven
758 * by a different driver (e.g., ACP).
763 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
765 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
767 return adev->irq.virq[src_id];