2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 * DOC: Interrupt Handling
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
45 #include <linux/irq.h>
46 #include <linux/pci.h>
48 #include <drm/drm_crtc_helper.h>
49 #include <drm/drm_irq.h>
50 #include <drm/drm_vblank.h>
51 #include <drm/amdgpu_drm.h>
53 #include "amdgpu_ih.h"
55 #include "amdgpu_connectors.h"
56 #include "amdgpu_trace.h"
57 #include "amdgpu_amdkfd.h"
59 #include <linux/pm_runtime.h>
61 #ifdef CONFIG_DRM_AMD_DC
62 #include "amdgpu_dm_irq.h"
65 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
68 * amdgpu_hotplug_work_func - work handler for display hotplug event
70 * @work: work struct pointer
72 * This is the hotplug event work handler (all ASICs).
73 * The work gets scheduled from the IRQ handler if there
74 * was a hotplug interrupt. It walks through the connector table
75 * and calls hotplug handler for each connector. After this, it sends
76 * a DRM hotplug event to alert userspace.
78 * This design approach is required in order to defer hotplug event handling
79 * from the IRQ handler to a work handler because hotplug handler has to use
80 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
83 static void amdgpu_hotplug_work_func(struct work_struct *work)
85 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
87 struct drm_device *dev = adev->ddev;
88 struct drm_mode_config *mode_config = &dev->mode_config;
89 struct drm_connector *connector;
91 mutex_lock(&mode_config->mutex);
92 list_for_each_entry(connector, &mode_config->connector_list, head)
93 amdgpu_connector_hotplug(connector);
94 mutex_unlock(&mode_config->mutex);
95 /* Just fire off a uevent and let userspace tell us what to do */
96 drm_helper_hpd_irq_event(dev);
100 * amdgpu_irq_disable_all - disable *all* interrupts
102 * @adev: amdgpu device pointer
104 * Disable all types of interrupts from all sources.
106 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
108 unsigned long irqflags;
112 spin_lock_irqsave(&adev->irq.lock, irqflags);
113 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
114 if (!adev->irq.client[i].sources)
117 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
118 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
120 if (!src || !src->funcs->set || !src->num_types)
123 for (k = 0; k < src->num_types; ++k) {
124 atomic_set(&src->enabled_types[k], 0);
125 r = src->funcs->set(adev, src, k,
126 AMDGPU_IRQ_STATE_DISABLE);
128 DRM_ERROR("error disabling interrupt (%d)\n",
133 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
137 * amdgpu_irq_handler - IRQ handler
139 * @irq: IRQ number (unused)
140 * @arg: pointer to DRM device
142 * IRQ handler for amdgpu driver (all ASICs).
145 * result of handling the IRQ, as defined by &irqreturn_t
147 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
149 struct drm_device *dev = (struct drm_device *) arg;
150 struct amdgpu_device *adev = dev->dev_private;
153 ret = amdgpu_ih_process(adev, &adev->irq.ih);
154 if (ret == IRQ_HANDLED)
155 pm_runtime_mark_last_busy(dev->dev);
160 * amdgpu_irq_handle_ih1 - kick of processing for IH1
162 * @work: work structure in struct amdgpu_irq
164 * Kick of processing IH ring 1.
166 static void amdgpu_irq_handle_ih1(struct work_struct *work)
168 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
171 amdgpu_ih_process(adev, &adev->irq.ih1);
175 * amdgpu_irq_handle_ih2 - kick of processing for IH2
177 * @work: work structure in struct amdgpu_irq
179 * Kick of processing IH ring 2.
181 static void amdgpu_irq_handle_ih2(struct work_struct *work)
183 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
186 amdgpu_ih_process(adev, &adev->irq.ih2);
190 * amdgpu_msi_ok - check whether MSI functionality is enabled
192 * @adev: amdgpu device pointer (unused)
194 * Checks whether MSI functionality has been disabled via module parameter
198 * *true* if MSIs are allowed to be enabled or *false* otherwise
200 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
204 else if (amdgpu_msi == 0)
211 * amdgpu_irq_init - initialize interrupt handling
213 * @adev: amdgpu device pointer
215 * Sets up work functions for hotplug and reset interrupts, enables MSI
216 * functionality, initializes vblank, hotplug and reset interrupt handling.
219 * 0 on success or error code on failure
221 int amdgpu_irq_init(struct amdgpu_device *adev)
225 spin_lock_init(&adev->irq.lock);
227 /* Enable MSI if not disabled by module parameter */
228 adev->irq.msi_enabled = false;
230 if (amdgpu_msi_ok(adev)) {
231 int ret = pci_enable_msi(adev->pdev);
233 adev->irq.msi_enabled = true;
234 dev_dbg(adev->dev, "amdgpu: using MSI.\n");
238 if (!amdgpu_device_has_dc_support(adev)) {
239 if (!adev->enable_virtual_display)
240 /* Disable vblank IRQs aggressively for power-saving */
241 /* XXX: can this be enabled for DC? */
242 adev->ddev->vblank_disable_immediate = true;
244 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
249 INIT_WORK(&adev->hotplug_work,
250 amdgpu_hotplug_work_func);
253 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
254 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
256 adev->irq.installed = true;
257 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
259 adev->irq.installed = false;
260 if (!amdgpu_device_has_dc_support(adev))
261 flush_work(&adev->hotplug_work);
264 adev->ddev->max_vblank_count = 0x00ffffff;
266 DRM_DEBUG("amdgpu: irq initialized.\n");
271 * amdgpu_irq_fini - shut down interrupt handling
273 * @adev: amdgpu device pointer
275 * Tears down work functions for hotplug and reset interrupts, disables MSI
276 * functionality, shuts down vblank, hotplug and reset interrupt handling,
277 * turns off interrupts from all sources (all ASICs).
279 void amdgpu_irq_fini(struct amdgpu_device *adev)
283 if (adev->irq.installed) {
284 drm_irq_uninstall(adev->ddev);
285 adev->irq.installed = false;
286 if (adev->irq.msi_enabled)
287 pci_disable_msi(adev->pdev);
288 if (!amdgpu_device_has_dc_support(adev))
289 flush_work(&adev->hotplug_work);
292 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
293 if (!adev->irq.client[i].sources)
296 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
297 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
302 kfree(src->enabled_types);
303 src->enabled_types = NULL;
307 adev->irq.client[i].sources[j] = NULL;
310 kfree(adev->irq.client[i].sources);
311 adev->irq.client[i].sources = NULL;
316 * amdgpu_irq_add_id - register IRQ source
318 * @adev: amdgpu device pointer
319 * @client_id: client id
321 * @source: IRQ source pointer
323 * Registers IRQ source on a client.
326 * 0 on success or error code otherwise
328 int amdgpu_irq_add_id(struct amdgpu_device *adev,
329 unsigned client_id, unsigned src_id,
330 struct amdgpu_irq_src *source)
332 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
335 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
341 if (!adev->irq.client[client_id].sources) {
342 adev->irq.client[client_id].sources =
343 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
344 sizeof(struct amdgpu_irq_src *),
346 if (!adev->irq.client[client_id].sources)
350 if (adev->irq.client[client_id].sources[src_id] != NULL)
353 if (source->num_types && !source->enabled_types) {
356 types = kcalloc(source->num_types, sizeof(atomic_t),
361 source->enabled_types = types;
364 adev->irq.client[client_id].sources[src_id] = source;
369 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
371 * @adev: amdgpu device pointer
372 * @entry: interrupt vector pointer
374 * Dispatches IRQ to IP blocks.
376 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
377 struct amdgpu_ih_ring *ih)
379 u32 ring_index = ih->rptr >> 2;
380 struct amdgpu_iv_entry entry;
381 unsigned client_id, src_id;
382 struct amdgpu_irq_src *src;
383 bool handled = false;
386 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
387 amdgpu_ih_decode_iv(adev, &entry);
389 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
391 client_id = entry.client_id;
392 src_id = entry.src_id;
394 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
395 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
397 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
398 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
400 } else if (adev->irq.virq[src_id]) {
401 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
403 } else if (!adev->irq.client[client_id].sources) {
404 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
407 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
408 r = src->funcs->process(adev, src, &entry);
410 DRM_ERROR("error processing interrupt (%d)\n", r);
415 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
418 /* Send it to amdkfd as well if it isn't already handled */
420 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
424 * amdgpu_irq_update - update hardware interrupt state
426 * @adev: amdgpu device pointer
427 * @src: interrupt source pointer
428 * @type: type of interrupt
430 * Updates interrupt state for the specific source (all ASICs).
432 int amdgpu_irq_update(struct amdgpu_device *adev,
433 struct amdgpu_irq_src *src, unsigned type)
435 unsigned long irqflags;
436 enum amdgpu_interrupt_state state;
439 spin_lock_irqsave(&adev->irq.lock, irqflags);
441 /* We need to determine after taking the lock, otherwise
442 we might disable just enabled interrupts again */
443 if (amdgpu_irq_enabled(adev, src, type))
444 state = AMDGPU_IRQ_STATE_ENABLE;
446 state = AMDGPU_IRQ_STATE_DISABLE;
448 r = src->funcs->set(adev, src, type, state);
449 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
454 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
456 * @adev: amdgpu device pointer
458 * Updates state of all types of interrupts on all sources on resume after
461 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
465 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
466 if (!adev->irq.client[i].sources)
469 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
470 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
474 for (k = 0; k < src->num_types; k++)
475 amdgpu_irq_update(adev, src, k);
481 * amdgpu_irq_get - enable interrupt
483 * @adev: amdgpu device pointer
484 * @src: interrupt source pointer
485 * @type: type of interrupt
487 * Enables specified type of interrupt on the specified source (all ASICs).
490 * 0 on success or error code otherwise
492 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
495 if (!adev->ddev->irq_enabled)
498 if (type >= src->num_types)
501 if (!src->enabled_types || !src->funcs->set)
504 if (atomic_inc_return(&src->enabled_types[type]) == 1)
505 return amdgpu_irq_update(adev, src, type);
511 * amdgpu_irq_put - disable interrupt
513 * @adev: amdgpu device pointer
514 * @src: interrupt source pointer
515 * @type: type of interrupt
517 * Enables specified type of interrupt on the specified source (all ASICs).
520 * 0 on success or error code otherwise
522 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
525 if (!adev->ddev->irq_enabled)
528 if (type >= src->num_types)
531 if (!src->enabled_types || !src->funcs->set)
534 if (atomic_dec_and_test(&src->enabled_types[type]))
535 return amdgpu_irq_update(adev, src, type);
541 * amdgpu_irq_enabled - check whether interrupt is enabled or not
543 * @adev: amdgpu device pointer
544 * @src: interrupt source pointer
545 * @type: type of interrupt
547 * Checks whether the given type of interrupt is enabled on the given source.
550 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
553 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
556 if (!adev->ddev->irq_enabled)
559 if (type >= src->num_types)
562 if (!src->enabled_types || !src->funcs->set)
565 return !!atomic_read(&src->enabled_types[type]);
568 /* XXX: Generic IRQ handling */
569 static void amdgpu_irq_mask(struct irq_data *irqd)
574 static void amdgpu_irq_unmask(struct irq_data *irqd)
579 /* amdgpu hardware interrupt chip descriptor */
580 static struct irq_chip amdgpu_irq_chip = {
582 .irq_mask = amdgpu_irq_mask,
583 .irq_unmask = amdgpu_irq_unmask,
587 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
589 * @d: amdgpu IRQ domain pointer (unused)
590 * @irq: virtual IRQ number
591 * @hwirq: hardware irq number
593 * Current implementation assigns simple interrupt handler to the given virtual
597 * 0 on success or error code otherwise
599 static int amdgpu_irqdomain_map(struct irq_domain *d,
600 unsigned int irq, irq_hw_number_t hwirq)
602 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
605 irq_set_chip_and_handler(irq,
606 &amdgpu_irq_chip, handle_simple_irq);
610 /* Implementation of methods for amdgpu IRQ domain */
611 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
612 .map = amdgpu_irqdomain_map,
616 * amdgpu_irq_add_domain - create a linear IRQ domain
618 * @adev: amdgpu device pointer
620 * Creates an IRQ domain for GPU interrupt sources
621 * that may be driven by another driver (e.g., ACP).
624 * 0 on success or error code otherwise
626 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
628 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
629 &amdgpu_hw_irqdomain_ops, adev);
630 if (!adev->irq.domain) {
631 DRM_ERROR("GPU irq add domain failed\n");
639 * amdgpu_irq_remove_domain - remove the IRQ domain
641 * @adev: amdgpu device pointer
643 * Removes the IRQ domain for GPU interrupt sources
644 * that may be driven by another driver (e.g., ACP).
646 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
648 if (adev->irq.domain) {
649 irq_domain_remove(adev->irq.domain);
650 adev->irq.domain = NULL;
655 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
657 * @adev: amdgpu device pointer
658 * @src_id: IH source id
660 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
661 * Use this for components that generate a GPU interrupt, but are driven
662 * by a different driver (e.g., ACP).
667 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
669 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
671 return adev->irq.virq[src_id];