2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __AMDGPU_IH_H__
25 #define __AMDGPU_IH_H__
27 /* Maximum number of IVs processed at once */
28 #define AMDGPU_IH_MAX_NUM_IVS 32
31 struct amdgpu_iv_entry;
33 struct amdgpu_ih_regs {
35 uint32_t ih_rb_base_hi;
39 uint32_t ih_doorbell_rptr;
40 uint32_t ih_rb_wptr_addr_lo;
41 uint32_t ih_rb_wptr_addr_hi;
48 struct amdgpu_ih_ring {
55 struct amdgpu_bo *ring_obj;
56 volatile uint32_t *ring;
60 volatile uint32_t *wptr_cpu;
63 volatile uint32_t *rptr_cpu;
67 struct amdgpu_ih_regs ih_regs;
69 /* For waiting on IH processing at checkpoint. */
70 wait_queue_head_t wait_process;
73 /* provided by the ih block */
74 struct amdgpu_ih_funcs {
75 /* ring read/write ptr handling, called from interrupt context */
76 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
77 void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
78 struct amdgpu_iv_entry *entry);
79 void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
82 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
83 #define amdgpu_ih_decode_iv(adev, iv) \
84 (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
85 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
87 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
88 unsigned ring_size, bool use_bus_addr);
89 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
90 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
92 int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
93 struct amdgpu_ih_ring *ih);
94 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
95 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
96 struct amdgpu_ih_ring *ih,
97 struct amdgpu_iv_entry *entry);