2 * Copyright 2014 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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24 #include <linux/dma-mapping.h>
27 #include "amdgpu_ih.h"
30 * amdgpu_ih_ring_init - initialize the IH state
32 * @adev: amdgpu_device pointer
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
35 * @use_bus_addr: true when we can use dma_alloc_coherent
37 * Initializes the IH state and allocates a buffer
38 * for the IH ring buffer.
39 * Returns 0 for success, errors for failure.
41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
42 unsigned ring_size, bool use_bus_addr)
48 rb_bufsz = order_base_2(ring_size / 4);
49 ring_size = (1 << rb_bufsz) * 4;
50 ih->ring_size = ring_size;
51 ih->ptr_mask = ih->ring_size - 1;
53 ih->use_bus_addr = use_bus_addr;
61 /* add 8 bytes for the rptr/wptr shadows and
62 * add them to the end of the ring allocation.
64 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
65 &dma_addr, GFP_KERNEL);
69 ih->gpu_addr = dma_addr;
70 ih->wptr_addr = dma_addr + ih->ring_size;
71 ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
72 ih->rptr_addr = dma_addr + ih->ring_size + 4;
73 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
75 unsigned wptr_offs, rptr_offs;
77 r = amdgpu_device_wb_get(adev, &wptr_offs);
81 r = amdgpu_device_wb_get(adev, &rptr_offs);
83 amdgpu_device_wb_free(adev, wptr_offs);
87 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
88 AMDGPU_GEM_DOMAIN_GTT,
89 &ih->ring_obj, &ih->gpu_addr,
92 amdgpu_device_wb_free(adev, rptr_offs);
93 amdgpu_device_wb_free(adev, wptr_offs);
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs];
99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
100 ih->rptr_cpu = &adev->wb.wb[rptr_offs];
103 init_waitqueue_head(&ih->wait_process);
108 * amdgpu_ih_ring_fini - tear down the IH state
110 * @adev: amdgpu_device pointer
111 * @ih: ih ring to tear down
113 * Tears down the IH state and frees buffer
114 * used for the IH ring buffer.
116 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
118 if (ih->use_bus_addr) {
122 /* add 8 bytes for the rptr/wptr shadows and
123 * add them to the end of the ring allocation.
125 dma_free_coherent(adev->dev, ih->ring_size + 8,
126 (void *)ih->ring, ih->gpu_addr);
129 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
131 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
132 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
137 * amdgpu_ih_ring_write - write IV to the ring buffer
139 * @ih: ih ring to write to
140 * @iv: the iv to write
141 * @num_dw: size of the iv in dw
143 * Writes an IV to the ring buffer using the CPU and increment the wptr.
144 * Used for testing and delegating IVs to a software ring.
146 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
149 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
152 for (i = 0; i < num_dw; ++i)
153 ih->ring[wptr++] = cpu_to_le32(iv[i]);
156 wptr &= ih->ptr_mask;
158 /* Only commit the new wptr if we don't overflow */
159 if (wptr != READ_ONCE(ih->rptr)) {
161 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
165 /* Waiter helper that checks current rptr matches or passes checkpoint wptr */
166 static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev,
167 struct amdgpu_ih_ring *ih,
168 uint32_t checkpoint_wptr,
171 uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask);
173 /* rptr has wrapped. */
174 if (cur_rptr < *prev_rptr)
175 cur_rptr += ih->ptr_mask + 1;
176 *prev_rptr = cur_rptr;
178 /* check ring is empty to workaround missing wptr overflow flag */
179 return cur_rptr >= checkpoint_wptr ||
180 (cur_rptr & ih->ptr_mask) == amdgpu_ih_get_wptr(adev, ih);
184 * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint
186 * @adev: amdgpu_device pointer
187 * @ih: ih ring to process
189 * Used to ensure ring has processed IVs up to the checkpoint write pointer.
191 int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
192 struct amdgpu_ih_ring *ih)
194 uint32_t checkpoint_wptr, rptr;
196 if (!ih->enabled || adev->shutdown)
199 checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
200 /* Order wptr with rptr. */
202 rptr = READ_ONCE(ih->rptr);
204 /* wptr has wrapped. */
205 if (rptr > checkpoint_wptr)
206 checkpoint_wptr += ih->ptr_mask + 1;
208 return wait_event_interruptible(ih->wait_process,
209 amdgpu_ih_has_checkpoint_processed(adev, ih,
210 checkpoint_wptr, &rptr));
214 * amdgpu_ih_process - interrupt handler
216 * @adev: amdgpu_device pointer
217 * @ih: ih ring to process
219 * Interrupt hander (VI), walk the IH ring.
220 * Returns irq process return code.
222 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
224 unsigned int count = AMDGPU_IH_MAX_NUM_IVS;
227 if (!ih->enabled || adev->shutdown)
230 wptr = amdgpu_ih_get_wptr(adev, ih);
233 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
235 /* Order reading of wptr vs. reading of IH ring data */
238 while (ih->rptr != wptr && --count) {
239 amdgpu_irq_dispatch(adev, ih);
240 ih->rptr &= ih->ptr_mask;
243 amdgpu_ih_set_rptr(adev, ih);
244 wake_up_all(&ih->wait_process);
246 /* make sure wptr hasn't changed while processing */
247 wptr = amdgpu_ih_get_wptr(adev, ih);
248 if (wptr != ih->rptr)
255 * amdgpu_ih_decode_iv_helper - decode an interrupt vector
257 * @adev: amdgpu_device pointer
258 * @ih: ih ring to process
261 * Decodes the interrupt vector at the current rptr
262 * position and also advance the position for for Vega10
265 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
266 struct amdgpu_ih_ring *ih,
267 struct amdgpu_iv_entry *entry)
269 /* wptr/rptr are in bytes! */
270 u32 ring_index = ih->rptr >> 2;
273 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
274 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
275 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
276 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
277 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
278 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
279 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
280 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
282 entry->client_id = dw[0] & 0xff;
283 entry->src_id = (dw[0] >> 8) & 0xff;
284 entry->ring_id = (dw[0] >> 16) & 0xff;
285 entry->vmid = (dw[0] >> 24) & 0xf;
286 entry->vmid_src = (dw[0] >> 31);
287 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
288 entry->timestamp_src = dw[2] >> 31;
289 entry->pasid = dw[3] & 0xffff;
290 entry->pasid_src = dw[3] >> 31;
291 entry->src_data[0] = dw[4];
292 entry->src_data[1] = dw[5];
293 entry->src_data[2] = dw[6];
294 entry->src_data[3] = dw[7];
296 /* wptr/rptr are in bytes! */